CN117673121A

CN117673121A - MOS transistor and method for manufacturing the same

Info

Publication number: CN117673121A
Application number: CN202211040172.2A
Authority: CN
Inventors: 杭华
Original assignee: Minhua Micro Shanghai Electronic Technology Co ltd
Current assignee: Minhua Micro Shanghai Electronic Technology Co ltd
Priority date: 2022-08-29
Filing date: 2022-08-29
Publication date: 2024-03-08

Abstract

The invention discloses a MOS transistor, comprising: the first well region comprises a source end lightly doped drain region and a drain end lightly doped drain region, and the source end lightly doped drain region and the drain end lightly doped drain region are respectively self-aligned with two side surfaces of the grid structure. Side walls are formed on two side surfaces of the grid structure. The source region is self-aligned with the side of the sidewall on the first side of the gate structure, and the effective lateral length of the source lightly doped drain region is determined by the width of the sidewall. The drain region and the side of the side wall on the second side of the grid structure are provided with a first interval, and the effective transverse length of the drain end lightly doped drain region is determined by the sum of the width of the side wall and the first interval. The first dielectric layer covers the surface of the drain end lightly doped drain region between the side wall and the drain region of the second side face of the grid structure. The invention also discloses a manufacturing method of the MOS transistor. The invention can increase the withstand voltage of the device and reduce the complexity and cost of the process.

Description

MOS transistor and method for manufacturing the same

Technical Field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a MOS transistor; the invention also relates to a manufacturing method of the MOS transistor.

Background

In many integrated circuit chip designs, the internal circuitry of the chip often needs to be used to a higher operating voltage than supported by standard process platforms, for example in a 2.5od3.3V IO process platform, the internal high voltage circuitry may need to be used to a voltage of 5V or higher, and standard 2.5V devices have no way to deliver voltages higher than 3.6V depending on reliability requirements. Such chips have an embedded non-volatile memory (NVM) of the microcontroller and a peripheral driver module; a Radio Frequency (RF) power circuit, and a boost or high voltage transmission module that controls the chip-like. There are currently two mainstream solutions in the industry for this application:

the prior first improvement method is to introduce a high-voltage MOS transistor device with a thicker gate oxide film in the original process so as to improve the voltage withstanding characteristic of the device. As shown in fig. 1, a schematic cross-sectional structure of a conventional first MOS transistor for improving withstand voltage is shown; taking NMOS as an example:

a P-well 102 is formed in a semiconductor substrate such as a silicon substrate 101.

The active region is defined by field oxide formed on the silicon substrate 101, such as shallow trench isolation 103.

The gate structure is formed by superimposing a gate oxide layer 104 and a polysilicon gate 105. The withstand voltage of the device is increased by increasing the thickness of the gate oxide layer 104.

Lightly Doped Drain (LDD) regions 106 are self-aligned to the surface of the P-well 102 on both sides of the gate structure.

A sidewall 107 is also formed on the side of the gate structure.

The sides of the sidewall 107 on both sides of the gate structure are self-aligned to form an active region 108 and a drain region 109.

The existing second improvement method is that the LDMOS which can resist high voltage is formed by changing the structure of the device on the basis of adopting the original device gate oxide layer. As shown in fig. 2, a schematic cross-sectional structure of a conventional second MOS transistor for improving withstand voltage is shown; also taking an N-type LDMOS as an example:

a P-well 202 is formed in a semiconductor substrate such as a silicon substrate 201.

The active region is defined by field oxide formed on the silicon substrate 201, such as shallow trench isolation 203.

The gate structure is formed by the superposition of a gate oxide 205 and a polysilicon gate 206. The gate oxide 205 here is set to be the same thickness as that of a standard NMOS.

A lightly doped drain region 207 is self-aligned to the surface of the P-well 202 outside the first side of the gate structure.

Side walls 208 are also formed on the sides of the gate structure.

An active region 209 is formed in self-alignment at a side of the sidewall 208 at the first side of the gate structure.

An N-doped drift region 204 is also formed in the P-well 202, and a drain region 210 is formed in the drift region 204. A drift region field oxide 203a is also formed in the drift region 204 between the drain region 210 and the sidewall 208 of the second side of the gate structure.

The two solutions mentioned above are currently more common methods for providing both withstand voltage and transmitting high voltage, but are not entirely satisfactory, for the main reasons:

in the existing first MOS transistor structure for improving the withstand voltage, as a thicker gate oxide layer is required to form a high-voltage MOS device, the process steps are obviously increased, usually 3-5 extra mask layers are required to be introduced into the existing MOS process flow, the complexity and the heat history of the process are increased, the characteristics of other devices can be possibly changed, and the compatibility of an IP module of an original platform is deteriorated.

In the existing second MOS transistor structure for improving the withstand voltage, although the gate oxide dielectric of the original device can be adopted, because the device structure is significantly changed, an additional field oxide isolation, i.e. a drift region field oxide 203a, is introduced into the drain terminal, thereby significantly increasing the device area, and in addition, because the drain terminal needs to form an additional drift region 204, an additional mask layer is needed for implantation doping.

Both of the above-mentioned existing improvement methods have additional mask layers introduced, which not only increases the complexity of the process flow, but also significantly increases the device area, which brings about production costs and reduces the competitiveness of the product. In addition, during the manufacturing process of the advanced technology, the introduction of thermal histories and etching steps of the additional mask layers can significantly affect the compatibility of the existing IP module, even disable the original IP module.

Disclosure of Invention

The invention aims to solve the technical problem of providing the MOS transistor, which can increase the voltage-resistant capability of the device without increasing the thickness of a gate dielectric layer and the field oxygen of a drift region, is beneficial to realizing the integrated manufacture of a plurality of MOS transistors with different voltage resistances, can reduce the complexity and the cost of the process, can not bring additional heat histories to the MOS transistors with different voltage resistances, can further stabilize the performance of the device, can also reduce the area of the device, and can improve the compatibility of an IP module of a process platform. For this purpose, the invention also provides a manufacturing method of the MOS transistor.

In order to solve the above technical problems, the MOS transistor provided by the present invention includes:

a second conductivity type doped first well region is formed in a selected region of the semiconductor substrate.

And the gate structure is formed on the surface of the selected area of the first well region and is formed by laminating a gate dielectric layer and a gate conductive material layer.

The source end lightly doped drain region and the drain end lightly doped drain region are formed by the lightly doped drain region of the first conductivity type, the source end lightly doped drain region and the first side face of the grid structure are self-aligned, and the drain end lightly doped drain region and the second side face of the grid structure are self-aligned.

And the side wall is formed on the first side surface and the second side surface of the grid electrode structure in a self-aligned mode.

The source region and the drain region are formed by heavily doped source-drain injection regions of the first conductivity type, the source region and the side face of the side wall on the first side face of the grid structure are self-aligned, the junction depth of the source region is larger than that of the source-end lightly doped drain region, and the effective transverse length of the source-end lightly doped drain region is determined by the width of the side wall.

The drain region and the side surface of the side wall on the second side surface of the grid structure are provided with a first interval, the junction depth of the drain region is larger than that of the drain end lightly doped drain region, and the effective transverse length of the drain end lightly doped drain region is determined by the sum of the width of the side wall and the first interval.

And the first dielectric layer covers the surface of the drain end lightly doped drain region between the side wall of the second side surface of the grid structure and the drain region.

And under the condition that the thickness of the gate dielectric layer is kept unchanged, adjusting the voltage withstand of the MOS transistor by adjusting the first spacing, wherein the larger the first spacing is, the larger the voltage withstand of the MOS transistor is.

Further, the MOS transistors having different first pitches are integrated on the same semiconductor substrate, so that the MOS transistors having different withstand voltages are integrated on the semiconductor substrate at the same time.

In the MOS transistor with various withstand voltages, the gate dielectric layer, the first well region and the first conductive type lightly doped drain region have the same process structure and are determined by the withstand voltage value of the MOS transistor with the lowest withstand voltage.

A further improvement is that 2 MOS transistors with different first pitches are integrated on the same semiconductor substrate at the same time, so that 2 voltage-resistant MOS transistors are integrated on the semiconductor substrate at the same time;

the first interval of the MOS transistor with the lowest withstand voltage is 0nm, and the effective lateral length of the drain-end lightly doped drain region is determined by the width of the side wall.

The further improvement is that the gate dielectric layer comprises a gate oxide layer; the gate conductive material layer includes a polysilicon gate.

A further improvement is that metal silicide is formed on the surfaces of the source region, the drain region and the polysilicon gate.

The first dielectric layer is formed by adopting a self-aligned metal silicide blocking layer.

A further improvement is that the MOS transistor comprises an NMOS and a PMOS, and the NMOS and the PMOS are integrated on the semiconductor substrate at the same time;

when the MOS transistor is the NMOS, the first conduction type is N type, and the second conduction type is P type;

when the MOS transistor is the PMOS, the first conductive type is P-type, and the second conductive type is N-type.

In order to solve the technical problems, the manufacturing method of the MOS transistor provided by the invention comprises the following steps:

forming a first well region doped with a second conductivity type in a selected region of a semiconductor substrate, and forming a gate structure formed by stacking a gate dielectric layer and a gate conductive material layer on the surface of the selected region of the first well region;

secondly, carrying out lightly doped drain injection of a first conductivity type by taking the side surface of the grid structure as a self-alignment condition to form a lightly doped drain injection region, wherein the lightly doped drain injection region and the two side surfaces of the grid structure are self-aligned;

thirdly, forming side walls on the first side face and the second side face of the grid structure in a self-aligned mode;

step four, forming a first graph structure; in a forming region of the MOS transistor, the first graph structure at least covers the surface of the lightly doped drain injection region with the width of a first space outside the side wall of the second side surface of the grid structure, and the region outside the first graph structure is opened;

the first side surface of the first graph structure is positioned between the side surfaces of the side walls on two sides of the grid structure, the second side surface of the first graph structure is positioned on the surface of the lightly doped drain injection region outside the side walls on the second side surface of the grid structure, and the distance between the second side surface of the first graph structure and the side surfaces of the side walls on the second side surface of the grid structure is the first distance;

fifthly, performing source-drain implantation of heavy doping of a first conduction type by taking the first graph structure and the grid structure as masks to form a source region and the drain region;

the source region and the side surface of the side wall on the first side surface of the grid structure are self-aligned, the junction depth of the source region is larger than that of the lightly doped drain injection region, the source end lightly doped drain region is formed by the lightly doped drain injection region between the source region and the first side surface of the grid structure, and the effective transverse length of the source end lightly doped drain region is determined by the width of the side wall;

the drain region and the side surface of the side wall on the second side surface of the grid structure are provided with the first interval, the junction depth of the drain region is larger than that of the lightly doped drain injection region, a drain end lightly doped drain region is formed by the lightly doped drain injection region between the drain region and the second side surface of the grid structure, and the effective transverse length of the drain end lightly doped drain region is determined by the sum of the width of the side wall and the first interval;

under the condition that the thickness of the gate dielectric layer is kept unchanged, the voltage withstand of the MOS transistor is adjusted by adjusting the first spacing, and the larger the first spacing is, the larger the voltage withstand of the MOS transistor is;

step six, removing the first graph structure;

and step seven, forming a first dielectric layer, wherein the first dielectric layer covers the surface of the drain end lightly doped drain region between the side wall and the drain region of the second side surface of the grid structure.

The process structures of the gate dielectric layer, the first well region and the first conductive type lightly doped drain region of the MOS transistor with various withstand voltages are the same and are determined by the withstand voltage value of the MOS transistor with the lowest withstand voltage.

A further improvement is that the various voltage-resistant MOS transistors share the steps one to seven;

in the fourth step, the first pattern structures of the formation regions of the various withstand voltages of the MOS transistors are formed simultaneously to set the first pitches corresponding to the various withstand voltages of the MOS transistors.

The further improvement is that the gate dielectric layer comprises a gate oxide layer, and the gate oxide layer is formed by adopting a thermal oxidation process; the gate conductive material layer includes a polysilicon gate.

In a further improvement, in the step seven, the first dielectric layer is formed by adopting a patterned self-aligned metal silicide blocking layer.

After the self-aligned metal silicide blocking layer is subjected to graphical etching, the source region, the drain region and the region on the surface of the polysilicon gate, in which metal silicide needs to be formed, are opened.

And then, forming metal silicide on the source region, the drain region and the polysilicon gate surface in a self-aligned manner.

Compared with the prior art that the breakdown voltage, namely the withstand voltage, of the device is improved by increasing the thickness of a gate dielectric layer such as a gate oxide layer or increasing the field oxygen of a drift region or a drift region, the invention only needs to adjust the effective lateral length of a drain-end lightly doped drain region and mainly increases the first interval outside the width of a side wall, and the effective lateral length of the drain-end lightly doped drain region is adjusted by the first interval so as to adjust the withstand voltage of the device, thus the withstand voltage of the device can be increased by increasing the first interval.

The invention can increase the voltage resistance of the device without increasing the thickness of the gate dielectric layer and the field oxide of the drift region, and the invention can increase the complexity and the cost of the process and the heat history because the growth process and the photoetching process of the gate dielectric layer are increased once every time the thickness of one gate dielectric layer is increased; the leakage current increases the field oxide of the drift region and the drift region, so that the process structures of the high-voltage-resistant MOS transistor and the standard MOS transistor are completely different, the complexity and the cost of the process are increased, the heat history is increased, and the area of the device is increased; the invention can increase the voltage resistance of the device without increasing the thickness of the gate dielectric layer and the field oxide of the drift region, thereby reducing the complexity and cost of the process, avoiding bringing additional heat histories to MOS transistors with different voltage resistance, stabilizing the performance of the device, reducing the area of the device and improving the compatibility of the IP module of a process platform.

Drawings

The invention is described in further detail below with reference to the attached drawings and detailed description:

fig. 1 is a schematic cross-sectional view of a conventional first voltage-withstand-improving MOS transistor;

fig. 2 is a schematic cross-sectional structure of a conventional second type of voltage-withstand-improving MOS transistor;

fig. 3 is a schematic cross-sectional structure of a MOS transistor according to an embodiment of the present invention;

fig. 4 is a schematic top view of a MOS transistor according to an embodiment of the present invention;

fig. 5A to 5H are schematic cross-sectional views of a device in each step of a method for manufacturing a MOS transistor according to an embodiment of the present invention.

Detailed Description

Fig. 3 is a schematic cross-sectional view of a MOS transistor according to an embodiment of the invention; fig. 4 is a schematic top view of a MOS transistor according to an embodiment of the present invention; the MOS transistor of the embodiment of the invention comprises:

a second conductivity type doped first well region 402 is formed in a selected region of the semiconductor substrate 401.

A gate structure is formed on a surface of the selected region of the first well region 402 and is formed by overlapping a gate dielectric layer (not shown) and a gate conductive material layer 403.

In some embodiments, the gate dielectric layer includes a gate oxide layer; the gate oxide layer is formed by adopting a thermal oxidation process. The gate conductive material layer 403 includes a polysilicon gate.

A source lightly doped drain 4041 and a drain lightly doped drain 4042 comprised of lightly doped drain 407 of the first conductivity type, the source lightly doped drain 4041 and the first side of the gate structure being self-aligned, the drain lightly doped drain 4042 and the second side of the gate structure being self-aligned.

Side walls 405 are formed on the first side and the second side of the gate structure in a self-aligned manner.

A source region 406 and a drain region 407 formed by a heavily doped source-drain implant region of a first conductivity type, the source region 406 and a side of the sidewall 405 on a first side of the gate structure being self-aligned, a junction depth of the source region 406 being greater than a junction depth of the source lightly doped drain region 4041, an effective lateral length of the source lightly doped drain region 4041 being determined by a width of the sidewall 405.

The drain region 407 and the side of the sidewall 405 on the second side of the gate structure have a first interval, the junction depth of the drain region 407 is greater than the junction depth of the drain terminal lightly doped drain region 4042, and the effective lateral length of the drain terminal lightly doped drain region 4042 is determined by the sum of the width of the sidewall 405 and the first interval.

Comparing the effective lateral lengths of the source LDD 4041 and the drain LDD 4042 in fig. 3, the lateral length of the source LDD 4041 is defined by the width of the sidewall 405, and the drain LDD 4042 also extends outside the area covered by the sidewall 405, so the drain LDD 4042 can be referred to as an Extended LDD (ELDD) and the MOS transistor can be referred to as an ELDD MOS transistor.

A first dielectric layer 408 overlies the surface of the drain lightly doped drain region 4042 between the sidewall 405 and the drain region 407 on the second side of the gate structure.

In some embodiments, a metal silicide 409 is formed on the source region 406, the drain region 407, and the polysilicon gate surface.

The metal silicide 409 needs to define a formation region by using a salicide block layer, so that the first dielectric layer 408 can be formed by using a salicide block layer, that is, when forming the pattern structure of the salicide block layer, the salicide block layer on the surface of the drain end lightly doped drain 4042 between the sidewall 405 and the drain 407 of the second side of the gate structure remains and is used as the first dielectric layer 8, so that the formation region of the first dielectric layer 8 does not need to be defined separately, thereby saving the process cost. Of course, in other embodiments, the first dielectric layer 8 may not use a salicide block layer or use an overlying salicide block layer and other dielectric layers, as may be desired.

In the embodiment of the present invention, a plurality of the MOS transistors with different first pitches are integrated on the same semiconductor substrate 401 at the same time, so that a plurality of the MOS transistors with withstand voltages are integrated on the semiconductor substrate 401 at the same time.

In the various withstand voltage MOS transistors, the gate dielectric layer, the first well region 402, and the first conductivity type lightly doped drain region have the same process structure and are determined by the withstand voltage value of the MOS transistor with the lowest withstand voltage.

In some preferred embodiments, 2 MOS transistors having different first pitches are simultaneously integrated on the same semiconductor substrate 401, so that 2 voltage-withstanding MOS transistors are simultaneously integrated on the semiconductor substrate 401. The first pitch of the MOS transistor with the lowest withstand voltage is 0nm, and the effective lateral length of the drain-end lightly doped drain region 4042 is determined by the width of the sidewall 405. For example, in some embodiments, a MOS transistor that is a 2.5V IO device can be used as a standard MOS transistor, where the first pitch of the standard MOS transistor is 0nm, to achieve an operating voltage of 2.5V; on the basis of the standard MOS transistor, the 5V voltage withstand capability can be realized by only increasing the first spacing, so that the device can work at 5V voltage, for example, the device requirement of a 5V high-voltage generation module or a high-voltage transmission path is met.

In the embodiment of the present invention, the MOS transistor further includes an interlayer film 410, a contact hole 411 passing through the interlayer film 410, and electrodes formed by patterning the front metal layer, such as a source electrode, a drain electrode and a gate electrode, wherein the source electrode is connected to the source region 406 through the contact hole 411, the drain electrode is connected to the source region 407 through the contact hole 411, and the gate electrode is connected to the gate conductive material layer 403 through the contact hole 411. The interlayer film 410 is shown in fig. 5H, and the contact hole 411 is shown in fig. 4.

The MOS transistor includes an NMOS and a PMOS, and the NMOS and the PMOS are integrated on the semiconductor substrate 401 at the same time.

When the MOS transistor is the NMOS, the first conductivity type is N type, and the second conductivity type is P type.

As shown in fig. 5H, the NMOS and PMOS of the ELDD MOS transistor are simultaneously integrated on the same semiconductor substrate 401, and in fig. 5H, the region 301 is a PMOS formation region, and the region 302 is a NMOS formation region.

In the region 301, the first well region of the N type is denoted by a reference numeral 402a alone, the source region is denoted by a reference numeral 406a alone, the drain region is denoted by a reference numeral 407a alone, the source-side lightly doped drain region is denoted by a reference numeral 404a1 alone, and the drain-side lightly doped drain region 404a 2.

In the region 302, the P-type first well region is denoted by a reference numeral 402b, the source region is denoted by a reference numeral 406b, the drain region is denoted by a reference numeral 407b, the source-side lightly doped drain region is denoted by a reference numeral 404b1, and the drain-side lightly doped drain region 404b 2.

In the embodiment of the invention, the effective lateral length of the drain terminal lightly doped drain region 4042 is only required to be adjusted, and the first interval is mainly increased outside the width of the side wall 405, so that the effective lateral length of the drain terminal lightly doped drain region 4042 is adjusted by the first interval, and then the withstand voltage of the device is adjusted, and thus the withstand voltage of the device can be increased by increasing the first interval.

The thickness of the gate dielectric layer is not required to be increased, the field oxide of the drift region and the drift region is not required to be increased, and the voltage withstand capability of the device is increased, so that the growth process and the photoetching process of the gate dielectric layer are required to be increased once when the thickness of one gate dielectric layer is increased, the complexity and the cost of the process are increased, and the heat history is increased; the leakage current increases the field oxide of the drift region and the drift region, so that the process structures of the high-voltage-resistant MOS transistor and the standard MOS transistor are completely different, the complexity and the cost of the process are increased, the heat history is increased, and the area of the device is increased; the embodiment of the invention can increase the voltage resistance of the device without increasing the thickness of the gate dielectric layer and the field oxide of the drift region, so that the embodiment of the invention can reduce the complexity and the cost of the process, can not bring additional heat histories to MOS transistors with different voltage resistances, thereby stabilizing the performance of the device, reducing the area of the device and improving the compatibility of an IP module of a process platform.

As shown in fig. 5A to 5H, schematic cross-sectional structure of the device in each step of the method for manufacturing a MOS transistor according to an embodiment of the present invention; the manufacturing method of the MOS transistor comprises the following steps:

step one, a first well region 402 doped with a second conductivity type is formed in a selected region of a semiconductor substrate 401, and a gate structure formed by stacking a gate dielectric layer and a gate conductive material layer 403 is formed on the surface of the selected region of the first well region 402.

In the method of the embodiment of the present invention, the MOS transistor includes an NMOS and a PMOS, and in order to fully understand that the NMOS and the PMOS are integrated in the same semiconductor substrate 401 at the same time, fig. 5A shows a PMOS forming region, i.e., region 301, and an NMOS forming region, i.e., region 302, at the same time.

In region 301, the first well region is an N-well (nwell) and is identified by reference numeral 402a alone.

In region 302, the first well region is a P-well (P-well) and is identified by reference numeral 402b alone.

A field oxide such as shallow trench isolation 403 is also formed on the semiconductor substrate 401, and an active region is isolated on the semiconductor substrate 401 by the shallow trench isolation 403.

The gate dielectric layer comprises a gate oxide layer, and the gate oxide layer is formed by adopting a thermal oxidation process.

The gate conductive material layer 403 includes a polysilicon gate.

And secondly, carrying out lightly doped drain injection of the first conductivity type by taking the side surface of the gate structure as a self-alignment condition to form a lightly doped drain injection region, wherein the lightly doped drain injection region and the two side surfaces of the gate structure are self-aligned. In the method of the embodiment of the invention, the steps are divided into the following sub-steps:

as shown in fig. 5B, a photoresist 303 pattern structure is formed, the region 302 is opened, and then an N-type lightly doped drain implant is performed to form a lightly doped drain implant region 404B.

The photoresist 303 is then removed.

As shown in fig. 5C, a photoresist 304 pattern structure is formed, the region 301 is opened, and then a P-type lightly doped drain implant is performed to form a lightly doped drain implant region 404a.

The photoresist 304 is then removed.

Step three, as shown in fig. 5D, a sidewall 405 is formed on the first side and the second side of the gate structure by self-alignment.

Step four, forming a first graph structure; in the forming region of the MOS transistor, the first pattern structure at least covers the surface of the lightly doped drain implantation region with the width of the first space outside the sidewall 405 on the second side of the gate structure, and the region outside the first pattern structure is opened.

The first side surface of the first pattern structure is located between the side surfaces of the side walls 405 on two sides of the gate structure, the second side surface of the first pattern structure is located on the surface of the lightly doped drain injection region outside the side walls 405 on the second side surface of the gate structure, and the distance between the second side surface of the first pattern structure and the side surfaces of the side walls 405 on the second side surface of the gate structure is the first interval.

And fifthly, performing source-drain implantation of the first conductive type heavy doping by taking the first pattern structure and the gate structure as masks to form a source region 406 and the drain region 407.

The source region 406 is self-aligned with the side of the sidewall 405 on the first side of the gate structure, the junction depth of the source region 406 is greater than the junction depth of the lightly doped drain injection region, the source lightly doped drain region 4041 is formed by the lightly doped drain injection region between the source region and the first side of the gate structure, and the effective lateral length of the source lightly doped drain region 4041 is determined by the width of the sidewall 405.

The drain region 407 and the side surface of the sidewall 405 on the second side surface of the gate structure have the first interval, the junction depth of the drain region 407 is greater than the junction depth of the lightly doped drain injection region, the lightly doped drain injection region between the drain region and the second side surface of the gate structure forms a drain end lightly doped drain region 4042, and the effective lateral length of the drain end lightly doped drain region 4042 is determined by the sum of the width of the sidewall 405 and the first interval.

And step six, removing the first graph structure.

In the method of the embodiment of the invention, as NMOS and PMOS are required to be integrally manufactured, the steps four to six are required to be repeated twice, and the method comprises the following steps:

as shown in fig. 5E, a photoresist 305 pattern structure is formed by using a photolithography process, the first pattern structure of the region 302 is composed of the photoresist 305 pattern structure, in the region 302, the photoresist 305 pattern structure covers the surface of the lightly doped drain injection region 404b with the width of the first space outside the sidewall 405 of the second side surface of the gate structure, and the region outside the first pattern structure is opened; in other embodiments, the photoresist 305 pattern structure can also extend onto the top surface of the gate structure. The photoresist 305 pattern structure will completely cover the region 301.

And then, performing N-type heavily doped source-drain implantation by taking the photoresist 305 pattern structure as a mask to form a source region 406b and a drain region 407b of the NMOS. The source region 406b and the drain region 407b are formed simultaneously, and a source lightly doped drain region 4041b and a drain lightly doped drain region 4042b are formed by the lightly doped drain implant region 404b, respectively.

The photoresist 305 is then removed.

As shown in fig. 5F, a photoresist 306 pattern structure is formed by using a photolithography process, the first pattern structure of the region 301 is composed of the photoresist 306 pattern structure, in the region 301, the photoresist 306 pattern structure covers the surface of the lightly doped drain injection region 404a with the width of the first space outside the sidewall 405 of the second side surface of the gate structure, and the region outside the first pattern structure is opened; in other embodiments, the photoresist 306 pattern structure can also extend onto the top surface of the gate structure. The patterned structure of photoresist 306 will completely cover region 302.

And then P-type heavily doped source and drain implantation is carried out by taking the photoresist 306 pattern structure as a mask to form a source region 406a and a drain region 407a of the PMOS. The source region 406a and the drain region 407a are formed simultaneously, and a source lightly doped drain region 4041a and a drain lightly doped drain region 4042a are formed by the lightly doped drain implant region 404a, respectively.

The photoresist 305 is then removed.

Step seven, a first dielectric layer 408 is formed, where the first dielectric layer 408 covers the surface of the drain-end lightly doped drain 4042 located between the sidewall 405 and the drain 407 on the second side of the gate structure.

As shown in fig. 5G, in the method of the embodiment of the present invention, the first dielectric layer 408 is formed by using a patterned salicide block layer, which includes the following sub-steps:

depositing a dielectric layer of the self-aligned metal silicide blocking layer;

patterning the dielectric layer of the salicide block layer by using a photolithography definition and etching process, wherein the patterned salicide block layer forms the first dielectric layer 408, and the source region 406, the drain region 407 and the region of the polysilicon gate surface where the metal silicide 409 needs to be formed are opened.

Thereafter, a metal silicide 409 is self-aligned to the source region 406, the drain region 407, and the polysilicon gate surface.

After the front end of line (FEOL) process is completed, the following middle of line (MOL) and back end of line (BEOL) processes are also included:

as shown in fig. 5H, an interlayer film 410 is formed.

A contact hole 411 is formed through the interlayer film 401, the contact hole 411 being shown with reference to fig. 4.

A front metal layer is formed and patterned to form a source electrode, a drain electrode and a gate electrode, wherein the source electrode is connected with the source region 406 through a contact hole 411, the drain electrode is connected with the source region 407 through the contact hole 411, and the gate electrode is connected with the gate conductive material layer 403 through the contact hole 411.

In the method of the embodiment of the present invention, a plurality of the MOS transistors with different first pitches are integrated on the same semiconductor substrate 401 at the same time, so that a plurality of the MOS transistors with voltage withstanding capability are integrated on the semiconductor substrate 401 at the same time. That is, when the MOS transistor is a PMOS, a plurality of the PMOS having different first pitches can be manufactured at the same time; when the MOS transistor is an NMOS, a plurality of NMOS with different first pitches can be manufactured at the same time.

The gate dielectric layer, the first well region 402, and the first conductive type lightly doped drain region of the MOS transistor of various withstand voltages have the same process structure and are determined by the withstand voltage value of the MOS transistor having the lowest withstand voltage.

The MOS transistors with various withstand voltages share the steps one to seven;

In some preferred embodiment methods, 2 of the MOS transistors having different first pitches are simultaneously integrated on the same semiconductor substrate 401, so that 2 of the MOS transistors having withstand voltages are simultaneously integrated on the semiconductor substrate 401. The first pitch of the MOS transistor with the lowest withstand voltage is 0nm, and the effective lateral length of the drain-end lightly doped drain region 4042 is determined by the width of the sidewall 405.

The following describes the beneficial effects obtained by the method according to the embodiment of the invention with reference to the parameters:

in the first modification of the prior art corresponding to fig. 1:

a55 nm low power process is used, which has two gate oxide layers, one is the gate oxide layer of 1.2V Core NMOS or PMOS (N/PMOS) of logic device, and the thickness is aboutThe other is a gate oxide layer of an input/output (IO) N/PMOS with a thickness of about +.>Because a high voltage generating module and a high voltage transmission path of 5V are required to be introduced in the chip design, the source-drain terminal and the gate-drain terminal of the existing standard 2.5V CMOS device cannot bear 5V voltage, which can cause the breakdown and reliability problem of the device, a 5V device is required to be introduced on the original process platform, a thicker gate oxide layer except 1.2V Core and 2.5V IO is required to be additionally introduced in the 5V CMOS device, and a corresponding N well or P well (N/P W) of the 5V device is required to be introducedell) and an N-type or P-type (N/P) LDD.

Thus, when introducing a 5V device, a 5 mask process is required, and a mask having a thickness of aboutAs a gate dielectric layer of a 5V device; wherein, introduced->The gate oxide layer of (2) is a high temperature process, which introduces an extra thermal history and can shift the characteristics of other 1.2V Core devices and 2.5V IO devices, so that the existing IP cannot be reused or a process window becomes apparent.

The method comprises the following steps:

also on the same 55nm low power process platform, as described above, the process has two gate oxide devices, one is a 1.2V Core NMOS or PMOS (N/PMOS) gate oxide of a logic device, with a thickness of aboutThe other is a gate oxide layer of an input/output (IO) N/PMOS with a thickness of about +.>In order to meet the device requirements of a 5V high voltage generation module and a high voltage transmission path in chip design, the method of the embodiment of the invention adopts the gate oxide layer of the existing 2.5V IO device, and the injection of N/P Well and LDD forms a durable structure>The 5V high voltage device is characterized in that an Extended Lightly Doped Drain (ELDD) is additionally formed at the drain end.

It can be seen that the method of the embodiment of the invention does not introduce an additional gate oxide layer or any masking process, so that an additional thermal history process is not provided, the original 1.2V Core and 2.5V IO devices keep the original characteristics, and the IP compatibility or the process window are all changed.

The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims

1. A MOS transistor, comprising:

a second conductivity type doped first well region formed in a selected region of the semiconductor substrate;

the grid structure is formed on the surface of the selected area of the first well region and is formed by laminating a grid dielectric layer and a grid conductive material layer;

a source-side lightly doped drain region and a drain-side lightly doped drain region formed by a lightly doped drain region of a first conductivity type, the source-side lightly doped drain region and a first side of the gate structure being self-aligned, the drain-side lightly doped drain region and a second side of the gate structure being self-aligned;

the side walls are formed on the first side face and the second side face of the grid structure in a self-aligned mode;

a source region and a drain region formed by a source-drain injection region heavily doped with a first conductivity type, wherein the source region and a side surface of the side wall on a first side surface of the grid structure are self-aligned, the junction depth of the source region is larger than that of the source-end lightly doped drain region, and the effective transverse length of the source-end lightly doped drain region is determined by the width of the side wall;

the drain region and the side surface of the side wall on the second side surface of the grid structure are provided with a first interval, the junction depth of the drain region is larger than that of the drain end lightly doped drain region, and the effective transverse length of the drain end lightly doped drain region is determined by the sum of the width of the side wall and the first interval;

the first dielectric layer covers the surface of the drain end lightly doped drain region between the side wall of the second side face of the grid structure and the drain region;

2. The MOS transistor of claim 1, wherein: and simultaneously integrating a plurality of MOS transistors with different first pitches on the same semiconductor substrate so as to simultaneously integrate a plurality of voltage-resistant MOS transistors on the semiconductor substrate.

3. The MOS transistor of claim 2, wherein: in the various withstand voltage MOS transistors, the gate dielectric layer, the first well region and the first conductive type lightly doped drain region have the same process structure and are determined by the withstand voltage value of the MOS transistor with the lowest withstand voltage.

4. A MOS transistor as in claim 3, wherein: simultaneously integrating 2 MOS transistors with different first pitches on the same semiconductor substrate so as to simultaneously integrate 2 voltage-resistant MOS transistors on the semiconductor substrate;

5. A MOS transistor as in claim 3, wherein: the gate dielectric layer comprises a gate oxide layer; the gate conductive material layer includes a polysilicon gate.

6. The MOS transistor of claim 5, wherein: and forming metal silicide on the surfaces of the source region, the drain region and the polysilicon gate.

7. The MOS transistor of claim 6, wherein: the first dielectric layer is formed by adopting a self-aligned metal silicide blocking layer.

8. A MOS transistor according to any of claims 1 to 7, characterized in that: the MOS transistor comprises an NMOS and a PMOS, and the NMOS and the PMOS are integrated on the semiconductor substrate at the same time;

9. A method of manufacturing a MOS transistor, comprising the steps of:

step six, removing the first graph structure;

10. The method of manufacturing a MOS transistor according to claim 9, wherein: and simultaneously integrating a plurality of MOS transistors with different first pitches on the same semiconductor substrate so as to simultaneously integrate a plurality of voltage-resistant MOS transistors on the semiconductor substrate.

11. The method of manufacturing a MOS transistor according to claim 10, wherein: the gate dielectric layer, the first well region and the first conductive type lightly doped drain region of the MOS transistor have the same process structure and are determined by the voltage resistance value of the MOS transistor with the lowest voltage resistance.

12. The method of manufacturing a MOS transistor according to claim 11, wherein: the MOS transistors with various withstand voltages share the steps one to seven;

13. The method of manufacturing a MOS transistor according to claim 12, wherein: simultaneously integrating 2 MOS transistors with different first pitches on the same semiconductor substrate so as to simultaneously integrate 2 voltage-resistant MOS transistors on the semiconductor substrate;

14. The method of manufacturing a MOS transistor according to claim 11, wherein: the gate dielectric layer comprises a gate oxide layer, and the gate oxide layer is formed by adopting a thermal oxidation process; the gate conductive material layer includes a polysilicon gate.

15. The method of manufacturing a MOS transistor according to claim 14, wherein: in the seventh step, the first dielectric layer is formed by adopting a patterned self-aligned metal silicide blocking layer;

after the self-aligned metal silicide blocking layer is subjected to graphical etching, the source region, the drain region and the region on the surface of the polysilicon gate, in which metal silicide needs to be formed, are opened;