CN117650169A - Structure, manufacturing method and electronic equipment of trench gate IGBT - Google Patents
Structure, manufacturing method and electronic equipment of trench gate IGBT Download PDFInfo
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- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 4
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- 229920005591 polysilicon Polymers 0.000 claims description 3
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- 238000010586 diagram Methods 0.000 description 9
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- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
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- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
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Abstract
A trench gate IGBT structure, a manufacturing method and electronic equipment belong to the technical field of semiconductors, and comprise two bilateral symmetry sub-field effect transistor structures, wherein the symmetry tangent plane is a sagittal plane, and the sub-field effect transistor structures are as follows: the substrate, the drift layer and the first active layer are arranged from bottom to top, the grid structure is positioned on one side of the sagittal plane and penetrates through the first active layer, the distance of the emitter groove structure is away from one side of the sagittal plane by a preset distance and penetrates through the first active layer, the first active region and the second active region are positioned on the upper surface of the first active layer and between the emitter groove structure and the grid structure, and the second active region is positioned on the side face of the grid structure; the emitter trench structure is: the first trench is a preset distance away from one side of the sagittal plane and penetrates through the first active layer, the first dielectric layer covers the inner surface of the first trench, and the first conductive column is filled in the first dielectric layer; the anti-latch-up capability and the turn-off capability are enhanced.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a trench gate IGBT structure, a manufacturing method and electronic equipment.
Background
An Insulated Gate Bipolar Transistor (IGBT) is composed of a bipolar junction transistor (bipolar junction transistor, BJT) and a metal-oxide-semiconductor field-effect transistor (MOSFET), and is a voltage-controlled switching power semiconductor device.
The IGBT has the advantages of high input impedance, small control power, simple driving circuit, high switching speed and the like, and meanwhile, the IGBT has the advantages of high current density, reduced saturation voltage, high current processing capacity and the like of the bipolar power transistor.
The IGBT with a planar structure has a huge lifting space in terms of on-loss, and the IGBT with a trench gate structure may seriously weaken the latch-up resistance and turn-off capability due to hole accumulation at the bottom of the gate structure.
The related trench gate IGBT has a defect of poor latch-up resistance and turn-off resistance.
Disclosure of Invention
The invention aims to provide a structure, a manufacturing method and electronic equipment of a trench gate IGBT, and aims to solve the problem that the latch-up resistance and turn-off capability of the related trench gate IGBT are poor.
The embodiment of the application provides a trench gate IGBT structure, including two bilateral symmetry's sub-field effect tube structures, bilateral symmetry's tangent plane is sagittal, sub-field effect tube structure includes:
a substrate;
a drift layer on the upper surface of the substrate;
a first active layer located on the upper surface of the drift layer;
a gate structure located on one side of the sagittal plane and penetrating the first active layer;
an emitter trench structure which is a preset distance away from one side of the sagittal plane and penetrates through the first active layer;
a first active region and a second active region located on an upper surface of the first active layer and located between the emitter trench structure and the gate structure; the second active region is positioned on the side surface of the grid structure;
the emitter trench structure includes:
a first trench penetrating the first active layer and having a predetermined distance from a side far from the sagittal plane;
a first dielectric layer covering the inner surface of the first trench;
a first conductive pillar filled inside the first dielectric layer;
wherein the substrate, the first active layer and the first active region are of a first type; the drift layer and the second active region are of a second type.
In one embodiment, the sub-field effect transistor structure further includes:
and a buffer layer between the drift layer and the substrate.
In one embodiment, the gate structure includes:
a second trench on one side of the sagittal plane and penetrating the first active layer;
a second dielectric layer covering the inner surface of the second trench;
second conductive column filled in second dielectric layer
In one embodiment, the first type is P-type and the second type is N-type; or alternatively
The first type is N-type, and the second type is P-type.
In one embodiment, the method further comprises:
an insulating layer covering the top of the first active layer and the upper surface of the gate structure;
a first metal layer covering the insulating layer, the emitter trench structure, the first active region and the second active region;
a second metal layer located on the lower surface of the substrate;
a third metal layer connected to the gate structure;
the first metal layer is an emitter electrode of the trench gate IGBT, the second metal layer is a collector electrode of the trench gate IGBT, and the third metal layer is a gate electrode of the trench gate IGBT.
In one embodiment, the gate structure material includes silicon dioxide and polysilicon; the materials of the drift layer, the first active region and the second active region comprise silicon or silicon carbide; the material of the first dielectric layer comprises silicon dioxide; the material of the first conductive post comprises a metal.
The embodiment of the application also provides a manufacturing method of the trench gate IGBT, wherein the trench gate IGBT is bilaterally symmetrical, and a tangential plane of the bilaterally symmetrical is a sagittal plane, and the manufacturing method comprises the following steps:
forming a drift layer on the upper surface of the substrate;
forming a first active layer on the upper surface of the drift layer;
forming a first active region on the upper surface of the first active layer, and forming a second active region between the first active region and the sagittal plane;
forming a second trench on the upper surface of the first active layer and between the sagittal plane side of the second active region, and forming a first trench on the upper surface of the first active layer and between the first active region and the sagittal plane side; the first groove and the second groove penetrate through the first active layer;
forming a gate structure in the second trench and forming an emitter trench structure in the first trench; the emitter trench structure includes a first dielectric layer covering an inner surface of the first trench and a first conductive pillar filled inside the first dielectric layer.
In one embodiment, before forming the drift layer on the upper surface of the substrate, the method further includes:
forming a buffer layer on the upper surface of the substrate;
the forming the drift layer on the upper surface of the substrate specifically comprises the following steps:
and forming the drift layer on the upper surface of the buffer layer.
In one embodiment, the forming the gate structure in the second trench and the forming the emitter trench structure in the first trench further includes:
forming an insulating layer on the top of the first active layer and the upper surface of the gate structure;
forming a first metal layer on the upper surface of the insulating layer, the upper surface of the emitter trench structure, the upper surface of the first active region and the upper surface of the second active region;
forming a second metal layer on the lower surface of the substrate;
and forming a third metal layer connected with the grid structure.
The embodiment of the application also provides electronic equipment, which comprises the structure of the trench gate IGBT.
Compared with the prior art, the embodiment of the invention has the beneficial effects that: since the substrate serves as a collector, the first active layer serves as a gate, and the first active region and the second active region serve as emitters. When the channel gate IGBT is applied with forward voltage, the collector electrode and the emitter electrode are conducted; meanwhile, a first parasitic MOS (the first active layer on the sagittal plane side is a source electrode, the drift layer is a grid electrode, the first active layer on the sagittal plane side is a drain electrode), holes accumulate in the bottom of the grid electrode structure and the first active layer on the sagittal plane side when the grid electrode and the emitter electrode are conducted, so that potential rises, the first parasitic MOS is started, holes flow from the first active layer on the sagittal plane side to the emitter electrode along the drift layer and the first active layer on the sagittal plane side, the second parasitic MOS comprising the second active region, the first active layer and the drift layer is conducted, and the possibility of reducing the possibility of the reduction of the anti-latch capability and the turn-off capability of the ground due to the accumulation of the holes on the bottom of the grid electrode structure is reduced.
Drawings
In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it will be apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of a trench gate IGBT according to an embodiment of the present disclosure;
fig. 2 is another schematic structural diagram of a trench gate IGBT according to an embodiment of the present disclosure;
fig. 3 is another schematic structural diagram of a trench gate IGBT according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram illustrating formation of a drift layer in a method for manufacturing a trench gate IGBT according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of forming a first active layer in the method for manufacturing a trench gate IGBT according to the embodiment of the present application;
fig. 6 is a schematic diagram of forming a first active region and a second active region in the method for manufacturing a trench gate IGBT according to the embodiment of the present application;
fig. 7 is a schematic diagram of forming a first trench and a second trench in the method for manufacturing a trench gate IGBT according to the embodiment of the present application;
fig. 8 is a schematic diagram of forming a gate structure and an emitter trench structure in the method for manufacturing a trench gate IGBT according to the embodiment of the present application;
fig. 9 is a schematic diagram of forming a buffer layer in a method for manufacturing a trench gate IGBT according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved by the present application more clear, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the present application and simplify description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and therefore should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Fig. 1 shows the structure of the trench gate IGBT according to the embodiment of the present invention, and for convenience of explanation, only the portions related to the embodiment of the present invention are shown, and the details are as follows:
the trench gate IGBT structure comprises two bilateral symmetry sub-field effect transistor structures, wherein the bilateral symmetry tangential plane is a sagittal plane 100, and each sub-field effect transistor structure comprises a substrate 90, a drift layer 01, a first active layer 02, a gate structure 03, an emitter trench structure 04, a first active region 05 and a second active region 06.
The drift layer 01 is located on the upper surface of the substrate 90.
The first active layer 02 is located on the upper surface of the drift layer 01.
The gate structure 03 is located on the sagittal plane 100 side and penetrates the first active layer 02.
The emitter trench structure 04 is spaced apart from the sagittal plane 100 by a predetermined distance and penetrates the first active layer 02.
The first active region 05 and the second active region 06 are located on the upper surface of the first active layer 02 and between the emitter trench structure 04 and the gate structure 03. The second active region 06 is located laterally to the gate structure 03.
The emitter trench structure 04 includes, among other things, a first trench 041, a first dielectric layer 042, and a first conductive post 043.
The first trench 041 is located at a predetermined distance from the side of the sagittal plane 100 and penetrates the first active layer 02.
A first dielectric layer 042 covers the inner surface of the first trench 041.
The first conductive pillars 043 are filled inside the first dielectric layer 042.
Wherein the substrate 90, the first active layer 02 and the first active region 05 are of a first type; the drift layer 01 and the second active region 06 are of the second type.
In a specific implementation, the substrate 90 serves as a collector, the first active layer 02 serves as a gate, and the first active region 05 and the second active region 06 serve as emitters. Taking the first type as P-type and the second type as N-type as an example, when the forward voltage is applied to the channel gate IGBT, the emitter is connected with low potential, electrons sequentially pass through the emitter electrode, the second active region 06, the first active layer 02, the drift layer 01 and the substrate 90 to the collector electrode, holes sequentially pass through the collector electrode, the substrate 90, the drift layer 01, the first active layer 02 and the first active region 05 to the emitter electrode, and the collector and the emitter are conducted; meanwhile, a PMOS is formed around the emitter trench structure 04 (the first active layer 02 on the side of the sagittal plane 100 is the source, the drift layer 01 is the gate, the first active layer 02 on the side of the sagittal plane 100 is the drain), and when the collector and the emitter are turned on, holes accumulate at the bottom of the gate structure 03 and (in the first active layer 02 on the side of the sagittal plane 100), so that the potential rises and the PMOS is turned on, and the holes flow from the first active layer 02 on the side of the sagittal plane 100 along the drift layer 01, the first active layer 02 on the side of the sagittal plane 100 and the first active layer 02 on the side of the sagittal plane 100 to the emitter electrode, thereby achieving the purpose of extracting holes, and reducing the possibility of falling of the ground latch-up resistance and the turn-off capability due to hole accumulation at the bottom of the gate structure 03.
It should be emphasized that, since the emitter trench structures 04 are disposed on both sides of the gate structure 03, and thus two PMOS are connected in parallel, the possibility of serious latch-up resistance and turn-off resistance degradation due to hole accumulation at the bottom of the gate structure 03 is further reduced.
It should be noted that the first type is P-type, and the second type is N-type; or alternatively
The first type is N type and the second type is P type.
As shown in fig. 2, the sub-field effect transistor structure further comprises a buffer layer 10.
A buffer layer 10 located between the drift layer 01 and the substrate 90.
The buffer layer 10 may be of a second type and the material of the buffer layer 10 may be silicon carbide or silicon.
By providing the buffer layer 10, lattice mismatch between the substrate 90 and the drift layer 01 layer is reduced, while defects terminating part of the substrate 90 are in the buffer layer 10, avoiding defects extending to the drift layer 01.
As shown in fig. 1, the gate structure 03 includes a second trench 031, a second dielectric layer 032, and a second conductive pillar 033.
A second trench 031 on the sagittal plane 100 side and penetrating the first active layer 02.
A second dielectric layer 032 covering the inner surface of the second trench 031.
A second conductive pillar 033 filled inside the second dielectric layer 032.
The gate structure 03 is simple and reliable.
As shown in fig. 3, the structure of the trench gate IGBT further includes an insulating layer 60, a first metal layer 70, a second metal layer 80, and a third metal layer.
An insulating layer 60 covers the top of the first active layer 02 and the upper surface of the gate structure 03;
the first metal layer 70 covers the insulating layer 60, the emitter trench structure 04, the first active region 05 and the second active region 06;
the second metal layer 80 is located on the lower surface of the substrate 90.
The third metal layer is connected to the gate structure 03.
It is emphasized that the first metal layer 70 is an emitter electrode of a trench gate IGBT, the second metal layer 80 is a collector electrode of the trench gate IGBT, and the third metal layer is a gate electrode of the trench gate IGBT.
Note that the material of the gate structure 03 includes silicon dioxide and polysilicon; the materials of the drift layer 01, the first active layer 02, the first active region 05, and the second active region 06 include silicon or silicon carbide; the material of the first dielectric layer 042 includes silicon dioxide; the material of the first conductive post 043 includes a metal.
Corresponding to an embodiment of the trench gate IGBT, the invention also provides an embodiment of a method of manufacturing a trench gate IGBT.
A manufacturing method of a trench gate IGBT comprises the steps 401 to 406, wherein the trench gate IGBT is bilaterally symmetrical, and a tangential plane of the bilaterally symmetrical is a sagittal plane 100.
In step 401, as shown in fig. 4, a drift layer 01 is formed on the upper surface of a substrate 90;
the drift layer 01 is formed on the upper surface of the substrate 90 by vapor deposition or sputtering.
In step 402, as shown in fig. 5, a first active layer 02 is formed on the upper surface of the drift layer 01;
the first active layer 02 is formed on the upper surface of the drift layer 01 by vapor deposition or sputtering.
In step 403, as shown in fig. 6, a first active region 05 is formed on the upper surface of the first active layer 02, a second active region 06 is formed between the first active region 05 and the sagittal plane 100, the first active region 05 is formed on the upper surface of the first active layer 02 by ion implantation, and the second active region 06 is formed between the first active region 05 and the sagittal plane 100 by ion implantation.
In step 404, as shown in fig. 7, a second trench 031 is formed on the upper surface of the first active layer 02 and between the side of the sagittal plane 100 of the second active region 06, and a first trench 041 is formed on the upper surface of the first active layer 02 and between the side of the first active region 05 and the side away from the sagittal plane 100; the first trench 041 and the second trench 031 each penetrate the first active layer 02;
a second trench 031 is formed on the upper surface of the first active layer 02 by etching and between the side of the sagittal plane 100 of the second active region 06, and a first trench 041 is formed on the upper surface of the first active layer 02 by etching and between the side of the active region remote from the sagittal plane 100.
In step 405, as shown in fig. 8, a gate structure 03 is formed within the second trench 031 and an emitter trench structure 04 is formed within the first trench 041; the emitter trench structure 04 includes a first dielectric layer 042 covering the inner surface of the first trench 041 and a first conductive post 043 filled inside the first dielectric layer 042.
By way of example and not limitation, a second dielectric layer 032 is formed on the inner surface of the second trench 031 by vapor deposition or sputtering, and a second conductive pillar 033 is formed inside the second dielectric layer 032 by vapor deposition or sputtering to form a gate structure 03; a first dielectric layer 042 is formed on the inner surface of the first trench 041 by vapor deposition or sputtering, and a first conductive post 043 is formed inside the first dielectric layer 042 by vapor deposition or sputtering to form an emitter trench structure 04.
In particular, step 401 is preceded by step 400.
In step 400, as shown in fig. 9, a buffer layer 10 is formed on the upper surface of a substrate 90;
the buffer layer 10 is formed on the upper surface of the substrate 90 by vapor deposition or sputtering.
The formation of the drift layer 01 on the upper surface of the substrate 90 is specifically: a drift layer 01 is formed on the upper surface of the buffer layer 10.
In practice, step 405 is followed by steps 406 to 409.
In step 406, an insulating layer is formed on top of the first active layer and on top of the gate structure;
an insulating layer is formed on top of the first active layer and on top of the gate structure by epitaxy and development.
Forming a first metal layer on the insulating layer upper surface, the emitter trench structure upper surface, the first active region upper surface, and the second active region upper surface in step 407;
in step 408, forming a second metal layer on the lower surface of the substrate;
in step 409, a third metal layer is formed in connection with the gate structure.
It is worth emphasizing that the first metal layer is an emitter electrode of the trench gate IGBT, the second metal layer is a collector electrode of the trench gate IGBT, and the third metal layer is a gate electrode of the trench gate IGBT.
It is noted that the metal layer may be gold or palladium. The contacts of the respective metal layers may be ohmic contacts.
The embodiment of the invention comprises two bilateral symmetry sub-field effect tube structures, wherein the bilateral symmetry tangential planes are sagittal planes, and each sub-field effect tube structure comprises a substrate, a drift layer, a first active layer, a grid structure, an emitter groove structure, a first active region and a second active region; the drift layer is positioned on the upper surface of the substrate; the first active layer is positioned on the upper surface of the drift layer; the grid structure is positioned on one side of the sagittal plane and penetrates through the first active layer; the emitter groove structure is a preset distance away from one side of the sagittal plane and penetrates through the first active layer; the first active region and the second active region are positioned on the upper surface of the first active layer and between the emitter trench structure and the gate structure; the second active area is positioned on the side surface of the grid structure; the emitter groove structure comprises a first groove, a first dielectric layer and a first conductive column; the first groove is away from one side of the sagittal plane by a preset distance and penetrates through the first active layer; the first dielectric layer covers the inner surface of the first groove; the first conductive column is filled in the first dielectric layer; the substrate, the first active layer and the first active region are of a first type; the drift layer and the second active region are of a second type; the anti-latch-up capability and the turn-off capability are enhanced.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic of each process, and should not limit the implementation process of the embodiment of the present application in any way.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (10)
1. The utility model provides a trench gate IGBT's structure which characterized in that includes two bilateral symmetry's sub-field effect tube structures, bilateral symmetry's tangent plane is the sagittal, sub-field effect tube structure includes:
a substrate;
a drift layer on the upper surface of the substrate;
a first active layer located on the upper surface of the drift layer;
a gate structure located on one side of the sagittal plane and penetrating the first active layer;
an emitter trench structure which is a preset distance away from one side of the sagittal plane and penetrates through the first active layer;
a first active region and a second active region located on an upper surface of the first active layer and located between the emitter trench structure and the gate structure; the second active region is positioned on the side surface of the grid structure;
the emitter trench structure includes:
a first trench penetrating the first active layer and having a predetermined distance from a side far from the sagittal plane;
a first dielectric layer covering the inner surface of the first trench;
a first conductive pillar filled inside the first dielectric layer;
wherein the substrate, the first active layer and the first active region are of a first type; the drift layer and the second active region are of a second type.
2. The trench gate IGBT structure of claim 1 wherein the sub-field effect transistor structure further comprises:
and a buffer layer between the drift layer and the substrate.
3. The structure of the trench gate IGBT of claim 1 wherein the gate structure comprises:
a second trench on one side of the sagittal plane and penetrating the first active layer;
a second dielectric layer covering the inner surface of the second trench;
and the second conductive column is filled in the second dielectric layer.
4. The trench gate IGBT structure of claim 1 wherein the first type is P type and the second type is N type; or alternatively
The first type is N-type, and the second type is P-type.
5. The structure of a trench gate IGBT of claim 1 further comprising:
an insulating layer covering the top of the first active layer and the upper surface of the gate structure;
a first metal layer covering the insulating layer, the emitter trench structure, the first active region and the second active region;
a second metal layer located on the lower surface of the substrate;
a third metal layer connected to the gate structure;
the first metal layer is an emitter electrode of the trench gate IGBT, the second metal layer is a collector electrode of the trench gate IGBT, and the third metal layer is a gate electrode of the trench gate IGBT.
6. The trench gate IGBT structure of any one of claims 1 to 5 wherein the gate structure material comprises silicon dioxide and polysilicon; the materials of the drift layer, the first active region and the second active region comprise silicon or silicon carbide; the material of the first dielectric layer comprises silicon dioxide; the material of the first conductive post comprises a metal.
7. A method for manufacturing a trench gate IGBT, wherein the trench gate IGBT is bilaterally symmetrical and a tangential plane of the bilaterally symmetrical is a sagittal plane, the method comprising:
forming a drift layer on the upper surface of the substrate;
forming a first active layer on the upper surface of the drift layer;
forming a first active region on the upper surface of the first active layer, and forming a second active region between the first active region and the sagittal plane;
forming a second trench on the upper surface of the first active layer and between the sagittal plane side of the second active region, and forming a first trench on the upper surface of the first active layer and between the first active region and the sagittal plane side; the first groove and the second groove penetrate through the first active layer;
forming a gate structure in the second trench and forming an emitter trench structure in the first trench; the emitter trench structure includes a first dielectric layer covering an inner surface of the first trench and a first conductive pillar filled inside the first dielectric layer.
8. The method of manufacturing a trench gate IGBT of claim 7 wherein before forming the drift layer on the upper surface of the substrate further comprises:
forming a buffer layer on the upper surface of the substrate;
the forming the drift layer on the upper surface of the substrate specifically comprises the following steps:
and forming the drift layer on the upper surface of the buffer layer.
9. The method of manufacturing a trench gate IGBT of claim 7 wherein the forming a gate structure in the second trench and after forming an emitter trench structure in the first trench further comprises:
forming an insulating layer on the top of the first active layer and the upper surface of the gate structure;
forming a first metal layer on the upper surface of the insulating layer, the upper surface of the emitter trench structure, the upper surface of the first active region and the upper surface of the second active region;
forming a second metal layer on the lower surface of the substrate;
and forming a third metal layer connected with the grid structure.
10. An electronic device comprising the structure of the trench gate IGBT according to any one of claims 1 to 6.
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| CN115985942A (en) * | 2023-03-21 | 2023-04-18 | 晶艺半导体有限公司 | Trench gate IGBT device and manufacturing method |
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2024
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| CN111653616A (en) * | 2020-06-24 | 2020-09-11 | 程炜涛 | IGBT device structure and preparation method thereof |
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| CN115985942A (en) * | 2023-03-21 | 2023-04-18 | 晶艺半导体有限公司 | Trench gate IGBT device and manufacturing method |
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