CN117639778A - Non-binary unit capacitor C-alpha C DAC (digital-to-analog converter) applied to SAR ADC (analog-to-digital converter) and calibration method thereof - Google Patents

Abstract

The invention relates to a non-binary unit capacitor C-alpha C DAC applied to an SAR ADC and a calibration method thereof, belonging to the technical field of analog integrated circuits. The circuit comprises a sampling switch, a capacitor array, a comparator, a successive approximation control module and a digital calibration module, wherein one side of the input end of the comparator is connected with the capacitor array, the other side of the input end of the comparator is grounded, the output end of the comparator is connected with the successive approximation control module through an AND gate and an OR gate, one side of the successive approximation control module is connected with the capacitor array through the sampling switch, and the other side of the successive approximation control module is connected with the digital calibration module. The invention constructs a radix DAC circuit with high linearity using unit capacitors, so that the capacitance proportion alpha of two adjacent capacitors is less than 2:1, redundancy is generated, and the influence of capacitance mismatch is eliminated.

Description

Non-binary unit capacitor C-alpha C DAC (digital-to-analog converter) applied to SAR ADC (analog-to-digital converter) and calibration method thereof

Technical Field

The invention relates to a non-binary unit capacitor C-alpha C DAC applied to an SAR ADC and a calibration method thereof, belonging to the technical field of analog integrated circuits.

Background

The development of the integrated circuit industry has put higher index requirements on the analog-to-digital converter, and meanwhile, the continuous progress of the digital integrated circuit technology makes the design and architecture of the analog-to-digital converter capable of improving the performance by utilizing advanced technology. However, as the process supply voltage decreases and feature sizes decrease, accurate amplification of analog signals using conventional structures becomes increasingly difficult. Since the analog circuit modules in the successive approximation analog-to-digital converter are few, and the speed and the power consumption performance of the successive approximation analog-to-digital converter can be continuously improved along with the progress of the process, academic research and industrial production hot spots of the low-power consumption high-speed high-precision analog-to-digital converter have been converted from the traditional pipelined analog-to-digital converter to the successive approximation analog-to-digital converter.

The non-binary DAC can solve the problem of low quantization time utilization rate of the traditional successive approximation type digital-to-analog converter, improves the correction capability of the system on dynamic errors in the quantization process, and the traditional successive approximation type C-2C DAC has scaling capacitance of each bit, so that parasitic capacitance of all floating nodes must be considered, and the linearity of the DAC is greatly reduced. For this purpose, the present invention is proposed.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides a non-binary unit capacitor C-alpha C DAC applied to an SAR ADC and a calibration method thereof, wherein a base DAC circuit with high linearity using unit capacitors is constructed, so that the capacitance proportion alpha of two adjacent capacitors is smaller than 2:1, redundancy is generated, and the influence of capacitance mismatch is eliminated.

The technical scheme of the invention is as follows:

a non-binary unit capacitor C-alpha C DAC applied to SAR ADC comprises a sampling switch, a capacitor array, a comparator, a successive approximation control module and a digital calibration module, wherein,

one side of the input end of the comparator is connected with a capacitor array, the other side of the input end of the comparator is grounded, the output end of the comparator is connected with a successive approximation control module through an AND gate and an OR gate, one side of the successive approximation control module is connected with the capacitor array through a sampling switch, and the other side of the successive approximation control module is connected with a digital calibration module.

According to the invention, the capacitor array comprises a base convergence bit circuit and a valid bit circuit which are connected in series, wherein the base convergence bit circuit comprises a plurality of repeated structures which are connected in series, and the repeated structure at the most side is externally connected with the original unit capacitor C and parasitic capacitor p in the two circuits ₁ C, increasing the original unit capacitance C and parasitic capacitance p ₁ C is to give an initial value C in iteration ₁ Make C _n The expression of (2) holds. In order to make the capacitance matching degree higher, no new size capacitance is generated, so the original unit capacitance C and two parasitic capacitances p in two circuits are added ₁ The effective bit circuit comprises a plurality of repeated structures connected in series, the repeated structure at the most edge of the effective bit circuit is connected with a comparator, the effective bit circuit is an effective part required by a DAC function, the base convergence bit circuit converges all base numbers of the effective bit part to a constant value, the convergence part can converge to a certain base number even if parasitic capacitance exists, and the base convergence bit circuit and the effective bit circuit are formed by connecting the repeated structures in series;

the value of the base convergence bit circuit capacitance N is obtained through circuit simulation, the number of the base convergence part repeated structures is determined through N, the number of the remaining repeated structures is the number of effective bits, the number of the effective bits is matched with the DAC resolution, and the number of the repeated structures of the effective bits is the same as the DAC resolution, the DAC resolution is a bit, the number of the repeated structures of the effective bits is a bit, the number of the repeated structures of the base convergence bits is theoretically approximate to infinity, and obviously the number of the repeated structures of the base convergence bits cannot be realized in an actual circuit, so the number of the base convergence bits is determined through simulation results, the proposed DAC is compared with the linearity of an ideal non-binary DAC, and the repeated structures of the base convergence bits plus a few bits can enable the linearity of the DAC proposed by the invention to be infinitely close to the ideal non-binary DAC.

The present invention uses the same repetition structure for the significance circuit and the radix convergence bit circuit if the radix of the Least Significant Bit (LSB) is r _a Then 2 ^nd The base of the LSB is also r _a Thus, in case n is sufficiently large, C can be established _n Approximation of 2 yc.

According to a further preferred embodiment of the present invention, the repeating structure comprises a bridge capacitor 2αC and a unit capacitor C, wherein 2α is the ratio of the bridge capacitor to the unit capacitor C, and one side of the bridge capacitor 2αC is respectively connected with a top plate parasitic capacitor 2αp ₂ C and the previous repeated structure, the other side of the bridging capacitor 2αC is respectively connected with a bottom plate parasitic capacitor 2αp ₃ C and a unit capacitance C, p (i=1, 2, 3) representing the ratio of the parasitic capacitance to the design capacitance (C and 2αc), the unit capacitance C being connected to the bottom plate parasitic capacitance p ₁ C, parasitic capacitance p of the bottom plate ₁ And C is connected with a next repeated structure, a unit capacitor C of the repeated structure in the base convergence bit circuit is connected with a reference voltage Vref or grounded through a sampling switch, a unit capacitor C of the repeated structure in the effective bit circuit is connected with an input voltage Vin, the reference voltage Vref or grounded through a sampling switch, and a successive approximation control module is connected after all sampling switches are connected in series.

The analog input signal is sampled through a sampling switch, the signal is stored in a capacitor array, the voltages of two polar plates are compared through a comparator, a successive approximation control module switches the sampling switch of the capacitor array according to the output of the comparator, successive approximation comparison is carried out, a quantized value is obtained, and after the quantized value passes through a digital calibration module, the calibrated quantized value is obtained and output. The invention divides ADC into two working modes of calibration and normal conversion, the calibration mode is used for realizing digital foreground calibration to obtain the optimal weight of each bit, the normal conversion mode is used for normal sampling quantization output, and different from the normal conversion mode, the calibration mode realizes disturbance injection by changing the connection mode of a capacitance switch of a bit in a capacitance array before sampling, and quantized values of positive and negative disturbance are selected by a digital calibration module LMS, so that the optimal weight is stored for calibration output in the normal conversion mode.

According to a further preferred embodiment of the invention, the capacitance ratio α of adjacent bridge capacitances to unit capacitances is less than 2:1, the degradation of SAR ADC resolution and linearity due to degradation of DAC accuracy is suppressed.

Circuit design principle: each bit of the C-alpha-C DAC has the same base number, and the DAC is only composed of unit capacitors with a single size, and because alpha is a non-integer, two capacitors with different unit capacitors are needed on a common circuit, the total capacitance is composed of a capacitor center capacitance and a capacitor peripheral capacitance, the capacitor center capacitance is proportional to the area, the capacitor peripheral capacitance is proportional to the peripheral length, and therefore, the two capacitors with different unit capacitors are difficult to match. The circuit of the invention is composed of C and 2αC, and if α=n/2 m (n and m are natural numbers), then the unit capacitance C can be used for C and 2αC _u To represent. Compared with the traditional binary DAC, the non-binary unit capacitor C-alpha C SAR DAC used in the invention greatly reduces the total capacitance and can realize the analog-to-digital conversion with high energy efficiency ratio.

The digital calibration technology is further applied, the redundant digital codes obtained by quantization of the non-binary SAR ADC are calibrated into a relatively accurate binary capacity LMS algorithm, the complete conversion process comprises a sampling stage and a conversion stage, wherein a single SAR quantizer performs the same digitizing twice, two additional offsets +delta a and-delta a are injected, and the two additional offsets +delta a and-delta a are respectively resolved into two non-binary codes D ₊ And D _- These codes are then converted into binary codes d ₊ And d _- D if the conversion process is ideal ₊ And d _- The difference e minus 2Δd must be zero. Finally, an accurate binary capacity value W is obtained _i . The least mean square digital calibration algorithm is the statistical approximation of the steepest gradient method, the calculated amount of each iteration is small, the used storage space is also small, the digital calibration circuit is easy to realize, and the digital calibration algorithm does not occupy too large area and power consumption.

The calibration method of the non-binary unit capacitor C-alpha C DAC applied to the SAR ADC comprises the following steps of:

first, according to the circuit structure of the non-binary unit capacitor C-alpha C DAC, let C _j Deriving the total capacitance C of the radix converging part for the sum of the first j-bit capacitances of the radix converging bit circuit _n The expression of (2) is specifically:

C _P ＝p ₁ C+2α(p ₂ +p ₃ )C (1)

the recurrence of the above formulas (1) and (2) can be obtained from a circuit diagram;

wherein, C with subscript _j For sum of j-bit capacitors before base convergence bit circuit, C _n For N-bit total capacitance before the base convergence bit circuit, for the convenience of calculation, the total capacitance of a part of the repeated structure is written as C _P ，C _P The deduction formula can refer to the simplified figure 3;

using the relationship of two successive quadratic terms in the array:

is provided withSolving a binary once-through equation, if there is only one solution, then +.>For an equal-ratio array, if the equation has two solutions, then +.>Let C+C be the arithmetic progression _p ＝B；

The original may be changed as:

and (3) solving to obtain:

so that the number of the parts to be processed,is an equal-ratio array, and is obtained by recursion:>therefore (S)>This can be achieved by:

order thek＝b ² +4bαc, derived:

when n is sufficiently large, b and k are negative numbers, C _n The limit of (2) converges to a constant of 2γc, at which time the least significant bit of the DAC is expressed as:

wherein C is ₁ The total capacitance value C of the first repeating structure of the basic convergence circuit ₂ The total capacitance value of the front two-ring structure of the basic convergence circuit, q is the public ratio of the constructed equal ratio array, and gamma is the constant which is converged to the limit finally;

secondly, according to the circuit structure, assuming that a 10-bit resolution SAR ADC is needed, when the alpha value is about 1.8-1.9, a DAC with 14-bit precision is needed, the effective value of the base convergence bit circuit capacitor N is obtained at the moment, the value of N is obtained through a simulation circuit, an ideal non-binary DAC with the same parameters and a common structure is built through comparing the output analog voltages of the ideal DAC and the suggested DAC, and the circuit simulation of the DAC is compared with the circuit simulation of the DAC provided by the invention, and for convenience, an ideal amplifier is used for comparing the DAC provided by the invention with the ideal DAC, and when the output voltages are consistent between the ideal DAC and the DAC provided by the invention, the value of N can be determined;

thirdly, an LMS calibration algorithm is used for calibration, the algorithm is the statistical approximation of the steepest gradient method, the calculated amount of each iteration is small, the used storage space is small, a digital calibration circuit is easy to realize, and the area and the power consumption cost are small, specifically:

the single SAR quantizer performs twice conversion, and in order to make the digital codes of the twice conversion different, the conversion process introduces two additional offsets +Deltaa and-Deltaa, and respectively analyzes the two additional offsets into two non-binary codes D ₊ And D _- The code is then converted into a binary code d ₊ And d _- If the conversion process is ideal, e=d ₊ +d _- The 2Δd must be zero, the ideal result of the two conversions is:

the actual conversion result is:

wherein d ₊ (k)、d _- (k) A digital code representing the current time k, N being the total number of bits of the capacitance of the capacitor array, W _K A first ideal weight value W for each bit capacitance in the k capacitance array at the current moment _K ^initial For the first actual weight value of each bit capacitance in the k capacitance array at the current time, k represents the current time, x' ₊ 、x' _- The ideal conversion result of each bit capacitance of the k capacitance array at the current moment is x' ₊ 、x' _- E (k) represents the error value of two accumulated results at the current moment k, d _x For the difference of two actual results of conversion of each bit capacitance of the k capacitance array at the current moment, d _x The weight values of the digital codes of the capacitors of the corresponding different bits can be modified in the correct direction until d _x Near zero, e (k) is also near zero;

and respectively superposing disturbance signals with opposite directions on the same input signal sampled twice, respectively superposing random disturbance signals, respectively carrying out N times of cyclic processing by utilizing the input signals superposed with the disturbance signals and the random disturbance signals through N-bit capacitors in the capacitor array to finish digital-to-analog conversion, and obtaining two quantized results, wherein N is a positive integer, subtracting the two quantized results in a digital domain, and adjusting the weight value of each bit capacitor in the capacitor array by utilizing an LMS algorithm, wherein the driving error approaches to 0, thereby finishing calibration.

The invention has the beneficial effects that:

the circuit configuration of the invention can improve DAC precision and reduce the number of non-binary DAC capacitors through different replications of the same unit capacitor.

The invention uses a non-binary DAC, the output of which is nonlinear and redundant, most of one voltage corresponds to one digital code, the final code word corresponding to each input voltage quantity is separated by one LSB, and the non-binary code word output by the SAR ADC is firstly and accurately converted into a binary code word by an LMS algorithm, so that the structure is convenient to use; meanwhile, non-ideal factors such as capacitance mismatch caused by actual process deviation can be calibrated, the calculated amount of each iteration of the LMS algorithm is small, the used storage space is also small, the digital calibration circuit is easy to realize, and the large area and the power consumption are not occupied.

Drawings

FIG. 1 is a schematic diagram of a circuit structure of the present invention;

FIG. 2 is a diagram showing the overall configuration of a capacitor array according to the present invention;

FIG. 3 is a circuit diagram of a repeating structure of the present invention;

FIG. 4 is a simplified diagram of the overall configuration of the capacitor array of the present invention, where the new variable is C _P ＝p ₁ C+2α(p ₂ +p ₃ )C；C _P1 ＝2p ₁ C+2αp ₂ C；C' _P ＝p ₁ C+2αp ₃ C。

Detailed Description

The invention will now be further illustrated by way of example, but not by way of limitation, with reference to the accompanying drawings.

Example 1:

as shown in fig. 1-4, the present embodiment provides a non-binary unit capacitor C-ac DAC for use in a SAR ADC, comprising a sampling switch, a capacitor array, a comparator, a successive approximation control module, and a digital calibration module, wherein,

one side of the input end of the comparator is connected with a capacitor array, the other side of the input end of the comparator is grounded, the output end of the comparator is connected with a successive approximation control module through an AND gate and an OR gate, one side of the successive approximation control module is connected with the capacitor array through a sampling switch, and the other side of the successive approximation control module is connected with a digital calibration module. The complete circuit structure is shown in fig. 1, and parasitic capacitance is not required to be added in the actual circuit diagram, so that all parasitic capacitance is omitted in the complete circuit diagram, D is a non-binary code with redundancy, dout is a binary code after Calibration, vin is an input voltage, gnd is a ground, vref is a reference voltage, vcm is a common mode voltage, clk and clk are clock signals, calization is a digital Calibration module, and SAR logic is a successive approximation control module.

The capacitor array comprises a base convergence bit circuit and an effective bit circuit which are connected in series, wherein the base convergence bit circuit comprises a plurality of repeated structures which are connected in series, and the repeated structure at the most side is externally connected with the original unit capacitor C and parasitic capacitor p in the two circuits ₁ C, increasing the original unit capacitance C and parasitic capacitance p ₁ C is to give an initial value C in iteration ₁ Make C _n The expression of (2) holds. In order to make the capacitance matching degree higher, no new size capacitance is generated, so the original unit capacitance C and two parasitic capacitances p in two circuits are added ₁ The effective bit circuit comprises a plurality of repeated structures connected in series, the repeated structure at the most edge of the effective bit circuit is connected with a comparator, the effective bit circuit is an effective part required by a DAC function, the base convergence bit circuit converges all base numbers of the effective bit part to a constant value, the convergence part can converge to a certain base number even if parasitic capacitance exists, and the base convergence bit circuit and the effective bit circuit are formed by connecting the repeated structures in series;

the value of the base convergence bit circuit capacitance N is obtained through circuit simulation, the number of the base convergence part repeated structures is determined through N, the number of the remaining repeated structures is the number of effective bits, the number of the effective bits is matched with the DAC resolution, and the number of the repeated structures of the effective bits is the same as the DAC resolution, the DAC resolution is a bit, the number of the repeated structures of the effective bits is a bit, the number of the repeated structures of the base convergence bits is theoretically approximate to infinity, and obviously the number of the repeated structures of the base convergence bits cannot be realized in an actual circuit, so the number of the base convergence bits is determined through simulation results, the proposed DAC is compared with the linearity of an ideal non-binary DAC, and the repeated structures of the base convergence bits plus a few bits can enable the linearity of the DAC proposed by the invention to be infinitely close to the ideal non-binary DAC.

The valid bit circuit and the radix convergence bit circuit of the invention are duplicated in the same wayComplex structure, if the base of the Least Significant Bit (LSB) is r _a Then 2 ^nd The base of the LSB is also r _a Thus, in case n is sufficiently large, C can be established _n Approximation of 2 yc.

The repeated structure comprises a bridging capacitor 2 alpha C and a unit capacitor C, wherein 2 alpha is the ratio of the bridging capacitor to the unit capacitor C, and one side of the bridging capacitor 2 alpha C is respectively connected with a top plate parasitic capacitor 2 alpha p ₂ C and the previous repeated structure, the other side of the bridging capacitor 2αC is respectively connected with a bottom plate parasitic capacitor 2αp ₃ C and a unit capacitance C, p (i=1, 2, 3) representing the ratio of the parasitic capacitance to the design capacitance (C and 2αc), the unit capacitance C being connected to the bottom plate parasitic capacitance p ₁ C, parasitic capacitance p of the bottom plate ₁ And C is connected with a next repeated structure, a unit capacitor C of the repeated structure in the base convergence bit circuit is connected with a reference voltage Vref or grounded through a sampling switch, a unit capacitor C of the repeated structure in the effective bit circuit is connected with an input voltage Vin, the reference voltage Vref or grounded through a sampling switch, and a successive approximation control module is connected after all sampling switches are connected in series.

The analog input signal is sampled through a sampling switch, the signal is stored in a capacitor array, the voltages of two polar plates are compared through a comparator, a successive approximation control module switches the sampling switch of the capacitor array according to the output of the comparator, successive approximation comparison is carried out, a quantized value is obtained, and after the quantized value passes through a digital calibration module, the calibrated quantized value is obtained and output. The invention divides ADC into two working modes of calibration and normal conversion, the calibration mode is used for realizing digital foreground calibration to obtain the optimal weight of each bit, the normal conversion mode is used for normal sampling quantization output, and different from the normal conversion mode, the calibration mode realizes disturbance injection by changing the connection mode of a capacitance switch of a bit in a capacitance array before sampling, and quantized values of positive and negative disturbance are selected by a digital calibration module LMS, so that the optimal weight is stored for calibration output in the normal conversion mode.

The capacitance ratio alpha of the adjacent bridge capacitance to the unit capacitance is less than 2:1, the degradation of SAR ADC resolution and linearity due to degradation of DAC accuracy is suppressed.

Circuit design principle: each bit of the C-alpha-C DAC has the same base number, and the DAC is only composed of unit capacitors with a single size, and because alpha is a non-integer, two capacitors with different unit capacitors are needed on a common circuit, the total capacitance is composed of a capacitor center capacitance and a capacitor peripheral capacitance, the capacitor center capacitance is proportional to the area, the capacitor peripheral capacitance is proportional to the peripheral length, and therefore, the two capacitors with different unit capacitors are difficult to match. The circuit of the invention is composed of C and 2αC, and if α=n/2 m (n and m are natural numbers), then the unit capacitance C can be used for C and 2αC _u To represent. Compared with the traditional binary DAC, the non-binary unit capacitor C-alpha C SAR DAC used in the invention greatly reduces the total capacitance and can realize the analog-to-digital conversion with high energy efficiency ratio.

The digital calibration technology is further applied, the redundant digital codes obtained by quantization of the non-binary SAR ADC are calibrated into a relatively accurate binary capacity LMS algorithm, the complete conversion process comprises a sampling stage and a conversion stage, wherein a single SAR quantizer performs the same digitizing twice, two additional offsets +delta a and-delta a are injected, and the two additional offsets +delta a and-delta a are respectively resolved into two non-binary codes D ₊ And D _- These codes are then converted into binary codes d ₊ And d _- D if the conversion process is ideal ₊ And d minus 2Δd must be zero. Finally, an accurate binary capacity value W is obtained _i . The least mean square digital calibration algorithm is the statistical approximation of the steepest gradient method, the calculated amount of each iteration is small, the used storage space is also small, the digital calibration circuit is easy to realize, and the digital calibration algorithm does not occupy too large area and power consumption.

The calibration method of the non-binary unit capacitor C-alpha C DAC applied to the SAR ADC comprises the following steps of:

first, according to the circuit structure of the non-binary unit capacitor C-alpha C DAC, let C _j Deriving the total capacitance C of the radix converging part for the sum of the first j-bit capacitances of the radix converging bit circuit _n The expression of (2) is specifically:

C _P ＝p ₁ C+2α(p ₂ +p ₃ )C (1)

the recurrence of the above formulas (1) and (2) can be obtained from a circuit diagram;

wherein, C with subscript _j For sum of j-bit capacitors before base convergence bit circuit, C _n For N-bit total capacitance before the base convergence bit circuit, for the convenience of calculation, the total capacitance of a part of the repeated structure is written as C _P ，C _P The deduction formula can refer to the simplified figure 3;

using the relationship of two successive quadratic terms in the array:

is provided withSolving a binary once-through equation, if there is only one solution, then +.>For an equal-ratio array, if the equation has two solutions, then +.>Let C+C be the arithmetic progression _p ＝B；

The original may be changed as:

and (3) solving to obtain:

so that the number of the parts to be processed,is an equal-ratio array, and is obtained by recursion:>therefore (S)>This can be achieved by:

order thek＝b ² +4bαc, derived:

when n is sufficiently large, b and k are negative numbers, C _n The limit of (2) converges to a constant of 2γc, at which time the least significant bit of the DAC is expressed as:

wherein C is ₁ The total capacitance value C of the first repeating structure of the basic convergence circuit ₂ The total capacitance value of the front two-ring structure of the basic convergence circuit, q is the public ratio of the constructed equal ratio array, and gamma is the constant which is converged to the limit finally;

secondly, according to the circuit structure, assuming that a binary DAC with 10-bit resolution is needed, when the alpha value is about 1.8-1.9, a non-binary DAC with 14-bit precision is needed, the effective value of the base convergence bit circuit capacitor N is obtained through circuit simulation, an ideal non-binary DAC with the same parameters and a common structure is built through comparison of the output analog voltage of an ideal DAC and a suggested DAC, and the circuit simulation of the DAC is compared with the circuit simulation of the DAC provided by the invention, in order to conveniently compare the DAC provided by the invention with the ideal DAC, an ideal amplifier is used, and when the output voltage is consistent between the ideal DAC and the DAC provided by the invention, the value of N can be determined;

thirdly, an LMS calibration algorithm is used for calibration, the algorithm is the statistical approximation of the steepest gradient method, the calculated amount of each iteration is small, the used storage space is small, a digital calibration circuit is easy to realize, and the area and the power consumption cost are small, specifically:

the single SAR quantizer performs twice conversion, and in order to make the digital codes of the twice conversion different, the conversion process introduces two additional offsets +Deltaa and-Deltaa, and respectively analyzes the two additional offsets into two non-binary codes D ₊ And D _- The code is then converted into a binary code d ₊ And d _- If the conversion process is ideal, e=d ₊ +d _- The 2Δd must be zero, the ideal result of the two conversions is:

the actual conversion result is:

wherein,d ₊ (k)、d _- (k) A digital code representing the current time k, N being the total number of bits of the capacitance of the capacitor array, W _K A first ideal weight value W for each bit capacitance in the k capacitance array at the current moment _K ^initial For the first actual weight value of each bit capacitance in the k capacitance array at the current time, k represents the current time, x' ₊ 、x' _- The ideal conversion result of each bit capacitance of the k capacitance array at the current moment is x' ₊ 、x' _- E (k) represents the error value of two accumulated results at the current moment k, d _x For the difference of two actual results of conversion of each bit capacitance of the k capacitance array at the current moment, d _x The weight values of the digital codes of the capacitors of the corresponding different bits can be modified in the correct direction until d _x Near zero, e (k) is also near zero;

and respectively superposing disturbance signals with opposite directions on the same input signal sampled twice, respectively superposing random disturbance signals, respectively carrying out N times of cyclic processing by utilizing the input signals superposed with the disturbance signals and the random disturbance signals through N-bit capacitors in the capacitor array to finish digital-to-analog conversion, and obtaining two quantized results, wherein N is a positive integer, subtracting the two quantized results in a digital domain, and adjusting the weight value of each bit capacitor in the capacitor array by utilizing an LMS algorithm, wherein the driving error approaches to 0, thereby finishing calibration.

The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (5)

1. A non-binary unit capacitor C-alpha C DAC applied to SAR ADC is characterized by comprising a sampling switch, a capacitor array, a comparator, a successive approximation control module and a digital calibration module, wherein,

one side of the input end of the comparator is connected with a capacitor array, the other side of the input end of the comparator is grounded, the output end of the comparator is connected with a successive approximation control module through an AND gate and an OR gate, one side of the successive approximation control module is connected with the capacitor array through a sampling switch, and the other side of the successive approximation control module is connected with a digital calibration module.

2. The non-binary unit capacitor C-alpha C DAC for SAR ADC as set forth in claim 1, wherein the capacitor array comprises a radix converging bit circuit and a valid bit circuit connected in series, the radix converging bit circuit comprises a plurality of series repeating structures, and the unit capacitor C and the parasitic capacitor p are connected outside the repeating structure at the most side ₁ And C, the valid bit circuit comprises a plurality of repeated structures connected in series, and the repeated structure at the most edge of the valid bit circuit is connected with a comparator.

3. The non-binary unit capacitor C- αC DAC for SAR ADC as set forth in claim 2, wherein the repeating structure comprises a bridge capacitor 2αC and a unit capacitor C,2α is the ratio of the bridge capacitor to the unit capacitor C, and a top plate parasitic capacitor 2αp is connected to one side of the bridge capacitor 2αC ₂ C and the previous repeated structure, the other side of the bridging capacitor 2αC is respectively connected with a bottom plate parasitic capacitor 2αp ₃ C and a unit capacitor C connected with a bottom plate parasitic capacitor p ₁ C, parasitic capacitance p of the bottom plate ₁ And C is connected with a next repeated structure, a unit capacitor C of the repeated structure in the base convergence bit circuit is connected with a reference voltage Vref or grounded through a sampling switch, a unit capacitor C of the repeated structure in the effective bit circuit is connected with an input voltage Vin, the reference voltage Vref or grounded through a sampling switch, and a successive approximation control module is connected after all sampling switches are connected in series.

4. The non-binary unit capacitance C-ac DAC for use in SAR ADC of claim 3, wherein the capacitance ratio α of adjacent bridge capacitance to unit capacitance is less than 2:1.

5. the method for calibrating a non-binary unit capacitor C-oc DAC for use in a SAR ADC according to claim 4, comprising the steps of:

first, according to the circuit structure of the non-binary unit capacitor C-alpha C DAC, let C _j Deriving the total capacitance C of the radix converging part for the sum of the first j-bit capacitances of the radix converging bit circuit _n The expression of (2) is specifically:

C _P ＝p ₁ C+2α(p ₂ +p ₃ )C (1)

wherein, C with subscript _j For sum of j-bit capacitors before base convergence bit circuit, C _n The front N-bit total capacitance of the base convergence bit circuit;

using the relationship of two successive quadratic terms in the array:

is provided withSolving a binary once-through equation, if there is only one solution, then +.>For an equal-ratio array, if the equation has two solutions, then +.>Let C+C be the arithmetic progression _p ＝B；

The original may be changed as:

and (3) solving to obtain:

so that the number of the parts to be processed,is an equal-ratio array, and is obtained by recursion:>therefore (S)>This can be achieved by:

order thek＝b ² +4bαc, derived:

when n is sufficiently large, b and k are negative numbers, C _n The limit of (2) converges to a constant of 2γc, at which time the least significant bit of the DAC is expressed as:

wherein C is ₁ The total capacitance value C of the first repeating structure of the basic convergence circuit ₂ The total capacitance value of the front two-ring structure of the basic convergence circuit, q is the public ratio of the constructed equal ratio array, and gamma is the constant which is converged to the limit finally;

secondly, according to the circuit structure, assuming that a 10-bit resolution SAR ADC is required, and a DAC with 14-bit precision is required when the alpha value is about 1.8-1.9, the effective value of the base convergence bit circuit capacitor N is obtained at the moment, and the value of N is obtained through a simulation circuit;

thirdly, calibrating by using an LMS calibration algorithm, wherein the method specifically comprises the following steps:

the single SAR quantizer performs twice conversion, and in order to make the digital codes of the twice conversion different, the conversion process introduces two additional offsets +Deltaa and-Deltaa, and respectively analyzes the two additional offsets into two non-binary codes D ₊ And D _- The code is then converted into a binary code d ₊ And d _- If the conversion process is ideal, e=d ₊ +d _- The 2Δd must be zero, the ideal result of the two conversions is:

the actual conversion result is:

wherein d ₊ (k)、d _- (k) A digital code representing the current time k, N being the total number of bits of the capacitance of the capacitor array, W _K A first ideal weight value W for each bit capacitance in the k capacitance array at the current moment _K ^initial For the first actual weight value of each bit capacitance in the k capacitance array at the current time, k represents the current time, x' ₊ 、x' _- The ideal conversion result of each bit capacitance of the k capacitance array at the current moment is x' ₊ 、x' _- E (k) represents the error value of two accumulated results at the current moment k, d _x For the difference of two actual results of conversion of each bit capacitance of the k capacitance array at the current moment, d _x The weight values of the digital codes of the capacitors of the corresponding different bits can be modified in the correct direction until d _x Near zero, e (k) is also near zero;

and respectively superposing disturbance signals with opposite directions on the same input signal sampled twice, respectively superposing random disturbance signals, respectively carrying out N times of cyclic processing by utilizing the input signals superposed with the disturbance signals and the random disturbance signals through N-bit capacitors in the capacitor array to finish digital-to-analog conversion, and obtaining two quantized results, wherein N is a positive integer, subtracting the two quantized results in a digital domain, and adjusting the weight value of each bit capacitor in the capacitor array by utilizing an LMS algorithm, wherein the driving error approaches to 0, thereby finishing calibration.