CN117639084A - Carrier synchronization method and device for parallel connection of multiple inverters - Google Patents

Abstract

The application discloses a carrier synchronization method and device for parallel connection of multiple inverters, which are applied to the field of new energy. In the method, a plurality of inverters are connected in parallel to supply power to a load, and the duty ratio of duty ratio signals of the inverters is more than 50%; the logic processing unit obtains the duty ratio signals of the inverters, and then performs AND operation on the duty ratio signals to generate the synchronous signals, so that the normal generation of the synchronous signals can be ensured even if part of the inverters have faults. After the synchronization signal is sent to the inverters, each inverter can realize carrier synchronization according to the synchronization signal. According to the scheme, master-slave distinction does not exist among the inverters, each inverter can serve as a source of a synchronizing signal, the inverters are redundant, reliability of a carrier synchronizing mode is improved, an additional CPU (central processing unit) is not needed to serve as a synchronizing signal source, and carrier synchronization of other inverters is guaranteed when abnormality occurs to part of the inverters.

Description

Carrier synchronization method and device for parallel connection of multiple inverters

Technical Field

The application relates to the field of new energy, in particular to a carrier synchronization method and device for parallel connection of multiple inverters.

Background

The most important equipment in the micro-grid is an inverter, and due to the increase of the electricity consumption of people, the single inverter cannot meet the requirement of the electricity consumption in most application scenes. The parallel operation of the inverters can improve the power output and the output power, and can well meet the increasing power requirements of people. However, since the power distribution accuracy and the current circulation are affected by the differences in factors such as equivalent output impedance, transmission line impedance, carrier non-synchronization and the like when the inverters are connected in parallel, carrier synchronization of a plurality of inverters is required. At present, carrier synchronization of each inverter is realized by obtaining a synchronization signal through a duty cycle signal of each inverter, specifically, one master inverter and a plurality of slave inverters are arranged, the synchronization signal is mainly obtained by depending on the duty cycle signal of the master inverter, and the rest slave inverters realize synchronization by tracking the synchronization signal.

However, in the current scheme, priority division needs to be performed on each inverter to distinguish the master and slave machines, and when the master machine fails, a synchronization signal cannot be generated, so that each inverter cannot realize carrier synchronization.

Therefore, how to ensure that all other inverters realize carrier synchronization when part of the inverters are abnormal is a problem to be solved urgently by those skilled in the art.

Disclosure of Invention

The purpose of the application is to provide a carrier synchronization method and device for parallel connection of multiple inverters, so that carrier synchronization of all other inverters is still guaranteed when abnormality occurs to part of the inverters.

In order to solve the above technical problems, the present application provides a carrier synchronization method for parallel connection of multiple inverters, including:

acquiring a duty ratio signal of each inverter; wherein the duty cycle of the duty cycle signal of each of the inverters is greater than 50%;

performing AND operation on the duty ratio signal of the inverter which normally works to generate a synchronous signal;

and sending the synchronizing signal to the inverter so that the inverter realizes carrier synchronization according to the synchronizing signal.

Preferably, before the performing an and operation on the duty cycle signal of the inverter that operates normally to generate a synchronization signal, the method further includes:

filtering the abnormal disconnection of the inverter;

said ANDed said duty cycle signal of said inverter operating normally to generate a synchronization signal comprises:

and performing AND operation on the duty ratio signals of the rest inverters to generate the synchronous signals.

Preferably, the inverter for filtering abnormal dropped lines includes:

and filtering the inverter in which the duty ratio signal is not in the over-high level state within the preset time.

Preferably, the inverter implementing carrier synchronization according to the synchronization signal includes:

according to the value of the CAP time mark register, the phase difference between the self carrier wave and the synchronous signal is obtained;

determining the change direction of the phase difference according to the change trend of the phase difference;

calculating an adjustment count value required by the current carrier according to the phase difference and the change direction;

and periodically loading the adjustment count value into a carrier time base count register to realize the synchronization of the carrier of each inverter and the synchronization signal.

Preferably, after calculating the adjustment count value required by the current carrier according to the phase difference and the change direction, the method further includes:

and carrying out numerical clipping on the adjusted count value.

Preferably, after calculating the adjustment count value required by the current carrier according to the phase difference and the change direction, the method further includes:

and carrying out numerical identification and fault signal rejection on the adjusted count value.

Preferably, the logic processing unit that acquires the duty cycle signal to generate the synchronization signal includes a plurality of CPLD synchronization signal processing circuits to acquire the duty cycle signal and generate a plurality of the synchronization signals, respectively.

Preferably, the CPLD synchronous signal processing circuit is connected with the inverter through an optical coupling isolation circuit and a low-pass filter circuit.

In order to solve the above technical problem, the present application further provides a carrier synchronization device with multiple inverters connected in parallel, including:

the acquisition module is used for acquiring the duty ratio signals of the inverters; wherein the duty cycle of the duty cycle signal of each of the inverters is greater than 50%;

the generating module is used for performing AND operation on the duty ratio signal of the inverter which normally works so as to generate a synchronous signal;

and the transmitting module is used for transmitting the synchronizing signal to the inverter so that the inverter can realize carrier synchronization according to the synchronizing signal.

Preferably, the carrier synchronization device with multiple parallel inverters further includes: the filtering module is used for filtering the inverter which is abnormally disconnected before performing AND operation on the duty ratio signal of the inverter which works normally to generate a synchronous signal; said ANDed said duty cycle signal of said inverter operating normally to generate a synchronization signal comprises: and performing AND operation on the duty ratio signals of the rest inverters to generate the synchronous signals.

Preferably, the carrier synchronization device with multiple parallel inverters further includes: and the amplitude limiting module is used for carrying out numerical amplitude limiting on the adjustment count value required by the current carrier after calculating the adjustment count value according to the phase difference and the change direction.

Preferably, the carrier synchronization device with multiple parallel inverters further includes: and the identification and rejection module is used for carrying out numerical identification and fault signal rejection on the adjustment count value required by the current carrier after calculating the adjustment count value according to the phase difference and the change direction.

In order to solve the above technical problem, the present application further provides a carrier synchronization device with multiple inverters connected in parallel, including: a memory for storing a computer program;

and the processor is used for realizing the carrier synchronization method of the parallel connection of the multiple inverters when executing the computer program.

In order to solve the above technical problem, the present application further provides a computer readable storage medium, where a computer program is stored on the computer readable storage medium, and the computer program when executed by a processor implements the steps of the carrier synchronization method for parallel connection of multiple inverters.

According to the carrier synchronization method for parallel connection of the multiple inverters, the multiple inverters are connected in parallel to supply power for a load, wherein the duty ratio of duty ratio signals of the inverters is greater than 50%; the logic processing unit obtains duty ratio signals of the inverters working normally, and then performs AND operation on the duty ratio signals to generate synchronous signals, so that the normal generation of the synchronous signals can be ensured even if part of the inverters fail. After the synchronization signal is sent to the inverters, each inverter can realize carrier synchronization according to the synchronization signal. According to the scheme, master-slave distinction does not exist among the inverters, each inverter can serve as a source of a synchronizing signal, the inverters are redundant, reliability of a carrier synchronizing mode is improved, an additional CPU (central processing unit) is not needed to serve as a synchronizing signal source, and carrier synchronization of other inverters is guaranteed when abnormality occurs to part of the inverters.

The application also provides a carrier synchronization device and a computer readable storage medium with multiple inverters connected in parallel, which correspond to the method, and have the same beneficial effects as the method.

Drawings

For a clearer description of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flowchart of a carrier synchronization method for parallel connection of multiple inverters according to an embodiment of the present application;

fig. 2 is a simplified diagram of a parallel structure of multiple inverters according to an embodiment of the present application;

fig. 3 is a control block diagram of a carrier synchronous redundant system according to an embodiment of the present application;

fig. 4 is a timing chart of generating synchronization signals of all online of the 3 inverters provided in the embodiment of the present application;

fig. 5 is a timing chart of generating a synchronization signal of an inverter with a dropped line according to an embodiment of the present application;

fig. 6 is a flowchart of a carrier synchronization implementation provided in an embodiment of the present application;

fig. 7 is a schematic diagram of a phase difference between a carrier and a synchronization signal before synchronization according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram of a phase difference after carrier synchronization with a synchronization signal according to an embodiment of the present disclosure;

fig. 9 is a control block diagram of another carrier synchronous redundant system according to an embodiment of the present application;

fig. 10 is a block diagram of a carrier synchronization device with multiple inverters connected in parallel according to an embodiment of the present application;

fig. 11 is a block diagram of a carrier synchronization device with multiple parallel inverters according to another embodiment of the present application.

Detailed Description

The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments herein without making any inventive effort are intended to fall within the scope of the present application.

The core of the application is to provide a carrier synchronization method and device for parallel connection of multiple inverters, so that carrier synchronization of all other inverters is still ensured when abnormality occurs to part of the inverters.

In order to provide a better understanding of the present application, those skilled in the art will now make further details of the present application with reference to the drawings and detailed description.

The global multilateral effort to cope with climate change is never stopped, and the major trend of green low carbon transformation is irreversible. Under the aim of 'double carbon', the traditional power generation mode is gradually replaced by new energy power supply, and at present, the new energy mainly comprises wind energy and solar energy, the new energy is zero-pollution and endless, but the collection and utilization places of the new energy are scattered, so that the technology of the micro-grid is greatly developed. The most important equipment in the micro-grid is an inverter, and due to the increase of the electricity consumption of people, the single inverter cannot meet the requirement of the electricity consumption in most application scenes. The parallel operation of the inverters can improve the power output and the output power, and can well meet the increasing power requirements of people. However, the power distribution accuracy and the current circulation are affected by the differences of the equivalent output impedance, the impedance of the transmission line, the carrier wave asynchronism and other factors when the inverters are connected in parallel. The present application is mainly directed to solving the high frequency loop current caused by the carrier wave dyssynchrony of the inverter.

Fig. 1 is a flowchart of a carrier synchronization method for parallel connection of multiple inverters according to an embodiment of the present application; as shown in fig. 1, the method comprises the steps of:

s10: the duty cycle signal of each inverter is acquired.

Fig. 2 is a simplified diagram of a parallel structure of multiple inverters according to an embodiment of the present application; in fig. 2, the inverter is a three-phase four-wire system T-type three-level inverter, the filter adopts an LCL type filtering structure (in which L2 is small and the effect of suppressing high frequency components is limited), when the three-phase inverters based on the LCL filter are connected in parallel, when the inductance of L2 is small, the line damping is also small and the suppression of high frequency components is limited, so that the high frequency loop current of the switching frequency needs to be suppressed by directly adopting a carrier synchronization mode. Each inverter R, S, T, N is wired in parallel to the PCC points forming a common ac bus and then supplying power to the load. In practical application, the duty ratio signals of the inverters are required to be obtained, then a synchronizing signal is generated according to the duty ratio signals, and finally carrier synchronization of the inverters is realized according to the synchronizing signal; the duty ratio modulation modes mainly include the following three modes: pulse width modulation (Pulse Width Modulation, PWM), pulse frequency modulation (Pulse Frequency Modulation, PFM) and pulse cross-period modulation mode (Pulse Skip Modulation, PSM). Fig. 3 is a control block diagram of a carrier synchronous redundant system according to an embodiment of the present application; as shown in fig. 3, the logic processing unit 1 is connected to each inverter, respectively, for generating a synchronization signal according to the duty cycle signal. The configuration in fig. 3 is only one example provided in the embodiment of the present application, and the logic processing unit 1 may generate only one synchronization signal, and a plurality of synchronization signal processing circuits may also be included in the logic processing unit 1 to obtain the duty cycle signals respectively to generate a plurality of synchronization signals. Wherein the duty cycle of the duty cycle signal of each inverter needs to be set to be greater than 50%.

S11: the duty cycle signal of the normally operating inverter is ANDed to generate a synchronization signal.

In the implementation, only the duty ratio signal of the inverter which works normally is taken and calculated to generate the synchronous signal, and the duty ratio signal is taken as a PWM wave signal as an example, 3 inverters are connected in parallel, and the 3 inverters work normally. The specific generation process is as follows: the 3 inverters respectively send PWM duty ratio signals c1, c2 and c3 with different initial phases and switching periods. To ensure that the synchronization signal can be generated, the duty cycle of the duty cycle signal sent by each inverter needs to be more than 50%. Fig. 4 is a timing chart of generating synchronization signals of all online of the 3 inverters provided in the embodiment of the present application; as shown in fig. 4, PWM duty cycle signals c1, c2 and c3 undergo a logical processing unit to perform an and operation, so as to obtain a generated synchronization signal. Since the periods of c1, c2 and c3 are the same and the duty ratio is more than 50%, the duty ratio of the generated synchronizing signal can be ensured to be more than 0%, namely, the synchronizing signal can be normally generated. Fig. 5 is a timing chart of generating a synchronization signal of an inverter with a dropped line according to an embodiment of the present application; as shown in fig. 5, 1 inverter out of the 3 inverters is accidentally disconnected. When 1 inverter (for example, the inverter corresponding to c 1) in the 3 inverters breaks down the output relay due to the conditions of module failure and the like and unexpected disconnection occurs, the rest duty ratio signals c2 and c3 continue to complete the operation of taking AND through the logic processing unit and normally generate the synchronous signal, and the synchronous signal in fig. 5 is changed compared with the synchronous signal in fig. 4. In fig. 5, the newly added portion in one switching period is a portion in which the duty ratio changes after the first inverter is accidentally disconnected. The only difference between the normal operation of the 3 inverters and the occurrence of the disconnection of one inverter is that the duty ratio of the synchronous signal generated after the disconnection of one inverter is possibly larger than the duty ratio of the synchronous signal when three inverters are all on line. When the N inverters are connected in parallel, the method for generating the synchronization signal is identical to the above. Further, it can be seen that the duty ratio relationship of the synchronization signals of the plurality of inverters is as follows:

D_((N))≤D_((N-1))……≤D_((2))≤D_((1))

wherein, D is the duty ratio, N represents the number of inverters which do not fall off in normal operation, namely, the more the number of the inverters which fall off, the larger the duty ratio.

S12: the synchronization signal is sent to the inverter so that the inverter achieves carrier synchronization according to the synchronization signal.

Finally, the synchronizing signal is sent to an inverter, and after the inverter obtains the synchronizing signal, the inverter can obtain the phase difference between the self carrier wave and the synchronizing signal according to the value of the CAP time mark register; determining the change direction of the phase difference according to the change trend of the phase difference; calculating an adjustment count value required by the current carrier according to the phase difference and the change direction; and finally, periodically loading the adjusted count value into a carrier time base count register to realize the synchronization of the carrier and the synchronizing signals of the inverters. In other embodiments, the value recognition, the value clipping and the fault signal eliminating process can be added to the adjusted count value, so that the condition of inverter shutdown is avoided.

In the parallel control of each inverter in this embodiment, a virtual synchronous machine is used, and if the resistance component is greater than the inductance component in each inverter output line, coupling exists between the active power and the reactive power output by the inverter. Therefore, virtual impedance of the L2 side is increased in basic control, the resistance-inductance ratio in a circuit can be improved, and the problem of power circulation is solved. The method and the device solve the problem that the switching frequency secondary circulation exists due to carrier wave asynchronization among a plurality of inverters. In this embodiment, the period of the synchronization signal is consistent with the switching period of the inverter, so as to ensure that the switching frequencies before and after carrier synchronization are consistent, and the carriers of the plurality of inverters are all in carrier synchronization with the synchronization signal. Once the synchronous signal is faulty, carrier synchronization will be invalid when a plurality of inverters are connected in parallel, which may cause the inverter to have overcurrent fault and affect the service life of the machine, and in order to ensure that the synchronous signal can be normally generated, the duty ratio of the duty ratio signal sent by each inverter needs to be more than 50%. According to the embodiment of the application, the inverters are not different from each other, the source of the synchronous signal is not single, the redundancy design is increased, the synchronous signal cannot be influenced by accidental disconnection of part of the inverters, and the reliability and the stability of the system are ensured. The scheme does not need to complete carrier synchronization in a mode similar to the communication of a controller area network (Controller Area Network, CAN), is simple in implementation mode, and reduces the influence of communication delay and the like.

According to the carrier synchronization method for the parallel connection of the multiple inverters, the multiple inverters are connected in parallel to supply power for a load, wherein the duty ratio of duty ratio signals of the inverters is greater than 50%; the logic processing unit obtains duty ratio signals of the inverters working normally, and then performs AND operation on the duty ratio signals to generate synchronous signals, so that the normal generation of the synchronous signals can be ensured even if part of the inverters fail. After the synchronization signal is sent to the inverters, each inverter can realize carrier synchronization according to the synchronization signal. According to the scheme provided by the embodiment of the application, master-slave distinction does not exist among the inverters, each inverter can be used as a source of a synchronizing signal, the inverters are mutually redundant, the reliability of a carrier synchronizing mode is improved, an additional CPU (central processing unit) is not needed to be used as a synchronizing signal source, and carrier synchronization of other inverters is still guaranteed when part of the inverters are abnormal.

The above embodiment mentions that, in implementation, only the duty cycle signal of the inverter that works normally needs to be taken and operated, and before the duty cycle signal of the inverter that works normally is taken and operated to generate the synchronization signal, the method further includes: an inverter for filtering abnormal disconnection; anding the duty cycle signal of the normally operating inverter to generate a synchronization signal includes: and performing AND operation on the duty ratio signals of the rest inverters to generate a synchronous signal. If the duty ratio signal of the inverter is not in the excessively high level state in the preset time, the corresponding abnormal disconnection of the inverter is judged, and the abnormal disconnection of the inverter is required to be filtered.

Taking 3 inverters as an example, when 1 inverter in the 3 inverters breaks down an output relay due to the conditions of module faults and the like and unexpected disconnection occurs, a logic processing unit receives a duty ratio signal sent by the inverter, and when a high level is not received for a period of time, the current duty ratio signal is judged to be invalid, the corresponding inverter is judged to be abnormally disconnected, and the normal input duty ratio signals of the other 2 inverters are processed. The rest duty ratio signals c2 and c3 continue to complete the AND operation through the logic processing unit, and a synchronous signal is normally generated. The only difference is that the duty cycle of the synchronous signal generated after one inverter is disconnected may be larger than the duty cycle of the synchronous signal when three inverters are all on line.

The inverter implementing carrier synchronization according to the synchronization signal includes: according to the value of the CAP time mark register, the phase difference between the self carrier wave and the synchronous signal is obtained; determining a change direction (increase or decrease) of the phase difference according to a trend of the phase difference change; calculating an adjustment count value required by the current carrier according to the phase difference and the change direction; and periodically loading the adjustment count value into a carrier time base count register to realize the synchronization of the carrier and the synchronizing signals of the inverters. In the carrier synchronization process, when the duty ratio changes drastically, the waveform output by the modulated wave is instantaneously distorted and the output current flows. When the inverter is accidentally disconnected, the duty ratio of the synchronous signal is suddenly changed, and the modulated waves are basically consistent before and after the sudden change of the duty ratio, and the sudden change of the carrier phase can cause sudden change of the instantaneous value of the output voltage, so that frequent inversion overcurrent and even frying are caused. Therefore, in the solution provided in this embodiment, after calculating the adjustment count value required by the current carrier according to the phase difference and the change direction, the method further includes: and carrying out numerical clipping on the adjusted count value, thereby avoiding the occurrence of shutdown of the inverter. In addition, after the adjustment count value needed by the current carrier is calculated according to the phase difference and the change direction, the adjustment count value can be subjected to numerical identification and fault signal rejection. The synchronous process increases the numerical recognition, numerical clipping and fault signal rejection, and avoids the situation that when the synchronous signal is suddenly changed, the modulated output is instantaneously distorted and the inversion is over-current due to the sudden change of the adjusted count value of the carrier, and even the inverter is stopped. The following describes embodiments of the present application in detail with reference to the drawings.

Fig. 6 is a flowchart of a carrier synchronization implementation provided in an embodiment of the present application; as shown in fig. 6, the method comprises the following steps: s20: and acquiring the synchronous signals, and obtaining the phase difference between the respective carrier wave and the synchronous reference signals according to the value of the CAP time mark register. S21: the direction in which the phase difference increases or decreases is determined by the tendency of the phase difference change. S22: in the phase difference increasing (or decreasing) direction, an adjustment count value required for the current carrier is calculated based on the phase difference. S23: and carrying out numerical identification, numerical limiting and fault signal rejection on the calculated adjustment count value, so as to avoid misoperation. S24: and periodically loading the adjusted count value into a carrier time base count register to realize the synchronization of each inverter carrier and the synchronizing signal. Fig. 6 shows an example of the embodiment, and is not limited to other embodiments of the present application. And each inverter acquires a synchronous signal in the power-on self-checking stage, and each inverter equivalently obtains the phase difference between each carrier and a synchronous reference signal according to the value of the pulse capturing unit time mark register. Fig. 7 is a schematic diagram of a phase difference between a carrier and a synchronization signal before synchronization according to an embodiment of the present disclosure; as shown in fig. 7, since the carrier phase angle difference varies from 0 ° to 180 ° and 180 ° to 360 ° (360 ° represents resynchronization), the phase difference corresponding to the inverter carrier and the synchronization signal appears as a process of varying from small to large and then from large to small. The direction in which the phase difference increases or decreases is determined by the trend of the phase difference change, and the adjustment count value of the carrier can be compensated in one direction. And selecting to calculate an adjustment count value required by each inverter PWM module carrier based on the phase difference in the direction of reducing the phase difference.

This implementation resembles a proportional regulator, since the final goal is to reduce the trim count value to approximately 0, but requires a significant determination of the regulator input during the process. Firstly, numerical recognition is carried out, namely, range screening is needed to be carried out on the input value of the regulator based on a threshold value, for example, when abnormal connection of the synchronous signals occurs, the input value of the regulator can be presented as an abnormal disturbance value which obviously exceeds the threshold value, and the abnormal value can be removed through the range screening. And secondly, further performing fault signal rejection, namely selecting n continuous regulator input values, reasonably selecting n aiming at the occurrence probability of abnormal values, sliding to obtain the average value of the n numbers, further screening the values in a reasonable range near the average value based on the average value, and sacrificing a small part of effective values to obtain the stability.

Further, in order to avoid oscillation caused by overlarge change of the adjustment count value when the carrier wave phase difference is larger, the output of the regulator needs to be subjected to numerical amplitude limiting, so that slight adjustment is ensured each time, and the intensity of the change of the output adjustment count value is reduced (carrier wave synchronization is started after each inverter is powered on and self-inspected before inversion occurs, and the carrier wave adjustment speed is not required to be too high). Finally, the adjusted count value is periodically loaded into a carrier time base count register to realize the synchronization of the carrier wave and the synchronizing signal of each inverter. Fig. 8 is a schematic diagram of a phase difference after carrier synchronization with a synchronization signal according to an embodiment of the present disclosure; as shown in fig. 8, the carrier phase difference after synchronization is reduced to about 1/1000 of the original carrier phase difference, carrier synchronization is basically realized, and the high-frequency circulation of the switching frequency is reduced.

In practical application, redundancy design can be performed for generating the synchronization signal, and the logic processing unit for acquiring the duty cycle signal to generate the synchronization signal in the embodiment includes a plurality of complex programmable logic devices (Complex Programmable Logic Device, CPLDs) synchronization signal processing circuits to respectively acquire the duty cycle signal and generate the plurality of synchronization signals, wherein two CPLDs synchronization signal processing circuits can be specifically adopted, and the redundancy of the synchronization signal is ensured on the basis of minimum cost. The logic processing unit is independent of the inverters and is used for receiving and processing the high-frequency duty ratio signals sent by the inverters to generate final synchronous signals. Fig. 9 is a control block diagram of another carrier synchronous redundant system according to an embodiment of the present application; fig. 9 shows a specific structure of the logic processing unit, and as shown in fig. 9, the logic processing unit 1 receives PWM signals sent by external inverters, and the signals pass through an optocoupler isolation circuit, so that digital isolation of input and output is realized. Then, the signals pass through a low-pass filter circuit, and nanosecond high-frequency interference signals of the signal flowing through the channel are filtered. For the generation of the synchronous signals, redundancy design is also considered, and the two CPLD synchronous signal processing circuits which are redundant are included, so that the single-point fault probability of the system is reduced, and the two CPLD synchronous signal processing circuits can be respectively provided with independent power supply and are not affected by each other.

In the above embodiments, the detailed description is given for the carrier synchronization method of the parallel multiple inverters, and the application further provides a corresponding embodiment of the carrier synchronization device of the parallel multiple inverters. It should be noted that the present application describes an embodiment of the device portion from two angles, one based on the angle of the functional module and the other based on the angle of the hardware.

Based on the angle of the functional module, this embodiment provides a carrier synchronization device with multiple inverters connected in parallel, and fig. 10 is a structural diagram of the carrier synchronization device with multiple inverters connected in parallel, as shown in fig. 10, where the device includes:

an acquisition module 10 for acquiring duty cycle signals of the inverters; wherein the duty cycle of the duty cycle signal of each inverter is greater than 50%;

a generating module 11, configured to perform and operation on a duty cycle signal of the inverter that normally operates to generate a synchronization signal;

and a transmitting module 12, configured to transmit the synchronization signal to the inverter so that the inverter realizes carrier synchronization according to the synchronization signal.

Since the embodiments of the apparatus portion and the embodiments of the method portion correspond to each other, the embodiments of the apparatus portion are referred to the description of the embodiments of the method portion, and are not repeated herein.

As a preferred embodiment, the carrier synchronization device with multiple inverters connected in parallel further includes: the filtering module is used for filtering the abnormal off-line inverter before performing AND operation on the duty ratio signal of the normally-working inverter to generate a synchronous signal; anding the duty cycle signal of the normally operating inverter to generate a synchronization signal includes: and performing AND operation on the duty ratio signals of the rest inverters to generate a synchronous signal.

And the amplitude limiting module is used for carrying out numerical amplitude limiting on the adjustment count value after calculating the adjustment count value required by the current carrier according to the phase difference and the change direction.

And the recognition and elimination module is used for carrying out numerical recognition and fault signal elimination on the adjustment count value after calculating the adjustment count value required by the current carrier according to the phase difference and the change direction.

The carrier synchronization device with multiple parallel inverters provided in the embodiment corresponds to the method, and therefore has the same beneficial effects as the method.

Based on the hardware angle, the present embodiment provides another carrier synchronization device with multiple parallel inverters, and fig. 11 is a structural diagram of the carrier synchronization device with multiple parallel inverters provided in another embodiment of the present application, as shown in fig. 11, where the carrier synchronization device with multiple parallel inverters includes: a memory 20 for storing a computer program;

a processor 21 for implementing the steps of the multi-inverter parallel carrier synchronization method as mentioned in the above embodiments when executing a computer program.

Processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 may be implemented in hardware in at least one of a digital signal processor (Digital Signal Processor, DSP), a Field programmable gate array (Field-Programmable Gate Array, FPGA), a programmable logic array (Programmable Logic Array, PLA). The processor 21 may also comprise a main processor, which is a processor for processing data in an awake state, also called central processor (Central Processing Unit, CPU), and a coprocessor; a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 21 may be integrated with an image processor (Graphics Processing Unit, GPU) for taking care of rendering and rendering of the content that the display screen is required to display. In some embodiments, the processor 21 may also include an artificial intelligence (Artificial Intelligence, AI) processor for processing computing operations related to machine learning.

Memory 20 may include one or more computer-readable storage media, which may be non-transitory. Memory 20 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 20 is at least used for storing a computer program 201, where the computer program, after being loaded and executed by the processor 21, can implement the relevant steps of the multi-inverter parallel carrier synchronization method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may further include an operating system 202, data 203, and the like, where the storage manner may be transient storage or permanent storage. The operating system 202 may include Windows, unix, linux, among others. The data 203 may include, but is not limited to, data related to a carrier synchronization method of multiple inverter parallel connection, and the like.

In some embodiments, the carrier synchronization device with multiple parallel inverters may further include a display 22, an input/output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

It will be appreciated by those skilled in the art that the configuration shown in the figures does not constitute a limitation of a multi-inverter parallel carrier synchronization device and may include more or fewer components than shown.

The carrier synchronization device with multiple parallel inverters provided by the embodiment of the application comprises a memory and a processor, wherein when the processor executes a program stored in the memory, the processor can realize the following method: a carrier synchronization method for parallel connection of multiple inverters.

The carrier synchronization device with multiple parallel inverters provided in the embodiment corresponds to the method, and therefore has the same beneficial effects as the method.

Finally, the present application also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when executed by a processor, performs the steps as described in the method embodiments above.

It will be appreciated that the methods of the above embodiments, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored on a computer readable storage medium. With such understanding, the technical solution of the present application, or a part contributing to the prior art or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium, performing all or part of the steps of the method described in the various embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The computer readable storage medium provided in the present embodiment corresponds to the above method, and thus has the same advantageous effects as the above method.

The carrier synchronization method and the device for parallel connection of multiple inverters provided by the application are described in detail above. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it would be obvious to those skilled in the art that various improvements and modifications can be made to the present application without departing from the principles of the present application, and such improvements and modifications fall within the scope of the claims of the present application.

It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Claims (10)

1. A carrier synchronization method for parallel connection of multiple inverters, comprising:

acquiring a duty ratio signal of each inverter; wherein the duty cycle of the duty cycle signal of each of the inverters is greater than 50%;

performing AND operation on the duty ratio signal of the inverter which normally works to generate a synchronous signal;

and sending the synchronizing signal to the inverter so that the inverter realizes carrier synchronization according to the synchronizing signal.

2. The carrier synchronization method of claim 1, wherein the performing an and operation on the duty cycle signals of the inverters that are operating normally to generate a synchronization signal is preceded by:

filtering the abnormal disconnection of the inverter;

said ANDed said duty cycle signal of said inverter operating normally to generate a synchronization signal comprises:

and performing AND operation on the duty ratio signals of the rest inverters to generate the synchronous signals.

3. The carrier synchronization method of multiple inverter parallel connection according to claim 2, wherein the inverter that filters abnormal drop lines includes:

and filtering the inverter in which the duty ratio signal is not in the over-high level state within the preset time.

4. The carrier synchronization method of multiple inverters in parallel according to claim 1, wherein the inverter achieving carrier synchronization according to the synchronization signal includes:

according to the value of the CAP time mark register, the phase difference between the self carrier wave and the synchronous signal is obtained;

determining the change direction of the phase difference according to the change trend of the phase difference;

calculating an adjustment count value required by the current carrier according to the phase difference and the change direction;

and periodically loading the adjustment count value into a carrier time base count register to realize the synchronization of the carrier of each inverter and the synchronization signal.

5. The method for synchronizing carriers in parallel with multiple inverters according to claim 4, further comprising, after calculating an adjustment count value required for a current carrier according to the phase difference and the change direction:

and carrying out numerical clipping on the adjusted count value.

6. The method for synchronizing carriers in parallel with multiple inverters according to claim 5, further comprising, after calculating an adjustment count value required for a current carrier according to the phase difference and the change direction:

and carrying out numerical identification and fault signal rejection on the adjusted count value.

7. The carrier synchronization method in parallel with multiple inverters according to any one of claims 1 to 6, wherein the logic processing unit that acquires the duty cycle signal to generate the synchronization signal includes a plurality of CPLD synchronization signal processing circuits to acquire the duty cycle signal and generate a plurality of the synchronization signals, respectively.

8. The carrier synchronization method of multiple inverters in parallel according to claim 7, wherein the CPLD synchronization signal processing circuit is connected with the inverters through an optocoupler isolation circuit and a low-pass filter circuit.

9. A carrier synchronization device with multiple inverters connected in parallel, comprising:

the acquisition module is used for acquiring the duty ratio signals of the inverters; wherein the duty cycle of the duty cycle signal of each of the inverters is greater than 50%;

the generating module is used for performing AND operation on the duty ratio signal of the inverter which normally works so as to generate a synchronous signal;

and the transmitting module is used for transmitting the synchronizing signal to the inverter so that the inverter can realize carrier synchronization according to the synchronizing signal.

10. A carrier synchronization device with multiple inverters connected in parallel, comprising a memory for storing a computer program;

a processor for implementing the steps of the multi-inverter parallel carrier synchronization method according to any one of claims 1 to 8 when executing the computer program.