CN117637460A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN117637460A CN117637460A CN202210956365.6A CN202210956365A CN117637460A CN 117637460 A CN117637460 A CN 117637460A CN 202210956365 A CN202210956365 A CN 202210956365A CN 117637460 A CN117637460 A CN 117637460A
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- dielectric layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000002360 preparation method Methods 0.000 title abstract description 11
- 238000005498 polishing Methods 0.000 claims abstract description 130
- 239000000203 mixture Substances 0.000 claims abstract description 97
- 230000002378 acidificating effect Effects 0.000 claims abstract description 94
- 239000002245 particle Substances 0.000 claims abstract description 87
- 239000000126 substance Substances 0.000 claims abstract description 75
- 238000007517 polishing process Methods 0.000 claims abstract description 59
- 238000000034 method Methods 0.000 claims description 91
- 230000008569 process Effects 0.000 claims description 55
- 239000012452 mother liquor Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- -1 primary amine salt Chemical class 0.000 claims description 19
- 239000004094 surface-active agent Substances 0.000 claims description 18
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- 238000004519 manufacturing process Methods 0.000 claims description 13
- 239000002738 chelating agent Substances 0.000 claims description 8
- 239000002270 dispersing agent Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 239000008367 deionised water Substances 0.000 claims description 7
- 229910021641 deionized water Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 7
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- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
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- 235000011054 acetic acid Nutrition 0.000 description 2
- BJEPYKJPYRNKOW-UHFFFAOYSA-N alpha-hydroxysuccinic acid Natural products OC(=O)C(O)CC(O)=O BJEPYKJPYRNKOW-UHFFFAOYSA-N 0.000 description 2
- SNAAJJQQZSMGQD-UHFFFAOYSA-N aluminum magnesium Chemical compound [Mg].[Al] SNAAJJQQZSMGQD-UHFFFAOYSA-N 0.000 description 2
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
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- 229910000278 bentonite Inorganic materials 0.000 description 2
- SVPXDRXYRYOSEX-UHFFFAOYSA-N bentoquatam Chemical compound O.O=[Si]=O.O=[Al]O[Al]=O SVPXDRXYRYOSEX-UHFFFAOYSA-N 0.000 description 2
- 235000015165 citric acid Nutrition 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
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- KGOGNDXXUVELIQ-UHFFFAOYSA-N dioctadecylazanium;chloride Chemical compound Cl.CCCCCCCCCCCCCCCCCCNCCCCCCCCCCCCCCCCCC KGOGNDXXUVELIQ-UHFFFAOYSA-N 0.000 description 2
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- 239000001267 polyvinylpyrrolidone Substances 0.000 description 2
- 235000010413 sodium alginate Nutrition 0.000 description 2
- 239000000661 sodium alginate Substances 0.000 description 2
- 229940005550 sodium alginate Drugs 0.000 description 2
- 235000019982 sodium hexametaphosphate Nutrition 0.000 description 2
- GCLGEJMYGQKIIW-UHFFFAOYSA-H sodium hexametaphosphate Chemical compound [Na]OP1(=O)OP(=O)(O[Na])OP(=O)(O[Na])OP(=O)(O[Na])OP(=O)(O[Na])OP(=O)(O[Na])O1 GCLGEJMYGQKIIW-UHFFFAOYSA-H 0.000 description 2
- 239000001488 sodium phosphate Substances 0.000 description 2
- 229910000162 sodium phosphate Inorganic materials 0.000 description 2
- 235000011008 sodium phosphates Nutrition 0.000 description 2
- 235000019832 sodium triphosphate Nutrition 0.000 description 2
- BDHFUVZGWQCTTF-UHFFFAOYSA-N sulfonic acid Chemical compound OS(=O)=O BDHFUVZGWQCTTF-UHFFFAOYSA-N 0.000 description 2
- 239000011975 tartaric acid Substances 0.000 description 2
- 235000002906 tartaric acid Nutrition 0.000 description 2
- 239000001577 tetrasodium phosphonato phosphate Substances 0.000 description 2
- 238000000427 thin-film deposition Methods 0.000 description 2
- RYFMWSXOAZQYPI-UHFFFAOYSA-K trisodium phosphate Chemical compound [Na+].[Na+].[Na+].[O-]P([O-])([O-])=O RYFMWSXOAZQYPI-UHFFFAOYSA-K 0.000 description 2
- 235000010493 xanthan gum Nutrition 0.000 description 2
- 239000000230 xanthan gum Substances 0.000 description 2
- 229920001285 xanthan gum Polymers 0.000 description 2
- 229940082509 xanthan gum Drugs 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 244000124853 Perilla frutescens Species 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 125000003277 amino group Chemical group 0.000 description 1
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 235000005985 organic acids Nutrition 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- USHAGKDGDHPEEY-UHFFFAOYSA-L potassium persulfate Chemical compound [K+].[K+].[O-]S(=O)(=O)OOS([O-])(=O)=O USHAGKDGDHPEEY-UHFFFAOYSA-L 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 241000894007 species Species 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
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Classifications
-
- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09G—POLISHING COMPOSITIONS; SKI WAXES
- C09G1/00—Polishing compositions
- C09G1/02—Polishing compositions containing abrasives or grinding agents
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
Abstract
The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, wherein the preparation method of the semiconductor structure comprises the following steps: providing a first dielectric layer and a second dielectric layer, wherein at least one first opening is formed in the first dielectric layer, and the second dielectric layer fills the first opening and covers the surface of the first dielectric layer; providing an acidic polishing composition comprising positively charged abrasive particles; and performing a chemical mechanical polishing process on the second dielectric layer by adopting the acidic polishing composition so that the upper surface of the second dielectric layer is flush with the upper surface of the first dielectric layer.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
In the fabrication of semiconductor structures, it is often desirable to deposit multiple layers of conductive, semiconductive and/or dielectric materials on the surface of a substrate. Common deposition techniques in modern processing include Physical Vapor Deposition (PVD) (also known as sputtering), chemical Vapor Deposition (CVD), plasma Enhanced Chemical Vapor Deposition (PECVD), electrochemical plating (ECP), and the like.
After deposition of the material layer, a removal process is also performed on portions of the material to form a structure of a particular shape, which is typically repeated a number of times to complete the fabrication of the semiconductor structure. However, during this process, the surface of the uppermost material layer of the substrate becomes non-planar, and a chemical mechanical polishing process is required for the material layer.
However, the existing chemical mechanical polishing process still has a plurality of defects in terms of chemical mechanical polishing efficiency, process cost and the like.
Disclosure of Invention
The embodiment of the disclosure provides a preparation method of a semiconductor structure, which comprises the following steps:
providing a first dielectric layer and a second dielectric layer, wherein at least one first opening is formed in the first dielectric layer, and the second dielectric layer fills the first opening and covers the surface of the first dielectric layer;
providing an acidic polishing composition comprising positively charged abrasive particles;
and performing a chemical mechanical polishing process on the second dielectric layer by adopting the acidic polishing composition so that the upper surface of the second dielectric layer is flush with the upper surface of the first dielectric layer.
In some embodiments, the surface of the second dielectric layer has a negative charge characteristic and the surface of the first dielectric layer has a positive charge characteristic under acidic conditions.
In some embodiments, the first dielectric layer comprises silicon nitride and the second dielectric layer comprises silicon oxide.
In some embodiments, performing a chemical mechanical polishing process on the second dielectric layer with the acidic polishing composition comprises:
performing a first chemical mechanical polishing process, performing a chemical mechanical polishing process on the second dielectric layer at a first rate using the acidic polishing composition, and stopping at a predetermined distance from the first dielectric layer;
and executing a second chemical mechanical polishing process, and carrying out chemical mechanical polishing treatment on the second dielectric layer at a second rate by adopting the acidic polishing composition until the second dielectric layer on the surface of the first dielectric layer and a part of the thickness of the first dielectric layer are removed, wherein the first rate is greater than the second rate.
In some embodiments, the acidic polishing composition has a removal selectivity for the second dielectric layer and for the first dielectric layer of greater than 50.
In some embodiments, the first dielectric layer is removed by no more than 1.5nm when the second cmp process is performed.
In some embodiments, the second dielectric layer is removed at a rate ranging from 400 nm/min to 500nm/min when the first cmp process is performed.
In some embodiments, the positively charged abrasive particles comprise silica particles.
In some embodiments, a method of providing an acidic polishing composition comprises:
providing an acidic polishing composition mother liquor having a zeta potential of between 30 and 50 mV;
diluting the acidic polishing composition mother liquor to obtain the acidic polishing composition.
In some embodiments, the acidic polishing composition mother liquor comprises deionized water in an amount ranging from 85 to 90 wt.% and abrasive particles in an amount ranging from 10 to 15 wt.% and a cationic surfactant such that the acidic polishing composition mother liquor has a zeta potential of between 30 and 50mV based on the acidic polishing composition mother liquor.
In some embodiments, the cationic surfactant comprises at least one of a primary amine salt surfactant, a secondary amine salt surfactant, and a tertiary amine salt surfactant, or a combination thereof.
In some embodiments, the acidic polishing composition mother liquor further comprises an additive comprising at least one of a suspending dispersant, a metal chelator, a biocide, and an organic acid, the additive being present in an amount less than 0.5 wt.% based on the acidic polishing composition mother liquor.
In some embodiments, the acidic polishing composition mother liquor has a pH of 3 to 6.
In some embodiments, the abrasive particles are present in an amount ranging from 1.5 to 2 wt.% based on the acidic polishing composition.
In some embodiments, the abrasive particles have a particle size in the range of 40 to 50 nm.
In some embodiments, the planarization efficiency of the chemical mechanical polishing process is not less than 90%.
In some embodiments, providing a first dielectric layer and a second dielectric layer includes:
providing a substrate;
forming a first dielectric layer on the substrate:
etching the first dielectric layer and the substrate to form at least one first opening in the first dielectric layer, and forming a second opening on the substrate below the first opening, wherein the bottom of the first opening is communicated with the top of the second opening;
and forming a second dielectric layer, wherein the second dielectric layer fills the first opening and the second opening and covers the surface of the first dielectric layer, and a concave area exists in the second dielectric layer right above the first opening.
The embodiment of the disclosure also provides a semiconductor structure prepared by the method related to any embodiment.
In some embodiments, the semiconductor structure includes at least one of an active region, a bit line, a source region, and a drain region.
The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, wherein the preparation method of the semiconductor structure comprises the following steps: providing a first dielectric layer and a second dielectric layer, wherein at least one first opening is formed in the first dielectric layer, and the second dielectric layer fills the first opening and covers the surface of the first dielectric layer; providing a polishing composition comprising positively charged abrasive particles; and performing a chemical mechanical polishing process on the second dielectric layer by adopting the acidic polishing composition so that the upper surface of the second dielectric layer is flush with the upper surface of the first dielectric layer. In the embodiment of the disclosure, the acid polishing composition containing the positively charged polishing particles is applied to the chemical mechanical polishing process, and the effect of chemical mechanical polishing is realized and improved by utilizing the difference of the removal rate/polishing rate of the first dielectric layer and the second dielectric layer in the acid polishing composition containing the positively charged polishing particles, so that the defects in the chemical mechanical polishing are reduced, the cost is reduced, and the yield is improved.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.
Fig. 1 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;
fig. 2 to 8 are process flow diagrams of a semiconductor structure provided in an embodiment of the present disclosure during a fabrication process;
fig. 9 to 11 are diagrams showing the mechanism of action of the acidic polishing composition provided in the embodiments of the present disclosure in performing a chemical mechanical polishing process on a semiconductor structure.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.
In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.
Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Chemical mechanical polishing processes can be used to remove unwanted surface topography and surface defects such as rough surfaces, agglomerated materials, lattice damage, scratches, and contaminated layers or materials, among others. However, if the flatness of the surface of the semiconductor structure formed after performing the cmp process is poor, the structure formed on the surface is unstable, and the phenomenon of inclination or collapse is easily caused, thereby affecting the stability and reliability of the finally formed semiconductor structure.
In addition, during the chemical mechanical polishing process of the semiconductor structure, the problem of the removal selectivity between the materials involved also affects the performance of the finally formed semiconductor structure.
Based on this, the following technical solutions of the embodiments of the present disclosure are provided:
the embodiment of the disclosure provides a method for preparing a semiconductor structure, as shown in fig. 1, the method comprises the following steps:
step S101: providing a first dielectric layer and a second dielectric layer, wherein at least one first opening is formed in the first dielectric layer, and the second dielectric layer fills the first opening and covers the surface of the first dielectric layer;
step S102: providing an acidic polishing composition comprising positively charged abrasive particles;
Step S103: a chemical mechanical polishing process is performed on the second dielectric layer using the acidic polishing composition such that the upper surface of the second dielectric layer is flush with the upper surface of the first dielectric layer.
In embodiments of the present disclosure, an acidic polishing composition containing positively charged abrasive particles is applied to a chemical mechanical polishing process, and the difference in the polishing rate/removal rate of the first dielectric layer and the second dielectric layer in the acidic polishing composition containing positively charged abrasive particles is utilized to achieve and enhance the effect of chemical mechanical polishing.
In order that the above-recited objects, features and advantages of the present disclosure will become more readily apparent, a more particular description of the disclosure will be rendered by reference to the appended drawings. In describing embodiments of the present disclosure in detail, the schematic drawings are not necessarily to scale and are merely illustrative and should not be taken as limiting the scope of the disclosure.
Fig. 1 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure; fig. 2 to 8 are process flow diagrams of a semiconductor structure provided in an embodiment of the present disclosure during a fabrication process; fig. 9 to 11 are diagrams showing the mechanism of action of the acidic polishing composition provided in the embodiments of the present disclosure in performing a chemical mechanical polishing process on a semiconductor structure.
The method for manufacturing the semiconductor structure provided by the embodiment of the disclosure is further described in detail below with reference to the accompanying drawings.
First, step S101 is performed, and as shown in fig. 2, 3, 4, 5, and 6, a first dielectric layer 11 and a second dielectric layer 12 are provided, where at least one first opening H1 is formed in the first dielectric layer 11, and the second dielectric layer 12 fills the first opening H1 and covers the surface of the first dielectric layer 11.
In some embodiments, providing the first dielectric layer 11 and the second dielectric layer 12 includes:
providing a substrate 10;
forming a first dielectric layer 11 on a substrate:
etching the first dielectric layer 11 and the substrate 10 to form at least one first opening H1 in the first dielectric layer 11, and forming a second opening H2 on the substrate 10 located under the first opening H1, wherein the bottom of the first opening H1 is communicated with the top of the second opening H2;
the second dielectric layer 12 is formed, the second dielectric layer 12 fills the first opening H1 and the second opening H2 and covers the surface of the first dielectric layer 11, wherein a concave region T exists in the second dielectric layer 12 located right above the first opening H1.
Here, the substrate 10 may be a semiconductor substrate; specifically included are at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the substrate 10 is a silicon substrate.
In some embodiments, the formation of the first dielectric layer 11 and the second dielectric layer 12 may be formed using one or more thin film deposition processes; in particular, thin film deposition processes include, but are not limited to, chemical Vapor Deposition (CVD) processes, plasma Enhanced Chemical Vapor Deposition (PECVD) processes, atomic Layer Deposition (ALD) processes, or combinations thereof.
Alternatively, in some embodiments, the second dielectric layer may be formed by a high density plasma chemical vapor deposition process.
Alternatively, in an actual process, an etching process may be used to form the first opening and the second opening, specifically, at least one of a dry etching process or a wet etching process or a combination thereof.
In practical processes, the materials of the first dielectric layer 11 and the second dielectric layer 12 may be insulating materials, and in order to ensure the effect of the chemical mechanical polishing process, the materials of the first dielectric layer 11 and the second dielectric layer 12 are preferably different materials.
In some embodiments, the surface of the first dielectric layer 11 may have a positive charge characteristic and the surface of the second dielectric layer 12 may have a negative charge characteristic under acidic conditions.
In some embodiments, the first dielectric layer 11 comprises silicon nitride and the second dielectric layer 12 comprises silicon oxide. Wherein the surface of silicon oxide has negative charge characteristic under acidic environment, and the surface of silicon nitride has positive charge characteristic under acidic environment.
Because the surface of the second dielectric layer 12 presents negative charge characteristic, in the chemical mechanical polishing process, positively charged polishing particles and the surface of the negatively charged second dielectric layer 12 are attracted positively and negatively, so that the polishing efficiency can be improved, and the rapid chemical mechanical polishing of the second dielectric layer 12 can be realized. In addition, the acidic polishing composition allows for more dilution due to the enhanced polishing effect caused by the positive and negative suction effect, and the desired amount of abrasive particles can be lower, which in turn reduces the cost of materials required for the cmp process, and also reduces scratches during the cmp process.
Meanwhile, positively charged abrasive particles and the surface of the negatively charged second dielectric layer 12 will attract each other positively and negatively, and positively charged abrasive particles and the surface of the positively charged first dielectric layer 11 will repel each other positively and negatively, so that the method has higher removal rate of the second dielectric layer and lower removal rate of the first dielectric layer in an acidic environment, and the selection ratio of the second dielectric layer/the first dielectric layer is improved.
To further increase the charge on the surface of the second dielectric layer 12, and thus further increase the polishing efficiency, embodiments of the present disclosure provide methods of forming the second dielectric layer 12 with a more strongly negatively charged characteristic, such as oxygen-enriched silicon oxide formation by Inductively Coupled Plasma Enhanced Chemical Vapor Deposition (ICPECVD), low temperature plasma assisted radical oxidation, remote generation, or microwave plasma in a more strongly diluted silane plasma. Since the silicon surface is oxidized by the plasma species including neutral oxygen radicals, oxygen ions, and electrons, negative charges are generated. Thus under process conditions where plasma oxidation is the primary factor, the net charge is negative and a function of layer thickness.
It should be understood that the above-mentioned charging characteristics and material selection are merely examples of some possible embodiments, and are not the only limitations of the application scenario of the embodiments of the present disclosure, and the embodiments of the present disclosure may be applied to chemical mechanical polishing processes of various other mixed material structures.
In some embodiments, as shown in fig. 3, before forming the first dielectric layer 11, the method further includes: an insulating layer L1 is formed on the substrate 10.
Here, when the material of the first dielectric layer 11 includes silicon nitride, dislocation may be generated by directly forming silicon nitride on the substrate 10, so that the embodiment of the disclosure grows an insulating layer L1 before growing the first dielectric layer 11, which can effectively avoid the situation that the stress is mismatched and a film defect is generated due to the direct growth of silicon nitride on the substrate 10. For example, the insulating layer L1 may be silicon oxide.
It will be appreciated that in a practical process, as shown in fig. 5, the second opening H2 may penetrate through the insulating layer L1, and a top surface of the second opening H2 is flush with an upper surface of the insulating layer L1.
Next, step S102 is performed to provide an acidic polishing composition comprising positively charged abrasive particles.
Here, the pH of the acidic polishing composition can range between 3 and 6.8, such as a pH of between 3 and 6 or between 4 and 5, etc. In some specific embodiments, the acidic polishing composition can have a pH of 5.
In some embodiments, the positively charged abrasive particles comprise silica particles.
Optionally, in some embodiments, the method of providing an acidic polishing composition comprises:
providing an acidic polishing composition mother liquor having a zeta potential of between 30 and 50 mV;
diluting the acidic polishing composition mother liquor to obtain the acidic polishing composition.
Here, the pH of the acidic polishing composition mother liquor is 3 to 6.
Optionally, in some embodiments, the acidic polishing composition mother liquor comprises deionized water in an amount ranging from 85 to 90 wt.% and abrasive particles in an amount ranging from 10 to 15 wt.% based on the acidic polishing composition mother liquor, and a cationic surfactant such that the acidic polishing composition mother liquor has a zeta potential of between 30 and 50 mV.
Here, the cationic surfactant may be a nitrogen-containing organic amine derivative in which a nitrogen atom in the molecule contains a lone pair of electrons, and thus can be combined with hydrogen in an acid molecule by a hydrogen bond to positively charge an amino group. Thus, they have good surface activity under acidic conditions and may include at least one of a primary amine salt surfactant, a secondary amine salt surfactant, and a tertiary amine salt surfactant, or a combination thereof.
Alternatively, in some embodiments, the primary amine salt surfactant includes, but is not limited to, octadecylamine (stearylamine) hydrochloride (C 18 H 37 NH 2 HCl), and the like; secondary amine salt surfactants include, but are not limited to, dioctadecyl amine hydrochloride ((C) 18 H 37 ) 2 NH HCl), and the like; tertiary amine salt surfactants include, but are not limited to, N-dimethyloctadecylamine hydrochloride (C 18 H 37 N(CH 3 ) 2 HCl) and the like.
It is to be appreciated that in some embodiments, the acidic polishing composition mother liquor further comprises an additive comprising at least one of a suspending dispersant, a metal chelator, a biocide, and an organic acid, the additive being present in an amount of less than 0.5 wt.% based on the acidic polishing composition mother liquor. The content of the suspending dispersant, the metal chelating agent, the bactericide may each independently be 0.1wt%.
In some specific embodiments, the material of the suspending dispersant includes, but is not limited to, at least one of polyacrylamide, polyvinyl alcohol, xanthan gum, polyurethane, acacia, polyvinylpyrrolidone, sodium alginate, sodium phosphate, sodium tripolyphosphate, sodium hexametaphosphate, magnesium aluminum silicate, bentonite, and the like, or a combination thereof; materials for the metal chelator include, but are not limited to, organic compounds such as ethylenediamine tetraacetic acid (EDTA) and the like; materials for bactericides include, but are not limited to, isothiazolinones and the like; the material of the organic acid includes, but is not limited to, one or more of citric acid, malic acid, tartaric acid, acetic acid, lactic acid, sulfonic acid, and the like.
In practice, in order to ensure smooth execution of the chemical mechanical polishing process, it is necessary to use an acidic polishing composition having good performance when executing the chemical mechanical polishing process. In embodiments of the present disclosure, in preparing an acidic polishing composition for use in a chemical-mechanical polishing process, the following steps can be employed:
first, the required materials are prepared, including but not limited to: deionized water, abrasive particles, suspending dispersants, metal chelators, bactericides, organic acids, cationic surfactants, and the like.
Alternatively, the abrasive particles may include, but are not limited to, silica or the like.
Next, deionized water is mixed with the abrasive particles and stirred to disperse the abrasive particles in the deionized water.
Alternatively, the content of the abrasive grains may be controlled in the range of 10 to 15wt%, such as 10wt%, 12.5wt%, 15wt%, etc., in this step.
Here, it is noted that the particle size of the abrasive particles needs to be focused on, and neither too large nor too small. For example, when the size of the abrasive particles is too large, although the chemical mechanical polishing rate can be improved to some extent and the execution time of the chemical mechanical polishing process can be shortened, defects such as pits are easily generated on the surface of the polished material layer due to the too large particles, so that surface scratches are caused and the final surface flatness is affected. When the size of the polishing particles is too small, chemical mechanical polishing efficiency tends to be too low, and process time is increased. Specifically, in the actual process, the appropriate particle size can be selected according to the specific material type and thickness of the polished surface.
Alternatively, in this step, the abrasive particles may have an average particle size distribution ranging from 40 to 50 nm. Not only can the chemical mechanical polishing rate be increased and the execution time of the chemical mechanical polishing process be shortened, but also the scratch can be reduced.
Next, an organic acid, such as: one or more of citric acid, malic acid, tartaric acid, acetic acid, lactic acid, sulphonic acid, etc. to adjust the pH of the mixture.
Optionally, in this step, the pH of the mixture may be adjusted to a pH in the range of 3 to 6 using an acid, and in some embodiments, the pH may be in the range of 4 to 5, or the pH may be 5.
The magnitude of the pH affects the charge characteristics of the polishing surface and also affects the roughness of the polishing surface, and embodiments of the present disclosure can achieve a better cmp surface by adjusting the pH to the above range.
Then, a cationic surfactant is added to the mixture with the adjusted pH.
Since the abrasive particles themselves are negatively charged when the abrasive particles are silica, when it is desired to form positively charged abrasive particles, it is necessary to introduce a positive charge on the abrasive particles to neutralize the negative charge carried by themselves and to make the abrasive particles positively charged. In this step, the charge carried by the abrasive particles can be converted from negative to positive by the addition of a cationic surfactant.
In the actual process, the type of the charges of the polishing particles can influence the contact condition of the polishing particles and the polished surface in the chemical mechanical polishing process, for example, the charges of the polishing particles can cause the phenomenon of mutual attraction or mutual repulsion between the polishing particles and the material layer, so that the removal selection ratio among materials involved in the chemical mechanical polishing process can be influenced to a certain extent, and the conditions of excessive consumption of some materials and the like are easily caused. Thus, in this step, the amount of cationic surfactant is controlled.
Meanwhile, in this step, the purpose of introducing the cationic surfactant also includes an effect of changing the zeta potential of the surface of the abrasive particle. The zeta potential can represent the dispersion condition of the grinding particles to a certain extent, if the dispersion condition of the grinding particles is poor, the phenomenon of agglomeration of the grinding particles can be caused, and the agglomeration of the grinding particles can cause inconsistent chemical mechanical polishing rates of all areas in the chemical mechanical polishing process, so that the planarization efficiency of the polished surface is affected. Thus, the amount of cationic surfactant added in this step needs to be controlled so that the abrasive particles achieve the desired zeta potential.
Alternatively, in some embodiments, the zeta potential of the surface of the abrasive particle is between 30 and 50 mV.
In some cmp processes, it may be desirable to dilute the acidic polishing composition prior to use, so that it is desirable to control the mother liquor of the acidic polishing composition to have a higher zeta potential, such as in the range of 30 to 50mV, to ensure that the abrasive particles in the acidic polishing composition are positively charged after dilution for better cmp.
Herein, the cationic surfactant includes at least one of a primary amine salt surfactant, a secondary amine salt surfactant, and a tertiary amine salt surfactant, or a combination thereof.
Alternatively, in some embodiments, primary amine salt surfactants include, but are not limited to, octadecylamine (stearylamine) hydrochloride, and the like; secondary amine salt surfactants include, but are not limited to, dioctadecyl amine hydrochloride, and the like; tertiary amine salt surfactants include, but are not limited to, N-dimethyloctadecylamine hydrochloride and the like.
Finally, optionally, at least one of a suspending dispersant, a metal chelating agent, a bactericide, etc. may be added to the mixture after the addition of the cationic surfactant to prepare an acidic polishing composition for use in a chemical mechanical polishing process.
In some specific embodiments, the material of the suspending dispersant includes, but is not limited to, at least one of polyacrylamide, polyvinyl alcohol, xanthan gum, polyurethane, acacia, polyvinylpyrrolidone, sodium alginate, sodium phosphate, sodium tripolyphosphate, sodium hexametaphosphate, magnesium aluminum silicate, bentonite, and the like, or a combination thereof; materials for the metal chelator include, but are not limited to, organic compounds such as ethylenediamine tetraacetic acid (EDTA) and the like; materials for bactericides include, but are not limited to, isothiazolinones and the like.
Thus, through the steps, the acid polishing composition with good performance can be prepared, the acid polishing composition has acidity, the grinding particles have positive charges, the positively charged grinding particles and the surface of the negatively charged second dielectric layer are positively and negatively attracted in the chemical mechanical polishing process, and the positively charged grinding particles and the surface of the positively charged first dielectric layer are positively and positively repelled, so that the acid polishing composition has higher second dielectric layer removal rate and lower first dielectric layer removal rate in an acid environment, and the selection ratio of the second dielectric layer/the first dielectric layer is improved.
In addition, while conventional processes typically include an oxidizing agent, such as one or more selected from hydrogen peroxide, peracetic acid, potassium persulfate, and/or ammonium persulfate, the acidic polishing composition provided by the embodiments of the present disclosure does not require the addition of an oxidizing agent, which can reduce the complexity of the preparation and effectively reduce the cost.
In some embodiments, the abrasive particles have a particle size in the range of 40 to 50 nm. Specifically, in some particular embodiments, the abrasive particles can have a particle size of 43nm, 45nm, 46nm, 47nm, 48nm, 49nm, or the like.
Specifically, the particle size of the abrasive particles may be selected according to the kind and thickness of the specific material to be chemically and mechanically polished, and is not particularly limited herein.
Finally, step S103 is performed, as shown in fig. 7 to 8, of performing a chemical mechanical polishing process on the second dielectric layer 12 using the acidic polishing composition so that the upper surface of the second dielectric layer 12 is flush with the upper surface of the first dielectric layer 11.
It is understood that the first dielectric layer 11 may be used as a stop layer for performing the chemical mechanical polishing process on the second dielectric layer 12. The structure formed after the chemical mechanical polishing process is completed may include, but is not limited to, an active region and a shallow trench isolation structure, wherein the portion filled in the opening H2 may be used as the shallow trench isolation structure and the substrate 10 located between the shallow trench isolation structures may be used as the active region.
In the disclosed embodiment, a step of diluting the mother liquor of the acidic polishing composition is included before performing the chemical mechanical polishing process on the second dielectric layer 12 by using the acidic polishing composition, and the content of the abrasive particles ranges from 1.5 to 2wt% after the dilution step based on the acidic polishing composition.
The acidic polishing composition provided in the examples of the present disclosure has an abrasive grain content equivalent to that obtained when the conventional alkaline silica polishing solution is diluted 7.5 to 10 times as compared with the conventional polishing solution. Therefore, the embodiment of the disclosure effectively reduces the content of the grinding particles in the acid polishing composition, thereby effectively reducing the production cost and reducing the scratch condition on the surface of the polished material in the execution process of the chemical mechanical polishing process so as to improve the yield.
In addition, compared with the size of the abrasive particles between 100 and 150nm when the alkaline silica polishing solution is adopted in the traditional process or between 100 and 120nm when the acidic ceria polishing solution is adopted, the size of the abrasive particles adopted in the embodiment of the disclosure is between 40 and 50nm in the process of carrying out the chemical mechanical polishing process, and the abrasive particles with smaller particle size are used in the process of carrying out the chemical mechanical polishing process, so that scratches on the surface of the polished material in the process of carrying out the chemical mechanical polishing process are smaller, defects are reduced, and a smoother surface can be obtained at the end of the final chemical mechanical polishing process.
In this embodiment, since the surface of the abrasive particles 21 has a higher zeta potential, such as a zeta potential of between 30 and 50mV, during the preparation of the mother liquor of the acidic polishing composition, even if the mother liquor of the acidic polishing composition is diluted before the chemical mechanical polishing process is performed, the charged property of the abrasive particles 21 in the diluted acidic polishing composition is not affected, and the abrasive particles 21 are still positively charged, so that good contact between the abrasive particles 21 and the second dielectric layer 12 can be ensured to increase the removal selectivity of the acidic polishing composition to the second dielectric layer 12 and to decrease the selection of the acidic polishing composition to the first dielectric layer 11, so that the removal amount of the first dielectric layer 11 is reduced during the chemical mechanical polishing of the second dielectric layer 12.
In addition, since the zeta potential of the surface of the abrasive particles 21 has a high value, the agglomeration phenomenon of the abrasive particles 21 during the chemical mechanical polishing process of the second dielectric layer 12 by using the acidic polishing composition can be effectively prevented, so that the chemical mechanical polishing rate of each region during the chemical mechanical polishing process is nearly uniform, and the planarization efficiency of the second dielectric layer 12 can be effectively improved.
In some embodiments, the acidic polishing composition provided by embodiments of the present disclosure has a planarization efficiency of not less than 90% for performing a chemical mechanical polishing process on the second dielectric layer 12.
In a practical process, the chemical mechanical polishing process performed on the second dielectric layer 12 using the acidic polishing composition may specifically include:
performing a first chemical mechanical polishing process, performing a chemical mechanical polishing process on the second dielectric layer 12 at a first rate using an acidic polishing composition, and stopping at a predetermined distance from the first dielectric layer 11;
and performing a second chemical mechanical polishing process, and performing chemical mechanical polishing on the second dielectric layer 12 at a second rate by using the acidic polishing composition until the second dielectric layer 12 on the surface of the first dielectric layer 11 and a part of the thickness of the first dielectric layer 11 are removed, wherein the first rate is greater than the second rate.
In practice, the first cmp process may be stopped at a distance of 2-5 nm from the first dielectric layer. In particular, it may stop at a position 3nm, 3.5nm or 4nm from the first dielectric layer.
In some embodiments, the removal rate of the second dielectric layer is in the range of 400-500 nm/min when the first chemical mechanical polishing process is performed.
Alternatively, the first chemical mechanical polishing process may be performed at a pressure ranging from 4 to 5psi and a rotational speed ranging from 90 to 110 rpm.
Here, when the first cmp process is performed, a larger rate may be used, and the removed second dielectric layer 12 includes the second dielectric layer 12 located in the peripheral area of the recess area T and a portion of the second dielectric layer 12 located below the plane of the recess area T, where the removed second dielectric layer 12 is stopped at a certain distance from the first dielectric layer 11.
It will be appreciated that the second cmp process may be performed at a lower rate than the first cmp process, since a greater rate may result in more severe planar scratches that are eventually formed, and thus the rate of the second cmp process needs to be controlled. After the second chemical mechanical polishing process is performed, the first dielectric layer and the second dielectric layer have flush surfaces.
Alternatively, in embodiments of the present disclosure, the chemical mechanical polishing machine type used to perform the chemical mechanical polishing process may include, but is not limited to, a chemical mechanical polishing machine type manufactured by american Application Materials (AMAT), common perilla source machinery (EBARA), china Hua Haiqing, etc.
In some embodiments, the mechanism of action of the acidic polishing composition provided by embodiments of the present disclosure when performing a chemical mechanical polishing process on the second dielectric layer 12 may be as shown in fig. 9-11.
As shown in fig. 9, it can be seen that, since the abrasive particles 21 in the acidic polishing composition have positive charges and the polished second dielectric layer 12 has negative charges, when the abrasive particles 21 are placed on the second dielectric layer 12, the positively charged abrasive particles 21 and the negatively charged second dielectric layer 12 attract each other, and at this time, when the first cmp process is performed, the abrasive particles 21 have high removal efficiency on the second dielectric layer 12, which effectively shortens the time for performing the cmp process and improves the manufacturing efficiency of the semiconductor structure.
Next, referring to fig. 10, it can be seen that the surface of the second dielectric layer 12 becomes smoother after the first cmp process is performed. At this time, since the uppermost material layer of the substrate 10 remains the second dielectric layer 12, the abrasive grains 21 and the second dielectric layer 12 remain attracted to each other.
On the basis of this, the second chemical mechanical polishing process is started to be performed so that the upper surface of the second dielectric layer 12 is flush with the upper surface of the first dielectric layer 11. In this process, when a certain distance exists between the second dielectric layer 12 and the first dielectric layer 11 all the time, since the abrasive particles 21 only keep in contact with the second dielectric layer 12, the abrasive particles 21 will not generate a chemical mechanical polishing effect on the first dielectric layer 11, and after the first dielectric layer 11 is exposed in the etching process, since the first dielectric layer 11 is positively charged, the abrasive particles 21 and the first dielectric layer 11 will generate a mutual repulsive effect (refer to fig. 11), so in the embodiment of the disclosure, the abrasive particles 21 can have a higher removal selectivity to the second dielectric layer 12 and a very small removal amount to the first dielectric layer 11.
In some embodiments, the acidic polishing composition has a removal selectivity for the second dielectric layer 12 and for the first dielectric layer 11 of greater than 50. That is, the acidic polishing composition has a removal selectivity of greater than 50 for the second dielectric layer/first dielectric layer.
In some embodiments, the removal amount of the first dielectric layer 11 is not more than 1.5nm when the second cmp process is performed.
For example, in some embodiments, the amount of removal of the first dielectric layer 11 may range from 1 to 1.5nm, i.e., the acidic polishing composition provided by embodiments of the present disclosure may maintain the amount of removal of the first dielectric layer 11 at a level of less than 1.5 nm. It is understood that in some other embodiments, the acidic polishing composition provided by embodiments of the present disclosure may also remove the first dielectric layer 11 to a level of 1 nm.
The disclosed embodiments significantly reduce the amount of acidic polishing composition removed from the first dielectric layer compared to conventional techniques where the amount of polishing solution removed from the first dielectric layer is at a level of 5nm or 10 nm. Therefore, when the first dielectric layer is formed, the embodiment of the disclosure can form the first dielectric layer with smaller thickness, namely, the aspect ratio of the first dielectric layer is reduced, so that the hole filling capability of a material formed later is improved.
Here, the specific formation process of the positively charged first dielectric layer 11 may refer to a conventional technique. However, the specific process of forming the positively charged first dielectric layer 11 may be other possible processes, and is not limited thereto.
It should be noted that the arrows shown in fig. 9 to 11 are only schematically used to indicate the interaction relationship between the abrasive particles and the material layer to be polished, for example, the case where the two arrows are opposite to each other indicates mutual attraction, and the case where the two arrows are away from each other indicates mutual repulsion.
The embodiment of the disclosure also provides a semiconductor structure prepared by the method related to any one of the embodiments.
It will be appreciated that in forming a semiconductor structure, the methods of embodiments of the present disclosure may be employed when the chemical mechanical polishing process involved is the same as or similar to the structure referred to in any of the embodiments described above.
In some embodiments, a semiconductor structure may include at least one of an active region, a bit line, a source region, and a drain region, and a fabrication process thereof may include the method of any of the above embodiments.
It can be appreciated that the method provided by any of the embodiments described above can be used in a process for forming an active region, a bit line, a source region and/or a drain region in a DRAM (Dynamic Random Access Memory ), and a better cmp effect can be obtained.
In summary, the semiconductor structure and the preparation method thereof provided by the embodiment of the disclosure can obtain a polished surface with higher planarization efficiency and higher flatness, and have higher removal selection ratio for a material layer to be polished.
In addition, the semiconductor structure and the preparation method thereof provided by the embodiment of the disclosure can also improve the product yield while reducing the cost.
It should be noted that, the method for manufacturing a semiconductor device provided in the embodiments of the present disclosure may be applied to a DRAM structure or other semiconductor devices, which is not limited herein. Embodiments of the semiconductor device fabrication methods provided by the present disclosure are within the same concept as embodiments of the semiconductor device; the features of the embodiments described in the present invention may be combined arbitrarily without any conflict.
The foregoing description of the preferred embodiments of the present disclosure is not intended to limit the scope of the present disclosure, but is intended to cover any modifications, equivalents, and improvements within the spirit and principles of the present disclosure.
Claims (19)
1. A method of fabricating a semiconductor structure, comprising:
providing a first dielectric layer and a second dielectric layer, wherein at least one first opening is formed in the first dielectric layer, and the second dielectric layer fills the first opening and covers the surface of the first dielectric layer;
providing an acidic polishing composition comprising positively charged abrasive particles;
and performing a chemical mechanical polishing process on the second dielectric layer by adopting the acidic polishing composition so that the upper surface of the second dielectric layer is flush with the upper surface of the first dielectric layer.
2. The method of claim 1, wherein the surface of the second dielectric layer has a negative charge characteristic and the surface of the first dielectric layer has a positive charge characteristic under acidic conditions.
3. The method of claim 2, wherein the first dielectric layer comprises silicon nitride and the second dielectric layer comprises silicon oxide.
4. The method of any of claims 1-3, wherein performing a chemical mechanical polishing process on the second dielectric layer with the acidic polishing composition comprises:
performing a first chemical mechanical polishing process, performing a chemical mechanical polishing process on the second dielectric layer at a first rate using the acidic polishing composition, and stopping at a predetermined distance from the first dielectric layer;
and executing a second chemical mechanical polishing process, and carrying out chemical mechanical polishing treatment on the second dielectric layer at a second rate by adopting the acidic polishing composition until the second dielectric layer on the surface of the first dielectric layer and a part of the thickness of the first dielectric layer are removed, wherein the first rate is greater than the second rate.
5. The method of claim 4, wherein the acidic polishing composition has a removal selectivity for the second dielectric layer and the first dielectric layer of greater than 50.
6. The method of claim 4, wherein the first dielectric layer is removed by no more than 1.5nm when performing the second cmp process.
7. The method of claim 4, wherein the second dielectric layer is removed at a rate in the range of 400-500 nm/min when the first cmp process is performed.
8. A method according to any one of claims 1 to 3, wherein the positively charged abrasive particles comprise silica particles.
9. The method of claim 8, wherein the method of providing an acidic polishing composition comprises:
providing an acidic polishing composition mother liquor having a zeta potential of between 30 and 50 mV;
diluting the acidic polishing composition mother liquor to obtain the acidic polishing composition.
10. The method of claim 9, wherein the acidic polishing composition mother liquor comprises deionized water, abrasive particles, and a cationic surfactant, wherein the deionized water is present in an amount ranging from 85 to 90 wt.% and the abrasive particles are present in an amount ranging from 10 to 15 wt.% based on the acidic polishing composition mother liquor, and wherein the cationic surfactant provides the acidic polishing composition mother liquor with a zeta potential ranging from 30 to 50 mV.
11. The method of claim 10, wherein the cationic surfactant comprises at least one of a primary amine salt surfactant, a secondary amine salt surfactant, and a tertiary amine salt surfactant, or a combination thereof.
12. The method of claim 10, wherein the acidic polishing composition mother liquor further comprises an additive comprising at least one of a suspending dispersant, a metal chelator, a biocide, and an organic acid, the additive being present in an amount of less than 0.5 wt.% based on the acidic polishing composition mother liquor.
13. The method of any of claims 9-12, wherein the acidic polishing composition mother liquor has a pH of 3-6.
14. The method according to any one of claims 9 to 12, wherein the abrasive particles are present in an amount ranging from 1.5 to 2 wt.% based on the acidic polishing composition.
15. The method according to any one of claims 9-12, wherein the abrasive particles have a particle size in the range of 40-50 nm.
16. A method according to any one of claims 1-3, wherein the planarization efficiency of the cmp process is not less than 90%.
17. A method according to any of claims 1-3, wherein providing a first dielectric layer and a second dielectric layer comprises:
providing a substrate;
forming a first dielectric layer on the substrate:
etching the first dielectric layer and the substrate to form at least one first opening in the first dielectric layer, and forming a second opening on the substrate below the first opening, wherein the bottom of the first opening is communicated with the top of the second opening;
and forming a second dielectric layer, wherein the second dielectric layer fills the first opening and the second opening and covers the surface of the first dielectric layer, and a concave area exists in the second dielectric layer right above the first opening.
18. A semiconductor structure prepared by the method of any one of claims 1-17.
19. The semiconductor structure of claim 18, wherein the semiconductor structure comprises at least one of an active region, a bit line, a source region, and a drain region.
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| CN202210956365.6A CN117637460A (en) | 2022-08-10 | 2022-08-10 | Semiconductor structure and preparation method thereof |
| PCT/CN2022/114789 WO2024031744A1 (en) | 2022-08-10 | 2022-08-25 | Semiconductor structure and manufacturing method therefor |
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| CN202210956365.6A CN117637460A (en) | 2022-08-10 | 2022-08-10 | Semiconductor structure and preparation method thereof |
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| TW483094B (en) * | 2000-08-17 | 2002-04-11 | Macronix Int Co Ltd | Method to reduce micro-particle adsorption in semiconductor manufacturing process |
| KR100832993B1 (en) * | 2006-04-14 | 2008-05-27 | 주식회사 엘지화학 | Adjuvant for chemical mechanical polishing slurry |
| CN107243783B (en) * | 2017-08-09 | 2018-08-28 | 睿力集成电路有限公司 | Chemical and mechanical grinding method, equipment and cleaning solution |
| US10428241B2 (en) * | 2017-10-05 | 2019-10-01 | Fujifilm Electronic Materials U.S.A., Inc. | Polishing compositions containing charged abrasive |
| US10269579B1 (en) * | 2017-11-30 | 2019-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing semiconductor device |
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