CN117636940A - Memory control device and refresh control method thereof - Google Patents

Abstract

A memory control device and a refresh control method thereof are provided. The memory control device includes a threshold generation circuit configured to: a first threshold value is set for a first memory module electrically coupled to the memory control device. The first threshold is based on information associated with the first memory module. The attack defense circuit is further configured to: the input row addresses are counted, and a row address whose count value exceeds a first threshold among the row addresses of the first memory module is determined as an aggressor row address.

Description

Memory control device and refresh control method thereof

The present application claims priority from korean patent application No. 10-2022-0109161 filed on 8/30/2022 and korean patent application No. 10-2022-0143809 filed on 11/2022, the disclosures of which are incorporated herein by reference.

Technical Field

The disclosure relates to memory systems, and more particularly, to memory systems having memory control devices and refresh control logic in the memory control devices and methods of operating the memory systems.

Background

Volatile memory devices, such as Dynamic Random Access Memory (DRAM), may store data by storing charge within a capacitor of a memory cell and may read data by determining the charge stored in the capacitor. Because the charge stored in the capacitor may leak over time, the memory device may periodically perform a refresh operation on the memory cell.

A memory controller of a memory device may randomly access an address of the memory device and may frequently or centrally access a particular address. As the density of memory cells in a memory device increases, the effect of charge in memory cells of adjacent rows may increase due to the voltage distribution of the rows. In particular, when an "attack" caused by repeatedly accessing a particular row is performed, data stored in memory cells of an adjacent row(s) may be changed and data errors generated due to the voltage of the active state of the particular row. This phenomenon within DRAM devices is known as "row hammer". Memory devices that do not apply attack defense functions (such as row hammer defense functions) or that do not apply the latest attack defense functions may be vulnerable to such attacks.

Disclosure of Invention

Some embodiments include a memory control device that provides an attack defense function to a memory device and a refresh control method thereof.

According to some embodiments, a memory control device may be provided to which one or more memory modules including a first memory module are connected. The memory control device may include a threshold generation circuit and an attack defense circuit. The threshold generation circuit may set a first threshold for the first memory module based on information associated with the first memory module. The attack defense circuit may count the input row addresses and determine a row address whose count value exceeds a first threshold among the row addresses of the first memory module as an aggressor row address of the first memory module.

According to additional embodiments, a memory control device may be provided to which a plurality of memory modules are connected. The memory control device may include a threshold generation circuit, a counter circuit, a comparator circuit, and an address register. The threshold generation circuit may set a threshold for each of the plurality of memory modules based on information associated with each of the plurality of memory modules. The counter circuit may count the input row address. The comparator circuit may compare a count value of an input row address with the threshold value of a target memory module to which the input row address belongs among the plurality of memory modules. The address register stores an input row address, and the input row address may be determined as an aggressor row address of the target memory module when a count value of the input row address exceeds the threshold value of the target memory module.

According to some embodiments, a refresh control method of a memory controller coupled to one or more memory modules may be provided. The refresh control method may include: (i) receiving an input row address, (ii) setting a threshold value for a target memory module based on information of the target memory module to which the input row address belongs among the one or more memory modules, (iii) comparing a count value of the input row address with the threshold value, (iv) determining the input row address as an aggressor row address when the count value exceeds the threshold value, and (v) instructing the target memory module to refresh a row determined based on the aggressor row address.

Drawings

FIG. 1 is a block diagram illustrating a memory system according to some embodiments.

FIG. 2 is a block diagram illustrating a memory chip according to some embodiments.

Fig. 3 is a block diagram illustrating a refresh control circuit according to some embodiments.

Fig. 4 is a diagram illustrating an example of a refresh cycle controlled by a refresh control circuit, according to some embodiments.

Fig. 5 is a block diagram illustrating a refresh control circuit according to some embodiments.

Fig. 6 is a block diagram illustrating an embodiment of the attack defense logic shown in fig. 5.

Fig. 7 is a block diagram illustrating an embodiment of the threshold generation circuit shown in fig. 5.

Fig. 8 is a block diagram illustrating a refresh control circuit according to some embodiments.

Fig. 9 is a block diagram illustrating an embodiment of the attack defense circuit shown in fig. 8.

Fig. 10 is a block diagram illustrating a refresh control circuit according to some embodiments.

Fig. 11 is a block diagram illustrating an embodiment of the threshold generation circuit shown in fig. 10.

Fig. 12 is a block diagram illustrating a refresh control circuit according to some embodiments.

Fig. 13 is a flow chart illustrating a refresh control method of a memory controller according to some embodiments.

Fig. 14 is a diagram illustrating a computing device according to some embodiments.

Detailed Description

In the following detailed description, specific embodiments of the invention are shown and described simply by way of illustration only. As will be recognized by those skilled in the art, the described embodiments may be modified in various different ways without departing from the spirit or scope of the invention.

Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive. Like reference numerals designate like elements throughout the specification. The order of operations or steps is not limited to the order presented in the claims or figures unless specifically indicated otherwise. The order of operations or steps may be changed, several operations or steps may be combined, particular operations or steps may be partitioned, and particular operations or steps may not be performed.

As used herein, the singular is intended to include the plural unless the context clearly indicates otherwise. Although the terms first, second, etc. may be used herein to describe various elements, components, steps and/or operations, these terms are only used to distinguish one element, component, step or operation from another element, component, step or operation.

FIG. 1 is a block diagram illustrating an example of a memory system according to some embodiments. Referring to fig. 1, a memory system 100 may include a memory controller 110 and a memory module 120. The memory controller 110 may be referred to as a "memory control device". In some embodiments, the memory controller 110 and the memory module 120 may be connected through a memory interface to send and receive signals through the memory interface. In some embodiments, memory system 100 may include a plurality of memory modules 120.

The memory module 120 may include a plurality of memory chips. In some embodiments, the memory chips may be mounted on a circuit board to form the memory module 120. In some embodiments, the memory module 120 may be a dual in-line memory module (DIMM). In some embodiments, the memory chip may be a DRAM chip. In some other embodiments, the memory chip may be another memory chip for which a refresh operation may be used. The memory chip may include an array of memory cells. The memory cell array may include a plurality of memory cells defined by a plurality of rows and a plurality of columns.

The memory controller 110 may receive a memory request from a host. The memory request may include the address of the memory module 120 to be accessed and the type of memory request. The memory controller 110 may control memory operations of the memory module 120 by providing signals to the memory module 120 based on the memory requests. The signals may include a command CMD and an address ADDR. In some embodiments, the memory controller 110 may provide commands CMD and addresses ADDR to the memory module 120 to access the memory chips and control memory operations (such as reading or writing). Data may be transferred from the memory chip to the memory controller 110 in response to a read operation, and data may be transferred from the memory controller 110 to the memory chip in response to a write operation.

The commands CMD may include an activate command, a read/write command, and a refresh command. In some embodiments, the command CMD may also include a precharge command. The activate command may be a command for activating a target row of the memory chip to write data to the memory chip or read data from the memory chip. The read/write command may be a command for performing a read or write operation to a target memory cell of an activated row. The refresh command may be a command for performing a refresh operation in the memory chip. In some embodiments, the refresh command may include a normal refresh command and/or a target row refresh command. The target row refresh command may be a refresh command that indicates an operation to refresh a victim row. Since the row of targets is refreshed to sacrifice the behavioral targets, it may be referred to as a "target refresh" or a "forced refresh". The normal refresh command may be, for example, a refresh command indicating an operation for sequentially refreshing rows of the memory chip. The normal refresh may include, for example, an auto-refresh performed when the memory module 120 is in use and a self-refresh performed when the memory module 120 is in an idle state.

The memory controller 110 may include a refresh control circuit 111. The refresh control circuit 111 may detect an aggressor row (aggressor row) among a plurality of rows of the memory chip, and determine a victim row (i.e., a target row) to be refreshed based on a row address of the aggressor row (referred to as an "aggressor row address"). In some embodiments, the aggressor row may be a row hammer aggressor row, and the victim row may be a row to be refreshed in response to a row hammer attack. Refresh control circuit 111 may determine a threshold for detecting an aggressor row address based on information associated with memory module 120. In some embodiments, the refresh control circuit 111 may compare a count value indicating the number of accesses for each row in the memory module 120 to a threshold value and determine the address of the row having a count value exceeding the threshold value as an aggressor row address.

In some embodiments, the refresh control circuit 111 may communicate the victim row address VRA and the target row refresh command TRR, which are determined based on the aggressor row address, to the memory module 120. The memory module 120 may refresh the victim row indicated by the victim row address VRA in response to the target row refresh command TRR.

Fig. 2 is a block diagram illustrating an example of a memory chip according to some embodiments. Referring to fig. 2, the memory chip 200 may include a memory cell array 210, a sense amplifier 211, a control logic circuit 220 (or control logic 220), an address buffer 230, a row decoder 250, a column decoder 260, an input/output (I/O) gating circuit 270 (or I/O gating 270), and a data I/O buffer 280. The memory cell array 210 may include a plurality of memory cells MC, and may be arranged into a plurality of memory banks 210a to 210 h. Although fig. 2 shows eight memory banks (bank 0 to bank 7) 210a to 210h, the number of memory banks is not limited thereto. Each of the memory banks 210a to 210h may include a plurality of rows, a plurality of columns, and a plurality of memory cells MC arranged at intersections of the plurality of rows and the plurality of columns. In some embodiments, a row may be defined by a plurality of word lines WL and a column may be defined by a plurality of bit lines BL.

The control logic 220 may control the operation of the memory chip 200. For example, the control logic circuit 220 may generate control signals so that the memory chip 200 may perform a read operation, a write operation, or a refresh operation. In some embodiments, control logic 220 may include command decoder 221. The command decoder 221 may generate a control signal by decoding a command CMD received from a memory controller (see, e.g., 110 in fig. 1). In some embodiments, the command decoder 221 may receive a target row refresh command TRR from the memory controller 110. In some embodiments, the control logic 220 may also include a mode register 222 that sets the mode of operation of the memory chip 200.

Address buffer 230 may receive an address ADDR provided by memory controller 110. The address ADDR may include a row address RA indicating a row of the memory cell array 210 and a column address CA indicating a column of the memory cell array 210. The row address RA may be provided to the row decoder 250 and the column address CA may be provided to the column decoder 260. In some embodiments, the row address RA may be provided to the row decoder 250 via a row address multiplexer (RA MUX) 251. In some embodiments, address ADDR may further comprise a bank address BA indicating a memory bank.

In some embodiments, the memory chip 200 may also include a row address multiplexer 251. The row address multiplexer 251 may receive a row address RA from the address buffer 230 and a victim row address VRA to be refreshed from the memory controller 110. The row address multiplexer 251 may selectively output the victim row address and the row address RA received from the address buffer 230.

The row decoder 250 may select a row to be activated from among the rows of the memory cell array 210 based on the row address RA or the victim row address VRA. The row decoder 250 may apply a driving voltage to a word line corresponding to a row to be activated. In some embodiments, a plurality of row decoders 250a to 250h corresponding to the memory banks 210a to 210h, respectively, may be provided. The column decoder 260 may select a column to be activated from among the columns of the memory cell array 210 based on the column address CA. The column decoder 260 may activate the sense amplifier 211 corresponding to the column address CA through the I/O gating circuit 270. In some embodiments, a plurality of column decoders 260a to 260h corresponding to the memory banks 210a to 210h, respectively, may be provided. In some embodiments, I/O gating circuitry 270 may gate I/O data and may include data latches to store data read from memory cell array 210 and write drivers to write data to memory cell array 210. Data read from the memory cell array 210 may be sensed by the sense amplifier 211 and stored in the I/O gating circuit 270 (e.g., a data latch). In some embodiments, a plurality of sense amplifiers 211a to 211h corresponding to the memory banks 210a to 210h, respectively, may be provided.

In some embodiments, the memory chip 200 may further include bank control logic 240, the bank control logic 240 generating a bank control signal in response to the bank address BA. In response to the bank control signal, the row decoder 250 corresponding to the bank address BA among the row decoders 250a to 250h may be activated, and the column decoder 260 corresponding to the bank address BA among the column decoders 260a to 260h may be activated.

In some embodiments, data read from the memory cell array 210 (e.g., data stored in data latches) may be provided to the memory controller 110 via the data I/O buffer 280. Data to be written to the memory cell array 210 may be provided to the data I/O buffer 280 from the memory controller 110, and data provided to the data I/O buffer 280 may be provided to the I/O gating circuit 270.

Fig. 3 is a block diagram illustrating an example of a refresh control circuit according to some embodiments, and fig. 4 is a diagram illustrating an example of a refresh period controlled by the refresh control circuit according to some embodiments. Referring now to fig. 3, refresh control circuit 300 may include attack defense circuit 310, threshold generation circuit 320, and register 330. In some embodiments, the refresh control circuit 300 may be included in a memory controller (see, e.g., 110 in fig. 1).

The threshold generation circuit 320 may determine the threshold RH of the memory module 30 based on information MI of the memory module 30 received from the memory module 30 connected to the memory controller 110 _TH . In some embodiments, when multiple memory modules 30 are connected to the memory controller 110, the threshold generation circuit 320 may set the threshold RH of the corresponding memory module 30 based on the information MI of each memory module 30 _TH . In some embodiments, refresh control circuit 300 may also include a register 330 that records information MI of memory module 30. Thus, the threshold generation circuit 320 may use the value recorded in the register 330 as the information MI of the memory module 30. In some embodiments, during the process of connecting the memory module 30 to the memory controller 110, information MI of the memory module 30 may be recorded in the register 330. In some embodiments, the information MI recorded in the mode register (see, e.g., 222 in fig. 2) of the memory module 30 may be recorded in the register 330.

The threshold generation circuit 320 may determine the threshold RH by reflecting the information MI of the memory module 30 to an initial threshold _TH . In some embodiments, the threshold generation circuit320 may determine the threshold RH by adding an addition value determined based on the information MI of the memory module 30 to the initial threshold value _TH . In some embodiments, the information MI of the memory module 30 may include at least one of identification information associated with the memory module 30, performance of the memory module 30, and reliability of the memory module 30. The identification information may include, for example, the manufacturer of the memory module 30 or a serial number of the memory module 30. Performance may indicate, for example, read and/or write speed of memory module 30, and reliability may indicate, for example, a period of use of memory module 30. The period of use may be determined by, for example, the date of manufacture of the memory module 30. The threshold generation circuit 320 may generate the threshold RH _TH Is set to a value obtained by adding the initial threshold value of the memory module 30 to at least one of a basic value determined by the identification information associated with the memory module 30, a performance value determined by the performance of the memory module 30, and a reliability value determined by the reliability of the memory module 30. In some embodiments, the threshold generation circuit 320 may increase the performance value when the performance of the memory module 30 is increased (e.g., when the speed of the memory module 30 increases). Similarly, the threshold generation circuit 320 may increase the reliability value when the reliability of the memory module 30 is increased (e.g., when the usage period is reduced).

The attack defense circuit 310 may receive the address ADDR from the host and count a row address (hereinafter, referred to as an "input row address") included in the address ADDR. Further, the attack defense circuit 310 can identify the memory module 30 to which the input row address belongs based on the memory module address included in the address ADDR received from the host. When the count value of the input row address (i.e., the accumulated count value) exceeds the threshold RH _TH In this case, the attack defense circuit 310 may detect the input row address as an attacker row address. In some embodiments, when the count value of the input row address is compared with the threshold RH _TH For comparison, the attack defense circuit 310 can use the threshold RH of the memory module 30 to which the input row address belongs _TH . In some embodiments, attack defense circuit 310 can determine victim row address VRA based on detected aggressor row addresses and willThe victim row address VRA is transferred to the memory module 30 to which the aggressor row address belongs. In some embodiments, the attack defense circuitry 310 may communicate the aggressor row address to the memory module 30 to which the aggressor row address belongs. In this case, memory module 30 may determine the victim row address based on the aggressor row address. Attack defense circuitry 310 may determine a row adjacent to the attacker row indicated by the attacker row address as a victim row. In some embodiments, the victim row(s) may include a predetermined number of rows immediately adjacent to the aggressor row. For example, when the aggressor row is the mth row and the predetermined number is two, the victim row may include the (m+1) th row and the (m-1) th row as immediately adjacent two rows. Alternatively, when the aggressor row is the mth row and the predetermined number is four, the victim row may include the (m+2) th row, the (m+1) th row, the (m-1) th row, and the (m-2) th row. In some embodiments, when the victim row address VRA is transferred, the attack defense circuit 310 can transfer the target row refresh command TRR to the corresponding memory module 30.

As shown in fig. 4, it is assumed that a plurality of memory modules DIMM1, DIMM2, DIMM3, and DIMM4, which are different models, are connected to a memory controller. Accordingly, the refresh control circuit 300 of the memory controller may set the thresholds of the memory modules DIMM1, DIMM2, DIMM3, and DIMM4 to different values. Thus, when the memory modules DIMM1, DIMM2, DIMM3, and DIMM4 are under the same attack, the targeted rank refresh may be performed at different cycles for each of the memory modules DIMM1, DIMM2, DIMM3, and DIMM4 because the thresholds of the memory modules DIMM1, DIMM2, DIMM3, and DIMM4 are different from each other.

According to the above-described embodiments, when a memory module is connected to a memory controller, the memory controller may set a threshold value appropriate for the connected memory module, thereby providing appropriate attack defense logic. In some embodiments, when heterogeneous memory modules are connected to a memory controller, the memory controller may provide attack defense logic appropriate for each of the different memory modules by using different thresholds for the different memory modules. In some embodiments, a memory controller may be used to calculate a fast link (CXL), a Cache Coherence Interconnect (CCIX) for accelerators, or a Z-generation (Gen-Z) to which heterogeneous memory modules may be connected.

Fig. 5 is a block diagram illustrating an example of a refresh control circuit according to some embodiments, fig. 6 is a block diagram illustrating an example of attack defense logic illustrated in fig. 5, and fig. 7 is a block diagram illustrating an example of a threshold generation circuit illustrated in fig. 5. Referring now to fig. 5, refresh control circuit 500 may include attack defense circuit 510 and threshold generation circuit 520. A memory controller including refresh control circuit 500 may be connected to a plurality of memory modules 50 ₁ 、50 ₂ 、……、50 _n . Attack defense circuitry 510 may include and be associated with memory module 50 ₁ To 50 _n A plurality of attack defense logic 510 respectively corresponding to ₁ 、510 ₂ 、……、510 _n The threshold generation circuit 520 may include and be associated with the memory module 50 ₁ To 50 _n Multiple threshold generation logic 520 respectively corresponding to ₁ 、520 ₂ 、……、520 _n 。

Each threshold generation logic 520 _i May be based on memory module 50 ₁ To 50 _n Corresponding memory module 50 among _i Information MI of (2) _i To set the corresponding memory module 50 _i Threshold RH of (2) _THi . Here, i is an integer between 1 and n, n representing the number of memory modules. In some embodiments, threshold generation logic 520 _i Can be achieved by the memory module 50 _i Information MI of (2) _i The determined addition value is added to the initial threshold value to set the threshold value RH _THi . Threshold generation logic 520 _i Threshold RH can be set _THi Provided to attack defense logic 510 ₁ To 510 _n Corresponding attack defense logic 510 among _i . In some embodiments, memory module 50 _i Information MI of (2) _i May include and be associated with memory module 50 _i Associated identification information, memory module 50 _i Performance and memory module 50 of (c) _i At least one of the reliability of (a) is provided. Threshold generation logic 520 _i Memory module 50 may be connected to _i Threshold RH of (2) _THi Set to pass through initial threshold and pass through and storeThe device module 50 _i Basic values determined by associated identification information, via the memory module 50 _i Performance value determined by the performance of the memory module 50 _i A value obtained by adding at least one of reliability values of the reliability determination of (a).

The attack defense circuit 510 may receive an address (hereinafter, referred to as an "input address") ADDR from the host and divide the input address into a row address (input row address) RA and a memory module address. The attack defense circuit 510 may communicate the input row address RA to the memory module 50 as indicated by the memory module address _i Corresponding attack defense logic 510 _i 。

Attack defense logic 510 _i The input row address RA may be counted and the memory module 50 _i Of the row addresses whose count value exceeds the threshold value RH _THi The row address of the memory module 50 is determined _i Is the attacker row address of (c). Referring now to FIG. 6, in some embodiments, attack defense logic 510 _i An address register 511, a counter circuit 512, and a comparator circuit 513 may be included. The address register 511 may store a plurality of row addresses. The address register 511 may include a plurality of registers that store a plurality of row addresses, respectively. Address register 511 may store an input row address RA in a corresponding one of the registers.

The counter circuit 512 may store a count value of the row address stored in the address register 511. Each time the input row address RA is stored in the address register 511, the counter circuit 512 may increment the count value of the corresponding row address by a predetermined value (e.g., one). The counter circuit 512 may include a plurality of counters corresponding to the plurality of registers, respectively, and each counter may count a row address stored in a corresponding register among the registers.

In some embodiments, when there is a register hit by the input row address RA (i.e., a register storing the same row address as the input row address RA) among registers of the address register 511, the counter circuit 512 may increase the count value of a counter corresponding to the hit register by a predetermined value (e.g., one). When there is no register hit by the input row address RA but there is an empty register, the address register 511 may store the input row address RA in the empty register, and the counter circuit 512 may increase the count value of the counter corresponding to the empty register by a predetermined value from an initial value (e.g., zero). In some embodiments, when there is no register hit by the input row address RA and there is no empty register, the address register 511 may determine a register to be replaced among the registers according to a predetermined replacement algorithm and store the input row address RA in the register to be replaced, and the counter circuit 512 may increment the count value of the counter corresponding to the register to be replaced by a predetermined value.

The comparator circuit 513 can compare the count value counted by the counter circuit 512 with the count value counted by the memory module 50 _i Threshold RH set by the threshold value generation circuit 520 of (2) _THi A comparison is made. In some embodiments, the comparator circuit 513 may compare the count value incremented by the input row address RA with the memory module 50 whenever the input row address RA is received _i Threshold RH of (2) _THi A comparison is made. In some embodiments, when the count value to be incremented by the input row address RA is greater than the threshold RH _THi When comparing, the comparator circuit 513 can compare the count value of the row address (e.g., the count value before being incremented by the input row address RA) with the threshold RH _THi A comparison is made. In some other embodiments, the comparator circuit 513 may compare the count value incremented by the input row address with the threshold RH _THi Compare the count value of the row address with the threshold RH _THi A comparison is made.

The comparator circuit 513 can make the count value thereof out of the row addresses exceed the threshold RH _THi Is determined as the aggressor row address. Among the count values of the row addresses, the count value increased by inputting the row address RA may exceed the threshold RH _THi . Therefore, when the count value of the input row address RA exceeds the threshold RH _THi When this is the case, the comparator circuit 513 may generate a signal TRR having a predetermined level. The predetermined level may be, for example, a high level as a logic level. In addition, when the count value of the input row address RA exceeds the threshold RH _THi Time (i.e. in response to the ratio)The comparator circuit 513 outputs a signal TRR having a predetermined level, and the address register 511 can compare the row address having a value exceeding the threshold RH _THi The row address of the count value of (i.e., the input row address RA) is determined as the aggressor row address. In some embodiments, the output signal TRR of the comparator circuit 513 may be used as a target row refresh command. Thus, the memory module 50 _i The target row refresh may be performed on the victim row determined based on the aggressor row address in response to the output signal TRR of the comparator circuit 513. In some embodiments, attack defense logic 510 _i Victim row address VRA may be determined based on an aggressor row address and transferred to memory module 50 _i . In some other embodiments, memory module 50 _i Victim row address VRA, which indicates a victim row, may be determined based on the aggressor row address.

According to the above embodiments, the threshold generation circuit 520 may be based on each memory module 50 _i Is used to determine the corresponding memory module 50 _i And attack defense circuit 510 may be based on each memory module 50 threshold _i Provides attack defense logic 510 appropriate to the corresponding memory module 50i _i . Accordingly, the refresh control circuit 500 may provide a memory module 50 suitable for connection to a memory controller _i Attack defense logic of (a).

Referring to FIG. 7, in some embodiments, each threshold generation logic 520 _i One or more summing circuits 521, 522, and 523 may be included. In FIG. 7, it is assumed that identification Information (ID), performance, and reliability are available as a memory module 50 _i Associated information, and each threshold generation logic 520 _i Three adder circuits 521, 522, and 523 are included.

The adder 521 may output the signal by comparing the initial threshold value I_RH _TH And based on and memory module 50 _i A value (e.g., a basic value) IN1 determined by any piece of information (e.g., identification information) among the associated information is added. The adder 522 may output the data by ANDing the output of the adder 521 with the data of the AND memory module 50 _i Another piece of information among the associated pieces of informationA value obtained by adding the (e.g., performance) determined values (e.g., performance values) IN 2. Adder 523 may output the output from the adder 522 by ANDing the output of adder 522 with the output of AND memory module 50 _i A value (e.g., reliability value) IN3 determined by another piece of information (e.g., reliability) among the associated information is added to the value. Thus, the output of the adder 523 may be used as the threshold RH _THi 。

Thus, threshold generation logic 520 _i The initial threshold i_rh can be set by using addition circuits 521, 522, and 523 _TH And based on and memory module 50 _i The value(s) determined by the associated information are added to determine the threshold.

Fig. 8 is a block diagram illustrating an example of a refresh control circuit according to some embodiments, and fig. 9 is a block diagram illustrating an example of an attack defense circuit shown in fig. 8. Referring now to fig. 8, refresh control circuit 800 may include attack defense circuit 810 and threshold generation circuit 820. A memory controller including refresh control circuit 800 may be connected to a plurality of memory modules 80 ₁ 、80 ₂ 、……、80 _n . Attack defense circuitry 810 may correspond to a common memory module 80 ₁ To 80 degrees _n . The threshold generation circuit 820 may include and memory module 80 ₁ To 80 degrees _n Multiple threshold generation logic 820 respectively corresponding to ₁ 、820 ₂ 、……、820 _n 。

Each threshold generation logic 820 _i May be based on memory module 80 ₁ To 80 degrees _n Corresponding memory module 80 among _i Information MI of (2) _i To set the threshold value RH of the corresponding memory module 80i _THi And will store the module 80 _i Threshold RH of (2) _THi To attack defense circuitry 810. Thus, the threshold generation logic 820 ₁ To 820 _n May be associated with memory module 80 ₁ To 80 degrees _n Respectively corresponding threshold RH _TH1 To RH _THn Provided to attack defense circuitry 810. In some embodiments, with memory module 80 _i The associated information may include information associated with the memory module 80 _i Associated identification information, memory module 80 _i Performance and memory module 80 of (c) _i At least one of the reliability of (a) is provided. Threshold generation logic 820 _i Memory module 80 may be connected to _i Threshold RH of (2) _THi Set to pass through the initial threshold and pass through and memory module 80 _i Basic values determined by associated identification information, via memory module 80 _i Performance value determined by performance of (c) and by memory module 80 _i A value obtained by adding at least one of reliability values of the reliability determination of (a).

Attack defense circuitry 810 may receive an input address ADDR from a host and split the input address ADDR into an input row address RA and a memory module address MA. Referring to fig. 9, in some embodiments, attack defense circuitry 810 may include address registers 811, counter circuitry 812, comparator circuitry 813, and module address registers 814.

The address register 811 may store a plurality of row addresses. The address register 811 may include a plurality of registers that store a plurality of row addresses, respectively. The address register 811 may store the input row address RA in a corresponding register among registers regardless of the memory module to which the input row address RA belongs. The module address register 814 may store a memory module address MA. That is, the module address register 814 may store the memory module 80 whenever an input row address RA is received ₁ To 80 degrees _n Memory module 80 to which input row address RA belongs _i Is provided for the memory module address MA.

Counter circuit 812 may store a count value of the row address stored in address register 811. Each time the input row address RA is stored in the address register 811, the counter circuit 812 may increment the count value of the corresponding row address by a predetermined value (e.g., increment by one). The counter circuit 812 may include a plurality of counters corresponding to the plurality of registers, respectively, and each counter may count a row address stored in a corresponding register among the registers.

The comparator circuit 813 can compare the count value counted by the counter circuit 812 with the count value counted by the memory module 80 _i Threshold RH set by the threshold value generation circuit 820 _THi A comparison is made. In some embodimentsIn an example, comparator circuit 813 may generate logic 820 from the threshold based on memory module address MA stored in module address register 814 ₁ To 820 _n Provided threshold RH _TH1 To RH _THn Among which the corresponding memory module 80 is selected _i Threshold RH of (2) _THi . In some embodiments, each time an input row address RA is received, the comparator circuit 813 can compare the count value of the counter circuit 812 with the corresponding memory module 80 _i Threshold RH of (2) _THi A comparison is made.

When the count value of the input row address RA exceeds the threshold RH _THi At this time, the comparator circuit 813 may output a signal TRR having a predetermined level. In addition, when the count value of the input row address RA exceeds the threshold RH _THi When (i.e., in response to an operation in which the comparator circuit 813 outputs a signal TRR having a predetermined level), the address register 811 may compare the row address having a value exceeding the threshold RH _THi The row address of the count value of (i.e., the input row address RA) is determined as the aggressor row address. In this case, since the count value increased by inputting the row address RA exceeds the threshold RH _THi The memory module address MA stored in module address register 814 may therefore indicate the memory module 80 to which the attacker row address belongs _i . Thus, the address register 811 may transfer the victim row address VRA determined based on the aggressor row address to the memory module 80 indicated by the memory module address MA stored in the module address register 814 _i And the comparator circuit 813 can transfer a signal TRR having a predetermined level to the memory module 80 indicated by the memory module address MA stored in the module address register 814 _i . According to the above embodiment, the attack defense circuit 810 can be implemented by providing the memory modules 80 ₁ To 80 degrees _n Sharing attack defense logic therebetween advantageously reduces the area and/or cost of refresh control circuit 800.

Fig. 10 is a block diagram illustrating an example of a refresh control circuit according to some embodiments, and fig. 11 is a block diagram illustrating an example of a threshold generation circuit illustrated in fig. 10. Referring now to fig. 10, refresh control circuit 1000 may include attack defense circuit 1010 and threshold generation circuit 1020. A memory controller including refresh control circuit 1000 may be connected to a plurality of memory modules 10 ₁ 、10 ₂ 、……、10 _n . Attack defense circuit 1010 may include and be associated with memory module 10 ₁ To 10 _n Respectively corresponding multiple attack defense logics 1010 ₁ 、1010 ₂ 、……、1010 _n And the threshold generation circuit 1020 may correspond to a common memory module 10 ₁ To 10 _n 。

Attack defense circuitry 1010 may receive an input address ADDR from a host and split the input address ADDR into an input row address RA and a memory module address MA. The attack defense circuit 1010 may communicate the input row address RA to the memory module 10 indicated by the memory module address MA _i Corresponding attack defense logic 1010 _i . Furthermore, the threshold generation circuit 1020 may be configured to store the memory module 10 indicated by the memory module address MA _i Threshold RH of (2) _THi To corresponding attack defense logic 1010 _i . Each attack defense logic 1010 due to the attack defense circuit 1010 _i Attack defense logic 510, which may be described with reference to fig. 5 and 6 _i Operate similarly, and thus their description is omitted.

The threshold generation circuit 1020 may be based on the memory module 10 indicated by the memory module address MA of the input address _i Associated information to set up the memory module 10 _i Threshold RH of (2) _THi And threshold RH _THi To and from the memory module 10 _i Corresponding attack defense logic 1010 _i . In some embodiments, with memory module 10 _i The associated information may include at least one of: (i) And memory module 10 _i Associated identification information, (ii) memory module 10 _i And (iii) memory module 10 _i Reliability of (3). The threshold generation circuit 1020 may be configured to generate the memory module 50 as indicated by the memory module address _i Threshold RH of (2) _THi Set to pass through the initial threshold and pass through and memory module 10 _i Basic values determined by the associated identification information, via the memory module 10 _i Performance of performance determination of (a)Value sum passing through memory module 10 _i A value obtained by adding at least one of reliability values of the reliability determination of (a). In one example, the threshold generation circuit 1020 may be based on the memory module 10 _i Information associated with a plurality of memory modules 10 ₁ To 10 _n A plurality of threshold values RH respectively corresponding to _TH1 To RH _THn Selected among (e.g., set by the method described above) for the memory module 10 _i Is set to a threshold value of (2). Advantageously, similar to the attack defense circuit 810 described hereinabove, the threshold generation circuit 1020 may be implemented by providing a plurality of memory modules 10 ₁ To 10 _n Sharing threshold generation logic therebetween reduces the area and/or cost of refresh control circuit 1000.

Referring to fig. 11, in some embodiments, threshold generation circuit 1020 may include one or more "add" circuits 1021, 1022, and 1023, and one or more multiplexing circuits 1024, 1025, and 1026. In fig. 11, it is assumed that identification information, performance, and reliability are used as the memory module 10 _i Associated information, and threshold generation circuit 1020 includes three adder circuits 1021, 1022, and 1023, and three multiplexing circuits 1024, 1025, and 1026.

In response to the memory module address MA, the multiplexing circuit 1024 may output a data base to the memory module 10 ₁ To 10 _n Of which memory module 10 is indicated by memory module address MA _i A value (e.g., a basic value) IN1 determined by any one piece of information (e.g., identification information) among the associated information _i . The summing circuit 1021 may output a signal by passing an initial threshold value I_RH _TH And a value (e.g., a basic value) IN1 output from the multiplexing circuit 1024 _i The values obtained by the addition. In response to memory module address MA, multiplexing circuit 1025 may output a base and memory module 10 ₁ To 10 _n Of which memory module 10 is indicated by memory module address MA _i A value (e.g., a performance value) IN2 determined by another piece of information (e.g., performance) among the associated information _i . The next adder 1022 may output a value (e.g., a performance value) IN2 by combining the output of the adder 1021 with the output from the multiplexer 1025 _i The values obtained by the addition. Multiplexing circuit 1026 may output and base memory module 10 in response to memory module address MA ₁ To 10 _n Of which memory module 10 is indicated by memory module address MA _i A value (e.g., reliability value) IN3 determined by a further piece of information (e.g., reliability) among the associated information _i . The final adder 1023 may output a value (e.g., reliability value) IN3 by combining the output of the adder 1022 with the value output from the multiplexer 1026 _i The values obtained by the addition. Thus, the output of adder 1023 may be used as memory module 10 indicated by memory module address MA _i Threshold RH of (2) _THi . In this way, the threshold generation circuit 1020 may use common threshold generation logic to generate the memory module 10 ₁ To 10 _n Threshold RH of (2) _TH1 To RH _THn 。

Fig. 12 is a block diagram illustrating an example of a refresh control circuit according to some embodiments. Referring now to fig. 12, refresh control circuit 1200 may include attack defense circuit 1210 and threshold generation circuit 1220. A memory controller including refresh control circuit 1200 may be connected to a plurality of memory modules 12 ₁ 、12 ₂ 、……、12 _n . The attack defense circuit 1210 may correspond to a common memory module 12 ₁ To 12 _n And the threshold generation circuit 1220 may correspond to a common memory module 12 ₁ To 12 _n 。

The attack defense circuit 1210 may receive an input address ADDR from the host and divide the input address ADDR into an input row address RA and a memory module address MA. The attack defense circuit 1210 may receive the memory module 12 indicated by the memory module address MA from the threshold generation circuit 1220 _i Threshold RH of (2) _THi . Since the attack defense circuit 1210 can operate similarly to the attack defense circuit 810 described with reference to fig. 8 and 9, a description thereof is omitted.

The threshold generation circuit 1220 may be based on the memory module 12 indicated by the memory module address MA of the input address ADDR _i Associated information to set up the memory module 12 _i Threshold RH of (2) _THi And threshold RH _THi To attack defense circuitry 1210. Since the threshold generating circuit 1220 may operate similarly to the threshold generating circuit 1020 described with reference to fig. 10 and 11, a description thereof is omitted. Thus, because the attack defense circuit 1210 is advantageously shared with the memory module 12 ₁ To 12 _n And the threshold generation circuit 1220 advantageously shares the attack defense logic for the memory module 12 ₁ To 12 _n The area and/or cost of refresh control circuit 1200 may be reduced.

Fig. 13 is a flowchart illustrating an example of a refresh control method of a memory controller according to some embodiments. Referring now to fig. 13, in step S1310, the memory controller may receive an input row address. In step S1320, the memory controller may set a threshold value of a target memory module based on information of a memory module (hereinafter, referred to as a "target memory module") to which an input row address belongs among one or more memory modules connected to the memory controller. The memory controller may compare the count value of the input row address with the threshold value of the target memory module at step S1330, and may determine the input row address as an aggressor row address when the count value of the input row address exceeds the threshold value of the target memory module at step S1340.

In step S1350, the memory controller may instruct the target memory module to refresh the victim row determined based on the aggressor row address. In some embodiments, the memory controller may issue a target row refresh command to the target memory module to indicate a refresh of the victim row. In some embodiments, the memory controller may communicate a victim row address indicating a victim row to the target memory module.

Fig. 14 is a diagram illustrating an example of a computing device according to some embodiments. Referring now to FIG. 14, a computing device 1400 may include a processor 1410, a memory 1420, a memory controller 1430, a storage device 1440, a communication interface 1450, and a bus 1460. Computing device 1400 may also include other components. The processor 1410 may control the overall operation of each component of the computing device 1400. The processor 1410 may be implemented with at least one of various processing units, such as a Central Processing Unit (CPU), an Application Processor (AP), and a Graphics Processor (GPU).

Memory 1420 may store various data and instructions. Memory 1420 may be implemented with the memory modules described with reference to fig. 1-13. Memory controller 1430 may control the transfer of data or commands to and from memory 1420. The memory controller 1430 may be implemented with the memory controller described with reference to fig. 1 through 13. In some embodiments, memory controller 1430 may be provided as a separate chip from processor 1410. In some embodiments, memory controller 1430 may be configured as an internal component of processor 1410.

The storage 1440 may store programs and data non-temporarily. In some embodiments, storage 1440 may be implemented with non-volatile memory. The communication interface 1450 may support wired or wireless internet communication for the computing device 1400. In addition, the communication interface 1450 can support various communication methods in addition to internet communication. Bus 1460 may provide communication functionality between the components of computing device 1400. Bus 1460 may comprise at least one type of bus that is dependent upon the communication protocols between the components.

In some embodiments, each of the components, elements, modules, or units represented by blocks as shown in fig. 1-13 may be implemented as a variety of numbers of hardware, software, and/or firmware structures that perform the corresponding functions described above, according to embodiments. For example, at least one of these components, elements, modules, or units may comprise various hardware components including digital circuits, programmable or non-programmable logic devices or arrays, application Specific Integrated Circuits (ASICs), or other circuitry using digital circuit structures (such as memories, processors, logic circuits, look-up tables, etc.) that may be controlled by one or more microprocessors or other control devices to perform the corresponding functions. Further, at least one of the components, elements, modules, or units may comprise a portion of a module, program, or code that includes one or more executable instructions for performing specified logical functions and that are executed by one or more microprocessors or other control devices. The functional aspects of the embodiments may be implemented in algorithms that execute on one or more processors.

While the invention has been described in connection with what is presently considered to be practical embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims (20)

1. A memory control apparatus comprising:

a threshold generation circuit configured to: setting a first threshold for a first memory module based on information associated with the first memory module electrically coupled to the memory control device; and

attack defense circuitry configured to: the input row address is counted, and a row address whose count value exceeds a first threshold value among the plurality of row addresses of the first memory module is determined as an aggressor row address.

2. The memory control device of claim 1, wherein the threshold generation circuit is further configured to: the first threshold is set by adding the initial threshold to an additional value determined based on information associated with the first memory module.

3. The memory control device of claim 2, wherein the information associated with the first memory module comprises at least one of: identification information of the first memory module, performance of the first memory module, and reliability of the first memory module.

4. The memory control apparatus of claim 3, wherein the additional value comprises a value determined based on identification information of the first memory module.

5. The memory control device of claim 3, wherein the additional value comprises a value determined based on a performance of the first memory module; and wherein the threshold generation circuit is further configured to: the value increases as the performance of the first memory module increases.

6. The memory control device of claim 3, wherein the additional value comprises a value determined based on reliability of the first memory module; and wherein the threshold generation circuit is further configured to: the value increases as the reliability of the first memory module increases.

7. The memory control device according to claim 1,

wherein the memory control device is further electrically coupled to a second memory module; and is also provided with

Wherein, attack defense circuit includes:

first attack defense logic configured to: determining a row address of the first memory module whose count value exceeds a first threshold value among the plurality of row addresses of the first memory module as an aggressor row address of the first memory module; and

second attack defense logic configured to: a row address of the second memory module whose count value exceeds a second threshold value for the second memory module is determined to be an aggressor row address of the second memory module.

8. The memory control device according to claim 7, wherein the threshold generation circuit includes:

first threshold generation logic configured to: setting a first threshold based on information associated with the first memory module; and

second threshold generation logic configured to: the second threshold is set based on information associated with the second memory module.

9. The memory control device of claim 7, wherein the threshold generation circuit is further configured to:

identifying a target memory module to which the input row address belongs from among at least the first memory module and the second memory module based on the input row address; and

based on information associated with the target memory module, a threshold value for the target memory module is selected among a plurality of threshold values including a first threshold value and a second threshold value.

10. The memory control device according to claim 1,

wherein the memory control device is further electrically coupled to a second memory module; and is also provided with

Wherein the attack defense circuit is further configured to:

storing a module address of a target memory module to which an input row address belongs among the first memory module and the second memory module; and

When the count value of the input row address exceeds a threshold value for the target memory module among a plurality of threshold values including the first threshold value, the input row address is determined as an aggressor row address of the target memory module.

11. The memory control device of claim 10,

wherein the plurality of thresholds includes a second threshold for a second memory module, an

Wherein the threshold generation circuit includes:

first threshold generation logic configured to: setting a first threshold based on information associated with the first memory module; and

second threshold generation logic configured to: the second threshold is set based on information associated with the second memory module.

12. The memory control device of claim 10, wherein the threshold generation circuit is further configured to: a threshold value for the target memory module is selected from among the plurality of threshold values based on information associated with the target memory module.

13. The memory control device of claim 1, wherein the attack defense circuit is further configured to: in response to determining that the count value exceeds a first threshold, a signal is transmitted to the first memory module indicating that a row determined based on the aggressor row address is refreshed.

14. A memory control apparatus to which a plurality of memory modules are connected, the memory control apparatus comprising:

a threshold generation circuit configured to: setting a threshold value for each of the plurality of memory modules based on information associated with each of the plurality of memory modules;

a counter circuit configured to: counting the input row addresses;

a comparator circuit configured to: comparing a count value of an input row address with a threshold value for a target memory module to which the input row address belongs among the plurality of memory modules; and

an address register configured to: the input row address is stored and is determined as an aggressor row address of the target memory module when the count value of the input row address exceeds a threshold value for the target memory module.

15. The memory control device of claim 14, wherein the comparator circuit is further configured to: when the count value of the input row address exceeds a threshold value for the target memory module, a signal is output that instructs the target memory module to refresh the row determined based on the aggressor row address.

16. The memory control device of claim 14, further comprising:

a module address register configured to: storing a memory module address of the target memory module; and is also provided with

Wherein the comparator circuit is further configured to: a threshold value for the target memory module is selected from among a plurality of threshold values for the plurality of memory modules based on the memory module address, and the threshold value for the target memory module is compared with a count value of the input row address.

17. The memory control device of claim 14,

wherein the counter circuit comprises a plurality of sub-counter circuits corresponding to respective ones of the plurality of memory modules;

wherein the comparator circuit comprises a plurality of sub-comparator circuits corresponding to respective ones of the plurality of memory modules; and

wherein the address register includes a plurality of sub-address registers corresponding to respective ones of the plurality of memory modules.

18. The memory control device of any one of claims 14 to 17, wherein the threshold generation circuit is further configured to: the threshold value for each of the plurality of memory modules is set by adding the initial threshold value to an addition value determined based on information associated with each of the plurality of memory modules.

19. The memory control device of claim 18, wherein the information associated with each of the plurality of memory modules comprises at least one of: identification information of each of the plurality of memory modules, performance of each of the plurality of memory modules, and reliability of each of the plurality of memory modules.

20. A refresh control method of a memory controller to which one or more memory modules are connected, the refresh control method comprising:

receiving an input row address;

setting a threshold value for a target memory module based on information of the target memory module to which an input row address belongs among the one or more memory modules;

comparing a count value of the input row address with the threshold value;

determining an input row address as an aggressor row address when the count value exceeds the threshold; and

the target memory module is instructed to refresh the row determined based on the aggressor row address.