CN117613117A - Back contact battery, preparation method thereof and battery assembly - Google Patents

Back contact battery, preparation method thereof and battery assembly Download PDF

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Publication number
CN117613117A
CN117613117A CN202410077506.6A CN202410077506A CN117613117A CN 117613117 A CN117613117 A CN 117613117A CN 202410077506 A CN202410077506 A CN 202410077506A CN 117613117 A CN117613117 A CN 117613117A
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layer
silicon
semiconductor layer
back contact
metal
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CN117613117B (en
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林楷睿
许志
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Golden Solar Quanzhou New Energy Technology Co Ltd
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Golden Solar Quanzhou New Energy Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1864—Annealing

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Abstract

The invention belongs to the technical field of back contact batteries, and in particular relates to a back contact battery, a preparation method thereof and a battery assembly, wherein the back contact battery comprises a silicon wafer with a front surface and a back surface, a first semiconductor layer and a second semiconductor layer which are arranged on the back surface and are alternately arranged along the Y-axis direction of the silicon wafer, and a silicon alloy layer and a metal conductive layer which are sequentially arranged outwards along the Z-axis direction of the silicon wafer, wherein the silicon alloy layer is arranged on the outer surface of the second semiconductor layer and extends to the outer surface of an adjacent first doped silicon crystal layer; the sheet resistance of the silicon alloy layer is 60-100And the metal conductive layerThe block resistance is 3-50. The back contact battery does not need to be additionally provided with the transparent conductive film layer, the thin grid and the main grid, the manufacturing process is simpler, expensive low-temperature silver paste and the transparent conductive film layer are not needed, the production cost of the battery is greatly reduced, and meanwhile, the excellent battery conversion efficiency is ensured.

Description

Back contact battery, preparation method thereof and battery assembly
Technical Field
The invention belongs to the technical field of back contact batteries, and particularly relates to a back contact battery, a preparation method thereof and a battery assembly.
Background
In the back contact battery of the prior art, a transparent conductive film is required to be deposited on the outer surfaces of the first semiconductor layer and the second semiconductor layer on the back surface of the silicon wafer. Currently, transparent conductive films generally employ transparent conductive films ITO (indium tin oxide) or TCO (conductive oxide); and an insulating groove is formed between the first semiconductor opening area and the second semiconductor opening area in an etching mode, a metal grid line electrode is formed on the first semiconductor opening area and the second semiconductor opening area of the silicon wafer to serve as a fine grid, a main grid is further arranged, and a silver grid line is formed by low-temperature silver paste generally.
Therefore, the use of expensive transparent conductive films and low temperature silver paste in the prior art makes the battery cost prohibitive.
It should be noted that this section of the disclosure only provides a background related to the present disclosure, and does not necessarily constitute prior art or known technology.
Disclosure of Invention
The invention aims to overcome the defect that the prior art needs to use an expensive transparent conductive film layer and low-temperature silver paste while ensuring excellent battery conversion efficiency, so that the battery cost is high.
In order to achieve the above object, the present invention provides the following technical solutions:
1. a back contact cell comprises a silicon wafer having a front surface and a back surface, a first semiconductor layer and a second semiconductor layer arranged on the back surface and alternately arranged along Y-axis direction of the silicon wafer, wherein the first semiconductor layer comprises a first doped silicon crystal layer, the second semiconductor layer comprises a second doped silicon crystal layer, and the end part of the second semiconductor layer extends to adjacent first semiconductorThe back contact battery further comprises a silicon alloy layer and a metal conducting layer which are sequentially arranged outwards along the Z-axis direction of the silicon wafer, wherein the silicon alloy layer is arranged on the outer surface of the second semiconductor layer and extends to the outer surface of the adjacent first doped silicon crystal layer, and insulation grooves are formed in part of the silicon alloy layer corresponding to the transition region and the corresponding metal conducting layer; wherein the silicon alloy layer contains metal silicide and has a sheet resistance of 60-100And the sheet resistance of the metal conductive layer is 3-50 +.>。
2. The back contact battery according to claim 1, wherein the metal elements contained in each of the metal silicide and the metal conductive layer each independently include at least one of nickel, aluminum, platinum, cobalt, titanium, and tungsten.
3. The back contact battery according to claim 2, wherein the metal silicide and the metal conductive layer each contain the same metal element.
4. The back contact battery of claim 2, wherein the metal silicide comprises at least one of nickel silicide, aluminum silicide, platinum silicide;
and/or the number of the groups of groups,
the metal conductive layer comprises at least one of a nickel layer, an aluminum layer and a platinum layer.
5. The back contact battery of claim 1, wherein the ratio of thicknesses of the silicon alloy layer and the metal conductive layer is 1:1-15;
and/or the number of the groups of groups,
the thickness of the silicon alloy layer is 2-7nm, and the thickness of the metal conductive layer is 5-30nm.
6. The back contact battery of claim 1, wherein the silicon alloy layer further comprises a doping element comprising boron or phosphorous.
7. The back contact cell of claim 6, wherein the ratio of the surface doping index of the silicon alloy layer to the first doped silicon crystal layer to the second doped silicon crystal layer is 1:30-1000:150-8000, wherein the in-plane doping index is the ratio of the effective doping concentration of the corresponding doped silicon layer to the thickness of the doped silicon layer.
In the present invention, the unit of the surface doping index is cm -3 /nm. That is, the effective doping concentration of the corresponding doped silicon crystal layer is in cm -3 The thickness is in nm.
8. The back contact battery of claim 7, wherein the silicon alloy layer has an effective doping concentration of 5e15 cm of doping element -3 -5e17 cm -3 ；
And/or the number of the groups of groups,
the ratio of the thickness of the silicon alloy layer to the second doped silicon crystal layer is 0.04-0.6:1, a step of;
and/or the number of the groups of groups,
the thickness of the first doped silicon crystal layer is 50-300nm, and the effective doping concentration is 1e19 cm -3 -4e20 cm -3 The thickness of the second doped silicon crystal layer is 10-50nm, and the effective doping concentration is 1e19 cm -3 -4e20 cm -3 。
9. The back contact cell of claim 1, wherein the first semiconductor layer further comprises a first passivation layer disposed on the back side of the silicon wafer, at least a portion of the first passivation layer being located between the back side of the silicon wafer and the first doped silicon crystal layer.
10. The back contact cell of claim 9, wherein the second semiconductor layer further comprises a second passivation layer disposed on the back side of the silicon wafer, the second passivation layer being located between the back side of the silicon wafer and the second doped silicon crystal layer; the second passivation layer comprises a second intrinsic amorphous silicon layer or a second tunneling oxide layer, the thickness of the second intrinsic amorphous silicon layer is 5-15nm, and the thickness of the second tunneling oxide layer is 1.5-2.5nm;
Or,
the first passivation layer is arranged on the back surface of the silicon wafer in a full-coverage mode, the first doped silicon crystal layer and the second doped silicon crystal layer are both located on one side, far away from the back surface of the silicon wafer, of the first passivation layer, the second doped silicon crystal layer and a part of the first passivation layer covered by the second doped silicon crystal layer form a second semiconductor layer, and the first doped silicon crystal layer and the second doped silicon crystal layer are doped polycrystalline layers.
11. The back contact cell of claim 9, wherein the first passivation layer comprises a first tunneling oxide layer, and the first doped silicon crystalline layer is a first doped polycrystalline layer; wherein,
the ratio of the thickness of the silicon alloy layer to the thickness of the first tunneling oxide layer is 1:0.05-1.25, and/or the thickness of the first tunneling oxide layer is 1.5-2.5nm.
12. The back contact battery according to claim 1, wherein the extended end of the second semiconductor layer is in direct contact with the first semiconductor layer in the thickness direction or a mask layer is provided.
In other embodiments, the width of the insulation groove is preferably 0.05-0.3mm.
13. The back contact battery according to claim 1, wherein the back contact battery is not provided with a fine grid and a main grid.
In other technical solutions, preferably, the back contact battery further includes a front passivation layer disposed on the front surface of the silicon wafer and facing outward, where the front passivation layer is any one of third intrinsic amorphous silicon, third intrinsic amorphous silicon externally superimposed doped microcrystalline silicon, tunneling silicon oxide, and tunneling silicon oxide externally superimposed doped polysilicon.
14. A method for preparing a back contact battery, comprising the steps of:
s1, forming a first semiconductor layer on the back surface of a silicon wafer, and forming first opening areas on the first semiconductor layer at intervals along the Y-axis direction of the silicon wafer; forming a second semiconductor layer on the back surface, and forming a second opening region on a part of the second semiconductor layer, which covers the outer surface of the first semiconductor layer; wherein the first semiconductor layer comprises a first doped silicon crystal layer and the second semiconductor layer comprises a second doped silicon crystal layer;
s2, sequentially forming a silicon alloy layer and a metal conductive layer on the back surface obtained in the step S1 through a magnetron sputtering process, wherein the silicon is formed in a controlled mannerThe sputtering power of the alloy layer is 5-12kW, preferably 5-10kW, the sputtering power of the metal conductive layer is 1-4kW, and the sheet resistance of the obtained silicon alloy layer is 60-100 The sheet resistance of the metal conductive layer is 3-50 +.>；
And S3, after the sputtering, performing third etching directly on the silicon alloy layer and the part of the metal conductive layer, which is positioned between the first opening area and the second opening area, so as to form an insulating groove.
15. The method for manufacturing a back contact battery according to claim 14, wherein the conditions of the magnetron sputtering process in S2 include: vacuum degree of 5X 10 -3 Pa- 5×10 -1 Pa, the sputtering time when the silicon alloy layer is formed is 10-60s, and the sputtering time when the metal conductive layer is formed is 30-300s;
and/or the number of the groups of groups,
the adopted metal target is at least one of nickel metal, aluminum metal, platinum metal, cobalt metal, titanium metal, tungsten metal, nickel-containing alloy, aluminum-containing alloy, platinum-containing alloy, cobalt-containing alloy, titanium-containing alloy and tungsten-containing alloy.
16. The method for manufacturing a back contact battery according to claim 14, wherein the third etching in S3 adopts a laser technology, and the laser used is a laser with a pulse width of picoseconds.
17. The method for manufacturing a back contact battery according to claim 14, wherein the process of S1 specifically includes:
s101, providing a silicon wafer;
s102, sequentially forming a first semiconductor layer and a mask layer on the back surface of the silicon wafer, wherein the first semiconductor layer comprises a first passivation layer and a first doped silicon crystal layer which are sequentially formed on the back surface;
S103, performing first etching on the first semiconductor layer and the mask layer in the back preset area obtained in the step S102 to form first opening areas which are distributed at intervals;
s104, removing all the residual mask layers;
s105, forming a second semiconductor layer on the back surface obtained in the step S104, wherein the second semiconductor layer comprises a second passivation layer and a second doped silicon crystal layer which are sequentially formed on the back surface;
and S106, performing second etching on the area with the first semiconductor layer remained on the back surface obtained in the step S105 so as to expose the first semiconductor layer and form a second opening area which is arranged with the first opening area.
18. The method for manufacturing a back contact battery according to claim 14, wherein the process of S1 specifically includes:
s11, providing a silicon wafer;
s12, sequentially forming a first semiconductor layer and a mask layer on the back surface of the silicon wafer, wherein the first semiconductor layer comprises a first passivation layer and a first doped silicon crystal layer which are sequentially formed on the back surface;
s13, performing first etching on the first doped silicon crystal layer and the mask layer in the back preset area obtained in the S12 to form first opening areas which are distributed at intervals;
s14, removing all the residual mask layers;
s15, forming a second doped silicon crystal layer on the back surface obtained in the step S14, wherein the second doped silicon crystal layer and a part of the first passivation layer covered by the second doped silicon crystal layer form a second semiconductor layer;
And S16, performing second etching on the area with the first semiconductor layer remained on the back surface obtained in the step S15 to expose part of the first semiconductor layer, so as to form a second opening area which is arranged with the first opening area.
19. A back contact battery, wherein it is produced by the production method of a back contact battery according to any one of claims 14 to 18.
20. A battery assembly comprising the back-contact battery according to any one of claims 1 to 13, or the back-contact battery according to claim 19, and solder strips directly provided on the surface of the silicon alloy layer corresponding to the different conductive regions in the back-contact battery.
The beneficial effects are that:
according to the technical scheme, the silicon alloy layer and the metal conducting layer which are particularly suitable for high conductivity (namely low square resistance) are adopted as electrode extraction modes, so that the electrode extraction modes of combining a transparent conducting film layer with a silver metal fine grid line and a main grid line of a conventional back contact battery are replaced, the fine grid and the main grid are not required to be additionally arranged, the manufacturing process is simpler, expensive low-temperature silver paste and a transparent conducting film layer (such as ITO) are not required, the production cost of the battery is greatly reduced, and excellent battery conversion efficiency is ensured. The silicon alloy layer can realize good ohmic contact between silicon and metal, ensure that the semiconductor layer and the metal conducting layer are in good ohmic contact, and have proper high conductivity (namely low square resistance), so that the silicon alloy layer can directly replace a transparent conducting film, a silver fine grid and a main grid in a back contact battery in the prior art. In particular, the lamination of the silicon alloy layer and the metal conductive layer is adopted, so that good ohmic contact can be formed at each layer interface, the conductivity of the whole material can be further improved by utilizing the metal conductive layer, current is led out more easily, and meanwhile, the surface of the metal conductive layer has higher hardness and wear resistance, and welding of a welding strip on the surface of the metal conductive layer is facilitated when the assembly is packaged.
In the preparation method, the magnetron sputtering is controlled to deposit metal, and high-energy particles (usually argon ions) are used for bombarding the surface of the metal target material, so that the metal target material is sputtered. The method is suitable for the sputtering process under the sputtering power condition, and meanwhile, a silicon alloy layer which is uniform and compact and has high crystallinity can be formed, the surface of the silicon alloy layer cannot be damaged due to too high ion energy in the subsequent metal conductive layer process, and the interface combination between the silicon alloy layer and the metal conductive layer is facilitated to be formed, so that the contact resistance and the interface loss are reduced, and the current transmission efficiency is improved. In addition, in the sputtering process, metal atoms flying out from the surfaces of the metal targets can be deposited on the surfaces of the first semiconductor layer and the second semiconductor layer and react with silicon atoms on the surfaces of the first semiconductor layer and the second semiconductor layer to form a silicon alloy layer, and a metal conducting layer without silicon is formed along with continuous sputtering under the condition of proper sputtering power, wherein annealing treatment is not needed after the sputtering of the silicon alloy layer, but the metal conducting layer is formed by direct sputtering, so that the subsequent annealing treatment process steps of the silicon alloy layer are reduced, the silicon alloy layer with higher quality is formed, and the process flow is further simplified. Among these, the reasons for forming a higher quality silicon alloy layer include at least: when the silicon alloy layer is formed by adopting magnetron sputtering with proper high sputtering power, 1, high-energy metal target ions (such as nickel ions) bombard the silicon surface to initiate rearrangement and activation of the silicon surface, so that the combination between silicon and nickel can be enhanced, and a firmer and high-quality interface is formed; 2. the crystal quality is improved, the magnetron sputtering atomic activation process can enable sputtered atoms to be deposited on the surface more uniformly, defects which are beneficial to combination can be introduced, and the overall performance of the silicon alloy layer is improved; magnetron sputtering atomic activation is helpful for reducing interface defects, and improves the quality and performance of the silicon-nickel alloy through more uniform atomic deposition and interface activation. 3. Controlling the alloy composition distribution: magnetron sputtering atomic activation can control the distribution of silicon and metal elements (such as nickel element) on the surface of the corresponding semiconductor layer more accurately, so that a uniform silicon alloy layer is formed.
In a further preferred embodiment of the invention, especially for the back contact cell with combined passivation, the laser grooving is easier for the third etching of the back surface, and the process flow is further simplified.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a structure of a back contact battery of the prior art in which a first main gate, a second main gate, and an insulating layer are disposed.
Fig. 2 is a schematic structural view of an embodiment of the back contact battery of the present invention.
Fig. 3 is a schematic structural diagram of the first opening area in embodiment 1;
FIG. 4 is a schematic diagram of a structure of the second semiconductor layer formed on FIG. 3;
FIG. 5 is a schematic view of the structure of FIG. 4 with a second opening area;
FIG. 6 is a schematic view of the structure of the silicon alloy layer and the metal conductive layer formed on FIG. 5;
fig. 7 is a schematic structural diagram of a back contact battery of another structure formed by providing an insulation groove in fig. 6.
Description of the reference numerals
1. The semiconductor device comprises a silicon wafer, 2, a first tunneling oxide layer, 3, a front lamination layer, 4, a first doped polycrystalline layer, 5, a second intrinsic amorphous silicon layer, 6, a second doped silicon crystal layer, 7, a silicon alloy layer, 8, a metal conducting layer, 9, an insulation groove, 10, a first main gate, 11, a second main gate, 12, an insulation layer, 13, a first fine gate, 14 and a second fine gate.
Detailed Description
In the present disclosure, the terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying a number of technical features being indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
The endpoints and any values of the ranges disclosed herein are not limited to the precise range or value, and are understood to encompass values approaching those ranges or values. For numerical ranges, one or more new numerical ranges may be found between the endpoints of each range, between the endpoint of each range and the individual point value, and between the individual point value, in combination with each other, and are to be considered as specifically disclosed herein. Wherein the terms "optional" and "optionally" mean either comprising or not comprising (or may not be present).
In the invention, the square resistance of the corresponding layer is obtained by testing the surface of the structure where the layer is positioned by a four-point probe (4 PP) method after the layer is deposited. For example, the sheet resistance of a metal conductive layer is tested on a surface coated with a silicon alloy layer and a metal conductive layer. The four-point probe method works on the principle that four equally spaced co-linear probes are in contact with a material to be measured, and this method is called the four-point probe method, in which Direct Current (DC) is driven between the outer two probes and voltage is measured between the inner two probes. Geometric correction coefficients are generally required when measuring small samples or near the edges, since the current path is affected by the sample geometry, and the most accurate values can be obtained in the central location area of the sample, in the present invention, the square resistances of the corresponding layers are obtained by performing the same test in the central location area of the sample to be measured.
In a first aspect, the invention provides a back contact battery, which comprises a silicon wafer with a front surface and a back surface, a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are arranged on the back surface and are alternately arranged along the Y-axis direction of the silicon wafer, the first semiconductor layer comprises a first doped silicon crystal layer, the second semiconductor layer comprises a second doped silicon crystal layer, the end part of the second semiconductor layer extends to the outer surface of the end part of the adjacent first semiconductor layer to form a transition region, the back contact battery also comprises a silicon alloy layer and a metal conducting layer, the silicon alloy layer and the metal conducting layer are sequentially arranged outwards along the Z-axis direction of the silicon wafer, the silicon alloy layer is arranged on the outer surface of the second semiconductor layer and extends to the outer surface of the adjacent first doped silicon crystal layer, and insulation grooves are formed on part of the silicon alloy layer corresponding to the transition region and the corresponding metal conducting layer; wherein the silicon alloy layer contains metal silicide and has a sheet resistance of 60-100And the sheet resistance of the metal conductive layer is 3-50 +.>。
In the invention, the metal conductive layer does not contain silicon. The metal conductive layer may be composed of one or more metal elements.
In some preferred embodiments of the present invention, the metal elements contained in each of the metal silicide and the metal conductive layer each independently include at least one of nickel, aluminum, platinum, cobalt, titanium, and tungsten.
In the invention, a silicon alloy layer and a metal conducting layer are arranged on the outer surfaces of a first semiconductor layer and a second semiconductor layer (corresponding to the preparation method, the silicon surfaces of the two semiconductor layers are subjected to magnetron sputtering silicon and metal to react to obtain metal silicide, and a silicon alloy layer with high conductivity can be formed), and the silicon alloy layer can enable a good current channel to be formed between the semiconductor layers and the metal conducting layer, so that electrons and holes in the silicon chip can well run to the surface of a battery and be conducted to an external circuit. The reason why the silicon alloy layer capable of forming a good ohmic contact is described by taking metallic nickel as an example is at least reflected in the following aspects:
1. compatibility: the lattice structures of silicon and nickel are relatively similar, with similar lattice parameters and crystal structures, which allows them to form Sini 2 The alloy phase has better compatibility. Compatibility means that there is a similar arrangement in the crystal structure, facilitating interatomic interactions and diffusion.
2. Chemical affinity: there is a certain chemical affinity between silicon and nickel. Nickel metal forms strong chemical bonds with silicon during adsorption on the silicon surface to form Si-Ni bonds, which helps to form stable SiNi 2 And (3) an alloy phase. This chemical affinity helps to increase the fluctuation boundary diffusion rate and promote the interaction between silicon and nickel.
3. Conductivity of: siNi 2 The alloy phase has higher conductivity due to the SiNi 2 The alloy phase has a high electrical conductivity so that current can be efficiently conducted between the metal and the semiconductor, thereby forming a good ohmic contact.
And the metal silicide can greatly reduce the direct contact resistance of silicon and metal (form excellent ohmic contact between silicon and metal), while the metal silicide is formed at a certain temperature, such as WSix, tiSix, coSix, ptSix, niSix, wherein x is a natural number satisfying the valence balance, and their forming temperatures are sequentially reduced, wherein the nickel silicide (NiSix) is required to have the lowest forming temperature, especially single crystal NiSi 2 Since the lattice symmetry and the crystal silicon constant of the phase are close to those of single crystal silicon, niSi 2 The phase formation requires minimal driving force, i.e., minimal temperature, and can be formed even when metallic nickel is plated on the surface of monocrystalline silicon, heated to 150 ℃. According to the preparation method, the silicon alloy layer of the proper metal silicide can be selected according to the temperature characteristics of the passivation structure of each semiconductor layer, for example, the formation temperature of nickel silicide, aluminum silicide and platinum silicide is low, the preparation method can be suitable for a heterojunction structure with intrinsic amorphous silicon passivation and a low-temperature process of a combined passivation structure, the required temperature for forming silicon alloy by W, ti and Co and silicon is relatively high, and the preparation method can be suitable for a Topcon battery structure with tunneling oxide passivation. The invention can be widely applied to the production of solar cells and semiconductor chips.
In the present invention, preferably, the metal silicide and the metal conductive layer each contain the same metal element.
Further preferably, the silicon alloy layer (including metal silicide) and the metal element contained in the metal conductive layer each independently include at least one of nickel, aluminum, and platinum.
In the present invention, the silicon alloy layer includes metal silicide, and may inevitably contain metal simple substance or metal alloy, because when the metal target is magnetron sputtered in preparation, part of sputtered metal reacts with silicon on the surface of the semiconductor layer to form metal silicide, and unreacted metal simple substance and alloy form of the metal simple substance and silicon can be doped.
In some preferred embodiments of the present invention, the metal silicide includes at least one of nickel silicide, aluminum silicide, and platinum silicide, which is more suitable for the heterojunction cell structure and the structure of the back contact cell of the combined passivation structure, and can be prepared in a low temperature process.
In the present invention, the specific form (or specific compound composition) of each metal silicide is not limited, and any product can be used as long as it is a product of the reaction between silicon-containing and metal-containing raw material elements to achieve the objects and technical effects of the present invention; the nickel silicide may be, for example, niSi 2 、NiSi、Ni 2 Si.
In some preferred embodiments of the present invention, the metal conductive layer includes at least one of a nickel layer, an aluminum layer, and a platinum layer.
In some preferred embodiments of the invention, the ratio of the thicknesses of the silicon alloy layer and the metal conductive layer is 1:1-15, for example, may be 1: 1. 1: 2. 1: 3. 1: 4. 1: 5. 1: 6. 1: 7. 1: 8. 1: 9. 1: 10. 1: 11. 1: 12. 1: 13. 1: 14. 1:15, etc., more preferably 1:3-10. By adopting the ratio of proper and preferable thickness, good ohmic contact can be formed between the silicon interface and the metal conductive layer, enough conductivity can be realized, and the balance of the conductivity of the whole material and good contact at each interface is facilitated.
In some preferred embodiments of the invention, the silicon alloy layer has a thickness of 2-7nm, preferably 2-6nm. The silicon alloy layer required by the invention is thinner, has high quality, is more beneficial to forming a good current channel by matching with the metal conducting layer, well enables electrons and holes in the silicon chip to run to the surface of the battery and be conducted to an external circuit, and further improves the conversion efficiency of the battery.
The thickness of the metal conductive layer is preferably 5-30nm, and may be 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 20, 25, 28, 30, etc., for example. The thickness of the solder strip is suitable, the proper conductivity can be provided for guiding out the current, and a surface suitable for welding the solder strip during packaging can be provided, so that the balance of conductivity and welding the solder strip and the cost reduction are facilitated.
In some preferred embodiments of the present invention, the silicon alloy layer further comprises a doping element, the doping element comprising boron or phosphorus.
It can be appreciated that in the present invention, one of the first doped silicon crystal layer and the second doped silicon crystal layer is N-type, and the other is P-type.
In some preferred embodiments of the present invention, the ratio of the surface doping index of the silicon alloy layer to the first doped silicon crystal layer and the second doped silicon crystal layer is 1:30-1000:150-8000, more preferably 1:50-800:400-7000, further preferably 1:50-600:400-6000, wherein the surface doping index is the ratio of the effective doping concentration of the corresponding doped silicon layer to the thickness of the doped silicon layer. In the scheme of the ratio of the surface doping indexes of the optimized silicon alloy layer to the first doped silicon crystal layer and the second doped silicon crystal layer, the thickness and the doping concentration of each layer are matched, so that the concentration of carriers can be better controlled, the electron mobility is improved, the resistance is reduced, and the stability of the preparation process and the overall performance of the battery are improved.
In some preferred embodiments of the present invention, the silicon alloy layer has an effective doping concentration of 5e15 cm of doping element -3 -5e17 cm -3 . The silicon alloy layer has low effective doping concentration of doping elements, can be matched with a proper thickness, and can improve the conversion efficiency of the battery while considering the cost and the manufacturing process.
In some preferred embodiments of the invention, the ratio of the thickness of the silicon alloy layer to the second doped silicon crystal layer is 0.04-0.6:1, for example, may be 0.04: 1. 0.1: 1. 0.2: 1. 0.3: 1. 0.4: 1. 0.5: 1. 0.6:1, etc. The specific structure layer has proper thickness ratio, can reduce the consumption of silicon and doping elements of the second doped silicon crystal layer, and simultaneously forms good contact at the interface of the second doped silicon crystal layer and the metal conductive layer to form a good current transmission channel, thereby being more beneficial to improving the current transmission efficiency and further improving the performance of the battery.
In some preferred embodiments of the present invention, the first doped silicon crystal layer has a thickness of 50-300nm and an effective doping concentration of 1e19 cm -3 -4e20 cm -3 。
The second doped silicon crystal layer may be a doped amorphous layer or a doped microcrystalline layer.
In some preferred embodiments of the present invention, the second doped silicon crystal layer has a thickness of 10-50nm and an effective doping concentration of 1e19 cm -3 -4e20 cm -3 . The thickness of the second doped silicon crystal layer of the present invention is thicker than the prior art to provide a suitable amount of silicon for consumption in the formation of the silicon alloy layer.
In some preferred embodiments of the present invention, the first semiconductor layer further comprises a first passivation layer disposed on the back side of the silicon wafer, at least a portion of the first passivation layer being located between the back side of the silicon wafer and the first doped silicon crystal layer. The first passivation layer may include a first intrinsic amorphous silicon layer or a first tunneling oxide layer.
In some preferred embodiments of the present invention, the second semiconductor layer further comprises a second passivation layer disposed on the back side of the silicon wafer, the second passivation layer being located between the back side of the silicon wafer and the second doped silicon crystal layer; the second passivation layer includes a second intrinsic amorphous silicon layer or a second tunneling oxide layer.
In the back contact battery of the present invention, the passivation structure of the first semiconductor layer and the second semiconductor layer may be one of a combined passivation structure (i.e., the first passivation layer and the second passivation layer are sequentially a tunneling oxide layer and intrinsic amorphous silicon), a heterojunction passivation structure (i.e., the passivation layers of the two semiconductor layers are both intrinsic amorphous silicon), and a tunneling polycrystal (i.e., the passivation layers of the two semiconductor layers are both tunneling oxide layers and the corresponding doped layers are both polycrystalline layers).
Further preferably, the thickness of the second intrinsic amorphous silicon layer is 5-15nm, and the thickness of the second tunneling oxide layer is 1.5-2.5nm;
in some preferred embodiments of the present invention, the first passivation layer is disposed on the back surface of the silicon wafer in a full coverage manner, the first doped silicon crystal layer and the second doped silicon crystal layer are both located on a side, far away from the back surface of the silicon wafer, of the first passivation layer, the second doped silicon crystal layer and a part of the first passivation layer covered by the second doped silicon crystal layer form a second semiconductor layer, and the first doped silicon crystal layer and the second doped silicon crystal layer are both doped polycrystalline layers. Further, the first passivation layer may be a first intrinsic amorphous silicon layer or a first tunneling oxide layer.
In the structure, the second doped silicon crystal layer shares a part of the first passivation layer to form the second semiconductor layer, and the first doped silicon crystal layer and the second doped silicon crystal layer are both doped polycrystalline layers, because the polycrystalline silicon is composed of a plurality of crystal grains, crystal boundaries exist among the crystal grains, and compared with an amorphous layer, the polycrystalline silicon has higher crystallinity and crystal boundary density due to the structure, the formation of the silicon alloy layer is facilitated, metal can form better combination at the crystal boundary of the polycrystalline silicon to form a stable silicon alloy layer, and therefore the formation of the high-quality silicon alloy layer is facilitated, and meanwhile, the consistency of the silicon alloy layers of the first doped silicon crystal layer region and the second doped silicon crystal layer region is improved.
In some preferred embodiments of the present invention, the first passivation layer includes a first tunneling oxide layer, and the first doped silicon crystal layer is a first doped polycrystalline layer. Further preferably, the second passivation layer is a second intrinsic amorphous silicon layer, and the second doped silicon crystal layer may be a doped amorphous layer or a doped microcrystalline layer; in the scheme, the back contact battery is of a combined passivation structure, and compared with other passivation structures, the battery conversion efficiency is higher.
Wherein preferably, the ratio of the thickness of the silicon alloy layer to the thickness of the first tunneling oxide layer is 1:0.05-1.25, the ratio of the thickness of the silicon alloy layer to the thickness of the first tunneling oxide layer is proper, the electron mobility and the tunneling effect can be balanced to a certain extent, the conductivity of the silicon alloy layer is improved, and meanwhile, the stability of the battery is maintained.
Preferably, the thickness of the first tunneling oxide layer is 1.5-2.5nm.
In some preferred embodiments of the present invention, the extended end of the second semiconductor layer is in direct contact with the first semiconductor layer in the thickness direction or a mask layer is provided. Preferably, no mask layer is arranged between the two semiconductor layers, which is more beneficial to reducing impurities or surface scattering introduced by the mask layer and is beneficial to improving the migration performance of carriers in the device compared with a mode of arranging the mask layer between the first semiconductor layer and the second semiconductor layer.
In some preferred embodiments of the present invention, the width of the insulation groove is 0.05-0.3mm.
Preferably, the width of the insulation groove is 0.05-0.15mm. The invention aims at the specific silicon alloy layers to be matched with the insulating layers with proper widths, can prevent electrons from migrating between the silicon alloy layers, avoid unnecessary loss of electrons, is more beneficial to the isolation of the first semiconductor layer and the second semiconductor layer, and better leads out the electrode.
In some preferred embodiments of the present invention, the back contact cell further comprises a front passivation layer disposed outwardly of the front side of the silicon wafer.
Further preferably, the front passivation layer is any one of third intrinsic amorphous silicon, third intrinsic amorphous silicon out-stack doped microcrystalline silicon, tunneling silicon oxide, and tunneling silicon oxide out-stack doped polysilicon.
According to the invention, an anti-reflection layer can be arranged or not arranged on the outer surface of the front passivation layer according to requirements.
The thickness of the front passivation layer, the effective doping concentration when doped amorphous silicon or doped polysilicon is contained, the specific composition and thickness of the anti-reflection layer can be carried out according to the prior art, and can be used in the invention. The front passivation layer has a thickness of 5-30nm, and the effective doping concentration of doped amorphous silicon or doped polysilicon is 1e19cm -3 -1e20cm -3 The thickness of the antireflection layer is 50-150nm, and the type of the antireflection layer can be at least one of silicon nitride, silicon oxide, silicon oxynitride, and the like.
The silicon alloy layer and the metal conducting layer have high conductivity and form excellent ohmic contact, can be directly used as an electrode outgoing line, can directly lead out current without additionally arranging a transparent conducting film layer, a fine grid and a main grid, have short manufacturing process, do not need to use expensive low-temperature silver paste and a transparent conducting film layer, greatly reduce the production cost of a battery and ensure excellent battery conversion efficiency.
In a second aspect, the present invention provides a method for preparing a back contact battery, comprising the steps of:
s1, forming a first semiconductor layer on the back surface of a silicon wafer, and forming first opening areas on the first semiconductor layer at intervals along the Y-axis direction of the silicon wafer; forming a second semiconductor layer on the back surface, and forming a second opening region on a part of the second semiconductor layer, which covers the outer surface of the first semiconductor layer; wherein the first semiconductor layer comprises a first doped silicon crystal layer and the second semiconductor layer comprises a second doped silicon crystal layer;
S2, sequentially forming a silicon alloy layer and a metal conductive layer on the back surface obtained in the step S1 through a magnetron sputtering process, wherein the sputtering power is controlled to be 5-12kW, preferably 6-10kW when the silicon alloy layer is formed, the sputtering power is controlled to be 1-4kW when the metal conductive layer is formed, and the square resistance of the obtained silicon alloy layer is 60-100The sheet resistance of the metal conductive layer is 3-50 +.>；
And S3, after the sputtering, performing third etching directly on the silicon alloy layer and the part of the metal conductive layer, which is positioned between the first opening area and the second opening area, so as to form an insulating groove.
The invention adopts the proper sputtering power range to respectively form the silicon alloy layer and the metal conductive layer, can provide proper energy and heat for different film depositions, is more beneficial to the formation of the silicon alloy layer and the metal conductive layer matched with a silicon interface, and improves the overall performance of the battery.
In the preparation method, when metal in the target material and silicon in the corresponding semiconductor layer contacted with the metal react to form the silicon alloy layer containing the metal silicide, the doping elements except the silicon in the corresponding semiconductor layer are inevitably doped, and the doping concentration of the doping elements can be adjusted through the sputtering condition for forming the silicon alloy layer and the doping concentration of the corresponding semiconductor layer.
In some preferred embodiments of the present invention, the magnetron sputtering tool described in S2The process conditions include: vacuum degree of 5X 10 -3 Pa- 5×10 -1 Pa。
The present invention may select the sputtering time according to the thickness of the desired layer, and in some preferred embodiments of the present invention, the sputtering time when the silicon alloy layer is formed is 10 to 60 seconds.
The present invention may select the sputtering time according to the thickness of the desired layer, and in some preferred embodiments of the present invention, the sputtering time when forming the metal conductive layer is 30 to 300 seconds.
In some preferred embodiments of the present invention, the metal target employed in the magnetron sputtering process is at least one of nickel metal, aluminum metal, platinum metal, cobalt metal, titanium metal, tungsten metal, nickel-containing alloy, aluminum-containing alloy, platinum-containing alloy, cobalt-containing alloy, titanium-containing alloy, tungsten-containing alloy.
In the third etching of the present invention S4, only the silicon alloy layer may be etched, or part (such as the second doped silicon crystal layer) or all (i.e. the second passivation layer) of the second semiconductor layer may be etched to form insulation grooves with different depths or thicknesses.
The inventor of the present invention further researches and discovers that the existing back contact battery needs to remove the conductive film layer between the first opening area and the second opening area to form an insulation groove; the third etching laser grooving on the back is to selectively groove the transparent conductive film layer or the transparent conductive film layer and the P-type (or transparent N-type) amorphous silicon passivation layer, because the material is transparent, the laser can not be absorbed by resonance, and the laser grooving difficulty is great; the wet etching mode is adopted, the process is complex, and the influence on the battery piece is large; further increasing the difficulty of the modulus production of the back contact electricity Chi Gui. The silicon alloy layer and the corresponding doped silicon crystal layer can form good ohmic contact, the wet etching is difficult to directionally open the grooves, and even if the grooves are opened by the wet etching, certain influence can be exerted on other structures. In some preferred embodiments of the present invention, the third etching of S3 is performed using a laser technique.
Further preferably, the laser used is a laser having a pulse width of the order of picoseconds. Picosecond-level laser, on the first hand, very fine processing can be achieved due to the extremely short pulses generated by the picosecond laser; in a second aspect, since the pulse time of the picosecond laser is very short, it produces a relatively small heat affected zone in the material, which helps to avoid thermal damage caused during processing; in a third aspect, the pulse energy generated by the picosecond laser is relatively low, so that the material is less thermally affected during laser irradiation; thereby being more beneficial to reducing the heat influence of the laser irradiation process, avoiding the heat damage possibly caused in the processing process and maximally reducing the deformation, cracking or other heat effects of the material.
Further, the pulse width of the laser is 1-10 picoseconds.
In some preferred embodiments of the present invention, the process of S1 specifically comprises:
s101, providing a silicon wafer;
s102, sequentially forming a first semiconductor layer and a mask layer on the back surface of the silicon wafer, wherein the first semiconductor layer comprises a first passivation layer and a first doped silicon crystal layer which are sequentially formed on the back surface;
s103, performing first etching on the first semiconductor layer and the mask layer in the back preset area obtained in the step S102 to form first opening areas which are distributed at intervals;
S104, removing all the residual mask layers;
s105, forming a second semiconductor layer on the back surface obtained in the step S104, wherein the second semiconductor layer comprises a second passivation layer and a second doped silicon crystal layer which are sequentially formed on the back surface;
and S106, performing second etching on the area with the first semiconductor layer remained on the back surface obtained in the step S105 so as to expose the first semiconductor layer and form a second opening area which is arranged with the first opening area.
In other preferred embodiments of the present invention, the process of S1 specifically comprises:
s11, providing a silicon wafer;
s12, sequentially forming a first semiconductor layer and a mask layer on the back surface of the silicon wafer, wherein the first semiconductor layer comprises a first passivation layer and a first doped silicon crystal layer which are sequentially formed on the back surface;
s13, performing first etching on the first doped silicon crystal layer and the mask layer in the back preset area obtained in the S12 to form first opening areas which are distributed at intervals;
s14, removing all the residual mask layers;
s15, forming a second doped silicon crystal layer on the back surface obtained in the step S14, wherein the second doped silicon crystal layer and a part of the first passivation layer covered by the second doped silicon crystal layer form a second semiconductor layer;
and S16, performing second etching on the area with the first semiconductor layer remained on the back surface obtained in the step S15 to expose part of the first semiconductor layer, so as to form a second opening area which is arranged with the first opening area.
The back contact cell of the present invention may further comprise a step of sequentially forming a front passivation layer and an optional anti-reflection layer on the front surface of the silicon wafer, preferably after forming the second semiconductor layer, and then performing a second etching; or before or after the first passivation layer is formed. The composition of the front passivation layer and the anti-reflection layer is the same as that in the first aspect, and will not be described herein.
The invention also provides a back contact battery, which is prepared by the preparation method of the back contact battery. The structure and composition of the back contact battery prepared by the preparation method are the same as those of the back contact battery, and are not described in detail herein.
The back contact battery is not provided with the main grid and the fine grid, and electrode wires are directly welded when the back contact battery is applied and assembled, specifically, the outer surfaces of a P region formed in the area of the first semiconductor opening area and an N region formed in the area of the second semiconductor opening area are respectively welded with welding strips by using solder paste in a mode of referencing electrodes when the assembly is packaged, and the welding strips are copper strips, aluminum strips and the like.
The invention also provides a battery assembly, which comprises the back contact battery and a welding strip directly arranged on the surface of the silicon alloy layer corresponding to different conductive areas in the back contact battery.
The following detailed description of the embodiments of the invention is exemplary and is merely illustrative of the invention and not to be construed as limiting the invention.
Example 1
A back contact battery as shown in fig. 7, prepared as follows:
s1 comprises the following steps:
s101, providing a silicon wafer 1;
s102, forming a front passivation layer (specifically a third intrinsic amorphous silicon layer with a thickness of 6nm, an effective doping concentration of 5e19 cm) -3 An antireflective layer (specifically silicon nitride) with a thickness of 100nm, forming the front side stack 3. Then forming a first semiconductor layer and a mask layer (specifically, silicon nitride, with the thickness of 50 nm) on the back surface of the silicon wafer 1, wherein the first semiconductor layer comprises a first tunneling oxide layer 2 and an N-type first doped polycrystalline layer 4 which are sequentially formed on the back surface; the first doped polycrystalline layer 4 has a thickness of 80nm and an effective doping concentration of 1e20cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the first tunnel oxide layer 2 is 2nm.
S103, as shown in FIG. 3, performing first etching on the first semiconductor layer and the mask layer on the back surface obtained in S102 to form first opening areas Wp with the interval distribution width of 500 μm;
s104, removing all the residual mask layers;
s105, forming a second semiconductor layer on the back surface obtained in S104, wherein the second semiconductor layer includes a second intrinsic amorphous silicon layer 5 and a second P-type doped silicon crystal layer 6 (specifically, a microcrystalline layer) sequentially formed on the back surface as shown in fig. 4; the thickness of the second doped silicon crystal layer 6 is 10nm, and the effective doping concentration is 1e20cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the second intrinsic amorphous silicon layer 5 is 10nm;
and S106, performing second etching on the region with the first semiconductor layer remained on the back surface obtained in the step S105, so as to expose the first semiconductor layer, and forming a second opening region Wn with a width of 150 μm which is arranged at intervals with the first opening region Wp, as shown in FIG. 5.
S2, sputtering on the back surface obtained in the step S106 by a magnetron sputtering method, and controlling sputtering technological parameters to enable the positions contacted with silicon on the outer surfaces of the first semiconductor layer and the second semiconductor layer to sequentially form a silicon alloy layer 7 and a metal conductive layer 8 without silicon.
Specifically, S is106, placing the obtained cell into a magnetron sputtering device, and vacuumizing until the vacuum degree reaches 5 multiplied by 10 - 2 Pa, setting the sputtering power of the nickel target to be 8kW; sputtering for 10s; obtaining a silicon alloy layer 7 containing nickel silicide with the thickness of 4 nm; the sheet resistance of the silicon alloy layer 7 was 80Containing nickel silicide (NiSi 2 NiSi) and doping with elemental phosphorus and effective doping concentration of 1e16cm -3 。
Then, the sputtering power is adjusted to 3kW, and the sputtering is continued for 150 seconds; a metal conductive layer 8 (specifically, a nickel layer) containing no silicon having a thickness of 20nm was obtained, and a stacked conductive film was formed of the silicon alloy layer 7 and the metal conductive layer 8 containing no silicon, as shown in fig. 6. The sheet resistance of the metal conductive layer 8 was 25 。
S3, scribing the part of the laminated conductive film (namely the metal conductive layer 8 and the silicon alloy layer 7 which do not contain silicon) between the second opening area and the first opening area on the back surface obtained in the step S2 by adopting a laser scribing mode to form an insulating groove, and forming an insulating groove 9 with the width of 0.05mm as shown in FIG. 7; and the third etching adopts a laser technology, and the laser pulse width is 5 picoseconds.
Example 2
The method of example 1 is performed, wherein the magnetron sputtering process parameters of the silicon alloy layer in S2 are partially different, and the specific different parameters are: setting the sputtering power of the nickel target to be 12kW; sputtering for 10s; obtaining a silicon alloy layer containing nickel silicide with the thickness of 7 nm; the sheet resistance of the silicon alloy layer was 70Effective doping concentration is 5e16cm -3 . The sputtering process of the metal conductive layer of example 1 was followed and the subsequent steps were followed.
Example 3
The process according to example 1 is carried out with the difference that the S2 magnetron sputtering process is different, i.e. specifically, the battery sheet obtained in S106 is put inMagnetron sputtering equipment is vacuumized until the vacuum degree reaches 5 multiplied by 10 -2 Pa, setting the sputtering power of the nickel target to be 5kW; sputtering for 23s; obtaining a silicon alloy layer containing nickel silicide with the thickness of 6 nm; the sheet resistance of the silicon alloy layer was 70 Effective doping concentration of 2e16cm -3 ；
Then the sputtering power is adjusted to 2w, and the sputtering is continued for 130s, thus obtaining the film with the thickness of 15nm and the square resistance of 35Silicon-free metallic conductive layers (in particular nickel layers).
Example 4
The process of example 1 was followed with the difference that the S2 magnetron sputtering process was varied, specifically, the battery sheet obtained in S106 was put into a magnetron sputtering apparatus and evacuated to a vacuum degree of 5X 10 -2 Pa, setting the sputtering power of the nickel target to be 5kW; sputtering for 15s; obtaining a silicon alloy layer containing nickel silicide with the thickness of 4 nm; the sheet resistance of the silicon alloy layer was 82Effective doping concentration of 1e16cm -3 ；
Then, the sputtering was continued with a sputtering power of 3kW for 220 seconds to give a sheet resistance of 20 and a thickness of 28nmSilicon-free metallic conductive layers (in particular nickel layers).
Example 5
The process of example 1 was conducted with the exception that the silicon alloy layer and the metal nickel target of the metal conductive layer were replaced with aluminum targets in S2, the thickness of the aluminum-silicon alloy layer formed was unchanged (the same as the silicon alloy layer of example 1, the same as the other examples), and the sheet resistance was 90Effective doping concentration is 5e15cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the formed aluminum metal conductive layer is unchangedSquare resistance of 22% >。/>
Example 6
The process of example 1 was conducted, except that the metallic nickel target of the silicon alloy layer and the metallic conductive layer in S2 was replaced with platinum, the thickness of the platinum silicon alloy layer formed was unchanged and the sheet resistance was 85Effective doping concentration of 1e16cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the formed platinum metal conductive layer is unchanged, and the square resistance is 32 + ->。
Example 7
The procedure of example 1 was carried out, except that the thickness of the metal conductive layer was adjusted to 30nm in S2, and the ratio of the thicknesses of the metal nickel target replaced with the silicon alloy layer and the metal conductive layer was calculated to be 1:7.5; in order to meet the thickness of the metal conductive layer, the process parameters which need to be correspondingly adjusted are as follows: the sputtering time was adjusted to 225s.
Example 8
The process according to example 1 is carried out, with the difference that the effective doping concentration of the silicon alloy layer is adjusted to 5e15 cm in S2 -3 The ratio of the surface doping indexes of the silicon alloy layer to the first doped silicon crystal layer and the second doped silicon crystal layer is calculated to be 1:1000:8000, in order to meet the effective doping concentration of the silicon alloy layer, the process parameters required to be correspondingly adjusted are as follows: the sputtering power was adjusted to 5kW and the sputtering time was adjusted to 18s.
Example 9
The method of example 1 was performed with the difference that the thickness of the silicon alloy layer was adjusted to 6nm in S2, and the ratio of the surface doping index of the silicon alloy layer to the first doped silicon crystal layer and the second doped silicon crystal layer was calculated to be 1:750:6000, the ratio of the thickness of the silicon alloy layer to the second doped silicon crystal layer is calculated to be 0.6:1, a step of; in order to meet the thickness of the silicon alloy layer, the process parameters which need to be correspondingly adjusted are as follows: the sputtering time was adjusted to 15s.
Example 10
The method of example 1 was performed with the difference that the thickness of the first tunneling oxide layer in S102 was adjusted to be 1nm such that the ratio of the thickness of the silicon alloy layer to the thickness of the first tunneling oxide layer was 1:0.25.
example 11
The method according to embodiment 1 is performed with the difference that the passivation structure is different, specifically, the first semiconductor layer is replaced with a first intrinsic amorphous silicon layer and a first impurity-doped amorphous silicon layer of N type sequentially formed on the back surface; the thickness of the first intrinsic amorphous silicon layer and the thickness of the N-type first doped amorphous silicon layer are 10nm, and the effective doping concentration of the first doped amorphous silicon layer is 1e19cm -3 。
Example 12
The method of embodiment 1 is different in that the second semiconductor layer in S1 has a different structure and is formed by the second doped silicon crystal layer 6 and the first tunneling oxide layer 2 in the corresponding region, as shown in fig. 2, S1 specifically is:
s11, providing a silicon wafer;
s12, sequentially forming a first semiconductor layer on the back surface of the silicon wafer 1, wherein the first semiconductor layer comprises a first tunneling oxide layer 2 and a first doped polycrystalline layer 4 which are sequentially formed on the back surface;
s13, performing first etching on the first doped polycrystalline layer 4 in the back preset area obtained in the S12 to form first opening areas which are distributed at intervals;
S14, forming a second doped silicon crystal layer 6 on the back surface obtained in the step S13, and forming a second semiconductor layer by the second doped silicon crystal layer 6 and a part of the first tunneling oxide layer 2 covered by the second doped silicon crystal layer;
and S15, performing second etching on the area with the first semiconductor layer remained on the back surface obtained in the step S14 so as to expose part of the first semiconductor layer and form a second opening area which is arranged with the first opening area. Wherein the thickness (or doping concentration) of each respective layer is the same as in example 1, respectively, with only structural differences.
Example 13
The method of embodiment 1 is different in that the third etching in S3 is a wet etching, and the specific process of the wet etching is as follows: and forming an insulation groove mask pattern of an insulation groove region required to be formed by exposing the back surface by adopting printing protective ink, corroding the exposed conductive film layer by adopting an etching solution to form an insulation groove, and removing the protective ink by adopting an alkaline solution (the composition of the protective ink is specifically sodium hydroxide solution, and the concentration of the protective ink is 2 weight percent).
Example 14
The process of example 12 was conducted, except that the metallic nickel target of the silicon alloy layer and the metallic conductive layer in S2 was replaced with cobalt, the thickness of the silicon alloy layer formed was unchanged and the sheet resistance was 85 Effective doping concentration of 5e17cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the formed metal conductive layer is unchanged, and the square resistance is 40->。
Example 15
The process according to example 1 was carried out, except that the width of the insulation groove in S3 was 0.15mm.
Example 16
The method of example 1 was performed except that S104 was not performed, i.e., a part of the mask layer was remained.
Comparative example 1
The process according to example 1 is carried out, except that S2-S3 are not carried out, but instead a conventional conductive film layer and a metal fine gate line are used, specifically:
s01, after S1, sequentially and outwards covering and paving a transparent conductive film layer (ITO) on the first semiconductor layer and the second semiconductor layer, wherein the thickness of the transparent conductive film layer is 100nm;
s02, performing third etching on the transparent conductive film layer part of the back surface, which is positioned in the transition area between the second opening area and the first opening area, by adopting a wet etching mode to form an insulating groove 9 (the width is the same as that of the embodiment 1), namely, a wet grooving; the wet etching method comprises the following specific technical processes: the insulating groove mask pattern of the insulating groove region required to be formed is formed on the back surface by printing protective ink, then the exposed conductive film layer is corroded by adopting an etching solution to form an insulating groove 9, and then the protective ink is removed by an alkaline solution (the composition of the protective ink is sodium hydroxide solution, and the concentration of the protective ink is 2 wt%).
S03, forming metal thin grid lines (namely a first thin grid 13 and a second thin grid 14) on the corresponding areas of the second opening area and the first opening area respectively, wherein the metal thin grid lines, the first semiconductor layer and the second semiconductor layer are arranged in parallel and are parallel to the X-axis direction of the silicon wafer;
then, the following steps S5-S6 are performed:
s5, preparing insulating layers 12 alternately on the surfaces of the first opening areas and the surfaces of the second opening areas; the insulating layer 12 is prepared by printing insulating ink by screen printing.
S6, preparing a first main grid 10 and a second main grid 11 along the Y-axis direction in the transverse direction provided with the insulating layer 12, wherein the preparation process is screen printing of silver main grids as shown in fig. 1.
Comparative example 2
The process of example 1 was followed with the difference that the S2 magnetron sputtering process was varied, specifically, the battery sheet obtained in S106 was put into a magnetron sputtering apparatus and evacuated to a vacuum degree of 5X 10 -2 Pa, setting the sputtering power of the nickel target to be 8kW; sputtering for 10s; obtaining a silicon alloy layer containing nickel silicide with the thickness of 4 nm; then sputtering is carried out for 50 seconds with sputtering power of 8kW, and a metal conductive layer (particularly a nickel layer) which does not contain silicon and has the thickness of 20nm is obtained; the sheet resistance of the silicon alloy layer was 55 Effective doping concentration of 1e16cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The sheet resistance of the metal conductive layer (in particular the nickel layer) which does not contain silicon is 30 + ->. In the comparative example, the continuous high-power deposition of the metal conductive layer on the surface of the silicon alloy layer can damage the interface between the formed silicon alloy layer and silicon, and the silicon alloy layer is closer to a metal state, so that the square resistance is smaller, but the contact resistance of the interface is affected, and the effect is poor.
Comparative example 3
The process of example 1 was followed with the difference that the S2 magnetron sputtering process was varied, specifically, the battery sheet obtained in S106 was put into a magnetron sputtering apparatus and evacuated to a vacuum degree of 5X 10 -2 Pa, setting the sputtering power of the nickel target to be 3kW; sputtering for 30s; obtaining a silicon alloy layer containing nickel silicide with the thickness of 4 nm; the sheet resistance of the silicon alloy layer was 50Effective doping concentration of 1e16cm -3 ；
Then sputtering was continued with a sputtering power of 8kW for 50 seconds to give a film thickness of 20nm and a sheet resistance of 26Silicon-free metallic conductive layers (in particular nickel layers).
Comparative example 4
The process according to example 1 is carried out with the difference that in S2, only a low-power nickel-plated metal conductive layer is used, and a silicon alloy layer is hardly formed at a low power; the method comprises the following steps: putting the battery piece obtained in the step S106 into a magnetron sputtering device, and vacuumizing until the vacuum degree reaches 5 multiplied by 10 -2 Pa, setting the sputtering power of the nickel target to be 2kW, and sputtering for 100s; a silicon-free metallic conductive layer (in particular, a nickel layer) having a thickness of 10nm was obtained, the sheet resistance of the metallic conductive layer being 50。
Test case
The back contact batteries obtained in the above examples and comparative examples were respectively passed through electrode lines and then subjected to battery performance testing, and specifically, the outer surfaces of the P-electrode conductive region formed in the region of the first semiconductor opening region and the N-electrode conductive region formed in the region of the second semiconductor opening region were respectively soldered with solder paste using a manner of referencing the electrodes during package of the components, and the solder tapes were copper tapes, aluminum tapes, and the like (copper tapes were used in this test example). The results of the performance test are shown in table 1.
Comparison of process flows (also called process):
the process flow (7 lanes) employed in the examples: the method comprises the steps of texturing and cleaning to form a double-sided polished silicon wafer, depositing a first semiconductor layer, depositing a first etching opening, depositing a second semiconductor layer, depositing a second etching opening, depositing a silicon alloy layer and a metal conducting layer, and etching for the second time to form an insulating groove.
Comparative example 1 process flow (10 lanes): the method comprises the steps of texturing and cleaning to form a double-sided polished silicon wafer, depositing a first semiconductor layer, depositing a first etching opening, depositing a second semiconductor layer, depositing a second etching opening, depositing a conductive film layer ITO, grooving an insulating groove, screen printing a fine grid, brushing insulating ink and screen printing a main grid.
The non-silicon cost refers to the cost of the battery piece production except the cost of the silicon wafer, and concretely comprises silver paste, a target material, chemicals, gas, depreciation and others, and the non-silicon cost of the conventional back contact battery produced in comparative example 1 is calculated and calculated preliminarily, wherein the silver paste in comparative example 1 accounts for 39% of the non-silicon cost, and the target material accounts for 7%. Because the invention adopts common metal targets which are cheaper and lower in dosage than ITO targets, the cost of the targets is 4 percent of the cost of non-silicon.
TABLE 1
Compared with the comparative example, the back contact battery adopting the embodiment of the invention does not need to additionally arrange a transparent conductive film layer, a fine grid and a main grid, has simpler manufacturing process, does not need to use expensive low-temperature silver paste and a transparent conductive film layer (such as ITO), greatly reduces the production cost of the battery, and ensures excellent battery conversion efficiency. The solution of the comparative example cannot achieve the cost, the process and the battery conversion efficiency.
Further, according to embodiment 1 and embodiments 2 to 16, the solution of the preferred back contact battery structure of the present invention can ensure low cost and simple manufacturing process, and is more beneficial to improving the battery conversion efficiency.
The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited thereto. Within the scope of the technical idea of the invention, a number of simple variants of the technical solution of the invention are possible, including combinations of the individual technical features in any other suitable way, which simple variants and combinations should likewise be regarded as being disclosed by the invention, all falling within the scope of protection of the invention.

Claims (20)

1. The back contact battery comprises a silicon wafer with a front surface and a back surface, a first semiconductor layer and a second semiconductor layer which are arranged on the back surface and are alternately arranged along the Y-axis direction of the silicon wafer, wherein the first semiconductor layer comprises a first doped silicon crystal layer, the second semiconductor layer comprises a second doped silicon crystal layer, and the end part of the second semiconductor layer extends to the outer surface of the end part of the adjacent first semiconductor layer to form a transition area; wherein the silicon alloy layer contains metal silicide and has a sheet resistance of 60-100 And the sheet resistance of the metal conductive layer is 3-50 +.>。
2. The back contact battery of claim 1, wherein the metal elements contained in each of the metal silicide and the metal conductive layer each independently comprise at least one of nickel, aluminum, platinum, cobalt, titanium, tungsten.
3. The back contact battery of claim 2, wherein the metal silicide and the metal conductive layer each contain the same metal element.
4. The back contact battery of claim 2, wherein the metal silicide comprises at least one of nickel silicide, aluminum silicide, platinum silicide;
and/or the number of the groups of groups,
the metal conductive layer comprises at least one of a nickel layer, an aluminum layer and a platinum layer.
5. The back contact battery of claim 1, wherein the ratio of thicknesses of the silicon alloy layer and the metal conductive layer is 1:1-15;
and/or the number of the groups of groups,
the thickness of the silicon alloy layer is 2-7nm, and the thickness of the metal conductive layer is 5-30nm.
6. The back contact battery of claim 1, wherein the silicon alloy layer further comprises a doping element comprising boron or phosphorous.
7. The back contact cell of claim 6, wherein the ratio of the surface doping index of the silicon alloy layer to the first doped silicon crystal layer to the second doped silicon crystal layer is 1:30-1000:150-8000, wherein the in-plane doping index is the ratio of the effective doping concentration of the corresponding doped silicon layer to the thickness of the doped silicon layer.
8. The back contact cell of claim 7, wherein the silicon alloy layer has an effective doping concentration of 5e15 cm of doping element -3 -5e17cm -3 ；
And/or the number of the groups of groups,
the ratio of the thickness of the silicon alloy layer to the second doped silicon crystal layer is 0.04-0.6:1, a step of;
and/or the number of the groups of groups,
the thickness of the first doped silicon crystal layer is 50-300nm, and the effective doping concentration is 1e19 cm -3 -4e20 cm -3 The thickness of the second doped silicon crystal layer is 10-50nm, and the effective doping concentration is 1e19 cm -3 -4e20 cm -3 。
9. The back contact cell of claim 1, wherein the first semiconductor layer further comprises a first passivation layer disposed on the back side of the silicon wafer, at least a portion of the first passivation layer being located between the back side of the silicon wafer and the first doped silicon crystal layer.
10. The back contact cell of claim 9, wherein the second semiconductor layer further comprises a second passivation layer disposed on the back side of the silicon wafer, the second passivation layer being located between the back side of the silicon wafer and the second doped silicon crystal layer; the second passivation layer comprises a second intrinsic amorphous silicon layer or a second tunneling oxide layer, the thickness of the second intrinsic amorphous silicon layer is 5-15nm, and the thickness of the second tunneling oxide layer is 1.5-2.5nm;
Or,
the first passivation layer is arranged on the back surface of the silicon wafer in a full-coverage mode, the first doped silicon crystal layer and the second doped silicon crystal layer are both located on one side, far away from the back surface of the silicon wafer, of the first passivation layer, the second doped silicon crystal layer and a part of the first passivation layer covered by the second doped silicon crystal layer form a second semiconductor layer, and the first doped silicon crystal layer and the second doped silicon crystal layer are doped polycrystalline layers.
11. The back contact cell of claim 9, wherein the first passivation layer comprises a first tunneling oxide layer, the first doped silicon crystalline layer being a first doped polycrystalline layer; wherein,
the ratio of the thickness of the silicon alloy layer to the thickness of the first tunneling oxide layer is 1:0.05-1.25, and/or the thickness of the first tunneling oxide layer is 1.5-2.5nm.
12. The back contact battery of claim 1, wherein the extended end of the second semiconductor layer is in direct contact with the first semiconductor layer in the thickness direction or a mask layer is provided; and/or the width of the insulation groove is 0.05-0.3mm.
13. The back contact battery of claim 1, wherein the back contact battery is free of thin grids and main grids;
and/or the number of the groups of groups,
The back contact battery also comprises a front passivation layer which is arranged outwards on the front of the silicon wafer, wherein the front passivation layer is any one of third intrinsic amorphous silicon, third intrinsic amorphous silicon externally superimposed doped microcrystalline silicon, tunneling silicon oxide and tunneling silicon oxide externally superimposed doped polycrystalline silicon.
14. A method for preparing a back contact battery, comprising the steps of:
s1, forming a first semiconductor layer on the back surface of a silicon wafer, and forming first opening areas on the first semiconductor layer at intervals along the Y-axis direction of the silicon wafer; forming a second semiconductor layer on the back surface, and forming a second opening region on a part of the second semiconductor layer, which covers the outer surface of the first semiconductor layer; wherein the first semiconductor layer comprises a first doped silicon crystal layer and the second semiconductor layer comprises a second doped silicon crystal layer;
s2, sequentially forming a silicon alloy layer and a metal conductive layer on the back surface obtained in the step S1 through a magnetron sputtering process, wherein the sputtering power is controlled to be 5-12kW when the silicon alloy layer is formed, the sputtering power is controlled to be 1-4kW when the metal conductive layer is formed, and the square resistance of the obtained silicon alloy layer is 60-100The sheet resistance of the metal conductive layer is 3-50 +. >；
And S3, after the sputtering, performing third etching directly on the silicon alloy layer and the part of the metal conductive layer, which is positioned between the first opening area and the second opening area, so as to form an insulating groove.
15. According to claim 1The method for manufacturing a back contact battery according to 4, wherein the conditions of the magnetron sputtering process in S2 include: vacuum degree of 5X 10 -3 Pa- 5×10 -1 Pa, the sputtering time when the silicon alloy layer is formed is 10-60s, and the sputtering time when the metal conductive layer is formed is 30-300s;
and/or the number of the groups of groups,
the adopted metal target is at least one of nickel metal, aluminum metal, platinum metal, cobalt metal, titanium metal, tungsten metal, nickel-containing alloy, aluminum-containing alloy, platinum-containing alloy, cobalt-containing alloy, titanium-containing alloy and tungsten-containing alloy.
16. The method of claim 14, wherein the third etching in S3 uses a laser technology, and the laser used is a laser with a pulse width of picoseconds.
17. The method for manufacturing a back contact battery according to claim 14, wherein the process of S1 specifically includes:
s101, providing a silicon wafer;
s102, sequentially forming a first semiconductor layer and a mask layer on the back surface of the silicon wafer, wherein the first semiconductor layer comprises a first passivation layer and a first doped silicon crystal layer which are sequentially formed on the back surface;
S103, performing first etching on the first semiconductor layer and the mask layer in the back preset area obtained in the step S102 to form first opening areas which are distributed at intervals;
s104, removing all the residual mask layers;
s105, forming a second semiconductor layer on the back surface obtained in the step S104, wherein the second semiconductor layer comprises a second passivation layer and a second doped silicon crystal layer which are sequentially formed on the back surface;
and S106, performing second etching on the area with the first semiconductor layer remained on the back surface obtained in the step S105 so as to expose the first semiconductor layer and form a second opening area which is arranged with the first opening area.
18. The method for manufacturing a back contact battery according to claim 14, wherein the process of S1 specifically includes:
s11, providing a silicon wafer;
s12, sequentially forming a first semiconductor layer and a mask layer on the back surface of the silicon wafer, wherein the first semiconductor layer comprises a first passivation layer and a first doped silicon crystal layer which are sequentially formed on the back surface;
s13, performing first etching on the first doped silicon crystal layer and the mask layer in the back preset area obtained in the S12 to form first opening areas which are distributed at intervals;
s14, removing all the residual mask layers;
s15, forming a second doped silicon crystal layer on the back surface obtained in the step S14, wherein the second doped silicon crystal layer and a part of the first passivation layer covered by the second doped silicon crystal layer form a second semiconductor layer;
And S16, performing second etching on the area with the first semiconductor layer remained on the back surface obtained in the step S15 to expose part of the first semiconductor layer, so as to form a second opening area which is arranged with the first opening area.
19. A back contact battery, characterized in that it is manufactured by the manufacturing method of a back contact battery according to any one of claims 14-18.
20. A battery assembly comprising a back contact cell according to any one of claims 1-13, or comprising a back contact cell according to claim 19, and solder strips directly provided on the surface of the silicon alloy layer corresponding to the different conductive areas in the back contact cell.
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CN113745356A (en) * 2021-09-13 2021-12-03 福建金石能源有限公司 Multi-main-grid back-contact heterojunction solar cell and manufacturing method thereof
WO2022100081A1 (en) * 2020-11-10 2022-05-19 浙江爱旭太阳能科技有限公司 Highly efficient solar battery and preparation method therefor

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Publication number Priority date Publication date Assignee Title
US20110197957A1 (en) * 2008-10-14 2011-08-18 Kaneka Corporation Silicon-based thin film solar cell and method for manufacturing same
CN106784047A (en) * 2016-12-30 2017-05-31 苏州阿特斯阳光电力科技有限公司 The preparation method and its obtained battery of a kind of local doped crystal silicon solar cell
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CN113745356A (en) * 2021-09-13 2021-12-03 福建金石能源有限公司 Multi-main-grid back-contact heterojunction solar cell and manufacturing method thereof

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