CN117608861A

CN117608861A - CPU device of central processing unit

Info

Publication number: CN117608861A
Application number: CN202410076225.9A
Authority: CN
Inventors: 刘瑞楷; 葛蕾; 葛云飞; 马占刚
Original assignee: Shanghai Xinlianxin Intelligent Technology Co ltd
Current assignee: Shanghai Xinlianxin Intelligent Technology Co ltd
Priority date: 2024-01-18
Filing date: 2024-01-18
Publication date: 2024-02-27

Abstract

The embodiment of the application provides a Central Processing Unit (CPU) device, which relates to the technical field of computers and comprises: a control unit CU, an arithmetic logic unit ALU and a storage unit MU; the ALU comprises a plurality of operator modules; the CU is used for determining an operator calling sequence of an operation to be executed and sending the operator calling sequence and an operand in the operation to be executed to the ALU; the ALU is used for sequentially calling each operator module in the operator calling sequence to perform operation of a corresponding operand, obtaining an operation result of the operation to be executed, and storing the operation result into the MU. The operator calling sequence of the operation to be executed and the operands required by the operation to be executed are sent to the ALU through the control unit CU, and the operation to be executed can be completed once in the ALU when the ALU executes the operation to be executed, so that the reduction of the operation efficiency caused by the interaction of the ALU with the storage unit for many times is avoided.

Description

CPU device of central processing unit

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a CPU device of a central processing unit.

Background

Typical calculation forces in the CPU mainly originate from the ALU, and the ALU provides addition, subtraction, multiplication, division and other operations, and when the CPU performs the operations, a certain operation instruction in the ALU is actually called.

In the prior art, if there are multiple operations, the ALU can only complete one operation at a time, and output the operation result and then perform the next operation, which results in low calculation efficiency of the CPU; if other arithmetic units are used, the problems of memory wall and communication delay between data transmission are caused.

Disclosure of Invention

The embodiment of the application provides a Central Processing Unit (CPU) device for improving the operation efficiency of a CPU.

In a first aspect, an embodiment of the present application provides an arithmetic device of a central processing unit CPU, including:

a control unit CU, an arithmetic logic unit ALU and a storage unit MU; the ALU comprises a plurality of operator modules;

the CU is used for determining an operator calling sequence of an operation to be executed and sending the operator calling sequence and an operand in the operation to be executed to the ALU;

the ALU is used for sequentially calling each operator module in the operator calling sequence to perform operation of a corresponding operand, obtaining an operation result of the operation to be executed, and storing the operation result into the MU.

In the embodiment of the application, the control unit CU determines the operator calling sequence of the operation to be executed, so that the arithmetic logic unit ALU sequentially executes the operation to be executed according to the sequence of the logic operation, and the correctness of the operation result is ensured; the control unit CU sends the operator calling sequence of the operation to be executed and the operands required by the operation to be executed to the ALU, when the ALU executes the operation to be executed, the operation to be executed can be completed once inside the ALU without frequently interacting with the storage unit, and the operation result is stored in the MU after the operation to be executed is completed, so that the reduction of the operation efficiency caused by the interaction of the ALU with the storage unit for a plurality of times is avoided.

Optionally, the ALU also comprises an exchange module, an operator calling module and a sub-storage module which are communicated with each operator module;

the CU is also used for sending the operator calling sequence to the operator calling module and sending the operands in the operation to be executed to the sub-storage module;

the operator calling module is used for sequentially calling each operator module in the operator calling sequence to carry out operation of a corresponding operand;

the exchange module is used for sequentially communicating the adjacent operator modules indicated by the operator calling sequence and sending the sub-operation result of the previous operator module to the next operator module.

In the embodiment of the application, the exchange module is used for communicating the operator modules, so that the next operator operation can be continuously finished after the single operator operation is finished, the communication with a storage module outside an ALU is not needed, all the operator operations are finished in the ALU at one time, and the operation efficiency of the CPU is improved; the operator module is sequentially called through the operator calling module, so that the operation to be executed completes the operation of each operator according to the sequence of the logic operation, and the correctness of the operation to be executed is ensured; through the sub-storage module, operands in the operation to be executed are stored, so that operation data are prevented from being acquired from external equipment in the execution process of the operation to be executed, and the operation efficiency of the CPU is improved.

Optionally, the CU is further configured to send an internal operation enabling signal to the switching module;

and the exchange module is used for sequentially communicating the adjacent operator modules indicated by the operator calling sequence according to the internal operation enabling signal and the clock signal.

In the embodiment of the application, the internal operation enabling signal is sent to the exchange module, so that the exchange module communicates adjacent operators according to the operator calling sequence, and when the internal operation enabling signal is not sent, the operation is carried out according to the existing operation, so that the embodiment of the application can be controlled and implemented through the control signal, and the existing operation mode and the operation mode of the application are both achieved.

Optionally, the CU is specifically configured to send the operator calling sequence to the operator calling module through a first configuration signal; and sending the operands in the operation to be executed to the sub-storage module through a second configuration signal.

In the embodiment of the application, different tasks are completed according to different configuration signals, so that resource conflict caused by conflict between the signals is avoided, and the operation efficiency of the CPU is further affected.

Optionally, the CU is specifically configured to send the internal operation enabling signal after the first configuration signal and the second configuration signal.

In the embodiment of the application, the internal operation enabling signal is sent after the first configuration signal and the second configuration signal, so that the problem of operation error reporting caused by the fact that the ALU does not complete internal configuration after the internal operation enabling signal is sent is avoided.

Optionally, when the ALU is further configured to receive the internal operation enabling signal, sequentially execute each operator unit of the operation to be performed under the control of the CU, and store a sub-operation result of a single operator module into the MU.

In the embodiment of the application, when the internal operation enabling signal is not received, the operation to be executed is executed according to the operation mode of the single operator module, so that the situation that the operation cannot be completed when the ALU internal operation cannot be used is avoided; meanwhile, the original operation mode is reserved, and the operation can be completed without using ALU internal operation.

In a second aspect, an embodiment of the present application provides a method for operating a central processing unit CPU, where the method includes:

a control unit CU in the CPU determines an operator calling sequence of an operation to be executed and sends the operator calling sequence and an operand in the operation to be executed to an arithmetic logic unit ALU in the CPU;

and sequentially calling each operator module in the operator calling sequence by the ALU to perform operation of a corresponding operand to obtain an operation result of the operation to be executed, and storing the operation result into a storage unit MU in the CPU.

Optionally, sending the operator call sequence and the operands in the operation to be performed to an arithmetic logic unit ALU in the CPU, comprising:

the CU sends the operator calling sequence to an operator calling module in the ALU, and sends operands in the operation to be executed to a sub-storage module in the ALU;

the ALU sequentially calls each operator module in the operator calling sequence to perform operation of a corresponding operand, and the ALU comprises the following steps:

the operator calling module sequentially calls each operator module in the operator calling sequence to carry out operation of a corresponding operand;

and the exchange module in the ALU sequentially communicates adjacent operator modules indicated by the operator calling sequence and sends the sub-operation result of the previous operator module to the next operator module.

Optionally, before the exchange module in the ALU sequentially communicates the adjacent operator modules indicated by the operator calling sequence, the method further includes:

the CU sends an internal operation enabling signal to the exchange module; the internal operation enabling signal is used for triggering the switching module to be in a working mode.

Optionally, before the CU sends an internal operation enabling signal to the switching module, the CU further includes:

the CU sends the operator calling sequence to the operator calling module through a first configuration signal; and sending the operands in the operation to be executed to the sub-storage module through a second configuration signal.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it will be apparent that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a Central Processing Unit (CPU) device;

FIG. 2 is a first CPU device provided in an embodiment of the present application;

FIG. 3 is a second embodiment of a CPU device provided in the present application;

fig. 4 is a schematic diagram of an operation method of a CPU according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantageous effects of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

In order to facilitate understanding of the present solution, an application scenario of the present solution is described below.

The central processing unit (Central Processing Unit, CPU) includes: the control unit CU, the arithmetic logic unit (Arithmetic and Logic Unit), abbreviated as ALU), and the memory unit MU are an internal structure of the CPU as shown in fig. 1.

An ALU is a combinational logic circuit capable of implementing multiple sets of arithmetic operations and logic operations, which are circuit boards embedded in a computer CPU, using a gateway made of transistors to perform the mathematical and logic operations. The internal power of the CPU is mainly derived from the ALU. At the heart of the ALU is a digital combining circuit that performs arithmetic and bitwise functions on integer binary variables. If the CPU is a computer brain, then the ALU is its calculator, which is where the circuitry that performs arithmetic calculations on the information stored in the registers occurs.

The CU is another key component in the CPU, the CU is responsible for analyzing and executing the instruction, the CU acquires the instruction from the storage unit, the type of the analyzed instruction and the operation in the CPU are coordinated by the CU (control unit), the type and the operand of the instruction are analyzed, and then corresponding control signals are transmitted to other components, so that the CPU performs corresponding operation according to the instruction. The control unit may be regarded as a command center of the CPU, which ensures that the computer is able to execute instructions in the correct order, enabling a correct operation of the program.

MU is a high-speed memory in the CPU for storing data and instructions. The method is positioned in the CPU, and compared with a main memory, the method has the advantage that the MU access speed is faster, so that the data access efficiency can be improved. The CPU includes a plurality of MUs of different types, such as general purpose registers, program Counters (PCs), instruction Registers (IRs), and the like. These registers serve to temporarily store data and instructions during operation of the CPU.

When a logic operation is performed inside the CPU, such as a+b=c, the calculation process in the CPU is as follows:

the procedure for the C language is as follows:

Int a，b，c；

A = 1;

B = 2;

C = a + b;

the assembly code translated after compiling is as follows:

Allocate word memory *A；

Allocate word memory *B；

Allocate word memory *C；

Store_i 1, *A；

Store_i 2, *B；

Li reg1, 1；

Li reg2, 2 ；

Add reg3, reg2, reg1；

Store_r reg3, *C；

as can be seen from the above assembly code, when the logical operation a+b=c is performed, substantially only add instructions of ALUs in the CPU are called, the remaining instructions are completely prepared for versatility of the CPU, and the prepared instructions occupy most of time and resources. If a plurality of operators exist, the ALU needs to output the operation result of one operator, then takes the operation result of the last time as input when the operation of the next operator is performed until all operators complete the operation, and outputs a final result.

In a typical scenario requiring great computation power, such as graphics rendering, format conversion, encryption and decryption, and algorithms such as gradient descent, cross entropy, linear regression, sigmoid function, etc. required by machine learning in the artificial intelligence field, the combination of operations such as addition, subtraction, multiplication and division is also substantial, but the CPU is low in operation efficiency because ALU resources occupied in actual application are subjected to preparation work, and continuous input and output are subject to constraint of read-write time sequences between registers and conflict of operation resources.

When faced with this situation, the prior art employs the following approach: an acceleration unit is employed. The CPU is only responsible for handling scheduling tasks, and in particular the algorithm uses other acceleration units like GPU, DPU, NPU or other special ASIC etc. However, since other acceleration units are used, a problem of communication delay is likely to occur during data transmission, and data transmission is also hindered due to incompatibility when data transmission is performed with other acceleration units.

Therefore, the present application provides a CPU, in which a swap module, an operator calling module and a sub-storage module are added in an ALU, when the CPU processes some complex operations, the CPU firstly stores the operands to be operated in the sub-storage module in the ALU, and the swap module in the ALU communicates adjacent operator modules according to the operator calling sequence, thereby completing the operation on the operands at one time.

Referring to fig. 2, an internal structure of a CPU according to an embodiment of the present application includes: a control unit CU, an arithmetic logic unit ALU and a storage unit MU; the ALU comprises a plurality of operator modules; the CU is used for determining an operator calling sequence of the operation to be executed and sending the operator calling sequence and an operand in the operation to be executed to the ALU; the ALU is used for sequentially calling each operator module in the operator calling sequence to perform operation of corresponding operands, obtaining an operation result of operation to be executed, and storing the operation result into the MU.

Specifically, the operation to be executed is an operation to be processed in the CPU, and the operators in the operation to be executed correspond to respective operator modules respectively. In an operation where there are a plurality of operators, the CU needs to determine the operator calling order of the operation to be performed and the operands in the operation to be performed, and send the determined result to the ALU. And the ALU sequentially calls operator modules corresponding to the operators according to the operator calling sequence determined in the CU to operate the operands, and the operation result is obtained and stored in the MU.

For example, the operations to be performed may be a+b=c, or, (a+b) ×c=d, etc., where "+", "×" are different operators, corresponding to "add operator module" and "multiply operator module", respectively. In the operation to be performed (a+b) ×c=d, the operator calling order is "+" then "×", the operands are "a", "b", and "c", and the CU sends the operator calling order "first ' + ' then ' +" and the operands "a", "b", and "c" to the ALU.

After the ALU receives the operator calling sequence and the operands, the ALU firstly performs addition operation on the operands "a" and "b" corresponding to the addition operator, then performs multiplication operation on the operands "c" corresponding to the multiplication operator, obtains an operation result "d", and stores the operation result "d" in the MU.

In some embodiments, as shown in fig. 3, the ALU further includes a swap module, an operator call module, and a sub-storage module that are in communication with each operator module; the CU is also used for sending the operator calling sequence to the operator calling module and sending the operands in the operation to be executed to the sub-storage module; the operator calling module is used for sequentially calling each operator module in the operator calling sequence to carry out operation of the corresponding operand; the exchange module is used for communicating adjacent operator modules indicated by the operator calling sequence in sequence and sending the sub-operation result of the previous operator module to the next operator module.

Specifically, the ALU comprises a swap module, an operator calling module and a sub-storage module. The CU determines the operator calling sequence of the operation to be performed and the operands in the operation to be performed, and sends the determined result to the ALU. The sub-storage module in the ALU stores operands in the operation to be executed, the operator calling module sequentially calls each operator module according to the operator calling sequence, the exchange module communicates adjacent operator modules, and meanwhile sub-operation results of the previous operator module are sent to the next operator module.

The switching modules may be CROSSBAR, CROSSBAR referred to as crossbar or crossbar, and switches based on bus structures are generally classified into two general categories, shared bus and shared memory bus. Firstly, the cross SBAR is relatively simple to realize, the physical connection from the line card in the shared switching architecture to the switching structure is simplified to be point-to-point connection, the realization is more convenient, and the stability of the high-capacity switch is easier to ensure. Second, the cross-bar is internally non-blocking, and as long as one cross-bar closes multiple cross-nodes (cross-points) simultaneously, multiple different ports can transmit data simultaneously. In this sense, all cross-sbars are considered to be non-blocking internally, as it can support all ports to exchange data at the same time. In addition, it can operate at very high rates due to its simple implementation principle and non-blocking switching architecture.

For example, the CU sends operator calls in order of "+" then "+" to the operator call module in the ALU, where the sub-memory modules in the ALU store operands "a", "b" and "c". The operator calling module calls the addition operator module according to the operator calling sequence of "+" and "+" afterwards ", then calls the multiplication operator module, and carries out operation according to the operands" a "," b "corresponding to the addition operator module and the operand" c "corresponding to the multiplication operator module. In the operation to be performed (a+b) ×c=d, the sub-operation result of the addition operator module corresponding to "+" is "a+b", and the sub-operation result of the multiplication operator module corresponding to "+" is "d". Before ALU carries out operation, the CROSSBAR communicates the addition operator module with the multiplication operator module according to the operator calling sequence of "+" then "+", and sends the sub operation result of the addition operator module to the multiplication operator module.

In some embodiments, as shown in fig. 3, the CU is further configured to send an internal operation enable signal to the switching module; the exchange module is used for communicating adjacent operator modules indicated by the operator calling sequence according to the internal operation enabling signal and the clock signal in sequence.

Specifically, the CU may also determine whether to send an internal operation enabling signal to the switch module according to an actual need, and if the switch module receives the internal operation enabling signal, this means that the ALU starts an internal operation function, and the ALU needs to sequentially communicate adjacent operator modules indicated by the operator calling sequence according to a clock signal. If the exchange module does not receive the internal operation enabling signal, the ALU does not start the internal operation function, and the ALU executes the operation to be executed according to the existing mode.

The clock signal is the basis of sequential logic to determine when the state in the logic cells is updated, and is a fixed period, operation independent semaphore. The clock signal has a fixed clock frequency, which is the inverse of the clock period. In an electronic, in particular signal, synchronous digital circuit, a clock signal is the high and low states between oscillations of a particular signal of the signal, the utilization of the signal acting in concert like a metronome, the digital clock signal being essentially a square wave voltage. The clock signal is generated by a clock generator. It has only two levels, one being a low level and the other being a high level. The high level may be different depending on the requirements of the circuit, for example, the high level of the TTL standard is 5V.

For example, to perform the operation (a+b) ×c=d, if the CU sends an internal operation enabling signal to the ALU, the ALU starts the internal operation function, the cross bar communicates the addition operator module and the multiplication operator module, and the sub-operation result of (a+b) is sent to the multiplication operation module and multiplied by the operand "c" to obtain the operation result.

In some embodiments, as shown in fig. 3, the CU is specifically configured to send the operator calling order to the operator calling module through the first configuration signal; and sending the operands in the operation to be executed to the sub-storage module through a second configuration signal.

Specifically, the CU sends an operator calling sequence to an operator calling module in the ALU through a first configuration signal; the CU sends operands in the operation to be executed to a memory module inside the ALU through a second configuration signal.

For example, in fig. 3, to perform the operation (a+b) ×c=d, the CU sends the operator call sequence of "+" and then "×to the operator call module in the ALU through the first configuration signal, and the CU sends the operands" a ", the operand" b ", the operand" c ", and the operand" d "to the sub-memory module in the ALU through the second configuration signal.

In some embodiments, the CU is specifically configured to send the internal operation enable signal after the first configuration signal and the second configuration signal.

Specifically, after the CU sends the first configuration signal and the second configuration signal, that is, after the operator calling module in the ALU receives the operator calling sequence, and the sub-storage module completes storing the operands in the operation to be performed, the CU sends the internal operation enabling signal.

In some embodiments, the ALU is further configured to sequentially execute each operator unit of the operation to be performed under the control of the CU when the internal operation enabling signal is not received, and store the sub-operation result of the single operator module into the MU.

Specifically, when the ALU does not receive the internal operation enabling signal sent by the CU, the CU controls the execution sequence of each operator unit to be operated, and the sub-operation result of the single operator module is stored in the MU.

For example, in the operation (a+b) ×c=d to be executed, if the CU does not send an internal operation enabling signal to the ALU, and the ALU does not start the internal operation function, the CU controls the operation sequence of (a+b) ×c=d, and outputs and stores the sub-operation result of the single operator module addition operator module into the MU, that is, the operation result of (a+b), and then obtains the operation result of (a+b) and the operation of the next single operator module multiplication operator module from the MU, so as to obtain the operation result "d", and stores "d" into the MU.

The embodiment of the present application provides an operation method of a central processing unit CPU, as shown in fig. 4, taking an operation (a+b) to be performed as an example, c=d, including the following steps:

step 401, the CU sends a first configuration signal, where the first configuration signal is used to determine the calling order of the operators, and is "+" before "×".

Step 402, the CU sends a second configuration signal, where the second configuration signal is used to store an operand "a", an operand "b", an operand "c", and an operand "d" in the to-be-executed operation into the sub-storage module.

Step 403, the CU transmits an internal operation enable signal.

Step 404, the cross bar communicates the addition operator module and the multiplication operator module.

Step 405, the operator calling module obtains the operands "a" and "b" corresponding to the addition operator module from the sub-storage module.

And 406, calling an addition operator module to add the operand "a" and the operand "b" to obtain a sub-operation result of the operand "(a+b)".

Step 407, call the multiplication operator module, and operate the sub-operation result of "(a+b)" and the operand "c", so as to obtain the operation result of "(a+b) ×c=d".

Step 408, the operation result of "(a+b) ×c=d" is sent to the memory unit MU.

In step 409, the memory unit MU stores the result of the operation "(a+b) ×c=d".

Claims

1. A central processing unit, CPU, comprising: a control unit CU, an arithmetic logic unit ALU and a storage unit MU; the ALU comprises a plurality of operator modules;

the ALU is used for sequentially calling each operator module in the operator calling sequence to perform operation of a corresponding operand, obtaining an operation result of the operation to be executed, and storing the operation result into the MU;

the ALU also comprises an exchange module, an operator calling module and a sub-storage module which are communicated with each operator module;

2. The apparatus of claim 1, wherein the CU is further to send an internal operation enable signal to the switching module;

3. The apparatus of claim 2, wherein the CU is specifically configured to send the operator call sequence to the operator call module via a first configuration signal; and sending the operands in the operation to be executed to the sub-storage module through a second configuration signal.

4. The apparatus of claim 3, wherein the CU is specifically configured to send the internal operation enable signal after the first configuration signal and the second configuration signal.

5. The apparatus of claim 2, wherein the ALU is further configured to sequentially execute each operator unit of the operation to be performed under the control of the CU and store a sub-operation result of a single operator module into the MU when the internal operation enable signal is not received.

6. A method for operating a central processing unit CPU, the method comprising:

7. The method of claim 6, wherein sending the operator call order and operands in the operation to be performed to an arithmetic logic unit, ALU, in the CPU comprises:

8. The method of claim 7, wherein before sequentially communicating adjacent operator modules indicated by the operator call order by the switch module in the ALU, further comprising:

9. The method of claim 8, wherein before the CU sends an internal operation enable signal to the switching module, further comprising: