CN117596118A - Arbitrary symbol rate OQPSK modulation signal generation device based on lookup table - Google Patents

Arbitrary symbol rate OQPSK modulation signal generation device based on lookup table Download PDF

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Publication number
CN117596118A
CN117596118A CN202311474583.7A CN202311474583A CN117596118A CN 117596118 A CN117596118 A CN 117596118A CN 202311474583 A CN202311474583 A CN 202311474583A CN 117596118 A CN117596118 A CN 117596118A
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symbol
signal
shaping filter
oqpsk
path
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方金辉
宋哲
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Beijing Shaobing Technology Co ltd
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Beijing Shaobing Technology Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/36—Modulator circuits; Transmitter circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20—Modulator circuits; Transmitter circuits
    • H04L27/2003—Modulator circuits; Transmitter circuits for continuous phase modulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

The invention discloses a random symbol rate OQPSK modulation signal generating device based on a lookup table, which comprises an OQPSK address accumulator, a data buffer, a shaping filter lookup table and a fractional sampling point interpolator, wherein the OQPSK address accumulator is used for generating sampling time address information delta of symbol data, the data buffer is used for buffering the data input by a data source and outputting corresponding symbol data b according to the sampling time address information given by the OQPSK address accumulator; the shaping filter lookup table is used for storing shaping filter coefficients g and outputting corresponding shaping filter signals according to sampling time address information; the fractional sample point interpolator is used for calculating the sampling value of a given interpolation position according to the output symbol data b of the buffer and the shaping filter signal g so as to generate an I path or Q path arbitrary symbol rate OQPSK modulation signal. Thus, OQPSK signals with IQ two paths and arbitrary symbol rate can be generated, and the method is simple to realize and is suitable for a satellite wireless communication system.

Description

Arbitrary symbol rate OQPSK modulation signal generation device based on lookup table
Technical Field
The invention relates to the technical field of communication, in particular to a device for generating an OQPSK modulation signal with any symbol rate based on a lookup table.
Background
The Offset Quadrature Phase Shift Keying (OQPSK) modulation signal is one of constant envelope modulation modes, is less affected by system nonlinearity, and has higher bandwidth utilization rate and power utilization rate. The realization process is that the zero crossing point generated by the simultaneous jump of two paths of signals is avoided by shifting the IQ two paths of code elements of QPSK signals by half a symbol period, thereby having smaller envelope fluctuation and better performance for resisting nonlinear distortion. Meanwhile, the channel conditions in satellite communication are complex and variable, and it is required to reduce the symbol rate under severe channel conditions to improve the reliability and robustness of signals, and to increase the symbol rate under good channel conditions to improve the data transmission rate. The traditional integer-times oversampling structure needs to ensure that the hardware working clock is an integer multiple of the symbol rate, which is unfavorable for meeting the design requirement of the communication system, so that an OQPSK modulation signal generation method with arbitrarily adjustable symbol rate needs to be designed.
The key to achieving the generation of an OQPSK modulated signal at an arbitrary rate is the rate digital shaping filtering. The variable rate shaping filtering commonly used at present mainly has two ideas, and the first is to switch different rate gears through keying and flexibly adjust the structure of a transmitting end. The second is done based on interpolation, decimation and anti-aliasing filtering. By interpolating and decimating a signal of a certain symbol rate, a signal of an arbitrary symbol rate can be theoretically constructed.
However, the currently used variable rate digital shaping filtering techniques have at least two major disadvantages. First, while theoretically interpolation and decimation can construct a signal of any symbol rate, it does not actually enable shaped filtering of continuously variable symbol rates, as with keying structures, due to computational resource limitations. Second, the signal constructed by interpolation and extraction has a certain time domain distortion although it has an equivalent arbitrary symbol rate.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems in the related art to some extent. To this end, an object of the present invention is to propose an arbitrary symbol rate OQPSK modulated signal generation apparatus based on a look-up table.
To achieve the above object, a look-up table-based arbitrary symbol rate OQPSK modulated signal generation apparatus according to an embodiment of the present invention includes:
the OQPSK address accumulator is used for generating sampling time address information of the symbol data, and the sampling time address information comprises sampling time address information of the I path symbol data and sampling time address information of the Q path symbol data;
the data buffer is used for buffering the symbol data and outputting corresponding symbol data b according to the sampling time address information;
The shaping filter lookup table is used for storing shaping filter coefficients g and outputting corresponding shaping filter signals g according to the sampling time address information;
and the fractional sampling point interpolator is used for calculating sampling values of given interpolation positions according to the output symbol data b of the data buffer and the shaping filter signal g so as to generate an I-path or Q-path arbitrary symbol rate OQPSK modulation signal.
Further, according to an embodiment of the present invention, the OQPSK address accumulator includes:
the system comprises an I-path accumulator and a Q-path accumulator, wherein each path of accumulator comprises a single-path symbol initial value accumulator and a 32-path parallel symbol rate control accumulator, the main difference between the I-path accumulator and the Q-path accumulator is the initialization assignment of the single-path symbol initial value accumulator, the I-path assignment is 0.5, and the Q-path is 0;
the single-path symbol initial value accumulator is used for generating initial value sampling time address information AccIni; the 32-path parallel symbol rate control accumulator is a parallel address accumulator, and the parallel address accumulator accumulates based on an initial single-path symbol initial value accumulator AccIni to generate sampling time address information of the 32-path symbol data; wherein the difference of the values between the parallel address accumulators of each path is R s /F smp ；
Wherein R is s For symbol rate, F smp Is the sampling frequency.
The OQPSK address accumulator includes two address accumulators. The address accumulators of the I path and the Q path are respectively provided with 32 paths of outputs, and the k path outputs of the address accumulators at the nth sampling point are AccQ respectively k (n) and AccQ k (n) the expression:
wherein the method comprises the steps ofF clk For the frequency of the working clock, F clk ＝32*F smp
Further, according to an embodiment of the present invention, the arbitrary symbol rate OQPSK modulated signal generation apparatus further includes:
and the baseband signal sampling control module is used for updating the control signal Rfd according to the sampling time address information so as to update the symbol data stored in the data buffer through the control signal Rfd.
And the Rfd signal is pulled Gao Yici at the overflow moment of the 32 nd accumulator of the 32-path parallel symbol rate control accumulator to finish one baseband data fetch, and the Rfd signal and the shaping filter signal g are multiplied and added to obtain the baseband OQPSK symbol output at the current moment.
Further, according to an embodiment of the present invention, the data buffer includes:
the first-stage Fifo is used for carrying out first-in first-out buffer memory on the symbol data output by the signal source, outputting the buffered symbol data under the action of a first-stage Fifo reading enabling signal pair, and the condition that the first-stage Fifo is not empty is obtained and the enabling is effective;
The second stage Fifo is used for carrying out first-in first-out buffer storage on the symbol data output by the first stage Fifo and outputting buffer symbol data under the action of the update control signal Rfd;
and the cyclic shift memory is used for caching the symbol data output by the second stage Fifo and outputting corresponding symbol data according to the sampling time address information.
Further, according to an embodiment of the present invention, the data buffer further includes:
and the accumulation trigger is used for generating a reading enabling signal of the first stage Fifo according to the updating control signal Rfd so as to output buffer symbol data of a given frame length data quantity.
Further, according to an embodiment of the present invention, the look-up tables of the shaping filter are divided into six groups of look-up tables, and a complete 1024-fold oversampled root raised cosine shaping filter is evenly distributed into the six groups of look-up tables, where the six groups of look-up tables include:
the first shaping filter lookup table is used for storing shaping filter quantized values of a first symbol and outputting corresponding first shaping filter quantized values according to the sampling time address information;
The second molding filter lookup table is used for storing the molding filter quantized value of the second symbol and outputting the corresponding second molding filter quantized value according to the sampling time address information;
the third shaping filter lookup table is used for storing shaping filter quantized values of a third symbol and outputting corresponding third shaping filter quantized values according to the sampling time address information;
a fourth shaping filter lookup table, which is used for storing shaping filter quantized values of a fourth symbol and outputting corresponding fourth shaping filter quantized values according to the sampling time address information;
a fifth shaping filter lookup table, which is used for storing shaping filter quantized values of a fifth symbol and outputting corresponding fifth shaping filter quantized values according to the sampling time address information;
and the sixth shaping filter lookup table is used for storing shaping filter quantized values of a sixth symbol and outputting corresponding sixth shaping filter quantized values according to the sampling time address information.
Further, according to an embodiment of the present invention, the fractional sample point interpolator includes:
the QPSK modulator multiplexes the QPSK modulator structure when the OQPSK modulated signal is subjected to constellation mapping, and is used for carrying out QPSK modulation according to the symbol data output by the cyclic shift memory;
a first multiplier for multiplying the first symbol modulation signal output from the QPSK modulator with the quantized value of the first shaping filter and outputting a first interpolation signal;
a second multiplier for multiplying the second symbol modulation signal output from the QPSK modulator with the quantized value of the second molding filter and outputting a second interpolation signal;
a third multiplier for multiplying the third symbol modulated signal output from the QPSK modulator with the third shaping filter quantized value and outputting a third interpolation signal;
a fourth multiplier for multiplying the fourth symbol modulation signal output from the QPSK modulator with the fourth shaping filter quantization value and outputting a fourth interpolation signal;
a fifth multiplier for multiplying the fifth symbol modulation signal output from the QPSK modulator with the quantization value of the fifth shaping filter and outputting a fifth interpolation signal;
A sixth multiplier for multiplying the sixth symbol modulated signal output from the QPSK modulator with the quantized value of the sixth shaping filter and outputting a sixth interpolation signal;
the adder is used for carrying out addition operation on the first interpolation signal, the second interpolation signal, the third interpolation signal, the fourth interpolation signal, the fifth interpolation signal and the sixth interpolation signal and outputting the I path or Q path arbitrary symbol rate OQPSK modulation signals; the first symbol modulation signal, the second symbol modulation signal, the third symbol modulation signal, the fourth symbol modulation signal, the fifth symbol modulation signal and the sixth symbol modulation signal are respectively modulation signals which are adjacent and consistent.
Further, according to an embodiment of the present invention, the shaping filter amount g is 1024 times of the oversampled root raised cosine filter, the filter length is adjacent 6 symbols, and the filter shaping coefficient support is set online.
Further, according to an embodiment of the present invention, the arbitrary symbol rate OQPSK modulated signal I/Q is output as:
wherein,T s for the symbol period, the sampling sequence n=1, 2.
And calculating an approximation value of a given interpolation position for a real analog waveform through interpolation processing of shaping filter coefficients of adjacent 6 symbols and high oversampling multiples, thereby generating high-precision OQPSK signal output.
Further, according to an embodiment of the present invention, the time domain waveform of the prototype analog signal corresponding to the symbol pulse sequence is a PCM signal, supporting common PCM patterns such as NRZ-L, NRZ-S and NRZ-M.
The embodiment of the invention provides a random symbol rate OQPSK modulation signal generating device based on a lookup table, wherein the OQPSK modulation signal generating device is used for generating sampling time address information of symbol data through an OQPSK address accumulator, and the sampling time address information comprises sampling time address information of I path symbol data and sampling time address information of Q path symbol data; the data buffer is used for buffering the symbol data and outputting corresponding symbol data b according to the sampling time address information; the shaping filter lookup table is used for storing a shaping filter G and outputting a corresponding shaping filter signal according to the sampling time address information; the fractional sampling point interpolator is used for calculating sampling values of given interpolation positions of the symbol data b and the shaping filter signal g according to the shaping filter signal so as to generate I-path or Q-path arbitrary symbol rate OQPSK modulation signals, thus generating IQ-path two-path arbitrary symbol rate parallel OQPSK signals and realizing stable and accurate OQPSK digital modulation. Because the interpolation position is calculated through the accumulator, the symbol rate is continuously variable, and the interpolation for approaching the real analog signal is directly calculated according to the interpolation position, the difference of the symbol rate of the transmitted signal compared with the set value is small, the communication requirement is met, the implementation is simple, the interface is flexible, and the method is suitable for a satellite wireless communication system.
Drawings
Fig. 1 is a block diagram of a look-up table-based arbitrary symbol rate OQPSK modulated signal generation apparatus according to an embodiment of the present invention;
FIG. 2 is a block diagram of a signal source and a buffer according to an embodiment of the present invention;
fig. 3 is a block diagram of an OQPSK address accumulator according to an embodiment of the present invention;
FIG. 4 is a block diagram of a look-up table of a shaping filter according to an embodiment of the present invention;
FIG. 5 is a block diagram of a fractional sample point interpolator according to an embodiment of the present invention;
fig. 6 is a waveform diagram of an OQPSK signal generated by the apparatus for generating an OQPSK modulated signal at an arbitrary symbol rate based on a lookup table according to an embodiment of the present invention.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
In order to enable those skilled in the art to better understand the present invention, the following description will make clear and complete descriptions of the technical solutions according to the embodiments of the present invention with reference to the accompanying drawings. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Referring to fig. 1, an embodiment of the present invention provides a device for generating an OQPSK modulated signal at an arbitrary symbol rate based on a lookup table, including: the system comprises a data and buffer, an OQPSK address accumulator, a shaping filter lookup table and a fractional sampling point interpolator, wherein the data buffer is used for buffering data input by a data source and outputting corresponding symbol data b according to sampling time address information given by the OQPSK address accumulator; the OQPSK address accumulator is used for generating sampling time address information delta of the symbol data, wherein the sampling time address information comprises sampling time address information of I path symbol data and sampling time address information of Q path symbol data; the shaping filter lookup table is used for storing shaping filters G and outputting corresponding shaping filter signals G according to the sampling time address information delta; the fractional sampling point interpolator is used for calculating sampling values of given interpolation positions according to the buffer output symbol data b and the shaping filter signal g so as to generate an I path or Q path arbitrary symbol rate OQPSK modulation signal. .
Specifically, in the embodiment of the invention, the time domain expression of the analog signal at any moment is approximated by interpolating the digital signal by using the fixed shaping filter lookup table and the data in the data buffer. For the generation process of signals with any symbol rate, since the hardware working clock and the symbol rate do not always have an integral multiple relationship, the shaping filter output analog signal sampling value at any moment needs to be considered, and the expression is as follows:
y(nT smp )＝y(mT s +δ)；
wherein T is smp For sampling period, T s For the symbol period, δ is a fraction with a value between 0 and 1. The right hand side of the equal sign shows a signal that can be digitized for m. The shaped filtered output signal may be represented as a convolution of the input signal and the shaping filter. Namely:
taking root cosine filter shaping as an example, a digital filter of 6 symbols in length is typically used to approximate the prototype filter. So for the mth symbol, only 6 symbols around it are taken for summation. Since b (n) is the prototype analog signal of the pulse train, its time domain waveform is a square wave, i.e. b (kT) s +δ)＝b(kT s ) Therefore, there are:
wherein nT is smp ＝mT s +δ, therefore there are:
to improve the signal processing capability, a parallel processing architecture is considered here. For N-channel parallel digital shaping filter, there is a sampling period between working clock and sampling period The above can be rewritten as:
wherein N is the number of parallel paths, ts is the symbol period, T clk For working clock cyclePhase, sampling sequence n=1, 2,..n. [.]Represents rounding down, { } represents taking a fraction.
As above principleThe shaping filter lookup table may include 6 lookup tables that respectively represent 6 symbols in the shaping filter. The shaping filter stored in the six look-up tables is a high precision filter time domain waveform generated with high oversampling multiples. The root cosine filter may be selected as a shaped digital filter and a digital filter of 6 symbols in length may be used to approximate the prototype filter. For each digital signal taken out of the data buffer, a determined delta value is required to determine the sample value of the shaping filter G multiplied by it. The OQPSK address accumulator can obtain decimal delta with arbitrary precision after bit cutting d By inputting these 6 lookup tables, respectively, it is possible to output the sample values of the waveform at the interpolation position for the 6 symbols before and after the given interpolation position.
The OQPSK address accumulator is used for sampling the symbol data by the I path and the Q path which are generated by accumulation. The I-path address and the Q-path address adopting the time address information finish rounding through high cut bits And obtaining an address signal of the read data buffer, inputting the address signal into the data buffer, reading the values of the 6 symbol data b before and after a given interpolation position, and outputting the values to the fractional sampling point interpolator.
In addition, the OQPSK address accumulator takes the fractional portion δ=nt by accumulating the generated I-way and Q-way addresses using the time address information by low-cut bits smp -mT s And obtaining an address signal for reading the shaping filter, inputting the address signal into a shaping filter lookup table, reading trailing values of waveforms formed by 6 symbols before and after a given interpolation position at the given interpolation position, and outputting a shaping filter signal g to a fractional sampling point interpolator.
Respectively acquiring the interpolation position before and afterAfter 6 symbol data b and shaping filter signal g corresponding to interpolation position, the output signals of the data buffer and the shaping filter lookup table are connected into the fractional sampling point interpolator according to the formulaThe logarithmic value at a given interpolation position is calculated to approximate the analog waveform after the symbol signal has passed through the shaping filter by means of a digital signal. Thus, the signal b [ (m+i) T after QPSK modulation of the parallel 6-channel symbol signal b s ]Respectively with the outputs g (iT s +delta), then an I-path or Q-path arbitrary symbol rate OQPSK modulated signal can be generated.
In the embodiment of the invention, the interpolation position is calculated through the OQPSK address accumulator, the symbol rate is continuously variable, the approximate interpolation of the analog signal is directly calculated according to the interpolation position, and the symbol rate of the transmitted signal is strictly equal to the set value, so that the accuracy is higher. Compared with the prior art that the variable symbol rate transmission of the OQPSK signal is not considered, the variable rate interpolation is usually needed to be carried out firstly, and then the OQPSK modulation is carried out. Any rate precision can be achieved only by a small amount of computing resources, and the computing resources are saved; can meet the design requirements of various communication systems. The embodiment of the invention is based on the communication requirements of nonlinear distortion resistance and variable symbol rate in satellite communication, combines the application background of high-rate satellite communication, breaks through the technical bottlenecks of discontinuous and variable symbol rate and time domain distortion of the OQPSK modulation signal, develops an OQPSK high-speed parallel digital forming filtering algorithm based on any symbol rate, and realizes stable and accurate OQPSK digital modulation.
Referring to fig. 2 to 4, the OQPSK address accumulator includes: the system comprises a Q-group address accumulator and an I-group address accumulator, wherein the Q-group address accumulator comprises a single-way accumulator and a Q-group multi-way address accumulator, and the single-way accumulator is used for generating initial value sampling moment address information AccIni; the Q group of multi-path address accumulators are parallel address accumulators which accumulate based on an initial single-path accumulator AccIni to generate the Q paths Sampling time address information of symbol data; wherein each Q-group multi-path address accumulator has self increment of R per clock cycle s /F clk The difference of the values between the parallel address accumulators of each path is R s /F smp ；
The I-group address accumulator comprises an I-group multi-path address accumulator, the I-group multi-path address accumulator is a parallel address accumulator, and the parallel address accumulator accumulates based on an initial single-path accumulator AccIni to generate sampling time address information of the I-path symbol data; wherein the self increment of the first path of the I-group multi-path address accumulator is half of a symbol period, and the self increment of each clock period of the rest I-group multi-path address accumulators is R s /F clk The difference of the values between the parallel address accumulators of each path is R s /F smp The method comprises the steps of carrying out a first treatment on the surface of the Wherein R is s For symbol rate, F clk For the frequency of the working clock, F smp For sampling frequency F clk ＝N*F smp N is the number of parallel ways.
As shown in fig. 1, the OQPSK address accumulator is used to generate sampling instants, nT, for the analog signal smp . For N-way parallel shaping filter, there is N-way address accumulator
Each accumulation module will output the integer m and fractional part delta of the current interpolation position. For the generation of OQPSK signals, a 32-way parallel structure is taken as an example, because of I, Q; there is a half symbol period time delay between the two signals, and two sets of address accumulators I, Q with 32 paths of initial accumulator values differing by half symbol period are required to be set. The parallel address accumulator accumulates based on an initial one-way accumulator AccIni, which self-increments by R each clock cycle s /F clk The initial value is 0. The difference of the values between the parallel address accumulators of each path is R s /F smp Thus, the interpolation position mT is constructed smp . AccIni is input into an I-path address accumulator after 0.5 increment, and the interpolation position of the I-path can be controlled to be nT smp +0.5, the interpolation position between the I, Q two signals is shifted by half a symbol period. AccI32 and AccQ32 are respectively input into two baseband signal access control modules, and when the judging device judges that the value of the baseband signal access control module in the next clock period is greater than 8, the updating judging signal is set high; the OQPSK address accumulator includes two address accumulators. The address accumulators of the I path and the Q path are respectively provided with 32 paths of outputs, and the k path outputs of the address accumulators at the nth sampling point are AccQ respectively k (n) and AccQ k (n) the expression:
wherein the method comprises the steps ofF clk For the frequency of the working clock, F clk ＝32*F smp 。
As shown in fig. 2 and 3, the 32-way parallel address accumulator signals AccI and AccQ are rounded up through high-cut bits, so as to obtain an address signal Index of a read Cache, the Index signal is input into a cyclic shift memory in the data buffer of fig. 2, the values of 6 symbols before and after a given interpolation position are read, and the values of 6 symbols are output in parallel through data 1-32, wherein each data comprises the value of 6 symbols;
the 32 paths of parallel address accumulator signals AccI and AccQ are subjected to decimal part extraction through low-cut bits, address signals Addr for reading a shaping filter LUT are obtained, the Addr signals are input into a shaping filter lookup table, the lookup table structure is shown in figure 4, trailing values of waveforms formed by 6 symbols before and after a given interpolation position are read at the given interpolation position, and the trailing values are output through g in parallel. The embodiment of the invention directly generates the OQPSK signal with variable symbol rate by adding 0.5 offset between the I, Q two-path address accumulators.
Referring to fig. 1, the apparatus for generating an arbitrary symbol rate OQPSK modulated signal further includes: and the baseband signal sampling control module is used for updating the control signal Rfd according to the sampling time address information so as to update the symbol data stored in the data buffer through the control signal Rfd. The baseband signal fetch control module judges whether the data buffer needs to be updated according to the value in the address accumulator. In each clock cycle, the judging device judges whether the value in the data buffer is required to be updated in the next clock cycle according to the value of the last path in the parallel address accumulator, so that the updating control of the stored coincidence data of the data buffer is realized.
Referring to fig. 2 and 3, the data buffer includes: the first-stage Fifo is used for carrying out first-in first-out buffer storage on the symbol data output by the signal source, and outputting buffer symbol data under the action of a first-stage Fifo reading enabling signal pair;
the second stage Fifo is configured to perform first-in first-out buffering on the symbol data output by the first stage Fifo, and output buffered symbol data under the effect of the update control signal Rfd; the cyclic shift memory is used for caching the symbol data output by the second stage Fifo and outputting corresponding symbol data according to the sampling time address information.
The data buffer further includes an accumulation trigger, which is configured to generate a read enable signal of the first stage Fifo according to the update control signal Rfd, so as to output buffered symbol data with a given frame length data size. As shown in fig. 2, the data source and data buffer generate symbol data for interpolation. Namely b [ (m+i) T) as described in the above principle s ]Is a symbol data b of (a). In addition, the data buffer needs to store and output signals at different rates for different symbol rates. The data buffer outputs a set of signals for interpolation whenever the update signal output by the baseband signal fetch control module is valid. In this way, real-time interpolation can be done for a given rate of data flow. For example, a 0-1 information sequence is generated at the data source, and source coding, framing, etc., signal source number is performedThe symbol rate of the data stream is denoted as R s The method comprises the steps of carrying out a first treatment on the surface of the The connection relationship between the data source and the data buffer is shown in fig. 2, where the signal generated by the data source enters the first stage Fifo in the data buffer, and the read enable signal of the first stage Fifo is the valid period counter of Rfd. Fifo1 outputs data of a given frame length data amount each time the read enable signal is valid; the signal of Fifo1 enters Fifo2, the reading enabling signal of Fifo is the output signal of baseband signal fetch control module, fifo2 outputs 8 signals to enter the cyclic shift memory each time the reading enabling signal is valid. As shown in fig. 3, the 32-way parallel address accumulator signals AccI and AccQ are rounded by high cut bits, to obtain an address signal Index for reading the cyclic shift memory, the Index signal is input to the cyclic shift memory in the data buffer of fig. 2, the values of 6 symbols before and after a given interpolation position are read, and output in parallel through data.
Referring to fig. 4, the shaping filter lookup table includes: a first shaping filter lookup table, a second shaping filter lookup table, a fourth shaping filter lookup table, a fifth shaping filter lookup table, and a sixth shaping filter lookup table; the first shaping filter lookup table is used for storing shaping filter quantized values of a first symbol and outputting corresponding first shaping filter quantized values according to the sampling time address information; the second shaping filter lookup table is used for storing shaping filter quantized values of a second symbol and outputting corresponding second shaping filter quantized values according to the sampling time address information; a third shaping filter look-up table; the third shaping filter lookup table is used for storing shaping filter quantized values of a third symbol and outputting corresponding third shaping filter quantized values according to the sampling time address information; the fourth shaping filter lookup table is used for storing shaping filter quantized values of a fourth symbol and outputting corresponding fourth shaping filter quantized values according to the sampling time address information; the fifth shaping filter lookup table is used for storing shaping filter quantized values of a fifth symbol and outputting corresponding fifth shaping filter quantized values according to the sampling time address information; the sixth shaping filter lookup table is used for storing shaping filter quantized values of a sixth symbol, and outputting corresponding sixth shaping filter quantized values according to the sampling time address information.
As shown in fig. 4, the shaping filter look-up table contains 6 look-up tables representing 6 symbols in the shaping filter, respectively, as mentioned in the principles section above. The shaping filter stored in the six look-up tables is a high precision filter time domain waveform generated with high oversampling multiples. From the following components It can be seen that for each digital signal taken out of the data buffer a determined delta value is required to determine the sample value of the shaping filter G multiplied by it. The OQPSK address accumulator can obtain decimal delta with arbitrary precision after flexible bit cutting d By inputting these 6 lookup tables, respectively, it is possible to output the sample values of the waveform at the interpolation position for the 6 symbols before and after the given interpolation position. The shaping filter amount g may be a root raised cosine filter, and it should be noted that in other embodiments, other types of digital filters may be adopted according to practical application requirements. The time domain waveform of the prototype analog signal corresponding to the symbol pulse sequence may be a square wave signal. As shown in fig. 3, the 32-channel parallel address accumulator signals AccI and AccQ obtain address signals Addr of the read shaping filter LUT by taking decimal parts through low cut bits, the Addr signals are input into a shaping filter lookup table, the lookup table structure is as shown in fig. 4, trailing values of waveforms formed by 6 symbols before and after a given interpolation position are read at the given interpolation position, and the trailing values are output through g in parallel.
Referring to fig. 5, the fractional sample point interpolator includes: a QPSK modulator, a first multiplier, a second multiplier, a third multiplier, a fourth multiplier, a fifth multiplier, a sixth multiplier, and an adder, where the QPSK modulator is configured to perform QPSK modulation according to the symbol data output from the cyclic shift memory in fig. 2; the first multiplier multiplies the first symbol modulation signal output by the QPSK modulator with the quantized value of the first shaping filter and outputs a first interpolation signal; the second multiplier multiplies the second symbol modulation signal output by the QPSK modulator with the quantized value of the second molding filter and outputs a second interpolation signal; the third multiplier multiplies the third symbol modulation signal output by the QPSK modulator with the quantized value of the third shaping filter and outputs a third interpolation signal; the fourth multiplier multiplies the fourth symbol modulation signal output by the QPSK modulator with the quantized value of the fourth shaping filter and outputs a fourth interpolation signal; the fifth multiplier multiplies the fifth symbol modulation signal output by the QPSK modulator with the quantized value of the fifth shaping filter and outputs a fifth interpolation signal; the sixth multiplier multiplies the sixth symbol modulation signal output by the QPSK modulator with the quantized value of the sixth shaping filter and outputs a sixth interpolation signal; the adder is used for carrying out addition operation on the first interpolation signal, the second interpolation signal, the third interpolation signal, the fourth interpolation signal, the fifth interpolation signal and the sixth interpolation signal and outputting the I path or Q path arbitrary symbol rate OQPSK modulation signals. The first symbol modulation signal, the second symbol modulation signal, the third symbol modulation signal, the fourth symbol modulation signal, the fifth symbol modulation signal and the sixth symbol modulation signal are respectively modulation signals of six adjacent symbols.
As shown in fig. 5, the output signals of the data buffer and the shaping filter look-up table are coupled into a fractional sample point interpolator according to the equationAn approximation to the analog waveform at a given interpolation position is calculated. Here, in din, the parallel 6 signals are QPSK modulated to form a signal b [ (m+i) T s ]Respectively with the outputs g (iT s +δ) multiplication; wherein b [ (m+i) T s ]Is obtained by data buffer input modulation, g (iT s +delta) is input through a lookup table, and the calculation result is any symbol rateOQPSK modulated signal of the rate.
With continued reference to fig. 1 to 6, specific signal processing implementation procedures are described herein by taking 32 parallel procedures for generating OQPSK modulated signals by an FPGA operating at 150MHz as an example:
(1) Generating 0-1 information sequence at the data source, performing source coding, framing and the like, and marking the symbol rate of the signal source data stream as R s 。
(2) The connection relationship between the data source and the data buffer is shown in fig. 2, the symbol signal generated by the data source enters the first stage Fifo1 in the data buffer, and the reading enabling signal of the first stage Fifo1 is the valid period counter of Rfd. Fifo1 outputs data of a given frame length data amount each time the read enable signal is active.
(3) The signal of the first stage Fifo1 enters the second stage Fifo2, the reading enabling signal of the second stage Fifo2 is the output signal of the baseband signal fetch control module, and when the reading enabling signal is valid each time, the second stage Fifo2 outputs 8 symbol signals to enter the cyclic shift memory.
(4) As shown in fig. 3, the OQPSK address accumulator accumulates based on an initial one-way accumulator AccIni, which self-increments by R each clock cycle s /F clk The initial value is 0. The difference of the values between the parallel address accumulators of each path is R s /F smp Thus, the interpolation position nT is constructed smp . AccIni is input into an I-path address accumulator after 0.5 increment, and the interpolation position of the I-path can be controlled to be nT smp +0.5, the interpolation position between the I, Q two signals is shifted by half a symbol period. AccI32 and AccQ32 are respectively input into two baseband signal fetch control modules, when the judgement device judges that its value in next clock period is greater than 8, then the update judgement signal is set high.
(5) The 32 paths of parallel address accumulator signals AccI and AccQ finish rounding through high cut bits, address signals Index for reading the cyclic shift memory are obtained, the Index signals are input into the cyclic shift memory in the data buffer of fig. 2, the values of 6 symbols before and after a given interpolation position are read, and the values are output in parallel through data.
(6) The 32 paths of parallel address accumulator signals AccI and AccQ are subjected to decimal part extraction through low-cut bits, address signals Addr of a read shaping filter LUT are obtained, the Addr signals are input into a shaping filter lookup table, the lookup table structure is shown in figure 4, trailing values of waveforms formed by 6 symbols before and after a given interpolation position are read at the given interpolation position, and the trailing values are output through g in parallel.
(7) As shown in fig. 5, the output signals of the data buffer and the look-up table of the shaping filter are connected to the fractional sample point interpolator according to the formulaAn approximation to the analog waveform at a given interpolation position is calculated. Here, in din, the parallel 6 signals are QPSK modulated to form a signal b [ (m+i) T s ]Respectively with the outputs g (iT s +δ) are multiplied.
(8) And grabbing the transmitted baseband data, and performing off-line analysis in MATLAB to obtain a time domain waveform shown in figure 6. As can be seen, there is a half symbol period offset between the I, Q paths of the OQPSK signal.
It should be noted that, each module of the look-up table-based random symbol rate OQPSK modulation signal generation apparatus may be implemented by a signal processor, preferably a field programmable gate array (Field Programmable Gate Array, FPGA) to implement each module. Of course, in other embodiments, the various modules may be implemented using other types of signal processors, such as other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), or other programmable logic devices, discrete gate or transistor logic devices, discrete preset hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that the present invention may be modified or equivalents substituted for some of the features thereof. All equivalent structures made by the content of the specification and the drawings of the invention are directly or indirectly applied to other related technical fields, and are also within the scope of the invention.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives, and variations may be made in the above embodiments by those skilled in the art without departing from the spirit and principles of the invention.

Claims (10)

1. An arbitrary symbol rate OQPSK modulated signal generation apparatus based on a lookup table, comprising:
the OQPSK address accumulator is used for generating sampling time address information delta of the symbol data, wherein the sampling time address information delta comprises sampling time address information of I-path symbol data and sampling time address information of Q-path symbol data;
the data buffer is used for buffering the symbol data and outputting corresponding symbol data b according to the sampling time address information;
the shaping filter lookup table is used for storing shaping filters and outputting corresponding shaping filter signals g according to the sampling time address information delta;
and the fractional sampling point interpolator is used for calculating sampling values of given interpolation positions according to the output symbol data b of the data buffer and the shaping filter signal g so as to generate an I-path or Q-path arbitrary symbol rate OQPSK modulation signal.
2. The arbitrary symbol rate OQPSK modulated signal generation apparatus according to claim 1, wherein the OQPSK address accumulator includes:
each path of accumulator comprises a single path of symbol initial value accumulator and a plurality of paths of parallel symbol rate control accumulators;
the single-path symbol initial value accumulator is used for generating initial value sampling time address information AccIni; the multi-path parallel symbol rate control accumulator is a parallel address accumulator, and the parallel address accumulator accumulates based on an initial single-path symbol initial value accumulator AccIni to generate sampling time address information of the multi-path symbol data;
wherein, the initial value sampling time address information AccIni of the I path accumulator is assigned to 0.5, and the initial value sampling time address information AccIni of the Q path accumulator is assigned to 0; the difference of the values between the parallel address accumulators of each path is R s /F smp The method comprises the steps of carrying out a first treatment on the surface of the Wherein R is s For symbol rate, F smp Is the sampling frequency.
3. The arbitrary symbol rate OQPSK modulated signal generation apparatus according to claim 2, further comprising:
the baseband signal sampling control module is used for updating a control signal Rfd according to the sampling time address information so as to update the symbol data stored in the data buffer through the control signal Rfd; and the control signal Rfd is pulled up once at the overflow moment of the last accumulator of the multi-path parallel symbol rate control accumulator, so as to finish one baseband data fetch.
4. The arbitrary symbol rate OQPSK modulated signal generation apparatus as defined in claim 3, wherein the data buffer includes:
the first-stage Fifo is used for carrying out first-in first-out buffer memory on the symbol data output by the signal source and outputting the buffered symbol data under the action of a first-stage Fifo reading enabling signal pair; wherein, the condition for the fetch enable to be valid is that the first stage FIFO state is not empty;
the second stage Fifo is used for carrying out first-in first-out buffer storage on the symbol data output by the first stage Fifo and outputting buffer symbol data under the action of the update control signal Rfd;
and the cyclic shift memory is used for caching the symbol data output by the second stage Fifo and outputting corresponding symbol data according to the sampling time address information.
5. The arbitrary symbol rate OQPSK modulated signal generation apparatus as defined in claim 4, wherein the data buffer further includes:
and the accumulation trigger is used for generating a reading enabling signal of the first stage Fifo according to the updating control signal Rfd so as to output buffer symbol data of a given frame length data quantity.
6. The apparatus for generating an OQPSK modulated signal at any symbol rate according to any of claims 2 to 5, wherein the look-up tables of the shaping filters are divided into six groups of look-up tables, and a complete 1024-fold oversampled root-raised cosine shaping filter is equally distributed to the six groups of look-up tables, the six groups of look-up tables including:
the first shaping filter lookup table is used for storing shaping filter quantized values of a first symbol and outputting corresponding first shaping filter quantized values according to the sampling time address information;
the second molding filter lookup table is used for storing the molding filter quantized value of the second symbol and outputting the corresponding second molding filter quantized value according to the sampling time address information;
the third shaping filter lookup table is used for storing shaping filter quantized values of a third symbol and outputting corresponding third shaping filter quantized values according to the sampling time address information;
a fourth shaping filter lookup table, which is used for storing shaping filter quantized values of a fourth symbol and outputting corresponding fourth shaping filter quantized values according to the sampling time address information;
A fifth shaping filter lookup table, which is used for storing shaping filter quantized values of a fifth symbol and outputting corresponding fifth shaping filter quantized values according to the sampling time address information;
and the sixth shaping filter lookup table is used for storing shaping filter quantized values of a sixth symbol and outputting corresponding sixth shaping filter quantized values according to the sampling time address information.
7. The arbitrary symbol rate OQPSK modulated signal generation apparatus as defined in claim 6, wherein the fractional sample point interpolator includes:
a QPSK modulator, multiplexing the QPSK modulator structure when the OQPSK modulated signal is subjected to constellation mapping, so as to carry out QPSK modulation according to the symbol data output by the cyclic shift memory;
a first multiplier for multiplying the first symbol modulation signal output from the QPSK modulator with the quantized value of the first shaping filter and outputting a first interpolation signal;
a second multiplier for multiplying the second symbol modulation signal output from the QPSK modulator with the quantized value of the second molding filter and outputting a second interpolation signal;
A third multiplier for multiplying the third symbol modulated signal output from the QPSK modulator with the third shaping filter quantized value and outputting a third interpolation signal;
a fourth multiplier for multiplying the fourth symbol modulation signal output from the QPSK modulator with the fourth shaping filter quantization value and outputting a fourth interpolation signal;
a fifth multiplier for multiplying the fifth symbol modulation signal output from the QPSK modulator with the quantization value of the fifth shaping filter and outputting a fifth interpolation signal;
a sixth multiplier for multiplying the sixth symbol modulated signal output from the QPSK modulator with the quantized value of the sixth shaping filter and outputting a sixth interpolation signal;
the adder is used for carrying out addition operation on the first interpolation signal, the second interpolation signal, the third interpolation signal, the fourth interpolation signal, the fifth interpolation signal and the sixth interpolation signal and outputting the I path or Q path arbitrary symbol rate OQPSK modulation signals; the first symbol modulation signal, the second symbol modulation signal, the third symbol modulation signal, the fourth symbol modulation signal, the fifth symbol modulation signal and the sixth symbol modulation signal are respectively modulation signals of six adjacent symbols.
8. The arbitrary symbol rate OQPSK modulated signal generation apparatus as defined in claim 7, wherein the shaping filter amount g is a 1024-fold oversampled root-raised cosine filter; the filter length is 6 adjacent symbols, and the coefficient of the shaping filter G is a parameter which can be set on line.
9. The arbitrary symbol rate OQPSK modulated signal generation apparatus according to claim 7 or 8, wherein the arbitrary symbol rate OQPSK modulated signal output by any one of I/Q is:
wherein,T s for the symbol period, the sampling sequence n=1, 2.
10. The apparatus for generating an OQPSK modulated signal at an arbitrary symbol rate according to claim 9, wherein the time-domain waveform of the prototype analog signal corresponding to the symbol pulse sequence is a PCM signal, and the PCM signal includes any one of NRZ-L, NRZ-S and NRZ-M patterns.
CN202311474583.7A 2023-11-07 2023-11-07 Arbitrary symbol rate OQPSK modulation signal generation device based on lookup table Pending CN117596118A (en)

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