CN117594674A

CN117594674A - Back contact battery, preparation method thereof and battery assembly

Info

Publication number: CN117594674A
Application number: CN202410077503.2A
Authority: CN
Inventors: 林楷睿; 许志
Original assignee: Golden Solar Quanzhou New Energy Technology Co Ltd
Current assignee: Golden Solar Quanzhou New Energy Technology Co Ltd
Priority date: 2024-01-19
Filing date: 2024-01-19
Publication date: 2024-02-23

Abstract

The invention belongs to the technical field of back contact batteries, and in particular relates to a back contact battery, a preparation method thereof and a battery assembly. The invention has simpler manufacturing process, does not need to use expensive low-temperature silver paste and transparent conductive film layers, greatly reduces the production cost of the battery, and ensures excellent battery conversion efficiency.

Description

Back contact battery, preparation method thereof and battery assembly

Technical Field

The invention belongs to the technical field of back contact batteries, and particularly relates to a back contact battery, a preparation method thereof and a battery assembly.

Background

Currently, back contact cell structures generally include a silicon wafer, a first semiconductor layer and a second semiconductor layer disposed on a back surface of the silicon wafer; the conductive film layer and the metal grid line are respectively arranged on the outer surfaces of the first semiconductor layer and the second semiconductor layer; and a passivation layer and an optional anti-reflection layer are sequentially arranged on the front surface of the silicon wafer. The process flow is generally as follows: s101, polishing two sides of a silicon wafer; s102, plating a first mask layer on the back of the silicon wafer for protection; s103, performing texture making and cleaning on the silicon wafer, forming a texture surface on the opposite side of the first mask layer, and then removing the first mask layer to form the silicon wafer with a single-sided texture making and single-sided polishing structure; s104, plating a first semiconductor layer and a second mask layer on the back surface of the silicon wafer in sequence; s105, etching an opening on the back surface of the silicon wafer, and removing the second mask layer and part of the first semiconductor layer to form a first opening area; s106, cleaning the silicon wafer to remove the first semiconductor layer in the first opening area; s107, an amorphous layer and an antireflection layer are sequentially formed on the front surface of the silicon wafer, and a second semiconductor layer is formed on the back surface of the silicon wafer; s108, etching openings on the back of the silicon wafer to form second opening areas which are alternately arranged with the first opening areas; s109, cleaning the silicon wafer, and removing the second mask layer in the second opening area; s110, depositing a conductive film layer on the back surface of the silicon wafer; s111, forming an insulating groove between the first opening area and the second opening area in an etching mode; s112, forming metal electrodes (namely thin grids) on the first opening area and the second opening area of the silicon wafer, and then forming main grids perpendicular to the metal electrodes.

However, in the back contact cell structure of the prior art, a conductive film layer needs to be deposited on the back surface of the silicon wafer, and the conductive film layer generally adopts a transparent conductive film ITO (indium tin oxide) or TCO (conductive oxide) at present; and an insulating groove is formed between the first opening area and the second opening area by etching, and a metal gate line electrode is formed on the first opening area and the second opening area of the silicon wafer, wherein the metal gate line electrode generally adopts low-temperature silver paste to form a silver gate line. Therefore, there is a problem in that the use of an expensive transparent conductive film layer and low-temperature silver paste makes the battery costly.

In addition, the existing back contact battery also needs to remove the conductive film layer between the first opening area and the second opening area to form an insulating groove; the third etching laser grooving on the back is to selectively groove the transparent conductive film layer or the transparent conductive film layer and the P-type (or transparent N-type) amorphous silicon passivation layer, because the material is transparent, the laser can not be absorbed by resonance, and the laser grooving difficulty is great; the wet etching mode is adopted, the process is complex, and the influence on the battery piece is large; further increasing the difficulty of the modulus production of the back contact electricity Chi Gui.

It should be noted that this section of the disclosure only provides a background related to the present disclosure, and does not necessarily constitute prior art or known technology.

Disclosure of Invention

The invention aims to overcome the defect that the cost of a battery is high due to the fact that an expensive transparent conductive film layer and low-temperature silver paste are required to be used while the conversion efficiency of a back contact battery is guaranteed in the prior art, and provides the back contact battery, a preparation method thereof and a battery assembly. The invention has simpler manufacturing process, does not need to use expensive low-temperature silver paste and transparent conductive film layers, greatly reduces the production cost of the battery, and ensures excellent battery conversion efficiency.

In order to achieve the above object, in a first aspect, the present invention provides a back contact battery, including a silicon wafer having a front surface and a back surface, a first semiconductor layer and a second semiconductor layer disposed on the back surface and alternately arranged along a Y-axis direction of the silicon wafer, the first semiconductor layer including a first doped silicon crystal layer, the second semiconductor layer including a second doped silicon crystal layer, and an end portion of the second semiconductor layer extending onto an outer surface of an end portion of an adjacent first semiconductor layer to form a transition region, the back contact battery further including a silicon alloy layer containing a metal silicide disposed outwardly in a Z-axis direction, the silicon alloy layer being disposed on an outer surface of the second semiconductor layer and extending to an outer surface of the adjacent first doped silicon crystal layer, and an insulating trench being opened on a portion of the silicon alloy layer corresponding to the transition region; wherein the sheet resistance of the silicon alloy layer is 5-70 。

In some preferred embodiments of the present invention, the metal element contained in the metal silicide includes at least one of nickel, aluminum, platinum, cobalt, titanium, and tungsten.

In some preferred embodiments of the present invention, the metal silicide comprises at least one of nickel silicide, aluminum silicide, platinum silicide.

In some preferred embodiments of the invention, the silicon alloy layer has a thickness of 2-30nm.

In some preferred embodiments of the present invention, the silicon alloy layer further comprises a doping element, the doping element comprising boron or phosphorus.

In some more preferred embodiments of the present invention, the ratio of the surface doping index of the silicon alloy layer to the first doped silicon crystal layer, the second doped silicon crystal layer is 1:1-250:3-800, preferably 1:1-250:3-500, wherein the in-plane doping index is the ratio of the effective doping concentration of the corresponding doped silicon layer to the thickness of the doped silicon layer.

In the present invention, the unit of the surface doping index is cm ^-3 /nm. That is, the effective doping concentration of the corresponding doped silicon crystal layer is in cm ^-3 The thickness is in nm.

In some preferred embodiments of the present invention, the silicon alloy layer has an effective doping concentration of 1e17 cm ^-3 -1e18 cm ^-3 。

In some preferred embodiments of the present invention, the first doped silicon crystal layer has a thickness of 50-300nm and an effective doping concentration of 1e19 cm ^-3 -4e20 cm ^-3 。

In some preferred embodiments of the present invention, the second doped silicon crystal layer has a thickness of 10-50nm and an effective doping concentration of 1e19 cm ^-3 -4e20 cm ^-3 。

In some preferred embodiments of the present invention, the first semiconductor layer further comprises a first passivation layer disposed on the back side of the silicon wafer, at least a portion of the first passivation layer being located between the back side of the silicon wafer and the first doped silicon crystal layer.

Further preferably, the second semiconductor layer further comprises a second passivation layer disposed on the back surface of the silicon wafer, the second passivation layer being located between the back surface of the silicon wafer and the second doped silicon crystal layer; the second passivation layer includes an intrinsic amorphous silicon layer or a second tunneling oxide layer.

More preferably, the thickness of the intrinsic amorphous silicon layer is 5-15nm, and the thickness of the second tunneling oxide layer is 1.5-2.5nm.

In some preferred embodiments of the present invention, the first passivation layer is disposed on the back surface of the silicon wafer in a full coverage manner, the first doped silicon crystal layer and the second doped silicon crystal layer are both located on a side, far away from the back surface of the silicon wafer, of the first passivation layer, the second doped silicon crystal layer and a part of the first passivation layer covered by the second doped silicon crystal layer form a second semiconductor layer, and the first doped silicon crystal layer and the second doped silicon crystal layer are both doped polycrystalline layers.

In some preferred embodiments of the present invention, the first passivation layer includes a first tunneling oxide layer, and the first doped silicon crystal layer is a first doped polycrystalline layer.

Further preferably, the ratio of the thickness of the silicon alloy layer to the thickness of the first tunneling oxide layer is 1:1:0.05-1.25.

Preferably, the thickness of the first tunneling oxide layer is 1.5-2.5nm.

In some preferred embodiments of the invention, the extended end of the second semiconductor layer is in direct contact with the first semiconductor layer in the thickness direction or a mask layer is provided in the transition region.

In some preferred embodiments of the present invention, the width of the insulation groove is 0.03-0.15mm.

In some preferred embodiments of the invention, the back contact cell is not provided with a main grid and a thin grid.

In some preferred embodiments of the present invention, the back contact cell further comprises a front passivation layer disposed outwardly of the front side of the silicon wafer.

Further, the front passivation layer is any one of intrinsic amorphous silicon, intrinsic amorphous external superposition doped microcrystalline silicon, tunneling silicon oxide and tunneling silicon oxide external superposition doped polycrystalline silicon.

In a second aspect, the present invention provides a method for preparing a back contact battery, comprising the steps of:

s1, forming a first semiconductor layer on the back surface of a silicon wafer, and forming first opening areas on the first semiconductor layer at intervals along the Y-axis direction of the silicon wafer; forming a second semiconductor layer on the back surface, and forming a second opening region on a part of the second semiconductor layer, which covers the outer surface of the first semiconductor layer; wherein the first semiconductor layer comprises a first doped silicon crystal layer and the second semiconductor layer comprises a second doped silicon crystal layer;

s2, forming a metal film layer on the back surface obtained in the step S1;

s3, performing heat treatment in an anaerobic environment to enable metal in the metal film layer to react with silicon in the corresponding doped silicon crystal layer in contact to generate a silicon alloy layer, and controlling the square resistance of the silicon alloy layer to be 5-70；

And S4, performing third etching on the part of the silicon alloy layer between the first opening area and the second opening area to form an insulating groove.

In some preferred embodiments of the present invention, the metal thin film layer has a thickness of 5 to 20nm.

In some preferred embodiments of the present invention, the metal thin film layer is at least one of a nickel metal film layer, an aluminum metal film layer, a platinum metal film layer, a cobalt metal film layer, a titanium metal film layer, a tungsten metal film layer, a nickel alloy metal film, an aluminum alloy metal film, a platinum alloy metal film, a cobalt alloy metal film layer, a titanium alloy metal film, and a tungsten alloy metal film.

In some preferred embodiments of the present invention, the metal thin film layer in S2 is obtained by magnetron sputtering or evaporation.

Further preferably, the conditions of the magnetron sputtering include: vacuum degree of 5X 10 ^-3 Pa- 5×10 ^-1 Pa, the sputtering power is 2-5kW, and the sputtering time is 30-90s.

Further preferably, the evaporation conditions include: vacuum degree of 5X 10 ^-3 Pa- 5×10 ^-1 Pa, the evaporation heating power is 5-10kW, and the evaporation time is 30-120s.

In some preferred embodiments of the present invention, the heat treatment in an anaerobic environment in S3 includes: under the anaerobic environment, adopting laser irradiation at 300-350 ℃ to carry out rapid photo-thermal treatment for 5-60s; or annealing at 100-220 deg.C for 5-30min in anaerobic environment.

In some preferred embodiments of the present invention, the third etching in S4 uses a laser technology, where the laser is a laser with a pulse width in picoseconds.

In some preferred embodiments of the present invention, the process of S1 specifically comprises:

s101, providing a silicon wafer;

s102, sequentially forming a first semiconductor layer and a mask layer on the back surface of the silicon wafer, wherein the first semiconductor layer comprises a first passivation layer and a first doped silicon crystal layer which are sequentially formed on the back surface;

S103, performing first etching on the first semiconductor layer and the mask layer in the back preset area obtained in the step S102 to form first opening areas which are distributed at intervals;

s104, removing all the residual mask layers;

s105, forming a second semiconductor layer on the back surface obtained in the step S104, wherein the second semiconductor layer comprises a second passivation layer and a second doped silicon crystal layer which are sequentially formed on the back surface;

and S106, performing second etching on the area with the first semiconductor layer remained on the back surface obtained in the step S105 so as to expose the first semiconductor layer and form a second opening area which is arranged with the first opening area.

In other preferred embodiments of the present invention, the process of S1 specifically comprises:

s11, providing a silicon wafer;

s12, sequentially forming a first semiconductor layer and a mask layer on the back surface of the silicon wafer, wherein the first semiconductor layer comprises a first passivation layer and a first doped silicon crystal layer which are sequentially formed on the back surface;

s13, performing first etching on the first doped silicon crystal layer and the mask layer in the back preset area obtained in the S12 to form first opening areas which are distributed at intervals;

s14, removing all the residual mask layers;

s15, forming a second doped silicon crystal layer on the back surface obtained in the step S14, wherein the second doped silicon crystal layer and a part of the first passivation layer covered by the second doped silicon crystal layer form a second semiconductor layer;

And S16, performing second etching on the area with the first semiconductor layer remained on the back surface obtained in the step S15 to expose part of the first semiconductor layer, so as to form a second opening area which is arranged with the first opening area.

In a third aspect, the present invention provides a back contact battery produced by the method for producing a back contact battery according to the second aspect.

In a fourth aspect, the present invention provides a battery assembly, which includes the back contact battery according to the first aspect, or includes the back contact battery according to the third aspect, and a solder strip directly disposed on a surface of the silicon alloy layer corresponding to the different conductive regions in the back contact battery.

The beneficial effects are that:

according to the technical scheme, the silicon alloy layer containing metal silicide with specific conductivity is particularly adopted as an electrode extraction mode, so that the electrode extraction mode of combining the transparent conductive film layer of the conventional back contact battery with the silver metal thin grid line is replaced, the manufacturing process is simpler, expensive low-temperature silver paste and the transparent conductive film layer (such as ITO) are not required, the production cost of the battery is greatly reduced, and excellent battery conversion efficiency is ensured. The silicon alloy layer can realize good ohmic contact between silicon and metal and has proper high conductivity (namely low square resistance), so that the silicon alloy layer can directly replace a transparent conductive film, a silver fine grid and a main grid in a back contact battery in the prior art.

The silicon alloy layer has high conductivity (namely low square resistance), can be directly used as an electrode lead-out wire, does not need to additionally arrange a fine grid and a main grid, can directly lead out current, has short manufacturing process, does not need to use expensive low-temperature silver paste and a transparent conductive film layer, greatly reduces the production cost of a battery, and ensures excellent battery conversion efficiency.

In the preparation method, a metal film layer is deposited on the silicon surfaces of the first semiconductor layer and the second semiconductor layer, after heat treatment, silicon and metal react to obtain metal silicide, a silicon alloy layer with high conductivity can be formed, a good current channel can be formed, and electrons and holes in the silicon wafer can well run to the surface of the battery and be conducted to an external circuit. The reason why the two silicon alloy layers are combined to form good ohmic contact is that, as exemplified by metallic nickel, it is at least reflected in the following aspects:

1. compatibility: the lattice structures of silicon and nickel are relatively similar, with similar lattice parameters and crystal structures, which allows them to form Sini ₂ The alloy phase has better compatibility. Compatibility means that there is a similar arrangement in the crystal structure, facilitating interatomic interactions and diffusion.

2. Chemical affinity: there is a certain chemical affinity between silicon and nickel. Nickel metal forms strong chemical bonds with silicon during adsorption on the silicon surface to form Si-Ni bonds, which helps to form stable SiNi ₂ And (3) an alloy phase. This chemical affinity helps to increase the fluctuation boundary diffusion rate and promote the interaction between silicon and nickel.

3. Conductivity of: siNi ₂ The alloy phase has higher conductivity due to the SiNi ₂ The alloy phase has a high electrical conductivity so that current can be efficiently conducted between the metal and the semiconductor, thereby forming a good ohmic contact.

And the metal silicide can greatly reduce the direct contact resistance of silicon and metal (form excellent ohmic contact between silicon and metal), while the metal silicide is formed at a certain temperature, such as WSix, tiSix, coSix, ptSix, niSix, where x is a natural number satisfying the valence balance, and their forming temperatures are sequentially reduced, wherein the nickel silicide (NiSix) is required to have the lowest forming temperature, especially single crystal NiSi ₂ Since the lattice symmetry and the crystal silicon constant of the phase are close to those of single crystal silicon, niSi ₂ The phase formation requires minimal driving force, i.e., minimal temperature, and can be formed even when metallic nickel is plated on the surface of monocrystalline silicon, heated to 150 ℃. The invention is characterized in that In the preparation method, the silicon alloy layer of the proper metal silicide can be selected according to the temperature characteristics of the passivation structure of each semiconductor layer, for example, the low formation temperature of nickel silicide, aluminum silicide and platinum silicide can be suitable for a heterojunction structure passivated by intrinsic amorphous silicon and a low-temperature process combined with a passivation structure, the required temperature for forming silicon alloy by W, ti and Co and silicon is relatively high, and the preparation method can be suitable for a Topcon battery structure passivated by a tunneling oxide layer. The invention can be widely applied to the production of solar cells and semiconductor chips.

In a further preferred embodiment of the invention, especially for the back contact cell with combined passivation, the laser grooving is easier for the third etching of the back surface, and the process flow is further simplified.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic view showing a structure in which a first semiconductor layer and a front surface laminate are formed in example 1 of an embodiment of a back contact battery of the present invention;

FIG. 2 is a schematic diagram of a structure of the mask layer shown in FIG. 1;

FIG. 3 is a schematic view of the structure of FIG. 2 with a first opening area;

FIG. 4 is a schematic diagram of the structure of FIG. 3 after removing the mask layer;

FIG. 5 is a schematic view illustrating a structure of the second semiconductor layer formed on FIG. 4;

FIG. 6 is a schematic view of the structure of FIG. 5 with a second opening area;

FIG. 7 is a schematic diagram of the structure of the metal thin film layer formed on FIG. 6 and subjected to an anaerobic annealing to form a silicon alloy layer;

FIG. 8 is a schematic view of the structure of the insulation slot of FIG. 7;

fig. 9 is a schematic structural view of another embodiment of the back contact battery of the present invention.

Fig. 10 is a schematic view of the structure of comparative example 1 in which the first and second main gates and the insulating layer are provided.

Description of the reference numerals

1. The semiconductor device comprises a silicon wafer, 2, a first tunneling oxide layer, 3, a front lamination layer, 4, a first doped polycrystalline layer, 5, an intrinsic amorphous silicon layer, 6, a second doped silicon crystal layer, 7, a nickel-silicon alloy layer, 8, a metal film layer, 9, an insulation groove, 10, a first main grid, 11, a second main grid, 12, an insulation layer, 13, a first fine grid, 14, a second fine grid, a1 and a mask layer.

Detailed Description

In the present invention, unless otherwise indicated, terms of orientation such as "upper, lower, left, right" and the like are used generally to refer to the orientation as shown in the drawings and in practice.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.

The endpoints and any values of the ranges disclosed herein are not limited to the precise range or value, and are understood to encompass values approaching those ranges or values. For numerical ranges, one or more new numerical ranges may be found between the endpoints of each range, between the endpoint of each range and the individual point value, and between the individual point value, in combination with each other, and are to be considered as specifically disclosed herein. Wherein the terms "optional" and "optionally" mean either comprising or not comprising (or may not be present).

In the invention, the silicon wafer is close to the inside and the silicon wafer is far from the outside.

In the invention, the square resistance of the corresponding layer is obtained by testing the surface of the structure where the layer is positioned by a four-point probe (4 PP) method after the layer is deposited. For example, sheet resistance of a silicon alloy layer is obtained by surface testing after plating with the silicon alloy layer. The four-point probe method works on the principle that four equally spaced co-linear probes are in contact with a material to be measured, and this method is called the four-point probe method, in which Direct Current (DC) is driven between the outer two probes and voltage is measured between the inner two probes. Geometric correction coefficients are generally required when measuring small samples or near the edges, since the current path is affected by the sample geometry, and the most accurate values can be obtained in the central location area of the sample, in the present invention, the square resistances of the corresponding layers are obtained by performing the same test in the central location area of the sample to be measured.

In a first aspect, the invention provides a back contact battery, comprising a silicon wafer having a front surface and a back surface, a first semiconductor layer and a second semiconductor layer which are arranged on the back surface and are alternately arranged along a Y-axis direction of the silicon wafer, wherein the first semiconductor layer comprises a first doped silicon crystal layer, the second semiconductor layer comprises a second doped silicon crystal layer, the end part of the second semiconductor layer extends to the outer surface of the end part of the adjacent first semiconductor layer to form a transition region, the back contact battery further comprises a silicon alloy layer containing metal silicide which is arranged outwards along a Z-axis direction, the silicon alloy layer is arranged on the outer surface of the second semiconductor layer and extends to the outer surface of the adjacent first doped silicon crystal layer, and an insulating groove is formed on a part of the silicon alloy layer corresponding to the transition region; wherein the silicon alloy layerSquare resistance of 5-70。

It should be noted that in the transition region, a first semiconductor layer and a second semiconductor layer are sequentially disposed from inside to outside in the Z-axis direction of the back surface of the silicon wafer. The first semiconductor layer and the second semiconductor layer extend along the X-axis direction of the silicon wafer, respectively.

In the invention, one of the first doped silicon crystal layer and the second doped silicon crystal layer is of an N type, and the other is of a P type.

The sheet resistance of the silicon alloy layer is low, indicating that the silicon alloy layer has a suitably high conductivity. In the present invention, the metal element contained in the metal silicide may be selected according to the conductivity of the silicon alloy layer. In some preferred embodiments of the present invention, the metal element contained in the metal silicide includes at least one of nickel, aluminum, platinum, cobalt, titanium, and tungsten.

Further preferably, the metal element contained in the metal silicide includes at least one of nickel, aluminum and platinum, which is more suitable for the structure of a heterojunction cell structure (i.e. the passivation layers of the two semiconductor layers are both intrinsic amorphous silicon) and a back contact cell with a combined passivation structure (i.e. the first passivation layer and the second passivation layer are sequentially a tunneling oxide layer and intrinsic amorphous silicon).

In some preferred embodiments of the present invention, the metal silicide comprises at least one of nickel silicide, aluminum silicide, platinum silicide. In the present invention, the specific form (or specific compound composition) of each metal silicide is not limited, and any product can be used as long as it is a product of the reaction between silicon-containing and metal-containing raw material elements to achieve the objects and technical effects of the present invention; the nickel silicide may be, for example, niSi ₂ 、NiSi、Ni ₂ Si.

In some preferred embodiments of the invention, the silicon alloy layer has a thickness of 2-30nm, preferably 2-15nm. The silicon alloy layer with the proper thickness can form good ohmic contact, and adverse factors on the battery structure caused by excessive consumption of silicon in the first doped silicon crystal layer and the second doped silicon crystal layer possibly existing are avoided, so that good ohmic contact is formed between interfaces under the condition that the corresponding doped silicon crystal layer is prevented from being damaged and the battery structure is not damaged to the greatest extent, and current can be conducted between metal and semiconductor effectively.

Further preferably, the sheet resistance of the silicon alloy layer is 5 to 36The thickness of the silicon alloy layer is 2-15nm, which is more beneficial to improving the conversion efficiency of the battery.

Further preferably, the ratio of the surface doping index of the silicon alloy layer to the first doped silicon crystal layer and the second doped silicon crystal layer is 1:1-100:10-200, more preferably 1:15-100:40-500, further preferably 1:15-100:40-200.

In the scheme of the ratio of the surface doping indexes of the optimized silicon alloy layer to the first doped silicon crystal layer and the second doped silicon crystal layer, the thickness and the doping concentration of each layer are matched, so that the concentration of carriers can be better controlled, the electron mobility is improved, the resistance is reduced, and the stability of the preparation process and the overall performance of the battery are improved.

In some preferred embodiments of the present invention, the first doped silicon crystal layer has a thickness of 50-300nm and an effective doping concentration of 1e19 cm ^-3 -4e20cm ^-3 。

In some preferred embodiments of the inventionThe thickness of the second doped silicon crystal layer is 10-50nm, and the effective doping concentration is 1e19 cm ^-3 -4e20cm ^-3 . The thickness of the second doped silicon crystal layer of the present invention is thicker than the prior art to provide a suitable amount of silicon for consumption in the formation of the silicon alloy layer.

The second doped silicon crystal layer may be a doped amorphous layer or a doped microcrystalline layer.

In some specific preferred embodiments, the back contact cell is a combined passivation structure, the thickness of the second doped silicon crystal layer is 10-40nm, and/or the second doped silicon crystal layer is a doped amorphous layer, which is more beneficial to improving the cell conversion efficiency.

Further preferably, the ratio of the thickness of the silicon alloy layer to the thickness of the first tunneling oxide layer is 1:1:0.05-1.25. In the preferred scheme, the ratio of the thickness of the silicon alloy layer to the thickness of the first tunneling oxide layer is proper, so that the electron mobility and the tunneling effect can be balanced to a certain extent, the conductivity of the silicon alloy layer is improved, and the stability of the battery is maintained.

Further, the ratio of the thickness of the silicon alloy layer to the thickness of the first tunneling oxide layer is 1:0.20-1.25.

Preferably, the thickness of the first tunneling oxide layer is 1.5-2.5nm.

In some preferred embodiments of the present invention, the second semiconductor layer further comprises a second passivation layer disposed on the back side of the silicon wafer, the second passivation layer being located between the back side of the silicon wafer and the second doped silicon crystal layer.

Further, the second passivation layer comprises an intrinsic amorphous silicon layer or a second tunneling oxide layer.

In some preferred embodiments of the present invention, the first passivation layer is disposed on the back surface of the silicon wafer in a full coverage manner, the first doped silicon crystal layer and the second doped silicon crystal layer are both located on a side, far away from the back surface of the silicon wafer, of the first passivation layer, the second doped silicon crystal layer and a part of the first passivation layer covered by the second doped silicon crystal layer form a second semiconductor layer, and the first doped silicon crystal layer and the second doped silicon crystal layer are both doped polycrystalline layers. In the structure, the second doped silicon crystal layer shares part of the first passivation layer to form the second semiconductor layer, and the first doped silicon crystal layer and the second doped silicon crystal layer are both doped polycrystalline layers, because the polycrystalline silicon is composed of a plurality of crystal grains, crystal boundaries exist among the crystal grains, and compared with an amorphous layer, the polycrystalline silicon has higher crystallinity and crystal boundary density due to the structure, the formation of a silicon alloy layer is facilitated, metal can form better combination at the crystal boundary of the polycrystalline silicon to form a stable silicon alloy layer, and therefore the formation of a high-quality silicon alloy layer is facilitated, and meanwhile, the consistency of the silicon alloy layers of the first doped silicon crystal layer region and the second doped silicon crystal layer region is improved.

In other preferred embodiments of the present invention, the first passivation layer includes a first tunneling oxide layer, the first doped silicon crystal layer is a first doped polycrystalline layer, the second passivation layer includes an intrinsic amorphous silicon layer, and the second doped silicon crystal layer may be a doped amorphous layer or a doped microcrystalline layer. In the scheme, the back contact battery is of a combined passivation structure, and compared with other passivation structures, the battery conversion efficiency is higher.

In some preferred embodiments of the invention, the extended end of the second semiconductor layer is in direct contact with the first semiconductor layer in the thickness direction or a mask layer is provided in the transition region. Preferably, the direct contact is more beneficial to reducing impurities or surface scattering introduced by the mask layer than the mode of arranging the mask layer between the first semiconductor layer and the second semiconductor layer, and is beneficial to improving the migration performance of carriers in the device.

In some preferred embodiments of the invention, the width of the insulation slot is 0.03-0.15mm, preferably 0.03-0.1mm. The invention aims at the specific silicon alloy layers to be matched with the insulating layers with proper widths, can prevent electrons from migrating between the silicon alloy layers, avoid unnecessary loss of electrons, is more beneficial to the isolation of the first semiconductor layer and the second semiconductor layer, and better leads out the electrode.

The silicon alloy layer has high conductivity and forms excellent ohmic contact, can be directly used as an electrode lead-out wire, does not need to additionally arrange a fine grid and a main grid, can directly lead out current, has short manufacturing process, does not need to use expensive low-temperature silver paste and a transparent conductive film layer, greatly reduces the production cost of a battery, and ensures excellent battery conversion efficiency.

In some embodiments of the present invention, the front passivation layer is any one of intrinsic amorphous silicon, intrinsic amorphous exo-stack doped microcrystalline silicon, tunnel silicon oxide exo-stack doped polysilicon.

In the invention, the anti-reflection layer can be arranged or not arranged on the outer surface of the front passivation layer according to the requirement. The thickness and material of the front passivation layer and the anti-reflection layer and the doping concentration of the front passivation layer containing doped amorphous silicon, doped microcrystalline silicon or doped polysilicon can be carried out according to the prior art, and the thickness of the front passivation layer is 5-30nm, the effective doping concentration of the doped amorphous silicon, doped microcrystalline silicon or doped polysilicon is 1e19cm ^-3 -1e20cm ^-3 The thickness of the antireflection layer is 50-150nm. The kind of the anti-reflection layer may be, for example, at least one of silicon nitride, silicon oxide, silicon oxynitride, and the like.

s2, forming a metal film layer on the back surface obtained in the step S1;

In the preparation method, metal in the metal film layer reacts with silicon in the corresponding semiconductor layer in contact with the metal film layer to form metal silicide, and the doping elements except the silicon in the corresponding semiconductor layer are inevitably doped, and the doping concentration of the doping elements can be regulated by the conditions for forming the metal film layer, the conditions for heat treatment and the doping concentration of the corresponding semiconductor layer.

In some preferred embodiments of the present invention, the metal thin film layer has a thickness of 5 to 20nm. Further, after heat treatment, the thickness of the metal film layer with proper thickness is 2-20nm.

The metal film layer can be a single metal film layer or an alloy film layer. In some preferred embodiments of the present invention, the metal thin film layer is at least one of a nickel metal film layer, an aluminum metal film layer, a platinum metal film layer, a cobalt metal film layer, a titanium metal film layer, a tungsten metal film layer, a nickel alloy metal film, an aluminum alloy metal film, a platinum alloy metal film, a cobalt alloy metal film layer, a titanium alloy metal film, and a tungsten alloy metal film.

Further preferably, the conditions of the magnetron sputtering include: vacuum degree of 5X 10 ^-3 Pa- 5×10 ^-1 Pa, the sputtering power is 2-5kW, and the sputtering time is 30-90s. By adopting the preferable scheme of magnetron sputtering, the metal film layer has lower defect density and better crystallinity and uniformity, and is more beneficial to realizing higher film quality and deposition rate.

Further preferably, the evaporation conditions include: vacuum degree of 5X 10 ^-3 Pa- 5×10 ^-1 Pa, the evaporation heating power is 5-10kW, and the evaporation time is 30-120s. By adopting the preferable scheme of vapor deposition, the existence of impurities can be reduced, and higher film purity can be realized more easily.

In some preferred embodiments of the present invention, the heat treatment in an anaerobic environment in S3 includes: under the anaerobic environment, adopting laser irradiation at 300-350 ℃ to carry out rapid photo-thermal treatment for 5-60s; or annealing at 100-220 deg.C for 5-30min in anaerobic environment. The photo-thermal treatment refers to heat treatment under irradiation of a light source, namely, laser energy is locally focused on the surface or the inside of a material, so that the material absorbs the light energy and is converted into heat energy, and local temperature rise is caused. The annealing treatment refers to no light source irradiation and only heat treatment.

In the third etching of the present invention S4, only the silicon alloy layer may be etched, or part (such as the second doped silicon crystal layer) or all (i.e. the second passivation layer) of the second semiconductor layer may be etched to form insulation grooves with different depths or thicknesses.

In the present invention, the third etching in S4 may be conventional wet etching, and in this regard, the inventor has further studied and found that ohmic contacts are formed between the silicon alloy layer and the corresponding doped silicon layer, and the wet etching is relatively difficult to orient the slot, and even if the slot is opened by the wet etching, the slot may have a certain influence on other structures. In some more preferred embodiments of the present invention, the third etching of S4 is performed using a laser technique.

Further preferably, the laser used is a laser having a pulse width of the order of picoseconds. Picosecond-level laser, on the first hand, very fine processing can be achieved due to the extremely short pulses generated by the picosecond laser; in a second aspect, since the pulse time of the picosecond laser is very short, it produces a relatively small heat affected zone in the material, which helps to avoid thermal damage caused during processing; in a third aspect, the pulse energy generated by the picosecond laser is relatively low, so that the material is less thermally affected during laser irradiation; thereby being more beneficial to reducing the heat influence of the laser irradiation process, avoiding the heat damage possibly caused in the processing process and maximally reducing the deformation, cracking or other heat effects of the material.

s101, providing a silicon wafer;

s104, removing all the residual mask layers;

s11, providing a silicon wafer;

s14, removing all the residual mask layers;

The back contact cell of the present invention may further comprise a step of sequentially forming a front passivation layer and an optional anti-reflection layer on the front surface of the silicon wafer, preferably after forming the second semiconductor layer, and then performing a second etching; or before or after the first passivation layer is formed. The composition of the front passivation layer and the anti-reflection layer is the same as that in the first aspect, and will not be described herein.

The back contact battery is not provided with the main grid and the fine grid, and electrode wires are directly welded when the back contact battery is applied and assembled, specifically, the outer surfaces of a P region formed in the area of the first semiconductor opening area and an N region formed in the area of the second semiconductor opening area are respectively welded with welding strips by using solder paste in a mode of referencing electrodes when the assembly is packaged, and the welding strips are copper strips, aluminum strips and the like.

In a third aspect, the present invention provides a back contact battery manufactured by the manufacturing method of the back contact battery of the second aspect, the structure and composition of the back contact battery being the same as those of the back contact battery of the first aspect.

The following detailed description of the embodiments of the invention is exemplary and is merely illustrative of the invention and not to be construed as limiting the invention.

Example 1

A back contact battery as shown in fig. 8, prepared as follows:

s1 comprises the following steps:

s101, providing a silicon wafer 1;

s102, forming a front passivation layer (specifically an intrinsic amorphous silicon layer with thickness of 6nm, thickness of 10nm and effective doping concentration of 5e19 cm) ^-3 An antireflective layer (specifically silicon nitride) with a thickness of 100nm, forming the front side stack 3. Then forming a first semiconductor layer and a mask layer a1 on the back surface of the silicon wafer 1, wherein the first semiconductor layer comprises a first tunneling oxide layer 2 and an N-type first doped polycrystalline layer 4 which are sequentially formed on the back surface, as shown in fig. 1 and 2; the first doped polycrystalline layer 4 has a thickness of 80nm and an effective doping concentration of 1e20cm ^-3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the first tunneling oxide layer 2 is 2nm; the thickness of the mask layer a1 is 50nm, and the mask layer a1 is specifically silicon nitride.

S103, as shown in FIG. 3, performing first etching on the first semiconductor layer on the back surface obtained in S102 to form first opening areas Wp with the interval distribution width of 500 μm;

s104, removing the mask layer a1, as shown in FIG. 4;

s105, forming a second semiconductor layer on the back surface obtained in S104, wherein the second semiconductor layer includes an intrinsic amorphous silicon layer 5 and a P-type second doped silicon crystal layer 6 (specifically, a doped amorphous silicon layer) sequentially formed on the back surface as shown in fig. 5; the thickness of the second doped silicon crystal layer 6 is 10nm, and the effective doping concentration is 1e20cm ^-3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the intrinsic amorphous silicon layer 5 is 10nm;

and S106, performing second etching on the region with the first semiconductor layer remained on the back surface obtained in the step S105, so as to expose the first semiconductor layer, and forming a second opening region Wn with a width of 150 μm which is arranged at intervals with the first opening region Wp, as shown in FIG. 6.

S2, forming a metal film layer 8 on the back surface obtained in the step S106 in a full coverage mode, wherein the thickness of the metal film layer 8 is 8nm as shown in FIG. 7; the metal film layer 8 is a nickel metal film layer.

The metal isThe film layer 8 is obtained by adopting a magnetron sputtering mode for coating, and the specific process comprises the following steps: putting the battery piece obtained in the step S106 into a magnetron sputtering device, and vacuumizing until the vacuum degree reaches 5 multiplied by 10 ^-2 Pa, the sputtering power of the nickel target was set to 2.4kW, and 34s were sputtered to obtain a nickel metal film having a thickness of 8 nm.

S3, placing the intermediate product obtained in the S2 in an anaerobic environment for heat treatment, and enabling the metal of the metal film layer 8 to react with silicon in the doped amorphous silicon layer or the doped polycrystalline silicon layer which are in contact with the metal to generate a nickel-silicon alloy layer 7; as shown in fig. 7; the thickness of the nickel-silicon alloy layer 7 is 8nm, and the square resistance is 35。

The nickel-silicon alloy layer 7 contains nickel silicide (NiSi ₂ NiSi) and doping with elemental phosphorus and effective doping concentration of 5e17cm ^-3 The method comprises the steps of carrying out a first treatment on the surface of the The heat treatment mode is as follows: annealing at 150 ℃ for 20min under the anaerobic environment.

S4, performing third etching on the nickel-silicon alloy layer 7 positioned between the second opening area and the first opening area on the back surface obtained in the step S3, and forming an insulating groove 9 with the width of 0.05mm as shown in FIG. 8; the third etching adopts a laser technology, and the laser pulse width is 10 picoseconds.

Example 2

The process was performed with reference to example 1, and the difference from example 1 was only that the heat treatment process of S3 was different, and the specific heat treatment method was: and (3) performing rapid photo-thermal treatment for 30s by adopting laser irradiation at 300 ℃ in an anaerobic environment. In this example, the nickel-silicon alloy layer obtained had a thickness of 8nm and a sheet resistance of 37 Effective doping concentration of 1e17cm ^-3 。

Example 3

The process is performed with reference to example 1, and the difference from example 1 is that the metal film layer in S2 is obtained by vapor deposition, and the thickness is the same as that of example 1, and the specific process is as follows: the vacuum degree of vapor deposition is 5 multiplied by 10 ^-2 Pa, the evaporation heating power was 8kW, and the evaporation time was 60s.

Example 4

With reference to example 1, the difference from example 1 is that the metal thin film layer in S2 is an aluminum metal film layer, and the preparation process of the aluminum metal film layer is as follows: the vacuum was kept constant as in example 1, and the sputtering power of the aluminum target was set to 2.4kW; sputtering for 30s; obtaining an aluminum metal film with the thickness of 8 nm; s3, correspondingly obtaining an aluminum-silicon alloy layer with the thickness of 8nm and the square resistance of 42Effective doping concentration of 5e17cm ^-3 。

Example 5

With reference to example 1, the difference from example 1 is that the metal thin film layer in S2 is a platinum metal thin film layer, and the preparation process of the platinum metal thin film layer is as follows: the vacuum was kept constant as in example 1, and the sputtering power of the platinum target was set to 2.5kW; sputtering for 30s; obtaining a platinum metal film with the thickness of 8 nm; s3, correspondingly obtaining a platinum-silicon alloy layer with the thickness of 8nm and the square resistance of 40 Effective doping concentration of 5e17cm ^-3 。

Example 6

With reference to example 1, the only difference from example 1 is that the doped amorphous silicon layer in the second semiconductor layer in S105 is replaced with a doped microcrystalline silicon layer having a thickness of 10nm.

Example 7

With reference to embodiment 1, the difference from embodiment 1 is that the second semiconductor layer in S1 is formed by the second doped silicon crystal layer 6 and the first tunneling oxide layer 2 of the corresponding region, and as shown in fig. 9, S1 specifically is:

s11, providing a silicon wafer 1;

s12, sequentially forming a front passivation layer (which is the same as that of the embodiment 1) and an anti-reflection layer (which is the same as that of the embodiment 1) on the front surface of the silicon wafer 1 to form a front lamination layer 3; sequentially forming a first semiconductor layer and a mask layer on the back surface of the silicon wafer 1, wherein the first semiconductor layer comprises a first tunneling oxide layer 2 and a first doped polycrystalline layer 4 which are sequentially formed on the back surface;

s13, performing first etching on the first doped polycrystalline layer 4 and the mask layer in the back preset area obtained in the S12 to form first opening areas which are distributed at intervals;

s14, removing all the residual mask layers;

s15, forming a second doped silicon crystal layer 6 on the back surface obtained in the step S14, and forming a second semiconductor layer by the second doped silicon crystal layer 6 and a part of the first tunneling oxide layer 2 covered by the second doped silicon crystal layer;

And S16, performing second etching on the area with the first semiconductor layer remained on the back surface obtained in the step S15 to expose part of the first semiconductor layer, so as to form a second opening area which is arranged with the first opening area. Wherein the thickness (or doping concentration) of each respective layer is the same as in example 1, respectively, with only structural differences.

Example 8

The process was performed with reference to example 1, and the difference from example 1 was only that the thickness of the silicon alloy layer was controlled to 19nm, and the process conditions were adjusted to meet the thickness: setting the sputtering power of the nickel target to be 4kW; sputtering for 40s; a nickel metal film having a thickness of 20nm was obtained.

Example 9

With reference to example 1, the only difference from example 1 is that the effective doping concentration of the first doped polycrystalline layer in S102 is adjusted to 5e19cm ^-3 So that the ratio of the surface doping index of the silicon alloy layer to the first doped polycrystalline layer is 1:10.

example 10

With reference to example 1, the only difference from example 1 is that the thickness of the first doped polycrystalline layer in S102 is adjusted to 300nm such that the ratio of the surface doping index of the silicon alloy layer to the first doped polycrystalline layer is 1:5.3.

example 11

With reference to example 1, the difference from example 1 is only that the effective doping concentration of the second doped silicon crystal layer in S105 is adjusted to 1e19cm ^-3 So that the ratio of the surface doping index of the silicon alloy layer to the second doped silicon crystal layer is 1:16.

example 12

With reference to example 1, the only difference from example 1 is that the thickness of the second doped silicon crystal layer in S105 is adjusted to 50nm such that the ratio of the surface doping index of the silicon alloy layer to the second doped silicon crystal layer is 1:32.

example 13

With reference to example 1, the difference from example 1 is only that the thickness of the first tunneling oxide layer in S102 is adjusted to be 1nm such that the ratio of the thickness of the silicon alloy layer to the thickness of the first tunneling oxide layer is 1:0.125.

example 14

The process was conducted with reference to example 1, and the difference from example 1 was only that the width of the insulation groove in S4 was 0.15mm.

Example 15

With reference to example 1, the difference from example 1 is only that the sputtering power in the magnetron sputtering of the metal thin film layer of S2 is 5kW, and a nickel metal film having a thickness of 20nm is obtained under this condition; the thickness of the nickel-silicon alloy layer obtained after the S3 heat treatment is 20nm, and the square resistance is 30Effective doping concentration of 1e18cm ^-3 。

Example 16

The process was conducted in accordance with example 1, and the difference from example 1 was that the annealing treatment temperature in S3 was 180℃and the annealing time was the same as that in example 1, and that the nickel-silicon alloy layer obtained under the conditions of 8nm in thickness and 40 in sheet resistance Effective doping concentration of 6e17cm ^-3 。

Example 17

The difference between the method according to embodiment 1 and embodiment 1 is that the third etching in S4 is a wet etching, and the specific process of the wet etching is as follows: and forming an insulation groove mask pattern of an insulation groove region required to be formed by exposing the back surface by adopting printing protective ink, corroding the exposed conductive film layer by adopting an etching solution to form an insulation groove, and removing the protective ink by adopting an alkaline solution (the composition of the protective ink is specifically sodium hydroxide solution, and the concentration of the protective ink is 2 weight percent).

Example 18

With reference to example 1, the difference from example 1 is only that the first semiconductor layer is replaced with a first intrinsic amorphous silicon layer and an N-type first doped amorphous silicon layer sequentially formed on the back surface in S102; the thicknesses of the first intrinsic amorphous silicon layer and the first N-type doped amorphous silicon layer are 10nm, and the effective doping concentration of the first doped amorphous silicon layer is the same as that of the first doped polycrystalline layer of embodiment 1.

Example 19

The method of example 1 was performed except that S104 was not performed, i.e., a part of the mask layer was remained.

Comparative example 1

With reference to example 1, the difference from example 1 is only that S2-S3 are not performed, but that a conventional conductive film layer and a metal fine gate line are used, specifically:

S01, after S1, sequentially and outwards covering and paving a transparent conductive film layer (ITO) on the first semiconductor layer and the second semiconductor layer, wherein the thickness of the transparent conductive film layer is 100nm;

s02, performing third etching on the transparent conductive film layer part of the back surface, which is positioned in the transition area between the second opening area and the first opening area, by adopting a wet etching mode to form an insulating groove 9 (the width is the same as that of the embodiment 1), namely, a wet grooving; the wet etching method comprises the following specific technical processes: the insulating groove mask pattern of the insulating groove region required to be formed is formed on the back surface by printing protective ink, then the exposed conductive film layer is corroded by adopting an etching solution to form an insulating groove 9, and then the protective ink is removed by an alkaline solution (the composition of the protective ink is sodium hydroxide solution, and the concentration of the protective ink is 2 wt%).

S03, forming metal thin grid lines (namely a first thin grid 13 and a second thin grid 14) on the corresponding areas of the second opening area and the first opening area respectively, wherein the metal thin grid lines, the first semiconductor layer and the second semiconductor layer are arranged in parallel and are parallel to the X-axis direction of the silicon wafer;

then, the following steps S5-S6 are performed:

s5, preparing insulating layers 12 alternately on the surfaces of the first opening areas and the surfaces of the second opening areas; the insulating layer 12 is prepared by printing insulating ink by screen printing.

S6, preparing a first main grid 10 and a second main grid 11 along the Y-axis direction in the transverse direction where the insulating layer 12 is arranged, as shown in fig. 10, wherein the preparation process is screen printing of silver main grids.

Comparative example 2

The reference to comparative example 1 is different from comparative example 1 only in that the etching of the insulating trench is performed using a laser, specifically, an ultraviolet laser, with a pulse width of 10ns.

Comparative example 3

With reference to example 1, the difference from example 1 is only that the heat treatment of S3 is not performed, in which case only a metal nickel thin film layer is plated, and no metal silicide is formed; the sheet resistance of the metallic nickel film layer is 55。

Test case

The back contact batteries obtained in the above examples and comparative examples were respectively passed through electrode lines and then subjected to battery performance testing, and specifically, the outer surfaces of P-region formed in the region of the first semiconductor opening region and N-region formed in the region of the second semiconductor opening region were respectively soldered with solder paste using a manner of referencing electrodes during package of the components, and the solder tapes were copper tape, aluminum tape, etc. (copper tape was used in this test example). The results of the performance test are shown in table 1.

Comparison of process flows (also called process):

the process flow (8 channels) adopted in the examples: the method comprises the steps of texturing and cleaning to form a double-sided polished silicon wafer, depositing a first semiconductor layer, depositing a first etching opening, depositing a second semiconductor layer, depositing a second etching opening, depositing a metal film layer, performing heat treatment to form a silicon alloy layer, and performing second etching to form an insulating groove.

Comparative example 1 process flow (10 lanes): the method comprises the steps of texturing and cleaning to form a double-sided polished silicon wafer, depositing a first semiconductor layer, depositing a first etching opening, depositing a second semiconductor layer, depositing a second etching opening, depositing a conductive film layer ITO, grooving an insulating groove, screen printing a fine grid, brushing insulating ink and screen printing a main grid.

The non-silicon cost refers to the cost of the battery piece production except the cost of the silicon wafer, and concretely comprises silver paste, a target material, chemicals, gas, depreciation and others, and the non-silicon cost of the conventional back contact battery produced in comparative example 1 is calculated and calculated preliminarily, wherein the silver paste in comparative example 1 accounts for 39% of the non-silicon cost, and the target material accounts for 7%. Because the invention adopts common metal targets which are cheaper than ITO targets and have low dosage, the cost of the targets is 4 percent of the cost of non-silicon targets.

TABLE 1

The above results show that, compared with the comparative example, the embodiment of the invention can realize simpler manufacturing process, and simultaneously, expensive low-temperature silver paste and transparent conductive film layers are not needed to be used, thereby greatly reducing the production cost of the battery and ensuring excellent battery conversion efficiency. The scheme of the comparative examples 1-2 with the conventional structure has long process and high production cost; the battery of comparative example 3 was significantly lower in conversion efficiency.

Furthermore, according to embodiment 1 and embodiments 2 to 19, the preferred structure or process scheme of the present invention can further improve the conversion efficiency of the battery on the basis of ensuring short manufacturing process and low production cost.

The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited thereto. Within the scope of the technical idea of the invention, a number of simple variants of the technical solution of the invention are possible, including combinations of the individual technical features in any other suitable way, which simple variants and combinations should likewise be regarded as being disclosed by the invention, all falling within the scope of protection of the invention.

Claims

1. A back contact cell comprises a silicon wafer having a front surface and a back surface, a first semiconductor layer and a second semiconductor layer arranged on the back surface and alternately arranged along Y-axis direction of the silicon wafer, wherein the first semiconductor layer comprises a first doped silicon crystalA layer comprising a second doped silicon crystalline layer, and an end portion of the second semiconductor layer extending onto an outer surface of an adjacent end portion of the first semiconductor layer to form a transition region, wherein the back contact cell further comprises a silicon alloy layer comprising a metal silicide disposed outwardly in a Z-axis direction, the silicon alloy layer is arranged on the outer surface of the second semiconductor layer and extends to the outer surface of the adjacent first doped silicon crystal layer, and an insulating groove is formed in a part of the silicon alloy layer corresponding to the transition region; wherein the sheet resistance of the silicon alloy layer is 5-70 。

2. The back contact battery of claim 1, wherein the metal element contained in the metal silicide comprises at least one of nickel, aluminum, platinum, cobalt, titanium, and tungsten.

3. The back contact battery of claim 2, wherein the metal silicide comprises at least one of nickel silicide, aluminum silicide, platinum silicide.

4. The back contact cell of claim 1, wherein the silicon alloy layer has a thickness of 2-30nm.

5. The back contact battery of claim 1, wherein the silicon alloy layer further comprises a doping element comprising boron or phosphorous.

6. The back contact cell of claim 5, wherein the ratio of the surface doping index of the silicon alloy layer to the first doped silicon crystal layer to the second doped silicon crystal layer is 1:1-250:3-800, wherein the in-plane doping index is the ratio of the effective doping concentration of the corresponding doped silicon layer to the thickness of the doped silicon layer.

7. According to claim 6A back contact cell is characterized in that the effective doping concentration of the silicon alloy layer is 1e17 cm ^-3 -1e18 cm ^-3 ；

And/or the number of the groups of groups,

the thickness of the first doped silicon crystal layer is 50-300nm, and the effective doping concentration is 1e19 cm ^-3 -4e20 cm ^-3 The thickness of the second doped silicon crystal layer is 10-50nm, and the effective doping concentration is 1e19 cm ^-3 -4e20 cm ^-3 。

8. The back contact cell of claim 1, wherein the first semiconductor layer further comprises a first passivation layer disposed on the back side of the silicon wafer, at least a portion of the first passivation layer being located between the back side of the silicon wafer and the first doped silicon crystal layer.

9. The back contact cell of claim 8, wherein the second semiconductor layer further comprises a second passivation layer disposed on the back side of the silicon wafer, the second passivation layer being located between the back side of the silicon wafer and the second doped silicon crystal layer; the second passivation layer comprises an intrinsic amorphous silicon layer or a second tunneling oxide layer, the thickness of the intrinsic amorphous silicon layer is 5-15nm, and the thickness of the second tunneling oxide layer is 1.5-2.5nm;

or,

the first passivation layer is arranged on the back surface of the silicon wafer in a full-coverage mode, the first doped silicon crystal layer and the second doped silicon crystal layer are both located on one side, far away from the back surface of the silicon wafer, of the first passivation layer, the second doped silicon crystal layer and a part of the first passivation layer covered by the second doped silicon crystal layer form a second semiconductor layer, and the first doped silicon crystal layer and the second doped silicon crystal layer are doped polycrystalline layers.

10. The back contact cell of claim 8, wherein the first passivation layer comprises a first tunneling oxide layer, the first doped silicon crystalline layer being a first doped polycrystalline layer; wherein,

the ratio of the thickness of the silicon alloy layer to the thickness of the first tunneling oxide layer is 1:0.05-1.25, and/or the thickness of the first tunneling oxide layer is 1.5-2.5nm.

11. The back contact battery of claim 1, wherein in the transition region, the extended end of the second semiconductor layer is in direct contact with the first semiconductor layer in the thickness direction or a mask layer is provided;

and/or the number of the groups of groups,

the width of the insulation groove is 0.03-0.15mm.

12. The back contact battery of claim 1, wherein the back contact battery is free of thin grids and main grids,

and/or the number of the groups of groups,

the back contact battery also comprises a front passivation layer which is arranged outwards on the front of the silicon wafer, wherein the front passivation layer is any one of intrinsic amorphous silicon, intrinsic amorphous externally superimposed doped microcrystalline silicon, tunneling silicon oxide and tunneling silicon oxide externally superimposed doped polycrystalline silicon.

13. A method for preparing a back contact battery, comprising the steps of:

s2, forming a metal film layer on the back surface obtained in the step S1;

14. The method for manufacturing a back contact battery according to claim 13, wherein the thickness of the metal thin film layer is 5-20nm;

and/or the number of the groups of groups,

the metal film layer is at least one of a nickel metal film layer, an aluminum metal film layer, a platinum metal film layer, a cobalt metal film layer, a titanium metal film layer, a tungsten metal film layer, a nickel alloy metal film, an aluminum alloy metal film, a platinum alloy metal film, a cobalt alloy metal film layer, a titanium alloy metal film and a tungsten alloy metal film;

And/or the number of the groups of groups,

the metal film layer in S2 is obtained by plating a film in a magnetron sputtering or vapor plating mode, and the magnetron sputtering conditions comprise: vacuum degree of 5X 10 ^-3 Pa- 5×10 ^-1 Pa, sputtering power of 2-5kW and sputtering time of 30-90s; the evaporation conditions include: vacuum degree of 5X 10 ^-3 Pa- 5×10 ^-1 Pa, the evaporation heating power is 5-10kW, and the evaporation time is 30-120s.

15. The method of claim 13, wherein the heat treatment in the anaerobic environment in S3 comprises:

under the anaerobic environment, adopting laser irradiation at 300-350 ℃ to carry out rapid photo-thermal treatment for 5-60s;

or annealing at 100-220 deg.C for 5-30min in anaerobic environment.

16. The method of claim 13, wherein the third etching in S4 uses a laser technique, and the laser used is a laser with a pulse width of picoseconds.

17. The method for manufacturing a back contact battery according to claim 13, wherein the process of S1 specifically includes:

s101, providing a silicon wafer;

s104, removing all the residual mask layers;

18. The method for manufacturing a back contact battery according to claim 13, wherein the process of S1 specifically includes:

s11, providing a silicon wafer;

s14, removing all the residual mask layers;

19. A back contact battery, characterized in that it is manufactured by the manufacturing method of a back contact battery according to any one of claims 13-18.

20. A battery assembly comprising a back contact cell according to any one of claims 1-12, or comprising a back contact cell according to claim 19, and solder strips directly provided on the surface of the silicon alloy layer corresponding to the different conductive areas in the back contact cell.