CN117594602A

CN117594602A - Thin film transistor substrate and display apparatus including the same

Info

Publication number: CN117594602A
Application number: CN202310967177.8A
Authority: CN
Inventors: 申星修; 梁祯烈; 李汉锡; 田惠知; 张允琼; 柳元相
Original assignee: LG Display Co Ltd
Current assignee: LG Display Co Ltd
Priority date: 2022-08-12
Filing date: 2023-08-02
Publication date: 2024-02-23

Abstract

Disclosed are a thin film transistor substrate and a display device including the same, the thin film transistor substrate including: a substrate; a first thin film transistor disposed on the substrate and including a first active layer and a first gate electrode; a second thin film transistor disposed on the substrate and including a second active layer and a second gate electrode disposed over the first active layer and the first gate electrode; a first insulating layer disposed between the first gate electrode and the second active layer; and a first connection electrode connecting the first active layer and the second active layer, wherein the first connection electrode extends through a first contact hole provided in the first insulating layer and is provided to contact each of the first active layer and the second active layer.

Description

Thin film transistor substrate and display apparatus including the same

Technical Field

The present disclosure relates to a thin film transistor substrate and a display device including the same.

Background

Since thin film transistors can be manufactured on a glass substrate or a plastic substrate, they are widely used as switching devices or driving devices for displays such as liquid crystal display devices or organic light emitting devices.

The display device includes a plurality of pixels and a driving unit for driving the plurality of pixels. The driving unit may include a plurality of thin film transistors. In particular, since a Gate In Panel (GIP) structure in which a gate driver is mounted on a display panel includes a plurality of thin film transistors, there is a problem in that a bezel size of a display device increases due to a size of the gate in panel structure.

Therefore, in order to reduce the size of the gate structure in the panel, a method of forming a large number of thin film transistors in a small area is required.

Disclosure of Invention

The present disclosure has been made in view of the above-described problems, and an object of the present disclosure is to provide a thin film transistor substrate and a display device including the thin film transistor substrate, which can form a large number of thin film transistors in a small region by disposing a plurality of thin film transistors up and down.

In accordance with an aspect of the present disclosure, the above and other objects can be accomplished by the provision of a thin film transistor substrate and a display device including the same, the thin film transistor substrate comprising: a substrate; a first thin film transistor disposed on the substrate and including a first active layer and a first gate electrode; a second thin film transistor disposed on the substrate and including a second active layer and a second gate electrode disposed over the first active layer and the first gate electrode; a first insulating layer disposed between the first gate electrode and the second active layer; and a first connection electrode connecting the first active layer and the second active layer, wherein the first connection electrode extends through a first contact hole provided in the first insulating layer and is provided to be in contact with each of the first active layer and the second active layer.

Drawings

The above and other objects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a schematic diagram of a display device according to one embodiment of the present disclosure.

Fig. 2 is a schematic diagram of a shift register according to one embodiment of the present disclosure.

Fig. 3 is a circuit diagram of a shift register according to one embodiment of the present disclosure.

Fig. 4 is a schematic diagram of a buffer unit of a shift register according to one embodiment of the present disclosure.

Fig. 5 is a schematic diagram of a buffer unit of a shift register according to another embodiment of the present disclosure.

Fig. 6 is a cross-sectional view of a buffer unit of a shift register according to one embodiment of the present disclosure.

Fig. 7 is a schematic plan view of a buffer unit of a shift register according to one embodiment of the present disclosure.

Fig. 8 is a cross-sectional view of a buffer unit of a shift register according to another embodiment of the present disclosure.

Fig. 9 is a schematic plan view of a buffer unit of a shift register according to another embodiment of the present disclosure.

Fig. 10 is a schematic cross-sectional view of a buffer unit of a shift register according to another embodiment of the present disclosure.

Fig. 11 is a schematic plan view of a buffer unit of a shift register according to another embodiment of the present disclosure.

Fig. 12 is a schematic cross-sectional view of a buffer unit of a shift register according to another embodiment of the present disclosure.

Fig. 13 is a schematic plan view of a buffer unit of a shift register according to another embodiment of the present disclosure.

Fig. 14 is a schematic cross-sectional view of a buffer unit of a shift register according to another embodiment of the present disclosure.

Fig. 15 is a schematic cross-sectional view of a buffer unit of a shift register according to another embodiment of the present disclosure.

Fig. 16 is a schematic cross-sectional view of a buffer unit of a shift register according to another embodiment of the present disclosure.

Fig. 17 is a schematic cross-sectional view of a buffer unit of a shift register according to another embodiment of the present disclosure.

Fig. 18 is a schematic cross-sectional view of a buffer unit of a shift register according to another embodiment of the present disclosure.

Fig. 19 is a schematic cross-sectional view of a buffer unit of a shift register according to another embodiment of the present disclosure.

Fig. 20 is a schematic cross-sectional view of a shift register according to another embodiment of the present disclosure.

Fig. 21 is a schematic cross-sectional view of a buffer unit of a shift register according to another embodiment of the present disclosure.

Fig. 22 is a schematic cross-sectional view of a shift register according to another embodiment of the present disclosure.

Fig. 23 is a schematic cross-sectional view of a display device according to one embodiment of the present disclosure.

Fig. 24 is a schematic diagram of a GIP circuit area according to one embodiment of the present disclosure.

Fig. 25 is a cross-sectional view of a buffer unit of a shift register according to another embodiment of the present disclosure.

Fig. 26 is a cross-sectional view of a buffer unit of a shift register according to another embodiment of the present disclosure.

Fig. 27 is a cross-sectional view of a buffer unit of a shift register according to another embodiment of the present disclosure.

Fig. 28 is a cross-sectional view of a buffer unit of a shift register according to another embodiment of the present disclosure.

Detailed Description

Advantages and features of the present disclosure and methods of accomplishing the same will be elucidated by the following embodiments described with reference to the accompanying drawings. This disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Furthermore, the present disclosure is limited only by the scope of the claims.

The shapes, dimensions, ratios, angles, and numbers disclosed in the drawings to describe embodiments of the present disclosure are merely examples, and thus the present disclosure is not limited to the exemplified details. Like numbers refer to like elements throughout. In the following description, when it is determined that detailed description of related known functions or configurations unnecessarily obscure the gist of the present disclosure, the detailed description will be omitted.

Where the terms "comprising," "having," and "including" are used in this specification, there may be another portion unless "only" is used. Unless specified to the contrary, singular terms may include the plural.

When elements are constructed, the elements are construed as including error ranges or tolerance ranges, although not explicitly described.

In describing positional relationships, for example, when the positional order is described as "on … …", "above … …", "under … …", "below … …", and "beside … …", unless "just" or "direct" is used, a case where there is no contact therebetween may be included.

If a first element is referred to as being "on" a second element, it is not intended that the first element necessarily be on the second element in the figures. The upper and lower portions of the subject may vary depending on the orientation of the subject. Thus, the case where a first element is located "on" a second element includes the case where the first element is located "under" the second element in the drawings or in an actual configuration as well as the case where the first element is located "on" the second element.

In describing the temporal relationship, for example, when the temporal sequence is described as "after", "subsequent", "next", and "before", unless "only" or "direct" is used, a discontinuous case may be included.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be termed a second element, and, similarly, a second element may be termed a first element.

It is to be understood that the term "at least one" includes all combinations relating to any one of the items. For example, "at least one of the first element, the second element, and the third element" may include all combinations of two or more elements selected from the first element, the second element, and the third element, and each of the first element, the second element, and the third element.

Features of various embodiments of the present disclosure may be partially or wholly coupled to one another or combined, and may be technically variously interoperable and driven with one another. Embodiments of the present disclosure may be performed independently of each other or may be performed together in an interdependent relationship.

In the drawings, the same or similar elements are denoted by the same reference numerals even though they are shown in different drawings.

In the embodiments of the present disclosure, the source and the drain are distinguished from each other for convenience of explanation. However, the source and drain may be used interchangeably. Thus, the source may be a drain, and the drain may be a source. Further, the source in any of the embodiments of the present disclosure may be a drain in another embodiment of the present disclosure, and the drain in any of the embodiments of the present disclosure may be a source in another embodiment of the present disclosure.

In one or more embodiments of the present disclosure, the source region is distinguished from the source region and the drain region is distinguished from the drain region for ease of illustration. However, the embodiments of the present disclosure are not limited to this structure. For example, the source region may be a source and the drain region may be a drain. Further, the source region may be a drain, and the drain region may be a source.

As shown in fig. 1, a display device according to one embodiment of the present disclosure may include a display panel 310, a gate driver 320, a data driver 330, and a controller 340.

The display panel 310 includes gate lines GL and data lines DL, and pixels P are disposed in intersections of the gate lines GL and the data lines DL. An image is displayed by driving the pixel P. The gate line GL, the data line DL, and the pixel P may be disposed on the substrate 100.

The controller 340 controls the gate driver 320 and the data driver 330. The controller 340 outputs a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 using signals supplied from an external system (not shown). In addition, the controller 340 samples input image data input from an external system and rearranges it to provide rearranged digital image data RGB to the data driver 330.

The gate control signal GCS includes a gate start pulse, a gate shift clock, a gate output enable signal, a start signal, and a gate clock. In addition, the gate control signal GCS may include a control signal for controlling the shift register.

The data control signal DCS includes a source start pulse, a source shift clock signal, a source output enable signal, and a polarity control signal.

The data driver 330 supplies a data voltage to the data line DL of the display panel 310. Specifically, the data driver 330 converts the image data RGB input from the controller 340 into analog data voltages and supplies the data voltages to the data lines DL.

According to one embodiment of the present disclosure, the gate driver 320 may be mounted on the display panel 310. In this way, a structure in which the gate driver 320 is directly mounted on the display panel 310 is referred to as a Gate In Panel (GIP) structure. In particular, in a Gate In Panel (GIP) structure, the gate driver 320 may be disposed on the substrate 100.

The gate driver 320 may include a shift register 350.

The shift register 350 sequentially supplies a gate-on signal to the gate line GL during one frame using the gate start pulse and the gate clock transmitted from the controller 340. In this case, one frame refers to a period in which one image is output through the display panel 310. The gate-on signal has a turn-on voltage capable of turning on a switching element provided in the pixel P.

In addition, the shift register 350 supplies a gate-off signal, which can turn off the switching element, to the gate line GL in the remaining portion of the frame where the gate-on signal is not supplied. The gate-on signal and the gate-off signal may be collectively referred to as a gate signal.

As shown in fig. 2, each of the plurality of GIP circuits GIP1 to GIP4 outputs the gate signals Vout1 to Vout4 during one frame and supplies them to the gate lines.

Specifically, the first Stage1 of the first GIP circuit GIP1 is started by a separate start signal Vst, and outputs the first gate signal Vout1 using the first clock signal CLK1 and supplies it to the first gate line.

Each of the second to fourth stages of the second to fourth GIP circuits GIP2 to GIP4 is activated by the start signal Vst including the gate signals Vout1 to Vout3 of the previous stage GIP circuits GIP1 to GIP3, and outputs the second to fourth gate signals Vout2 to Vout4 using the second to fourth clock signals CLK2 to CLK4 and supplies them to the second to fourth gate lines.

On the other hand, although not shown, when the last gate signal Vout is output at the stage of the last GIP circuit at the end of one frame, the stage of the last GIP circuit is initialized by receiving the reset signal Vreset. Subsequently, the first gate signal Vout1 is output at the first Stage1 of the first GIP circuit GIP1 at the start of the next frame, and the above-described process is repeated.

Fig. 3 is a circuit diagram of a shift register according to one embodiment of the present disclosure. Each of the plurality of GIP circuits GIP1 to GIP4 illustrated in fig. 2 may include the circuit illustrated in fig. 3, but is not necessarily limited thereto.

As shown in fig. 3, the GIP circuit includes a pull-up node Q, a pull-down node QB, a node controller NC, and a Buffer unit Buffer.

The buffer unit is connected to the output terminal, and includes a pull-up transistor Tu, a pull-down transistor Td, and a capacitor C.

When the pull-up node Q is charged with a gate high voltage, the pull-up transistor Tu is turned on and outputs a gate-on signal.

When the pull-down node QB is charged with the gate high voltage, the pull-down transistor Td is turned on and outputs a gate-off signal.

The capacitor C is for holding a high voltage supplied to the gate of the pull-up transistor Tu for one frame, and is disposed between the gate terminal and the source terminal of the pull-up transistor Tu.

The node controller NC controls the charging and discharging of the pull-up node Q and the pull-down node QB. The node controller NC may include a pull-up node controller nc_q for controlling the charge and discharge of the pull-up node Q and a pull-down node controller nc_qb for controlling the charge and discharge of the pull-down node QB. The pull-up node controller nc_q includes at least one transistor T for controlling the pull-up node Q _Q And the pull-down node controller nc_qb includes at least one transistor T for controlling the pull-down node QB _QB 。

The output of the gate signal Vout can be stably controlled by the node controller NC. Specifically, the node controller NC discharges the pull-down node QB to the gate low voltage when the pull-up node Q is charged with the gate high voltage, and discharges the pull-up node Q to the gate low voltage when the pull-down node QB is charged with the gate high voltage.

Therefore, when the start signal Vst is applied, the plurality of transistors T provided in the node controller NC pass _Q And T _QB The pull-up node Q is charged with a gate high voltage, and the pull-down node QB is discharged to a gate low voltage, and the high power voltage VDD is output as the gate signal Vout. In addition, when the discharge signal V _QB When applied, through a plurality of transistors T arranged in a node controller NC _Q And T _QB The pull-up node Q is charged with a gate low voltage, the pull-down node QB is charged with a gate high voltage, and the low power supply voltage VSS is output as the gate signal Vout.

As shown in fig. 4, the buffer unit of the shift register according to one embodiment of the present disclosure includes a first gate line GL1, a second gate line GL2, a first drain line DL1, a second drain line DL2, a first source line SL1, and a second source line SL2.

The first gate line GL1 is connected to the pull-up node Q so that a gate voltage may be applied to the pull-up transistor Tu. For example, two first gate lines GL1 connected to the left side of the drawing may be arranged in parallel.

The second gate line GL2 is connected to the pull-down node QB so that the gate voltage may be applied to the pull-down transistor Td.

The first drain line DL1 is connected to a wiring that supplies a high power supply voltage VDD so that the high power supply voltage VDD may be applied to the pull-up transistor Tu.

The first source line SL1 is electrically connected to an output terminal of the gate signal Vout so that the high power supply voltage VDD applied from the first drain line DL1 may be output to the gate signal Vout. In particular, two first source lines SL1 connected to the output terminal on the right side of the drawing may be arranged in parallel.

The second source line SL2 is connected to a wiring that supplies the low power supply voltage VSS so that the low power supply voltage VSS can be applied to the pull-down transistor Td.

The second drain line DL2 is electrically connected to an output terminal of the gate signal Vout so that the low power supply voltage VSS applied from the second source line SL2 may be output to the gate signal Vout.

The first source line SL1 and the second drain line DL2 are electrically connected to each other.

In addition, the buffer unit of the shift register according to one embodiment of the present disclosure includes a plurality of active lines AL arranged in a second direction (e.g., in a vertical direction). The plurality of pull-up transistors Tu and the plurality of pull-down transistors Td are arranged in regions where the plurality of active lines AL arranged in the second direction cross the first gate line GL1, the second gate line GL2, the first drain line DL1, the second drain line DL2, the first source line SL1, and the second source line SL2 arranged in the first direction. For convenience, a plurality of pull-up transistors Tu and a plurality of pull-down transistors Td are indicated with rectangular broken lines in the figure.

The plurality of pull-up transistors Tu are connected in parallel to each other, and each of the plurality of pull-up transistors Tu includes a gate electrode G formed of a portion of the first gate line GL1, a source electrode S formed of a portion of the first source line SL1, a drain electrode D formed of a portion of the first drain line DL1, and an active layer a formed of a portion of the active line AL.

The plurality of pull-down transistors Td are connected in parallel with each other, and each of the plurality of pull-down transistors Td includes a gate electrode G formed of a portion of the second gate line GL2, a source electrode S formed of a portion of the second source line SL2, a drain electrode D formed of a portion of the second drain line DL2, and an active layer a formed of another portion of the active line AL.

Since the first gate line GL1 and the first source line SL1 each include two, thereby forming a U-shaped structure interlocked with each other, and the second gate line GL2 and the second drain line DL2 are each formed as one, the number of the plurality of pull-up transistors Tu may be twice the number of the plurality of pull-down transistors Td. Therefore, reliability when the high power supply voltage VDD is output as the gate signal Vout can be improved.

The plurality of pull-up transistors Tu may be disposed in a structure of two or more layers up and down, and the plurality of pull-down transistors Td may also be disposed in a structure of two or more layers up and down, thereby reducing the width of the buffer unit of the shift register. This will be described later with reference to various sectional views.

Fig. 5 is a schematic diagram of a buffer unit of a shift register according to another embodiment of the present disclosure. Fig. 5 is different from the above-described fig. 4 in that the number of the first gate lines GL1 and the first drain lines DL1 extending in the first direction increases. Accordingly, the same reference numerals are assigned to the same configurations, and hereinafter, only different configurations will be described.

According to fig. 5, three first gate lines GL1 connected from one side (e.g., left side of the drawing) and two first drain lines DL1 connected from, for example, right side of the drawing are arranged in parallel. Accordingly, since the first gate line GL1, the first source line SL1, and the first drain line DL1 are formed in a U-shaped structure interlocked with each other, the number of the plurality of pull-up transistors Tu may be three times the number of the plurality of pull-down transistors Td.

In the case of fig. 5, a plurality of pull-up transistors Tu may be disposed in a structure of two or more layers up and down, and a plurality of pull-down transistors Td may also be disposed in a structure of two or more layers up and down, thereby reducing the width of the buffer unit of the shift register.

As shown in fig. 4 and 5, a large number of pull-up transistors Tu and pull-down transistors Td may be provided in the buffer unit of the shift register to improve reliability, and thus it is possible to increase the size of the buffer unit. However, according to one embodiment of the present disclosure, a method of disposing the plurality of pull-up transistors Tu and the plurality of pull-down transistors TD up and down to reduce the size of the buffer unit is provided, which will be described in detail below.

As shown in fig. 6, a buffer unit according to one embodiment of the present disclosure includes a substrate 100; first to seventh insulating layers 110, 120, 130, 140, 150, 160, 170; a first thin film transistor T1 including a first active layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1, and a second thin film transistor T2 including a second active layer A2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2; a capacitor including a first capacitor electrode C1 and a second capacitor electrode C2; and a first bridge electrode BE1 and a second bridge electrode BE2.

The first and second thin film transistors T1 and T2 may be formed of pull-up transistors Tu connected in parallel to each other. In this case, the first and second gates G1 and G2 may be electrically connected to the pull-up node Q, the first and second sources S1 and S2 may be electrically connected to an output terminal of the gate signal Vout, and the first and second drains D1 and D2 may be electrically connected to a wiring providing the high power supply voltage VDD.

Alternatively, the first thin film transistor T1 and the second thin film transistor T2 may be formed of pull-down transistors Td connected in parallel to each other. In this case, the first and second gates G1 and G2 may be electrically connected to the pull-down node QB, the first and second drains D1 and D2 may be electrically connected to an output terminal of the gate signal Vout, and the first and second sources S1 and S2 may be electrically connected to a wiring providing the low power supply voltage VSS.

For convenience of explanation, the first source S1 and the first drain D1 are distinguished, and the first source S1 and the first drain D1 may be changed from each other. For example, the first source S1 may be the first drain D1, and the first drain D1 may be the first source S1. The same is true between the second source S2 and the second drain D2.

The substrate 100 may be made of glass or plastic. In particular, the substrate 100 may be made of transparent plastic having a flexible property, such as polyimide. When polyimide is used as the substrate 100, a heat-resistant polyimide capable of withstanding high temperatures may be used in consideration of performing a high-temperature deposition process on the substrate 100.

The light blocking layer SL and the second capacitor electrode C2 are disposed on the substrate 100.

The light blocking layer SL is disposed to overlap the first active layer A1 of the first thin film transistor T1 to prevent or reduce external light from entering the first active layer A1. The light blocking layer SL may be omitted.

Although not illustrated, the second capacitor electrode C2 may be electrically connected to the light blocking layer SL, and may be integrally formed with the light blocking layer SL.

The second capacitor electrode C2 and the light blocking layer SL may be formed of the same material (e.g., metal or metal conductive material) in the same layer through the same process.

The first insulating layer 110 is disposed on the light blocking layer SL and the second capacitor electrode C2. The first insulating layer 110 may protect the first active layer A1 by blocking air and moisture. The first insulating layer 110 may be made of an inorganic insulating material such as silicon oxide, silicon nitride, or metal oxide, but is not limited thereto, and may be made of an organic insulating material. The first insulating layer 110 may be formed of a single layer or may be formed of multiple layers.

The first active layer A1 is disposed on the first insulating layer 110.

The first active layer A1 may include a channel portion A1n, a first connection portion A1a, and a second connection portion A1b. The first connection portion A1a may be connected to one side of the channel portion A1n, and the second connection portion A1b may be connected to the other side of the channel portion A1 n. The channel portion A1n is made of a semiconductor material and may overlap the first gate electrode G1 to be protected by the first gate electrode G1. The first and second connection portions A1a and A1b may have conductive characteristics by selectively making the semiconductor material conductive. The first and second connection parts A1a and A1b may not overlap the first gate electrode G1. The first connection portion A1a and the second connection portion A1b have excellent conductivity as compared to the channel portion A1n, and each can function as a wiring or a source/drain.

Although the second active layer A2 described below is not illustrated in detail, it may include a channel portion, a first connection portion, and a second connection portion in the same manner as the first active layer A1.

The second insulating layer 120 is disposed on the first active layer A1. The second insulating layer 120 insulates the first active layer A1 from the first gate electrode G1. The second insulating layer 120 may be formed of a single layer or multiple layers including an inorganic insulating material and/or an organic insulating material.

The first gate electrode G1 and the first capacitor electrode C1 of the first thin film transistor T1 are disposed on the second insulating layer 120.

The first gate electrode G1 is formed to overlap the first active layer A1, and the first capacitor electrode C1 is formed to overlap the second capacitor electrode C2. The first gate electrode G1 is connected to the first capacitor electrode C1, and the first gate electrode G1 and the first capacitor electrode C1 may be integrally formed.

The first gate electrode G1 and the first capacitor electrode C1 may be formed of the same material in the same layer through the same process.

The third insulating layer 130 is disposed on the first gate electrode G1 and the first capacitor electrode C1. The third insulating layer 130 may be formed of a single layer or multiple layers including an inorganic insulating material and/or an organic insulating material.

The fourth insulating layer 140 is formed on the third insulating layer 130. The fourth insulating layer 140 may serve as a planarization layer. The fourth insulating layer 140 may include a single layer or multiple layers including an organic insulating material, but is not limited thereto.

The fifth insulating layer 150 is formed on the fourth insulating layer 140. The fifth insulating layer 150 may be formed of a single layer or multiple layers including an inorganic insulating material and/or an organic insulating material.

The first source electrode S1 and the first drain electrode D1 of the first thin film transistor T1, and the second source electrode S2 and the second drain electrode D2 of the second thin film transistor T2 are disposed on the fifth insulating layer 150.

The first source electrode S1 of the first thin film transistor T1 may be electrically connected to the first active layer A1, particularly, the first connection portion A1a, and may also be electrically connected to the light blocking layer SL (not shown). Specifically, the first source electrode S1 is electrically connected to the first connection portion A1a of the first active layer A1 through contact holes provided in the second to fifth insulating layers 120, 130, 140, and 150, and is electrically connected to the light blocking layer SL through contact holes provided in the first to fifth insulating layers 110, 120, 130, 140, and 150. Therefore, the first source electrode S1 serves as a connection electrode electrically connecting the first active layer A1 and the light blocking layer SL. In addition, the first source electrode S1 serves as a connection electrode connecting the first active layer A1 and the second active layer A2.

The first drain electrode D1 of the first thin film transistor T1 is electrically connected to the first active layer A1, in particular, to the second connection portion A1b. Specifically, the first drain electrode D1 is electrically connected to the second connection portion A1b of the first active layer A1 through the contact holes provided in the second to fifth insulating layers 120, 130, 140, and 150. The first drain electrode D1 may serve as a connection electrode connecting the first active layer A1 with the first bridge electrode BE 1.

The second source electrode S2 of the second thin film transistor T2 may be integrally formed with the first source electrode S1. The second source electrode S2 may connect the second active layer A2 to the light blocking layer SL. In addition, the second source electrode S2 may connect the second active layer A2 with the first active layer A1.

The second source electrode S2 of the second thin film transistor T2 is connected to one side of the second active layer A2, and the second drain electrode D2 of the second thin film transistor T2 is connected to the other side of the second active layer A2. Although not specifically illustrated, the second drain electrode D2 of the second thin film transistor T2 is electrically connected to the first drain electrode D1 of the first thin film transistor T1. For example, one of the first and second drain electrodes D1 and D2 may extend to the other and BE connected to each other to BE integrally formed with each other, or the first and second drain electrodes D1 and D2 may BE electrically connected to each other by connecting first and second bridge electrodes BE1 and BE2 to BE described later.

The second active layer A2 is disposed on the second source electrode S2 and the second drain electrode D2.

A portion of the lower surface of the second active layer A2 is in direct contact with the upper surface and the side surface of the second source electrode S2, and is also in direct contact with the upper surface and the side surface of the second drain electrode D2. Specifically, one end of the lower surface of the second active layer A2 is in direct contact with a portion and one side of the upper surface of the second source electrode S2, and the other end of the lower surface of the second active layer A2 is in contact with a portion and one side of the upper surface of the second drain electrode D2.

Therefore, according to one embodiment of the present disclosure, since the lower end surface of the first source electrode S1 or the second source electrode S2 is in contact with the upper surface of the first active layer A1, and the side and top surfaces of the first source electrode S1 or the second source electrode S2 are in contact with the lower surface of the second active layer A2, the second thin film transistor T2 and the first thin film transistor T1 may be electrically connected to each other by the first source electrode S1 or the second source electrode S2 extending into the contact holes provided in the second to fifth insulating layers 120, 130, 140 and 150, thereby reducing the number of contact holes and masks for forming patterns.

The sixth insulating layer 160 is formed on the second active layer A2. The sixth insulating layer 160 may be formed of a single layer or multiple layers including an inorganic insulating material and/or an organic insulating material.

The second gate electrode G2 of the second thin film transistor T2 is disposed on the sixth insulating layer 160.

The seventh insulating layer 170 is disposed on the second gate electrode G2. The seventh insulating layer 170 may be formed of a single layer or multiple layers including an inorganic insulating material and/or an organic insulating material.

The first and second bridge electrodes BE1 and BE2 are disposed on the seventh insulating layer 170.

The first bridge electrode BE1 may BE electrically connected to the first drain electrode D1 through the contact hole provided in the sixth through seventh insulating layers 160 through 170, and the second bridge electrode BE2 may BE electrically connected to the second drain electrode D2 through the first contact hole CH1 provided in the sixth through seventh insulating layers 160 through 170.

When the first and second thin film transistors T1 and T2 are formed of the pull-up transistors Tu connected in parallel to each other, the first bridge electrode BE1 may connect the first drain D1 with a wiring providing the high power supply voltage VDD, and the first bridge electrode BE1 may BE formed as a part of the wiring providing the high power supply voltage VDD. In this case, the second bridge electrode BE2 is electrically connected to the first bridge electrode BE1, and the second bridge electrode BE2 may connect the second drain D2 with a wiring that supplies the high power supply voltage VDD, or may BE formed as a part of the wiring that supplies the high power supply voltage VDD.

When the first and second thin film transistors T1 and T2 are formed of the pull-down transistors Td connected in parallel to each other, the first bridge electrode BE1 may connect the first drain D1 with the output terminal of the gate signal Vout, and the first bridge electrode BE1 may BE formed as a part of the output terminal of the gate signal Vout. In this case, the second bridge electrode BE2 is electrically connected to the first bridge electrode BE1, and the second bridge electrode BE2 may connect the second drain D2 with the output terminal of the gate signal Vout, or may BE formed as a part of the output terminal of the gate signal Vout.

The first bridge electrode BE1 and the second bridge electrode BE2 may BE formed of the same material on the same layer through the same process. At least one of the first bridge electrode BE1 and the second bridge electrode BE2 may BE omitted.

Since the first thin film transistor T1 is disposed near the lower portion of the substrate 100 and the second thin film transistor T2 is disposed at the farther upper portion of the substrate 100, it is possible to more easily dispose a plurality of thin film transistors in the buffer unit, thereby reducing the size of the buffer unit and thus the bezel size of the display device.

In particular, when the second thin film transistor T2 includes the second active layer A2 having a high mobility characteristic, the second active layer A2 is directly connected to the second source electrode S2 and the second drain electrode D2 that are already disposed thereunder, so that a heat treatment process when forming the second source electrode S2 and the second drain electrode D2 does not affect the second active layer A2. So that deterioration of the high mobility characteristics of the second active layer A2 can be prevented or reduced.

Fig. 7 is a schematic plan view of a buffer unit of a shift register according to one embodiment of the present disclosure, which is a plan view of a region of the second thin film transistor T2 in fig. 6.

As shown in fig. 7, the second gate electrode G2 extends in a horizontal direction, the second drain electrode D2 is disposed at one side (e.g., an upper side) of the second gate electrode G2, the second source electrode S2 is disposed at the other side (e.g., a lower side) of the second gate electrode G2, and the second active layer A2 extends in a vertical direction and is disposed to overlap the second gate electrode G2, the second source electrode S2, and the second drain electrode D2.

In this case, the second bridge electrode BE2 is formed to overlap the second drain electrode D2 and the second active layer A2. The first contact hole CH1 is formed to overlap the second bridge electrode BE2, the second drain electrode D2, and the second active layer A2. The second bridge electrode BE2 and the second active layer A2 are connected through the first contact hole CH 1.

Fig. 8 is identical to fig. 6 except that the connection structure of the second bridge electrode BE2 is changed, so the same reference numerals are applied to the same configuration, and a different configuration will BE described below.

As shown in fig. 8, the second bridge electrode BE2 is connected to the second drain electrode D2 through the first contact hole CH1 provided in the sixth to seventh insulating layers 160 to 170.

That is, in fig. 6, the second bridge electrode BE2 is in contact with the second active layer A2, and in fig. 8, the second bridge electrode BE2 is in contact with the second drain electrode D2.

Fig. 9 is a schematic plan view of a buffer unit of a shift register according to another embodiment of the present disclosure, which is a plan view of a region of the second thin film transistor T2 in fig. 8.

Fig. 9 is identical to fig. 7 except for the change in the position of the second bridge electrode BE2, so the same reference numerals are applied to the same configuration, and a different configuration will BE described below.

As shown in fig. 9, the second bridge electrode BE2 is formed to overlap the second drain electrode D2 and the second active layer A2. In some cases, the second bridge electrode BE2 may overlap the second drain electrode D2, but may not overlap the second active layer A2.

The first contact hole CH1 overlaps the second bridge electrode BE2 and the second drain electrode D2, but does not overlap the second active layer A2. Accordingly, the second bridge electrode BE2 and the second drain electrode D2 are connected through the first contact hole CH 1.

Fig. 10 is identical to fig. 6 except that the connection structure of the second bridge electrode BE2 and the structure of the second active layer A2 are changed, and thus identical reference numerals are assigned to identical configurations, and only different configurations will BE described below.

As shown in fig. 10, the second bridge electrode BE2 is connected to the second drain electrode D2 through the first contact hole CH1 provided in the sixth to seventh insulating layers 160 to 170. That is, in fig. 6, the second bridge electrode BE2 is in contact with the second active layer A2, and in fig. 10, the second bridge electrode BE2 is in contact with the second drain electrode D2.

In addition, the second active layer A2 is in contact with one side of the second source electrode S2 and one side of the second drain electrode D2, and is not in contact with the upper surface of the second source electrode S2 and the upper surface of the second drain electrode D2.

Fig. 11 is a schematic plan view of a buffer unit of a shift register according to another embodiment of the present disclosure, which is a plan view of a region of the second thin film transistor T2 in fig. 10.

Hereinafter, only a configuration different from that of fig. 7 will be described.

As shown in fig. 11, the second active layer A2 is in contact with one end of the second source electrode S2 and one end of the second drain electrode D2, respectively, and does not overlap the second source electrode S2 and the second drain electrode D2.

The second bridge electrode BE2 overlaps the second drain electrode D2, but does not overlap the second active layer A2.

Fig. 12 is the same as fig. 6 except for the structural change of the second active layer A2, so the same reference numerals are applied to the same configuration, and different configurations will be described below.

As shown in fig. 12, the second active layer A2 is in contact with one side surface, the other side surface, and the entire upper surface of the second source electrode S2, and is also in contact with one side surface, the other side surface, and the entire upper surface of the second drain electrode D2.

Fig. 13 is a schematic plan view of a buffer unit of a shift register according to another embodiment of the present disclosure, which is a plan view of a region of the second thin film transistor T2 in fig. 12. Hereinafter, only a configuration different from that of fig. 7 will be described.

As shown in fig. 13, the second active layer A2 is formed to overlap the entire second source electrode S2 and the second drain electrode D2.

The second bridge electrode BE2 is formed to overlap the second drain electrode D2 and the second active layer A2.

The first contact hole CH1 is formed to overlap the second bridge electrode BE2, the second drain electrode D2, and the second active layer A2. The second bridge electrode BE2 and the second active layer A2 are connected through the first contact hole CH 1.

Fig. 14 is the same as fig. 6 except for the structural change of the second active layer A2, so the same reference numerals are applied to the same configuration, and different configurations will be described below.

As shown in fig. 14, the second active layer A2 is in contact with one side surface of the second source electrode S2 and is not in contact with the upper surface of the second source electrode S2. However, the second active layer A2 is in contact with a portion of the upper surface and one side surface of the second drain electrode D2.

Fig. 15 is the same as fig. 6 except for the structural change of the second active layer A2, so the same reference numerals are applied to the same configuration, and different configurations will be described below.

As shown in fig. 15, the second active layer A2 contacts one side surface, the other side surface, and the entire upper surface of the second source electrode S2. However, the second active layer A2 is in contact with a portion of the upper surface and one side surface of the second drain electrode D2.

As shown in fig. 14 and 15, an overlapping structure between one side of the second active layer A2 and the second source electrode S2 may be different from an overlapping structure between the other side of the second active layer A2 and the second drain electrode D2.

Fig. 16 is different from fig. 6 in that the second active layer A2 is in direct contact with the first active layer A1, and the third active layer A3 is in direct contact with the first active layer A1. Hereinafter, only different configurations will be described.

As shown in fig. 16, the second active layer A2 is connected to the first active layer A1 through contact holes provided in the second to fifth insulating layers 120, 130, 140, and 150. Specifically, the connection portion of the second active layer A2 is connected to the connection portion of the first active layer A1, and the connection portion of the second active layer A2 extends into the contact hole provided in the second to fifth insulating layers 120, 130, 140, and 150. Therefore, the connection portion of the second active layer A2 extending into the contact hole serves as a connection electrode connecting the first active layer A1 and the second active layer A2.

The second source electrode S2 is disposed at one side of the upper surface of the second active layer A2, and the second drain electrode D2 is disposed at the other side of the upper surface of the second active layer A2. The entire lower surface of the second source electrode S2 may be in contact with the one side of the upper surface of the second active layer A2, and the entire lower surface of the second drain electrode D2 may be in contact with the other side of the upper surface of the second active layer A2.

In addition, the second bridge electrode BE2 contacts the second drain electrode D2 through contact holes provided in the sixth to seventh insulating layers 160 to 170. In some cases, the second bridge electrode BE2 may BE in contact with the second active layer A2 through contact holes provided in the sixth to seventh insulating layers 160 to 170.

The third active layer A3 is connected to the first active layer A1 through contact holes provided in the second to fifth insulating layers 120, 130, 140, 150. In this case, the third active layer A3 may be formed on the same layer through the same process as the second active layer A2. The third active layer A3 may be formed of the same material having excellent conductivity as the connection portion of the second active layer A2.

The first drain electrode D1 is disposed on the upper surface of the third active layer A3. The entire lower surface of the first drain electrode D1 may be in contact with the upper surface of the third active layer A3.

In addition, the first bridge electrode BE1 contacts the first drain electrode D1 through contact holes provided in the sixth to seventh insulating layers 160 to 170. In some cases, the first bridge electrode BE1 may contact the third active layer A3 through contact holes provided in the sixth to seventh insulating layers 160 to 170.

According to another embodiment of the present disclosure, since the second active layer A2 is in contact with the first active layer A1, the second thin film transistor T2 and the first thin film transistor T1 may be electrically connected to each other by one second active layer A2 extending to the contact hole provided in the second to fifth insulating layers 120, 130, 140 and 150, thereby reducing the number of contact holes and masks for forming patterns.

Fig. 17 is different from fig. 16 described above in that the second active layer A2 and the second source electrode S2 extend inside one contact hole, and the third active layer A3 and the first drain electrode D1 extend inside one contact hole.

Fig. 18 is different from fig. 6 in that the first and second active layers A1 and A2 overlap each other, and the first and second gate electrodes G1 and G2 overlap each other.

As shown in fig. 18, since the first active layer A1, the second active layer A2, the first gate electrode G1, and the second gate electrode G2 are formed to overlap each other, the entire region of the first thin film transistor T1 may be formed to overlap the entire region of the second thin film transistor T2, and thus the size of the buffer unit may be further reduced.

In addition, in fig. 18, the first drain electrode D1 and the second drain electrode D2 are integrally formed with each other, and thus the first bridge electrode BE1 and the second bridge electrode BE2 are integrally formed with each other.

Fig. 19 differs from fig. 6 in that the position of the capacitor is changed upward.

Specifically, the first capacitor electrode C1 may be formed of the same material on the same layer through the same process as the second gate electrode G2. In this case, the first capacitor electrode C1 is connected to the second gate electrode G2, and the first capacitor electrode C1 and the second gate electrode G2 may be integrally formed.

In addition, the second capacitor electrode C2 is formed on the same layer as the first source electrode S1 and the second source electrode S2 while overlapping the first capacitor electrode C1. The second capacitor electrode C2 may be integrally formed with the first source electrode S1 and the second source electrode S2. Accordingly, the capacitor may be constituted by the first capacitor electrode C1 and the second capacitor electrode C2 spaced apart from each other with the sixth insulating layer 160 interposed therebetween.

In fig. 6 to 19, a two-stage thin film transistor structure in which a second thin film transistor T2 is formed on a first thin film transistor T1 is illustrated, but the present disclosure is not limited thereto, and may include a three-stage thin film transistor structure in which a third thin film transistor T3 is additionally formed on the second thin film transistor T2, in some cases, a four-stage thin film transistor structure or more.

In addition, fig. 6 to 19 describe a case where the first thin film transistor T1 and the second thin film transistor T2 are composed of the pull-up transistor Tu connected in parallel to each other or the pull-down transistor Td connected in parallel to each other. However, the present disclosure is not necessarily limited thereto, and according to another embodiment of the present disclosure, one of the first and second thin film transistors T1 and T2 may be made of the pull-up transistor Tu, and the other may be made of the pull-down transistor Td. In this case, the first and second drain electrodes D1 and D2 may be electrically insulated from each other, and one of the first and second drain electrodes D1 and D2 may be electrically connected to a wiring that supplies the high power supply voltage VDD, and the other may be electrically connected to a wiring that supplies the low power supply voltage VSS.

As shown in fig. 20, one first GIP circuit may include a plurality of sub-GIP circuits. The plurality of sub-GIP circuits may include a first sub-GIP circuit GIP 1A, a second sub-GIP circuit GIP 1B, a third sub-GIP circuit GIP 1C, and a fourth sub-GIP circuit GIP 1D, and each of the sub-GIP circuits may include a sub-shift register. For example, according to fig. 24, which will be described later, the first sub-GIP circuit GIP 1A may include a circuit for outputting the gate signal GS, the second sub-GIP circuit GIP 1B may include a circuit for outputting the sensing control signal SENSE, the third sub-GIP circuit GIP 1C may include a circuit for outputting the initialization signal ITIN, and the fourth sub-GIP circuit GIP 1D may include a circuit for outputting the light emission control signal EM.

The number and arrangement of the plurality of sub GIP circuits GIP 1A, GIP 1B, GIP C and GIP 1D can be variously changed.

According to another embodiment of the present disclosure, the second sub-GIP circuit GIP 1B is disposed above the first sub-GIP circuit GIP 1A, and the fourth sub-GIP circuit GIP 1D is disposed above the third sub-GIP circuit GIP 1C. In addition, the first sub-GIP circuit GIP 1A and the third sub-GIP circuit GIP 1C are disposed at the same height, and the second sub-GIP circuit GIP 1B and the fourth sub-GIP circuit GIP 1D are disposed at the same height. Therefore, the area of the shift register can be reduced.

Fig. 21 is a schematic cross-sectional view of a buffer unit of a shift register according to another embodiment of the present disclosure, corresponding to an embodiment in which the second sub-GIP circuit GIP 1B in fig. 20 is disposed above the first sub-GIP circuit GIP 1A.

As shown in fig. 21, each of the shift registers of the first and second sub-GIP circuits GIP 1A and GIP 1B includes a first thin film transistor T1, a second thin film transistor T2, a first capacitor electrode C1, and a second capacitor electrode C2.

The configurations of the first thin film transistor T1, the second thin film transistor T2, the first capacitor electrode C1, and the second capacitor electrode C2 may be variously changed as in the above-described embodiments. In fig. 21, the first thin film transistor T1, the second thin film transistor T2, the first capacitor electrode C1, and the second capacitor electrode C2 are illustrated in the same manner as in fig. 6, but are not limited thereto.

The configuration of the light blocking layer SL, the first thin film transistor T1, the second thin film transistor T2, the first capacitor electrode C1, and the second capacitor electrode C2 provided in the first sub GIP circuit GIP 1A is the same as in fig. 6, and thus duplicate descriptions will be omitted.

To illustrate the structure of the second sub GIP circuit GIP 1B, the light blocking layer SL and the second capacitor electrode C2 are disposed on the fourth insulating layer 140, the fifth insulating layer 150 is disposed on the light blocking layer SL and the second capacitor electrode C2, the first active layer A1 is disposed on the fifth insulating layer 150, the sixth insulating layer 160 is disposed on the first active layer A1, the first gate G1 and the first capacitor electrode C1 are disposed on the sixth insulating layer 160, the seventh insulating layer 170 is sequentially disposed on the first gate G1 and the first capacitor electrode, the first source S1 and the first drain D1 and the second source S2 and the second drain D2 are disposed on the seventh insulating layer, the second active layer A2 is disposed on the first source S1 and the first drain D1 and the second drain D2, the eighth insulating layer 160 is disposed on the second active layer A2, the second gate G2 is disposed on the eighth insulating layer 180, the ninth gate insulating layer 190 is disposed on the second bridge electrode BE2 and the ninth bridge electrode 190 is disposed on the ninth bridge electrode BE 2.

As described above, according to one embodiment of the present disclosure, the first active layer A1 of the second sub-GIP circuit GIP 1B may be formed in the same process as the second active layer A2 of the first sub-GIP circuit GIP 1A, and the first gate electrode G1 of the second sub-GIP circuit GIP 1B may be formed in the same process as the second gate electrode G2 of the first sub-GIP circuit GIP 1A on the same layer, and thus the process may be simplified while reducing the size of the buffer unit of the shift register.

Fig. 22 is a schematic cross-sectional view of a shift register according to another embodiment of the present disclosure. Fig. 22 shows that the arrangement structure of the sub GIP circuits GIP 1A, GIP 1B, GIP C and GIP 1D is different from the arrangement structure of fig. 20 described above.

According to another embodiment of the present disclosure, the second sub-GIP circuit GIP 1B is disposed above the first sub-GIP circuit GIP 1A, the third sub-GIP circuit GIP 1C is disposed above the second sub-GIP circuit GIP 1B, and the fourth sub-GIP circuit GIP 1D is disposed above the third sub-GIP circuit GIP 1C. Therefore, the area of the shift register can be further reduced.

As shown in fig. 23, a plurality of sub GIP circuits GIP 1A, GIP 1B, GIP C and GIP 1D may be disposed under an active array including an organic light emitting device. Since the area of the active array may be larger than the areas of the plurality of sub-GIP circuits GIP 1A, GIP 1B, GIP C and GIP 1D, a portion of the active array may not overlap the plurality of sub-GIP circuits GIP 1A, GIP 1B, GIP C and GIP 1D.

In this way, according to one embodiment of the present disclosure, since the plurality of sub GIP circuits GIP 1A, GIP 1B, GIP C and GIP 1D are disposed under the active array, a bezel area of the display device can be removed.

As shown in fig. 24, the plurality of GIP circuits GIP1, GIP2, and GIP3 are vertically arranged, and the plurality of clock lines CL1, CL2 and the plurality of power supply lines PL1 and PL2 are vertically arranged while overlapping the plurality of GIP circuits GIP1, GIP2, and GIP 3.

The plurality of clock lines CL1, CL2 include a first clock line CL1 that transmits the first clock signal CLK1 to the plurality of GIP circuits GIP1, GIP2, and GIP3, and a second clock line CL2 that transmits the second clock signal CLK2 to the plurality of GIP circuits GIP1, GIP2, and GIP 3. Although only two clock lines CL1 and CL2 are illustrated in the drawing, the number of clock lines CL1 and CL2 may be three or more.

The plurality of power lines PL1, PL2 include a first power line PL1 transmitting a high power supply voltage VDD to the plurality of GIP circuits GIP1, GIP2, and GIP3, and a second power line PL2 transmitting a low power supply voltage VSS to the plurality of GIP circuits GIP1, GIP2, and GIP 3.

In this way, since the plurality of clock lines CL1, CL2 and the plurality of power supply lines PL1, PL2 are formed to overlap the plurality of GIP circuits GIP1, GIP2, and GIP3, the bezel area of the display device can be reduced.

Fig. 25 is a cross-sectional view of a buffer unit of a shift register according to another embodiment of the present disclosure, which corresponds to the GIP circuit region of fig. 24. The following embodiments of fig. 26 to 28 correspond to the GIP circuit region of fig. 24.

The buffer unit according to fig. 25 is different from the buffer unit according to fig. 6 in that the first power line PL1 and the clock lines CL1 and CL2 are added. Therefore, hereinafter, only the configuration different from fig. 6 will be described.

As shown in fig. 25, the first power line PL1 and the clock lines CL1 and CL2 are disposed under the second active layer A2 of the second thin film transistor T2. The first power line PL1 and the clock lines CL1 and CL2 may be formed of the same material on the same layer, for example, the same material on the same layer as the first gate electrode G1 of the first thin film transistor T1, and in this case, the process may be simplified.

The first power line PL1 may be electrically connected to the second drain electrode D2 of the second thin film transistor T2. For example, the second drain electrode D2 may be connected to the first power line PL1 through contact holes provided in the third to fifth insulating layers 130, 140, and 150.

Since the second drain D2 is connected to the first power line PL1 transmitting the high power voltage VDD, the first and second thin film transistors T1 and T2 are composed of pull-up transistors Tu connected in parallel to each other.

Although not illustrated, when the first and second thin film transistors T1 and T2 are composed of pull-down transistors Td connected in parallel to each other, the second power line PL2 in fig. 24 may be connected to the second source S2 to apply the low power voltage VSS to the second source S2.

Fig. 26 is a sectional view of a buffer unit of a shift register according to another embodiment of the present disclosure, which is different from the buffer unit according to fig. 25 in that formation positions of clock lines CL1 and CL2 are changed. Therefore, hereinafter, only the configuration different from fig. 25 will be described.

As shown in fig. 26, the clock lines CL1 and CL2 are formed below the first power line PL 1. For example, the clock lines CL1 and CL2 may be formed of the same material on the same layer through the same process as the light blocking layer SL and the second capacitor electrode C2.

In addition, at least a portion of the clock lines CL1 and CL2 may overlap the first power line PL 1.

In this way, since the clock lines CL1 and CL2 are formed below the first power line PL1, the clock swing signals of the clock lines CL1 and CL2 can be shielded by the first power line PL 1.

Fig. 27 is a sectional view of a buffer unit of a shift register according to another embodiment of the present disclosure, which is different from the buffer unit according to fig. 26 in that the first power line PL1 additionally extends under the second active layer A2. Therefore, hereinafter, only the configuration different from fig. 26 will be described.

As shown in fig. 27, the first power line PL1 may extend below the second active layer A2, and thus may overlap with a channel portion of the second active layer A2. Accordingly, external light entering the channel portion of the second active layer A2 may be blocked by the first power line PL1.

On the other hand, although not illustrated, in the embodiment of fig. 25, the first power line PL1 may extend below the second active layer A2 and may overlap the channel portion of the second active layer A2.

Fig. 28 is a sectional view of a buffer unit of a shift register according to another embodiment of the present disclosure, which is different from the buffer unit according to fig. 27 in that the first power line PL1 is not connected to the second drain electrode D2 but is connected to the second bridge electrode BE2. Therefore, hereinafter, only the configuration different from fig. 27 will be described.

As shown in fig. 28, the second bridge electrode BE2 is connected to the first power line PL1 through contact holes provided in the third to seventh insulating layers 130, 140, 150, 160, and 170. Accordingly, the first power line PL1 may BE electrically connected to the second drain electrode D2 through the second bridge electrode BE2 (alternatively, through the second connection portion of the second bridge electrode BE2 and the second active layer A2).

Further, although not illustrated, in the above-described embodiments of fig. 25 and 26, the first power line PL1 may not BE connected to the second drain electrode D2, but may BE connected to the second bridge electrode BE2.

The above-described embodiments of fig. 25 to 28 are applied to the first and second thin film transistors T1 and T2 according to fig. 6, but are not limited thereto. In applying the first and second thin film transistors T1 and T2 according to the above-described various embodiments, the first power line PL1 and the clock lines CL1 and CL2 according to the embodiments of fig. 25 to 28 may be applied.

Accordingly, the present disclosure may have the following advantages.

According to one embodiment of the present disclosure, the first thin film transistor is disposed at a lower side near the substrate and the second thin film transistor is disposed at an upper side farther above the substrate, so that it is easier to dispose a plurality of thin film transistors in the buffer unit of the shift register, thereby reducing the size of the in-panel gate structure.

According to one embodiment of the present disclosure, since the second active layer of the second thin film transistor is directly connected to the second source electrode or the second drain electrode that is already disposed at the lower side, the heat treatment process when forming the second source electrode or the second drain electrode does not affect the second active layer, so that the high mobility characteristics of the second active layer can be prevented or reduced from being deteriorated, and low power driving can be performed.

According to one embodiment of the present disclosure, the lower end of the connection electrode is in contact with the upper surface of the first active layer of the first thin film transistor, and the side surface and the upper surface of the connection electrode are in contact with the lower surface of the second active layer of the second thin film transistor, so that the second thin film transistor and the first thin film transistor may be electrically connected to each other through one connection electrode, thereby reducing the number of contact holes and the number of masks for patterning, thereby optimizing the process.

It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made within the scope of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the disclosure is therefore indicated by the appended claims, and all changes or modifications that come within the meaning, range, and equivalency of the claims are therefore intended to be embraced therein.

Cross Reference to Related Applications

The present application claims the priority benefits of korean patent application No.10-2022-0101265 filed on month 8 of 2022 and korean patent application No.10-2022-0190713 filed on month 12 of 2022, which are incorporated herein by reference as if fully set forth herein.

Claims

1. A thin film transistor substrate, the thin film transistor substrate comprising:

a substrate;

a first thin film transistor disposed on the substrate and including a first active layer and a first gate electrode;

a second thin film transistor disposed on the substrate and including a second active layer and a second gate electrode disposed over the first active layer and the first gate electrode;

a first insulating layer disposed between the first gate electrode and the second active layer; and

A first connection electrode connecting the first active layer with the second active layer,

wherein the first connection electrode extends through a first contact hole provided in the first insulating layer and is provided in contact with each of the first active layer and the second active layer.

2. The thin film transistor substrate according to claim 1,

wherein a gate driver is disposed on the substrate, and the gate driver includes the first thin film transistor and the second thin film transistor.

3. The thin film transistor substrate according to claim 2,

wherein the gate driver includes a shift register including a pull-up transistor for outputting a gate-on signal and a pull-down transistor for outputting a gate-off signal,

and the first thin film transistor and the second thin film transistor are connected in parallel with each other and are constituted by the pull-up transistor, or are connected in parallel with each other and are constituted by the pull-down transistor.

4. The thin film transistor substrate according to claim 2,

wherein the gate driver includes a shift register, and the shift register includes a pull-up transistor for outputting a gate-on signal and a pull-down transistor for outputting a gate-off signal,

The first thin film transistor is constituted by one of the pull-up transistor and the pull-down transistor, and the second thin film transistor is constituted by the other of the pull-up transistor and the pull-down transistor.

5. The thin film transistor substrate according to claim 1,

wherein a lower surface of the second active layer is in contact with a portion of an upper surface and one side surface of the first connection electrode.

6. The thin film transistor substrate according to claim 1,

wherein one end of the second active layer is in contact with one side surface of the first connection electrode.

7. The thin film transistor substrate according to claim 1,

wherein the second active layer is in contact with one side, an upper surface and the other side of the first connection electrode.

8. The thin film transistor substrate according to claim 1,

wherein the second thin film transistor further includes a second drain electrode in contact with the second active layer,

one side of the second active layer is in contact with the first connection electrode, and the other side of the second active layer is in contact with the second drain electrode,

and an overlapping structure between the one side of the second active layer and the first connection electrode is different from an overlapping structure between the other side of the second active layer and the second drain electrode.

9. The thin film transistor substrate according to claim 1,

wherein each of the first active layer and the second active layer includes a channel portion and a connection portion connected to one side of the channel portion and having better conductivity than the channel portion,

and the first connection electrode is in contact with the connection portion of the first active layer and the connection portion of the second active layer.

10. The thin film transistor substrate according to claim 1,

wherein the first connection electrode includes a second source of the second thin film transistor.

11. The thin film transistor substrate according to claim 1,

wherein the first connection electrode includes the second active layer of the second thin film transistor.

12. The thin film transistor substrate according to claim 11,

wherein the second active layer includes a channel portion and a connection portion connected to one side of the channel portion and having better conductivity than the channel portion,

and the first connection electrode includes the connection portion.

13. The thin film transistor substrate of claim 11, further comprising:

And a second source electrode in contact with an upper surface of the first connection electrode.

14. The thin film transistor substrate of claim 1, further comprising:

a second insulating layer disposed on the second active layer and a bridge electrode disposed on the second insulating layer,

wherein the bridge electrode is electrically connected to a second drain electrode provided in the second thin film transistor through a second contact hole provided in the second insulating layer.

15. The thin film transistor substrate according to claim 14,

wherein the second contact hole overlaps the bridge electrode and the second drain electrode, and does not overlap the second active layer.

16. The thin film transistor substrate according to claim 14,

wherein the second contact hole overlaps the bridge electrode, the second drain electrode, and the second active layer.

17. The thin film transistor substrate of claim 1, further comprising:

a light blocking layer overlapping the first active layer, disposed under the first active layer, and electrically connected to the first active layer;

a first capacitor electrode electrically connected to the first gate electrode and located on the same layer as the first gate electrode; and

And a second capacitor electrode electrically connected to the light blocking layer and located on the same layer as the light blocking layer.

18. The thin film transistor substrate of claim 1, further comprising:

a first capacitor electrode electrically connected to the second gate electrode and on the same layer as the second gate electrode, and a second capacitor electrode on the same layer as the first connection electrode.

19. The thin film transistor substrate according to claim 1,

wherein the first gate electrode, the second gate electrode, the first active layer, and the second active layer overlap each other.

20. The thin film transistor substrate according to claim 1,

wherein the gate driver is disposed on the substrate, and the gate driver includes a first shift register and a second shift register,

the second shift register is disposed above the first shift register,

the first shift register includes a pull-up transistor for outputting a gate-on signal and a pull-down transistor for outputting a gate-off signal,

21. The thin film transistor substrate according to claim 1,

wherein the gate driver and the active array are disposed on the substrate,

the active array is disposed over and overlapping the gate driver,

the gate driver includes a shift register,

the shift register includes a pull-up transistor for outputting a gate-on signal and a pull-down transistor for outputting a gate-off signal,

22. The thin film transistor substrate of claim 1, further comprising:

a gate driver including the first and second thin film transistors, and a clock line and a power line overlapping the gate driver,

wherein the clock line and the power line are disposed under the second active layer.

23. The thin film transistor substrate of claim 22,

wherein the clock line and the power line are made of the same material on the same layer as the first gate electrode.

24. The thin film transistor substrate of claim 22,

wherein the clock line is disposed below the power line, and at least a portion of the clock line overlaps the power line.

25. The thin film transistor substrate of claim 22,

wherein the power line is disposed to overlap the second active layer.

26. The thin film transistor substrate of claim 22, further comprising:

a second drain electrode connected to the second active layer and a second bridge electrode connected to the second drain electrode,

wherein the power line is connected to the second drain electrode or the second bridge electrode through a contact hole.

27. A display device, the display device comprising:

a thin film transistor substrate having a first electrode and a second electrode,

wherein the thin film transistor substrate comprises,

a substrate;

and the first connection electrode extends through a first contact hole provided in the first insulating layer and is provided in contact with each of the first active layer and the second active layer.