CN117594480A - Semiconductor manufacturing apparatus and method for manufacturing semiconductor device - Google Patents

Semiconductor manufacturing apparatus and method for manufacturing semiconductor device Download PDF

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Publication number
CN117594480A
CN117594480A CN202310977852.5A CN202310977852A CN117594480A CN 117594480 A CN117594480 A CN 117594480A CN 202310977852 A CN202310977852 A CN 202310977852A CN 117594480 A CN117594480 A CN 117594480A
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China
Prior art keywords
dicing tape
bare chip
peeling
camera
peeled
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CN202310977852.5A
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Chinese (zh)
Inventor
名久井勇辉
齐藤明
小桥英晴
冈本直树
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Fasford Technology Co Ltd
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Fasford Technology Co Ltd
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Publication of CN117594480A publication Critical patent/CN117594480A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6838—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H01L2221/68386—Separation by peeling
    • H01L2221/6839—Separation by peeling using peeling wedge or knife or bar

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Die Bonding (AREA)
  • Dicing (AREA)

Abstract

The invention provides a semiconductor manufacturing apparatus and a method for manufacturing a semiconductor device. Provided is a technique capable of confirming the peeled state of a bare chip during the production process in a semiconductor manufacturing apparatus. The semiconductor manufacturing apparatus includes: a peeling unit provided below the dicing tape; a camera provided below the dicing tape and in the vicinity of the peeling unit; and a control device. The control device is configured to peel the dicing tape from at least a part of the die by the peeling means, capture an image by the camera through the dicing tape by capturing an image of the back surface of the die from which the dicing tape has been peeled, and confirm the peeled state of the die from the dicing tape based on the image.

Description

Semiconductor manufacturing apparatus and method for manufacturing semiconductor device
Technical Field
The present disclosure relates to a semiconductor manufacturing apparatus, which can be applied to a die mounter that performs, for example, confirmation of a die (die) peeled state.
Background
A semiconductor manufacturing apparatus such as a chip mounter is an apparatus that mounts (mounts and adheres) a component on a substrate or a component using a bonding material, for example. The bonding material is, for example, a liquid or film-like resin, a solder, or the like. Examples of the element include a semiconductor chip, a bare chip such as a MEMS (micro electro mechanical system: micro Electro Mechanical System) and a glass chip, and an electronic component. Examples of the substrate include a wiring substrate, a lead frame formed of a thin metal plate, and a glass substrate.
For example, in a die mounting process by a die mounter, there is a peeling process of peeling off bare chips separated from a semiconductor wafer (hereinafter, simply referred to as a wafer) from a dicing tape. The dicing tape is held by the wafer ring and carried into the die mounter. In the peeling step, the bare chips are lifted up from the back surface of the dicing tape by a lifting unit, and the bare chips are peeled off one by one from the dicing tape held in the wafer supply section, and the bare chips are picked up by using a suction nozzle such as a collet provided in the pick-up head or the mounting head.
Prior art literature
Patent literature
Patent document 1: japanese patent laid-open No. 2021-158166
Disclosure of Invention
For stabilization of pickup, it is desirable to manage the amount of bare chip peeling from the dicing tape. For example, when the bare chip is peeled from the dicing tape by a peeling means such as a jack-up means and the peeled state of the bare chip from the dicing tape (bare chip peeled state) is confirmed, the wafer ring holding the dicing tape having the peeled bare chip is carried out from the semiconductor manufacturing apparatus. Further, the back surface of the bare chip may be photographed to confirm the bare chip peeled state.
The present disclosure addresses the problem of providing a technique that enables verification of the peeled state of a die in a semiconductor manufacturing apparatus. Other objects and novel features will become apparent from the description and drawings of this specification.
The outline of the representative technical means in the present disclosure will be briefly described as follows.
That is, the semiconductor manufacturing apparatus includes: a peeling unit provided below the dicing tape; a camera provided below the dicing tape and in the vicinity of the peeling unit; and a control device. The control device is configured to peel the dicing tape from at least a part of the die by the peeling means, capture an image by the camera through the dicing tape by capturing an image of the back surface of the die from which the dicing tape has been peeled, and confirm the peeled state of the die from the dicing tape based on the image.
Effects of the invention
According to the present disclosure, a semiconductor manufacturing apparatus can confirm a bare chip peeled state.
Drawings
Fig. 1 is a schematic plan view showing an example of the structure of a chip mounter in the embodiment.
Fig. 2 is a diagram illustrating a schematic configuration when viewed from the arrow a direction in fig. 1.
Fig. 3 is a schematic cross-sectional view showing a main part of the wafer supply section shown in fig. 1.
Fig. 4 is a flowchart showing a method of manufacturing a semiconductor device using the die bonder shown in fig. 1.
Fig. 5 (a) is a schematic plan view of the peeling unit shown in fig. 3. Fig. 5 (b) is a main part sectional view of the peeling unit shown in fig. 5 (a) in a state of being in contact with the dicing tape. Fig. 5 (c) is a main part sectional view of the peeling unit shown in fig. 5 (a) in a state where the block is lifted up.
Fig. 6 is a view showing a main part configuration and a peeled state of the wafer supply section shown in fig. 3.
Fig. 7 (a) is a diagram showing an image of the case where the peeling unit and the bare chip in the second state are insufficiently peeled. Fig. 7 (b) is a diagram showing an image of the case where the peeling unit and the bare chip in the second state are sufficiently peeled.
Fig. 8 (a) is a diagram showing an image of a case where bare chip peeling is uneven. Fig. 8 (b) is a diagram showing an image in the case where the non-peeled area is displaced in the x-direction. Fig. 8 (c) is a diagram showing a case where the non-peeled area is displaced in the y direction. Fig. 8 (d) is a diagram showing an image in the case where the non-peeled area is displaced in the θ direction.
Fig. 9 is a diagram showing a main part configuration of the wafer supply section in the first modification.
Fig. 10 (a) is a plan view showing a main part configuration of the wafer supply section in the second modification. Fig. 10 (b) is a cross-sectional view showing a main part configuration of the wafer supply section in the second modification.
Fig. 11 is a diagram showing a main part configuration of a wafer supply section in the third modification.
Description of the reference numerals
1: chip mounter (semiconductor manufacturing device)
12: wafer holding table
13: stripping unit
15: upward-looking camera (cam)
80: control unit (control device)
D: bare chip
Dp: stripping bare chip
W: wafer with a plurality of wafers
WR: wafer ring
Detailed Description
Hereinafter, embodiments and modifications will be described with reference to the drawings. In the following description, the same reference numerals are given to the same components, and the repetitive description thereof may be omitted. For the sake of more clear explanation, the drawings may schematically show the width, thickness, shape, and the like of each portion as compared with the actual form. In addition, the dimensional relationship of the elements, the ratio of the elements, and the like do not necessarily coincide with each other among the plurality of drawings.
The configuration of a die mounter, which is an embodiment of a semiconductor manufacturing apparatus, will be described with reference to fig. 1 to 3. Fig. 1 is a schematic plan view showing an example of the structure of a chip mounter in the embodiment. Fig. 2 is a diagram illustrating a schematic configuration when viewed from the arrow a direction in fig. 1. Fig. 3 is a schematic cross-sectional view showing a main part of the wafer supply section shown in fig. 1.
The chip mounter 1 is generally divided into a wafer supply unit 10, a pickup unit 20, an intermediate stage unit 30, a mounting unit 40, a conveying unit 50, a substrate supply unit 60, a substrate take-out unit 70, and a control unit (control device) 80. The Y direction is the front-back direction of the chip mounter 1, the X direction is the left-right direction, and the Z direction is the up-down direction. The wafer supply unit 10 is disposed on the front side of the chip mounter 1, and the mounting unit 40 is disposed on the rear side.
The wafer supply section 10 has a wafer cassette lifter 11, a wafer holding stage 12, a peeling unit 13, a wafer recognition camera 14, and a bottom view camera (under vision camera) 15.
The wafer cassette lifter 11 moves up and down a wafer cassette (not shown) holding a plurality of wafer rings WR to a wafer transfer height. The wafer correction groove (not shown) aligns the wafer ring WR supplied from the wafer cassette lifter 11. The wafer extractor (not shown) takes out the wafer ring WR from the wafer cassette and supplies it to the wafer holding stage 12, or takes out the wafer ring WR from the wafer holding stage 12 and stores it in the wafer cassette.
The wafer holding stage 12 has: an extension ring 121 that holds the wafer ring WR; and a support ring 122 held by the wafer ring WR and horizontally positioning the dicing tape DT. The peeling unit 13 and the upward-looking camera 15 are disposed inside the support ring 122.
A wafer W is bonded (stuck) to the dicing tape DT, and the wafer W is divided into a plurality of bare chips D. The dicing tape DT is transparent to visible light. A film-like adhesive DF called a film-on-film (DAF) is adhered between the wafer W and the dicing tape DT. The adhesive DF is cured by heating.
The wafer holding stage 12 moves in the XY directions by a driving unit, not shown, and moves the bare chip D to be picked up to the position of the peeling unit 13. The wafer holder 12 rotates or XY-moves the wafer ring WR in the XY plane by a driving unit, not shown. The peeling means 13 is moved in the vertical direction by a driving unit not shown. The peeling unit 13 peels the bare chip D from the dicing tape DT.
The wafer recognition camera 14 grasps the pickup position of the bare chip D picked up from the wafer W and performs surface inspection of the bare chip D. The bottom view camera 15 confirms the bare chip peeled state.
The pickup section 20 has a pickup head 21 and a Y drive section 23. The pick-up head 21 is provided with a collet 22 for sucking and holding the peeled bare chip D at the tip. The pickup head 21 picks up the bare chip D from the wafer supply section 10 and places it on the intermediate stage 31. The Y drive section 23 moves the pickup head 21 in the Y axis direction. The pickup unit 20 includes driving units (not shown) for moving the pickup head 21 in the X direction while lifting and lowering the pickup head.
The intermediate stage section 30 has an intermediate stage 31 on which the bare chip D is mounted, and a stage recognition camera 34 for recognizing the bare chip D on the intermediate stage 31. The intermediate stage 31 has suction holes for sucking the mounted bare chips D. The mounted bare chip D is temporarily held on the intermediate stage 31. The intermediate stage 31 is a stage on which the bare chip D is placed, and is also a pickup stage that picks up the bare chip D.
The mounting section 40 has a mounting head 41, a Y driving section 43, a substrate recognition camera 44, and a mounting table 46. The mounting head 41 is provided with a collet 42 for sucking and holding the bare chip D at the tip. The Y driving section 43 moves the mounting head 41 in the Y axis direction. The board recognition camera 44 captures a position recognition mark (not shown) of the board S, and recognizes the mounting position. Here, a plurality of product regions (hereinafter referred to as package regions p.) that eventually become one package are formed on the substrate S. The position identification flag is set for each package region P. When the bare chip D is placed on the substrate S, the mounting table 46 is raised to support the substrate S from below. The mounting table 46 has a suction port (not shown) for vacuum-sucking the substrate S, and can fix the substrate S. The mounting table 46 has a heating portion (not shown) for heating the substrate S. The mounting unit 40 includes driving units (not shown) for moving the mounting head 41 in the X direction and lifting and rotating the mounting head.
According to such a configuration, the mounting head 41 corrects the pickup position and posture based on the pickup data of the stage recognition camera 34, and picks up the bare chip D from the intermediate stage 31. The mounting head 41 mounts the bare chip D on the package region P of the substrate S based on the imaging data of the substrate recognition camera 44, or mounts the bare chip D so as to be stacked on the bare chip mounted on the package region P of the substrate S.
The conveying section 50 includes a conveying claw 51 for gripping and conveying the substrate S and a conveying path 52 for moving the substrate S. The substrate S is moved in the X direction by driving a nut, not shown, of the conveyance claw 51 provided in the conveyance path 52 by a ball screw, not shown, provided along the conveyance path 52. According to this configuration, the substrate S is moved from the substrate supply unit 60 to the mounting position along the conveyance path 52, and after mounting, is moved to the substrate carry-out unit 70, and the substrate S is delivered to the substrate carry-out unit 70.
The substrate supply unit 60 takes out the substrate S stored in the transfer jig and carried in from the transfer jig, and supplies the substrate S to the transfer unit 50. The substrate carrying-out section 70 stores the substrate S carried by the carrying section 50 in the carrying jig.
The control unit 80 includes: a storage device for storing a program (software) and data for monitoring and controlling the operation of each part of the chip mounter 1; a Central Processing Unit (CPU) that executes a program stored in the storage device; and an input-output device (not shown). The input/output device includes an image acquisition device (not shown), a motor control device (not shown), an I/O signal control device (not shown), and the like. The image acquisition device acquires image data from the wafer recognition camera 14, the upward-looking camera 15, the stage recognition camera 34, and the substrate recognition camera 44. The motor control device controls the driving section of the wafer supply section 10, the driving section of the pickup section 20, the driving section of the mounting section 40, and the like. The I/O signal control device acquires various sensor signals, and a signal section for controlling a switch or the like of the lighting device or the like.
A part of a manufacturing process of a semiconductor device (a manufacturing method of a semiconductor device) using the chip mounter 1 will be described with reference to fig. 4. Fig. 4 is a flowchart showing a method of manufacturing a semiconductor device using the die bonder shown in fig. 1. In the following description, the operations of the respective parts constituting the chip mounter 1 are controlled by the control unit 80.
(wafer carrying-in step: step S1)
The wafer ring WR is supplied to the wafer cassette of the wafer cassette lifter 11. The supplied wafer ring WR is supplied to the wafer holding stage 12. The wafer W is inspected for each die in advance by an inspection device such as a probe, and wafer map data indicating the quality and failure of the die is generated. The wafer map data is stored in the memory device of the control unit 80.
(substrate carrying-in step: step S2)
The substrate supply unit 60 is supplied with a carrier tool storing the substrate S. The substrate S is taken out from the conveyance jig by the substrate supply unit 60, and the substrate S is fixed to the conveyance claw 51.
(pickup step: step S3)
After the process S1, the wafer holding stage 12 is moved so that the desired bare chips D can be picked up from the dicing tape DT. The bare chip D is photographed by the wafer recognition camera 14, and positioning and surface inspection of the bare chip D are performed based on image data obtained by photographing. The image data is subjected to image processing, whereby the offset amount (X, Y, θ direction) of the die D on the wafer holding stage 12 with respect to the die position reference point of the die mounter is calculated and positioned. The die position reference point is set and held in advance by setting a predetermined position of the wafer holding table 12 as an initial setting of the apparatus. The surface inspection of the bare chip D is performed by performing image processing on the image data.
The positioned bare chip D is peeled from the dicing tape DT by the peeling unit 13 and the pickup head 21. The bare chip D peeled from the dicing tape DT is sucked and held by the collet 22 provided to the pickup head 21, and is carried and placed on the intermediate stage 31.
The bare chip D on the intermediate stage 31 is photographed by the stage recognition camera 34, and positioning and surface inspection of the bare chip D are performed based on the image data obtained by photographing. The image data is subjected to image processing, whereby the offset amount (X, Y, θ direction) of the die D on the intermediate stage 31 with respect to the die position reference point of the die mounter is calculated and positioned. The die position reference point is set and held in advance with the predetermined position of the intermediate stage 31 as the initial setting of the device. The surface inspection of the bare chip D is performed by performing image processing on the image data.
The pickup head 21 having carried the bare chip D to the intermediate stage 31 returns to the bare chip supply section 10. The next die D is peeled from the dicing tape DT according to the above-described steps, and thereafter the die D are peeled from the dicing tape DT one by one according to the same steps.
(mounting Process: process S4)
The substrate S is transported to the mounting table 46 by the transport unit 50. The substrate S placed on the mounting table 46 is photographed by the substrate recognition camera 44, and image data is acquired by the photographing. By performing image processing on the image data, the offset amount (X, Y, θ direction) of the substrate S with respect to the substrate position reference point of the chip mounter 1 is calculated. The board position reference point is set and held in advance with a predetermined position of the mounting portion 40 as an initial setting of the device.
The suction position of the mounting head 41 is corrected based on the offset amount of the die D on the intermediate stage 31 calculated in step S3, and the die D is sucked by the collet 42. The die D is mounted on a predetermined portion of the substrate S supported on the mounting table 46 by the mounting head 41 that has suctioned the die D from the intermediate stage 31. Here, the predetermined portion of the substrate S is the package region P of the substrate S, or a region in which the component is mounted and the component is attached to the component, or a mounting region of the component to be stacked and mounted. The bare chip D mounted on the substrate S is photographed by the substrate recognition camera 44, and whether the bare chip D is mounted at a desired position or not is checked based on the image data obtained by photographing.
The mounting head 41, which has mounted the bare chip D to the substrate S, returns to the intermediate stage 31. The next bare chip D is picked up from the intermediate stage 31 and mounted on the substrate S in accordance with the above-described steps. The above steps are repeated to attach the bare chip D to all the package regions P of the substrate S.
(substrate carrying-out Process: process S5)
The substrate S on which the bare chip D is mounted is carried to the substrate carrying-out section 70. The substrate S is taken out from the transfer claw 51 by the substrate take-out section 70 and stored in the transfer jig. The carrier jig storing the substrate S is carried out from the die mounter 1.
As described above, the bare chip D is mounted on the substrate S and carried out from the die mounter 1. Then, for example, the carrier jig storing the substrate S on which the bare chip D is mounted is carried by the wire bonding step, and the electrodes of the bare chip D are electrically connected to the electrodes of the substrate S via Au wires or the like. Then, the substrate S is carried to a molding process, and the bare chip D and the Au wire are sealed with a molding resin (not shown), whereby the semiconductor package is completed.
In the case of lamination mounting, after the wire bonding process, a carrier jig on which a substrate S having a die D mounted thereon is mounted is carried into a die mounter, and the die D is laminated on the die D mounted on the substrate S. After being carried out from the die bonder, the wire is electrically connected to the electrode of the substrate S via an Au wire in a wire bonding process. The die D above the second layer is peeled off from the dicing tape DT by the above method, and then transported to the mounting section to be stacked on the die D. After the above steps are repeated a predetermined number of times, the substrate S is transferred to a molding step, and the plurality of bare chips D and Au wires are sealed with a molding resin (not shown), whereby the stack package is completed.
The structure and operation of the peeling unit 13 will be described with reference to fig. 5 (a) to 5 (c). Fig. 5 (a) is a schematic plan view of the peeling unit shown in fig. 3. Fig. 5 (b) is a main part sectional view of the peeling unit shown in fig. 5 (a) in a state of being in contact with the dicing tape. Fig. 5 (c) is a main part sectional view of the peeling unit shown in fig. 5 (a) in a state where the block is lifted up.
As shown in fig. 5 (a), the peeling unit 13 has: a block portion 131 having a plurality of blocks 131a to 131d; and a dome head 132 having a plurality of suction holes (not shown) for sucking the dicing tape DT. The four blocks 131a to 131d can be independently moved up and down by the control section 80. The planar shapes of the concentric tetragonal blocks 131a to 131D are configured to match the shape of the bare chip D.
The pickup operation starts from a state in which the bare chip D as the target on the dicing tape DT is positioned at the peeling unit 13 and the collet 22 of the pickup head 21 is positioned at the bare chip D. As shown in fig. 5 (b), when positioning is completed, vacuum is applied through suction holes and gaps, not shown, of the peeling unit 13, and the dicing tape DT is sucked onto the upper surface of the peeling unit 13. At this time, the upper surfaces of the blocks 131a to 131d are positioned at the same height (initial position) as the upper surface of the dome head 132. In this state, vacuum is supplied from a vacuum supply source, and the collet 22 descends toward the device surface (upper surface) of the bare chip D while drawing vacuum, and reaches the upper surface of the bare chip D.
Thereafter, the blocks 131a to 131d are simultaneously lifted up to bring the peeling unit 13 into the first state (PU 1). The first state (PU 1) is a state in which the blocks 131a to 131d are in contact with the dicing tape DT. Thereafter, the blocks 131b to 131d are simultaneously lifted up, and the peeling unit 13 is brought into the second state (PU 2). The second state (PU 2) is a state in which the blocks 131b to 131d are in contact with the dicing tape DT. Thereafter, the blocks 131c and 131d are simultaneously lifted up, and the peeling unit 13 is brought into the third state (PU 3). The third state (PU 3) is a state in which the blocks 131c and 131d are in contact with the dicing tape DT. Thereafter, as shown in fig. 5 (c), the block 131d is further lifted up to form the block 131 into a pyramid shape, and the peeling means 13 is placed in the fourth state (PU 4). The fourth state (PU 4) is a state in which the block 131d is in contact with the dicing tape DT. In this disclosure, this action is referred to as an MS (Multi Step) action.
The stripping means 13 can perform the following operations in addition to the MS operations described above. The blocks 131a to 131d are simultaneously lifted up to bring the peeling unit 13 into the first state (PU 1). The first state (PU 1) is a state in which the blocks 131a to 131d are in contact with the dicing tape DT. Thereafter, the block 131a is lowered to bring the peeling unit 13 into the second state (PU 2). The second state (PU 2) is a state in which the blocks 131b to 131d are in contact with the dicing tape DT. Thereafter, the block 131b is lowered to bring the peeling unit 13 into the third state (PU 3). The third state (PU 3) is a state in which the blocks 131c and 131d are in contact with the dicing tape DT. Thereafter, the block 131c is lowered to form the block 131 into a pyramid shape, and the peeling unit 13 is placed in the fourth state (PU 4). The fourth state (PU 4) is a state in which the block 131d is in contact with the dicing tape DT. In this disclosure, this action is referred to as an RMS (reverse multi-step: reverse Multi Step) action.
During the MS operation or RMS operation, the bare chip D is held in a state of being held by the collet 22 and the block 131 in its entirety or a part. The dicing tape DT is peeled from the die D by the tension of the dicing tape DT by providing a layer difference between the plurality of blocks such as the block portion 131 having a pyramid shape. In the state shown in fig. 5 (c), the dicing tape DT is bonded to the die D only at the portion where the block 131D is in contact with the dicing tape DT.
Thereafter, the collet 22 is pulled up Fang Shang and the block 131D is pulled down, whereby the bare chip D is completely peeled from the dicing tape DT and picked up.
The first state (PU 1), the second state (PU 2), the third state (PU 3), and the fourth state (PU 4) among the MS operation and the RMS operation are performed by the plurality of stepwise operations of the stripping unit 13. Based on the time chart process (time chart recipe) (pickup process), the control section 80 controls motors and the like that drive the respective blocks 131a to 131 d. In the time chart process, the operations of the blocks 131a to 131d are set by using the step-by-step time, the speed of raising or lowering the blocks, the height (position) of the blocks, and the like for each block and each step. Thereby, the peeling means 13 performs a stepwise operation.
The verification of the peeled state of the bare chip in the wafer supply unit will be described with reference to fig. 2, 5 (b), 5 (c) and 6. Fig. 6 is a diagram showing an example of an image of the main part configuration of the wafer supply section shown in fig. 3 and the peeled state of the bare chip. The X-axis and the Y-axis shown by the image IM in fig. 6 correspond to the X-axis and the Y-axis of the chip mounter 1.
As shown in fig. 2, the upward-looking camera 15 is located beside the peeling unit 13, and is fixedly disposed within the movable range of the wafer holding stage 12 without interfering with the peeling unit 13. The upward-looking camera 15 is disposed upward so as to capture a photograph thereabove, and the optical axis thereof is along the Z direction. The photographing is preferably performed using oblique illumination in which illumination light is irradiated from a direction oblique to the optical axis of the overhead camera 15.
In the present embodiment, the bare chip detachment state is checked when the conditions of the apparatus are set before the continuous operation of the chip mounter 1 (before the start of production). Alternatively, during the continuous operation of the die mounter 1 (during production), for example, when a new wafer ring WR is loaded on the wafer holding stage 12, the bare chip peeled state is confirmed. In the continuous operation, the bare chip separation state may be checked every time the wafer ring WR is loaded between the steps S1 and S3, or may be checked at a ratio of one time for a plurality of times of loading of the wafer ring WR. The number of times may be a predetermined number of times or may be any number of times. In addition, during the continuous operation, it is preferable to confirm the bare chip peeled state by using the bare chip which is determined to be defective based on the wafer map data. In this case, it is preferable to use a die that is not located at the end of the wafer for the die that confirms the die-peeled state. The sequence will be described below.
First, the control unit 80 sets the peeling means 13 to the fourth state (PU 4) as shown in fig. 5 (c) by the above-described pickup operation, for example, and lifts up the block 131 to locally peel the dicing tape DT from the die D.
Next, the control unit 80 returns the peeling means 13 from the fourth state (PU 4) shown in fig. 5 (c) to the initial state shown in fig. 5 (b).
Next, as shown in fig. 6, the control section 80 makes the peeling unit 13 downward Fang Tuibi. Then, the control unit 80 moves the wafer holding stage 12, and places the bare chip (peeled bare chip Dp) that has been partially peeled off by the dicing tape DT by lifting up, above the bottom camera 15. In this case, the collet 22 of the pickup head 21 also withdraws upward.
Next, the control unit 80 captures the peeled die Dp through the dicing tape DT by using the overhead camera 15 to acquire an image IM. The image IM is an image of a peeling trace including a peeling region PLD from which the peeled bare chip Dp has been peeled from the dicing tape DT and an unpeeled region UPL.
According to the above procedure, the bare chip peeled state can be confirmed without performing wafer collection and payment. The wafer pickup means a wafer ring WR for holding a dicing tape DT having a peeled bare chip Dp or the like with respect to the chip mounter 1.
Next, the control unit 80 performs image processing on the image IM captured by the upward-looking camera 15, separates the peeled area PLD from the non-peeled area UPL, and confirms the peeled state of the bare chip. For example, the control unit 80 confirms the bare chip peeled state from the positional relationship between the four outer side ends OP of the outermost block in contact with the dicing tape DT and the non-peeled area UPL in the block portion 131.
By setting the peeling unit 13 to the second state (PU 2), the bare chip peeled state can be confirmed from the positional relationship between the four outer side ends OP of the block 131b and the non-peeled area UPL. By setting the peeling unit 13 to the third state (PU 3), the bare chip peeled state can be confirmed from the positional relationship between the four outer side ends of the block 131c and the non-peeled area UPL. By setting the peeling unit 13 to the fourth state (PU 4), the bare chip peeled state can be confirmed from the positional relationship between the four outer side ends of the block 131d and the non-peeled area UPL.
The actual image IM is not an image having a high contrast between the peeled area PLD and the unpeeled area UPL as shown in fig. 6, but a light image having a low contrast. Therefore, in confirming the bare chip peeled state, the control section 80 performs smoothing processing on the image IM, performs edge detection processing in the band region on the image from which noise has been removed by the smoothing processing, separates the peeled region PLD and the unpeeled region UPL, and detects the peeling mark.
As the smoothing processing, smoothing filtering is performed one or more times. For example, the filter may be used once in a case of 5×5 or 7×7, and the filter may be used more than once in a case of 3×3.
Edge detection in a band region (edge detection in a band shape) is edge detection performed not for one pixel but for a plurality of pixels. Since edge detection is usually derived from a change in shade on a straight line, the inspection width is one pixel, but if the edge is sufficiently long for noise removal, the inspection width may be averaged by using a plurality of pixels. Therefore, it is effective to detect edges of, for example, about 10 pixels on each side, and set a rectangular region by extending each detected edge. The shape of the non-peeled area UPL is a rectangular shape similar to the shape of the block in plan view.
After confirming the peeled state of the bare chip, the control unit 80 can determine whether the pickup process is suitable or not or correct or warn the pickup process itself by using the image IM. This will be described with reference to fig. 7 (a) and 7 (b). Fig. 7 (a) is a diagram showing an image of the case where the peeling unit and the bare chip in the second state are insufficiently peeled. Fig. 7 (b) is a diagram showing an image of the case where the peeling unit and the bare chip in the second state are sufficiently peeled. In fig. 7 (a) and 7 (b), the block 131a is located between the upper surface of the dome 132 and the upper surfaces of the blocks 131b to 131 d.
The control unit 80 determines complete peeling (sufficient bare chip peeling) when the boundary between the peeled area PLD and the unpeeled area UPL is equal to or smaller than the outer periphery of the block formed by the four outer ends OP of the block that are in contact with the dicing tape DT, as shown in fig. 7 (b).
When the boundary between the peeled area PLD and the unpeeled area UPL is larger than the outer periphery of the block as shown in fig. 7 (a), the control unit 80 determines that the bare chip peeling is insufficient. In the case where the bare chip peeling is insufficient, as described below, correction of the pickup process can be performed.
In the MS operation, the block height immediately before shooting and the time of the pickup timer are increased.
In the RMS operation, the block height is increased by raising the entire block in the step of the first state (PU 1). Alternatively, the block height at which the block immediately before shooting is lowered (in fig. 7 (a), the block height of the block 131 a). Alternatively, the time of the pick-up timer is increased. Or these may be combined.
In the RMS operation, the priority of high speed and low stress (stress) is determined, and the correction of the pick-up process is selected based on this. In the case of giving priority to high-speed performance, the jack-up height is increased, or the time of the pickup timer is reduced. Or both. When low stress (stress) is prioritized, the jack-up height is reduced or the time of the pick-up timer is increased. Or both.
When the peeled area PLD (unpeeled area UPL) is not uniform in the x, y, and θ directions, the control unit 80 can perform positional correction of the mechanism according to the bare chip peeled state. This will be described with reference to fig. 8 (a) to 8 (d). Fig. 8 (a) is a diagram showing an image of a case where bare chip peeling is uneven. Fig. 8 (b) is a diagram showing an image in the case where the non-peeled area is displaced in the x-direction. Fig. 8 (c) is a diagram showing a case where the non-peeled area is displaced in the y direction. Fig. 8 (d) is a diagram showing an image in the case where the non-peeled area is displaced in the θ direction.
As shown in fig. 8 a, when the non-peeled area UPL is located at a non-uniform position with respect to the block periphery OP (when the bare chip peeling is non-uniform), the control unit 80 sets the height ratio of the block where the area surrounded by the ellipse is in contact with the dicing tape DT to be lower. That is, it is determined that the block 131 is obliquely raised. This makes it possible to diagnose the degree of normality of the block flatness. The control unit 80 may warn when it is determined that the block 131 is inclined.
When the boundary between the peeled area PLD and the unpeeled area UPL is equal to the size of the outer periphery of the block, the control unit 80 can check the amount of positional displacement of the block 131 with respect to the bare chip D. When the control unit 80 confirms that the non-peeled area UPL is deviated in the (+) direction of the Y axis from the original block outer periphery OPa as shown in fig. 8 (b), it determines that the block 131 is deviated in the (+) direction of the Y axis. When the control unit 80 confirms that the non-peeled area UPL is deviated in the X-axis (-) direction from the original block outer periphery OPa as shown in fig. 8 (c), it determines that the block 131 is deviated in the X-axis (+) direction. When it is confirmed that the non-peeled area UPL is deviated in the (+) direction θ with respect to the original block outer periphery OPa, as shown in fig. 8 (d), the control unit 80 determines that the block 131 is deviated in the (-) direction θ. The control unit 80 calculates the positional deviation amounts thereof, and corrects the positional relationship between the wafer holding stage 12 and the peeling unit 13 based on the calculated positional deviation amounts. For example, the position and posture of the wafer holding stage 12 may be corrected, or the position and posture of the peeling unit 13 may be corrected.
According to the embodiment, in the semiconductor manufacturing apparatus such as the die mounter, the bare chip peeled state can be checked. Thus, the quality of the pick-up process, the operation failure of the peeling means, and the like can be judged based on the peeled state of the bare chip.
Further, according to the embodiment, it is possible to confirm the bare chip peeling that has been performed in the middle of each stage of the multi-stage lifting by the plurality of blocks.
In addition, according to the embodiment, the peeling condition of the pick-up process can be optimized, and cracking and chipping of the bare chip at the time of pick-up can be prevented. This can cope with pick-up of a thinner bare chip. For example, for the purpose of promoting high-density mounting of semiconductor devices, a package on which a plurality of bare chips are three-dimensionally mounted on a wiring substrate is put into practical use. In assembling such a stack package, a so-called thin bare chip having a thickness reduced to the order of several tens μm is used. The pick-up of such thin bare chips can be dealt with.
< modification >
Representative modifications of several embodiments are exemplified below. In the following description of the modified example, the same reference numerals as those of the above-described embodiment can be used for the portions having the same configurations and functions as those described in the above-described embodiment. The description of the above embodiment can be appropriately given to the extent that the description of the related portions is not technically contradictory. In addition, some of the above embodiments and all or some of the plurality of modifications can be applied in a combined manner within a range that is not technically contradictory.
(first modification)
Fig. 9 is a diagram showing a main part configuration of the wafer supply section in the first modification.
In the embodiment, an example in which the bottom camera 15 is fixedly disposed is described. In contrast, the upward camera 15 in the first modification is provided so as to be movable between a position above the peeling unit 13 and a position not interfering with the peeling unit 13. The control unit 80 withdraws the peeling unit 13 downward without interfering with the bottom camera 15, and moves the bottom camera 15 itself to a position where the bare chip Dp is peeled off. As in the embodiment, the imaging by the upward-looking camera 15 is preferably performed using oblique illumination in which illumination light is emitted from a direction oblique to the optical axis of the upward-looking camera 15. The control unit 80 does not need to move the wafer holding stage 12 to move the peeled bare chip Dp, and therefore, does not need to retract the collet 22 of the pickup head 21 upward. This makes it possible to directly perform shooting while holding the peeled bare chip Dp adsorbed by the collet 22, and thus to prevent reattachment of the peeled bare chip Dp to the dicing tape DT during shooting.
(second modification)
Fig. 10 (a) is a plan view showing a main part configuration of the wafer supply section in the second modification. Fig. 10 (b) is a cross-sectional view showing a main part configuration of the wafer supply section in the second modification. In fig. 10 (a), the dicing tape DT and the peeled bare chip Dp are removed.
The dome 132 of the peeling unit 13 in the second modification is formed of a transparent material. The optical axis of the upward-looking camera 15 is inclined with respect to the Z direction, and the upward-looking camera 15 is provided at a position where the back surface of the peeled bare chip Dp is imaged from obliquely below. The upward-looking camera 15 is disposed opposite to one side of the peeled bare chip Dp. The bottom view cameras 15 may be arranged in two opposite sides of the peeled bare chip Dp. The bottom view camera 15 may be disposed to face four sides of the peeled bare chip Dp.
According to this configuration, even if the peeling means 13 is not retracted downward after the block 131 is lifted up, and the peeled bare chip Dp is not released from the collet 22, the bare chip peeled state of the peeled bare chip Dp can be confirmed. Thus, the bare chip peeled state can be confirmed even in the pick-up operation in the production process. In addition, as in the first modification, since the bare chip Dp can be directly photographed while being sucked by the collet 22, reattachment of the bare chip Dp to the dicing tape DT during photographing can be prevented.
(third modification)
Fig. 11 is a diagram showing a main part configuration of a wafer supply section in the third modification.
The dome 132 of the peeling unit 13 in the third modification is formed of a transparent material. The upward camera 15 is arranged in the same manner as in the embodiment. An optical reflection mechanism 16a such as a prism or a mirror is provided above the bottom camera 15 and below the dicing tape DT. The optical reflection mechanism 16a has a reflection surface at substantially 45 degrees with respect to the optical axis of the upward-looking camera 15. The optical reflection mechanism 16b is provided in the dome 132. The optical reflection mechanism 16b has a reflection surface at an angle smaller than 45 degrees with respect to the upper surface of the dome 132. The upward-looking camera 15 is disposed opposite to one side of the peeled bare chip Dp.
The bottom view cameras 15 may be arranged in two opposite sides of the peeled bare chip Dp. Two sets of optical reflection mechanisms 16a, 16b are also provided corresponding to the two heads 15. The bottom view camera 15 may be disposed to face four sides of the peeled bare chip Dp. Four sets of optical reflection mechanisms 16a, 16b are provided corresponding to the four heads 15.
According to this configuration, even if the peeling means 13 is not retracted downward after the block 131 is lifted up, and the peeled bare chip Dp is not released from the collet 22, the bare chip peeled state of the peeled bare chip Dp can be confirmed. Thus, the bare chip peeled state can be confirmed even in the pick-up operation in the production process. In addition, as in the first modification, since the imaging can be performed directly while the peeled bare chip Dp is held by the collet 22, reattachment of the peeled bare chip Dp to the dicing tape DT during the imaging can be prevented.
The invention completed by the present inventors has been specifically described above based on the embodiments and the modifications, but the present disclosure is not limited to the embodiments and the modifications, and various modifications are needless to say possible.
For example, in the embodiment, the example in which the number of blocks is four has been described, but the number of blocks may be three or less or five or more depending on the die size.
In the embodiment, the case where the plurality of blocks of the peeling means are concentric tetragonal blocks has been described, but the plurality of blocks may be concentric circular blocks or concentric elliptical blocks, or may be formed by arranging tetragonal blocks in parallel.
In the embodiment, the case where the peeling means lifts up the plurality of blocks to peel the blocks has been described, but the blocks may be slid to peel the blocks.
In the embodiment, the example of using the adhesive sheet film has been described, but a preformed portion for applying an adhesive to a substrate may be provided instead of using the adhesive sheet film.
In the embodiment, a die mounter has been described in which a die is picked up from a wafer supply unit by a pick-up head and mounted on an intermediate stage, and the die mounted on the intermediate stage is mounted on a substrate by a mounting head. However, the present invention is not limited to this, and can be applied to a die attach apparatus that picks up a die from a die supply unit.
For example, the present invention can be applied to a die mounter that mounts a bare chip of a wafer supply unit on a substrate by a mounting head without an intermediate stage and a pickup head.
Further, the present invention can be applied to a flip chip mounter that picks up a die from a wafer supply unit without an intermediate stage, rotates a die pick-up head upward, transfers the die to a mounting head, and mounts the die on a substrate using the mounting head.
In the embodiment, the description has been given taking the chip mounter as an example, but the invention is also applicable to a semiconductor manufacturing apparatus in which a picked-up bare chip is mounted on a tray.

Claims (16)

1. A semiconductor manufacturing apparatus is characterized by comprising:
a wafer holding stage that holds a wafer ring to which a dicing tape of bare chips separated from a wafer is attached;
a peeling unit provided below the dicing tape;
a camera provided below the dicing tape held on the wafer holding table and in the vicinity of the peeling unit; and
and a control device configured to peel the dicing tape from at least a part of the die by the peeling means during production, capture an image by the camera through the dicing tape by capturing a back surface of the die from which the dicing tape is peeled, and confirm a peeled state of the die from the dicing tape based on the image.
2. The semiconductor manufacturing apparatus according to claim 1, wherein,
the control device is configured to detect a peeling trace by smoothing the image and edge detection in a band region.
3. The semiconductor manufacturing apparatus according to claim 1, wherein,
the control device is configured to confirm a peeling state in which the defective bare chip is peeled from the dicing tape based on the wafer map data.
4. The semiconductor manufacturing apparatus according to claim 2, wherein,
the control device is configured to correct a positional relationship between the wafer holding stage and the peeling unit based on the peeling trace.
5. The semiconductor manufacturing apparatus according to claim 2, wherein,
the control device is configured to issue a warning based on the peeling trace, or to set or correct the operation condition of the peeling means.
6. The semiconductor manufacturing apparatus according to claim 2, wherein,
the camera also comprises an illumination device which irradiates illumination light with a prescribed angle relative to the optical axis of the camera.
7. The semiconductor manufacturing apparatus according to claim 4 or 5, wherein,
The camera is arranged beside the stripping unit and fixed.
8. The semiconductor manufacturing apparatus according to claim 7, wherein,
the control device is configured to move the bare chip to a position above the camera, and to take an image of the bare chip by the camera.
9. The semiconductor manufacturing apparatus according to claim 8, wherein,
the peeling unit has a plurality of blocks that jack up the bare chip via the dicing tape,
the control device is configured to control the operation of the vehicle,
when the peeling means is operated to peel the dicing tape from the bare chip by separating the plurality of blocks from the dicing tape in order from the outside after all of the plurality of blocks are lifted up,
after separating at least one of the plurality of blocks from the dicing tape, lowering the peeling unit,
the bare chip is moved over the camera using the wafer holding stage.
10. The semiconductor manufacturing apparatus according to claim 4 or 5, wherein,
the control device is configured to lower the peeling unit, move the camera to a position below the bare chip, and photograph the bare chip with the camera.
11. The semiconductor manufacturing apparatus according to claim 10, wherein,
the peeling unit has a plurality of blocks that jack up the bare chip via the dicing tape,
the control device is configured to control the operation of the vehicle,
when the peeling means is operated to peel the dicing tape from the bare chip by separating the plurality of blocks from the dicing tape in order from the outside after all of the plurality of blocks are lifted up,
after separating at least one of the plurality of blocks from the dicing tape, lowering the peeling unit,
the camera is moved to below the bare chip.
12. The semiconductor manufacturing apparatus according to claim 1, wherein,
the peeling unit is provided with a dome head formed of a transparent material for abutting against the dicing tape,
the camera is arranged at a position where the optical axis is inclined relative to the vertical direction to shoot the back surface of the bare chip,
the control device is configured to take an image of the back surface of the bare chip from which the dicing tape is peeled by the camera through the dome head and the dicing tape while the peeling unit is held in contact with the dicing tape.
13. The semiconductor manufacturing apparatus according to claim 1, wherein,
a first optical reflection mechanism is also arranged above the camera,
the peeling means is provided with: a round plug formed of a transparent material for abutting against the dicing tape; and a second optical reflection mechanism provided in the dome head,
the control device is configured to take an image of the back surface of the bare chip, from which the dicing tape is peeled, through the dicing tape by using the camera, the first optical reflection mechanism, and the second optical reflection mechanism while the peeling unit is held in contact with the dicing tape.
14. A semiconductor manufacturing apparatus is characterized by comprising:
a wafer holding stage that holds a wafer ring to which a dicing tape of bare chips separated from a wafer is attached;
a peeling unit provided below the dicing tape;
a camera provided below the dicing tape held on the wafer holding table and in the vicinity of the peeling unit;
a head having a collet chuck that adsorbs the bare chip; and
and a control device configured to peel the dicing tape from a part of the die by the peeling means, and to capture an image by imaging a back surface of the die from which the dicing tape is peeled through the dicing tape by the camera in a state in which the die is sucked by the collet, and to confirm a peeled state of the die from the dicing tape based on the image.
15. A method for manufacturing a semiconductor device, comprising:
a carry-in step of carrying in a wafer ring to a semiconductor manufacturing apparatus including a wafer holding stage that holds the wafer ring, a peeling unit that is provided below the dicing tape, and a camera that is provided below the dicing tape, the dicing tape to which bare chips separated from a wafer are attached;
a peeling confirmation step of peeling the dicing tape from at least a part of the die by the peeling means, capturing an image of the back surface of the die peeled by the dicing tape by the camera through the dicing tape, and confirming a peeled state of the die peeled from the dicing tape based on the image;
a pick-up step of picking up the bare chip held by the wafer ring; and
and a mounting step of mounting the picked-up bare chip on a substrate, or mounting the picked-up bare chip on a bare chip mounted on a substrate.
16. The method for manufacturing a semiconductor device according to claim 15, wherein,
the peeling confirmation step confirms a peeling state in which the defective bare chip is peeled from the dicing tape based on the wafer map data.
CN202310977852.5A 2022-08-09 2023-08-04 Semiconductor manufacturing apparatus and method for manufacturing semiconductor device Pending CN117594480A (en)

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