CN117590359A

CN117590359A - Peak processing circuit, chip and electronic device for histogram

Info

Publication number: CN117590359A
Application number: CN202311531721.0A
Authority: CN
Inventors: 马凯; 尹韬; 刘力源; 田娜; 王哲; 赵天; 刘剑; 吴南健
Original assignee: Institute of Semiconductors of CAS
Current assignee: Institute of Semiconductors of CAS
Priority date: 2023-11-16
Filing date: 2023-11-16
Publication date: 2024-02-23

Abstract

The present disclosure provides a peak processing circuit for a histogram, which can be applied to the technical field of peak processing. The peak processing circuit for a histogram includes: the counter unit is configured to obtain N partition statistical data according to preset partition distance measurement data corresponding to N partition times in the histogram data, wherein N is an integer greater than 1; the digital comparator array is configured to compare the N partition statistical data and determine the largest partition statistical data in the N partition statistical data as target partition statistical data; and a multiplexer array, coupled to the digital comparator array, configured to output the histogram peak of the histogram data based on the target partition statistics.

Description

Peak processing circuit, chip and electronic device for histogram

Technical Field

The present disclosure relates to the field of peak processing technology, and more particularly, to a peak processing circuit, chip, and electronic device related to a histogram.

Background

The basic working principle of the direct time-of-flight (Direct Time Of Flight, D-ToF) imaging technique is: the laser emits pulse laser to the target to be measured, the laser reflected by the object is focused through the lens and then imaged on the photosensor, the Single Photon Avalanche Diode (SPAD) responds to photons generated by the photosensor and generates pulses, and the distance between the photosensor and the target to be measured can be calculated by calculating the time difference between the laser emission and the response pulses. However, SPADs have dark counts and false counts due to ambient light, and single time of flight (ToF) measurements are unreliable. It is thus possible to obtain the ToF with the higher peak from the histogram by repeating the ToF measurement and generating the histogram.

In the process of implementing the disclosed concept, the inventor finds that at least the following problems exist in the related art: the time for processing the histogram acquired in the related art is long, and the area of the processing chip is also large.

Disclosure of Invention

In view of the above, the present disclosure provides a peak processing circuit, a chip, and an electronic device with respect to a histogram.

In a first aspect of the present disclosure, there is provided a peak processing circuit for a histogram, comprising:

the counter unit is configured to obtain N partition statistical data according to preset partition distance measurement data corresponding to N partition times in the histogram data, wherein N is an integer greater than 1;

the digital comparator array is configured to compare N pieces of partition statistical data and determine the largest partition statistical data in the N pieces of partition statistical data as target partition statistical data; and

and the multi-path gate array is connected with the digital comparator array and is configured to output a histogram peak value of the histogram data according to the target partition statistical data.

According to an embodiment of the present disclosure, the counter unit includes N counters, each of the N counters corresponding to one of the N partition times, each of the N partition times corresponding to one of the N counters.

According to an embodiment of the present disclosure, a digital comparator array includes Q digital comparators, Q being an integer greater than 0;

and the Q digital comparators are configured to form a tree structure digital comparator array, the tree structure digital comparator array is utilized to compare the N partition statistical data, and the largest partition statistical data in the N partition statistical data is determined as target partition statistical data.

According to an embodiment of the present disclosure, the multi-gate array is further configured to output histogram peaks of the histogram data based on target paths of the target partition statistics in the tree structure digital comparator array.

According to an embodiment of the present disclosure, the histogram peak includes a peak position and a peak size;

the multi-path gate array is further configured to output peak positions of the histogram data according to target paths of the target partition statistics in the tree structure digital comparator array;

and determining target partition time corresponding to the target partition statistical data according to the target path, determining a target counter corresponding to the target partition time from N counters, and outputting the peak value of the histogram data according to the target counter.

According to an embodiment of the present disclosure, the N counters constitute a counter array, which is an asynchronous counter array.

According to an embodiment of the present disclosure, the peak processing circuit for a histogram further includes:

the data processing unit is configured to acquire histogram data obtained by measuring the distance of the target object by using the measuring equipment, and process the histogram data according to N partition times of the histogram data to obtain preset partition distance measurement data corresponding to the N partition times in the histogram data.

According to an embodiment of the disclosure, the Q digital comparators are further configured to, in a case where Q is greater than a preset threshold, form the Q digital comparators into P digital comparator sets, compare the N partition statistics with the P digital comparator sets, and determine a maximum partition statistic from the N partition statistics.

A second aspect of the present disclosure provides a chip comprising:

such as any of the circuits described above.

A third aspect of the present disclosure provides an electronic device, comprising:

the chip.

According to the peak processing circuit, the chip and the electronic equipment related to the histogram, the counter unit obtains statistical data of each partition according to preset partition distance measurement data corresponding to each partition time in the histogram data; comparing the statistical data of each partition through a digital comparator array, and determining the largest statistical data of each partition as target statistical data of the partition; and the digital comparator array is connected with the multi-path selector array, and the histogram peak value of the histogram data is output according to the target partition statistical data. Because the histogram data is processed through the counter unit, the digital comparator array and the multi-path gate array can be utilized to directly output the histogram peak value according to the partition statistical data of the counter unit, the SRAM array is not required to be used for storing, the time for storing the data in the SRAM array and reading the data from the SRAM array is reduced, the speed for processing the histogram data is improved, the SRAM array is not required, and the integration level of a chip can be reduced.

Drawings

The foregoing and other objects, features and advantages of the disclosure will be more apparent from the following description of embodiments of the disclosure with reference to the accompanying drawings, in which:

FIG. 1 schematically illustrates a block diagram of a peak processing circuit for a histogram in accordance with an embodiment of the present disclosure;

FIG. 2 schematically illustrates a schematic diagram of a 4bit digital comparator in accordance with an embodiment of the present disclosure;

FIG. 3 schematically illustrates a schematic diagram of a 3bit digital comparator in accordance with an embodiment of the present disclosure;

FIG. 4 schematically illustrates a structural schematic of a tree-structured digital comparator array in accordance with an embodiment of the present disclosure;

FIG. 5 schematically illustrates a schematic diagram of a digital comparator array and a multiplexer array according to an embodiment of the present disclosure;

FIG. 6 schematically illustrates a schematic diagram of an asynchronous counter according to an embodiment of the present disclosure;

FIG. 7 schematically illustrates an architectural diagram of a peak processing circuit for histograms according to an embodiment of the disclosure;

FIG. 8 schematically illustrates a schematic diagram of a digital comparator array according to yet another embodiment of the present disclosure;

FIG. 9 schematically illustrates a block diagram of a chip according to an embodiment of the disclosure; and

fig. 10 schematically illustrates a block diagram of an electronic device according to an embodiment of the disclosure.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and/or the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.

All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the terms used herein should be construed to have meanings consistent with the context of the present specification and should not be construed in an idealized or overly formal manner.

Where expressions like at least one of "A, B and C, etc. are used, the expressions should generally be interpreted in accordance with the meaning as commonly understood by those skilled in the art (e.g.," a system having at least one of A, B and C "shall include, but not be limited to, a system having a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.).

Dark counts and false counts due to ambient light are present for SPAD. Thus, statistics can be obtained using the distribution characteristics of different photons over the detection window, i.e. the ToF with higher peaks obtained from the histogram. However, the related art circuit for processing the histogram requires a separate SRAM array to store the code value and the peak value obtained from the histogram, respectively, and the storage and readout of data through the SRAM array may result in a decrease in processing speed, and the SRAM array may also result in an increase in the occupation area of the processing circuit and also result in an increase in the occupation area of the processing circuit. The data obtained in each ToF measurement is time data with full precision, and correlation between the histogram data and the test data is not fully utilized, so that data waste and redundancy of a processing circuit are caused.

To at least partially solve the technical problems existing in the related art, embodiments of the present disclosure provide a peak processing circuit with respect to a histogram, including: the counter unit is configured to obtain N partition statistical data according to preset partition distance measurement data corresponding to N partition times in the histogram data, wherein N is an integer greater than 1; the digital comparator array is configured to compare N pieces of partition statistical data and determine the largest partition statistical data in the N pieces of partition statistical data as target partition statistical data; and the multi-path gate array is connected with the digital comparator array and is configured to output a histogram peak value of the histogram data according to the target partition statistical data.

The peak processing circuit regarding the histogram of the disclosed embodiment will be described in detail below with reference to fig. 1 to 7.

Fig. 1 schematically shows a block diagram of a structure of a peak processing circuit with respect to a histogram according to an embodiment of the present disclosure.

As shown in fig. 1, the peak processing circuit 100 of this embodiment includes a counter unit 110, a digital comparator array 120, and a multiplexer array 130.

The counter unit 110 is configured to obtain N partition statistical data according to preset partition distance measurement data corresponding to N partition times in the histogram data, where N is an integer greater than 1.

According to an embodiment of the present disclosure, the histogram data may be data having time as an abscissa axis and the number of pulses as an ordinate axis. The origin may be the starting time of the laser light emission to the object to be measured in each ToF measurement. The preset partition distance measurement data may characterize the partitioning of the histogram data by time, the data within each time partition. The size of each partition time can be preset manually according to actual measurement requirements. For example, it may be 5ns.

According to embodiments of the present disclosure, the partition statistics may characterize the sum of the number of pulses of the multiple ToF measurements over the corresponding partition time.

According to an embodiment of the present disclosure, the counter unit may be configured to count preset partition distance measurement data corresponding to each of N partition times in the histogram data.

For example, the histogram data M includes measurement data of 36ns, and may be divided into 9 bins according to a partition time of 4ns, i.e., n=9, where each bin corresponds to measurement data of 4 ns. The 9 partition times may include a first partition time, a second partition time … …, an eighth partition time, and a ninth partition time. The first preset partition distance measurement data may be corresponding to the first partition time (i.e., greater than 0 and equal to or less than 4 ns), the second preset partition distance measurement data may be corresponding to the second preset partition distance measurement data at the second partition time (i.e., greater than 4 and equal to or less than 8 ns), the eighth preset partition distance measurement data may be corresponding to … … at the eighth partition time (i.e., greater than 28 and equal to or less than 32 ns), and the ninth preset partition distance measurement data may be corresponding to the ninth preset partition distance measurement data at the ninth partition time (i.e., greater than 32 and equal to or less than 36 ns). According to the pulse number in each preset partition distance measurement data, partition statistical data corresponding to the preset partition distance measurement data can be obtained, and nine partition statistical data can be obtained. N may also be other values, and the disclosure is not limited thereto.

The digital comparator array 120 is configured to compare the N partition statistics and determine the largest partition statistic among the N partition statistics as the target partition statistic.

According to an embodiment of the disclosure, the digital comparator array is configured to compare preset partition distance statistics corresponding to respective partitions in the counter unit, so as to obtain a partition corresponding to the largest statistics. Wherein the largest partition statistics may characterize the target partition statistics.

For example, nine partition statistics (i.e., first partition statistics, second partition statistics … … eighth partition statistics, and ninth partition statistics) are included in the histogram data M, and of 9 partition statistics, the first partition statistics is 0, the second partition statistics is 18, the third partition statistics is 5, the fourth partition statistics is 0, the fifth partition statistics is 3, the sixth partition statistics is 12, the seventh partition statistics is 27, the eighth partition statistics is 0, and the ninth partition statistics is 0, and the largest partition statistics is 27, i.e., seventh partition statistics, and the seventh partition statistics is determined as target partition statistics.

A multiplexer array 130, coupled to the digital comparator array, is configured to output histogram peaks of the histogram data based on the target partition statistics.

According to the embodiments of the present disclosure, the histogram peak of the histogram data may be output according to the partition time corresponding to the target partition statistical data.

According to the embodiment of the disclosure, each partition statistical data is obtained through a counter unit according to preset partition distance measurement data corresponding to each partition time in the histogram data; comparing the statistical data of each partition through a digital comparator array, and determining the largest statistical data of each partition as target statistical data of the partition; and the digital comparator array is connected with the multi-path selector array, and the histogram peak value of the histogram data is output according to the target partition statistical data. Because the histogram data is processed through the counter unit, the digital comparator array and the multi-path gate array can be utilized to directly output the histogram peak value according to the partition statistical data of the counter unit, the SRAM array is not required to be used for storing, the time for storing the data in the SRAM array and reading the data from the SRAM array is reduced, the speed for processing the histogram data is improved, the SRAM array is not required, and the integration level of a chip can be reduced.

According to an embodiment of the present disclosure, the N counters in the counter unit may be used to record partition statistics data within N partition times corresponding to the N counters, that is, each counter in the counter unit is in a one-to-one correspondence with each partition in the histogram data.

For example, the histogram data M is divided into 9 bins, and the counter unit is also configured with 9 counters, each corresponding to one bin, each for recording preset partition distance measurement data within the respective partition time.

According to the embodiment of the disclosure, each counter in the counter unit corresponds to each partition in the histogram data, so that corresponding partition time is conveniently determined according to the counter corresponding to the target partition statistical data through the digital comparator array, the counter position and the numerical value in the counter are determined according to the corresponding partition time, and other transcoding operations are not needed, the problem that the area is overlarge because the data and the position in the histogram are required to be respectively stored in the SRAM in the prior art is solved, and the working mode of the image sensor in a scanning (scanning) mode is more matched.

According to an embodiment of the present disclosure, a digital comparator array includes Q digital comparators, Q being an integer greater than 0; and the Q digital comparators are configured to form a tree structure digital comparator array, the tree structure digital comparator array is utilized to compare the N partition statistical data, and the largest partition statistical data in the N partition statistical data is determined as target partition statistical data.

According to the embodiment of the disclosure, the tree structure digital comparator array can represent the counter position where the maximum value is located by comparing the multiple groups of data in pairs through the digital comparator, then combining again and comparing through the digital comparator, and classifying according to the comparison result.

According to the embodiment of the disclosure, the digital comparator array for comparing the code values can represent the series connection of comparators with low digits, only the comparison results of more than and not more than two types are reserved, and the situations of more than, less than and equal to three types are not reserved any more.

According to the embodiment of the disclosure, the digital comparator adopts a tree structure arrangement mode to form a digital comparator array, and the low-bit comparators can be obtained through pairwise comparison and are connected in series, so that the problem of area multiplication caused by the increase of the bit number is solved, multiplexing of modules is realized, and the symmetry is improved. Meanwhile, the digital comparator only keeps more than two comparison results and not more than two comparison results, and the area is reduced by more than half under the condition of not influencing the results.

Fig. 2 schematically illustrates a structural diagram of a 4bit digital comparator according to an embodiment of the present disclosure.

As shown in fig. 2, in the 4-bit digital comparator 200 of this embodiment, the two input data are a <0:3> and B <0:3>, respectively, and a <0:3> and B <0:3> can be four-bit data of partition statistics.

According to embodiments of the present disclosure, A <3> and B <3> may characterize the leading values of A <0:3> and B <0:3>, with BN <3> being the result of the inverse of B <3>. First, when the outputs are high, i.e., both A <3> and BN <3> are high, the results of A <3> being high and B <3> being low, i.e., A <3> being greater than B <3>, A <0:3> being greater than B <0:3> are obtained, and F being 1 is output. On the other hand, when the sum outputs of A <3> and BN <3> are low, that is, both A <3> and BN <3> are low, both A <3> and B <3> are high or both B <3> are low or A <3> is low and B <3> is high, that is, A <3> and B <3> are equal in value or A <3> is smaller than B <3>, and the sizes of A <0:3> and B <0:3> cannot be distinguished according to the first order, the second order values, namely A <2> and BN <2>, need to be compared, and the principle is adopted similarly. The high level in the embodiment of the present disclosure may represent 1, the low level may represent 0, or may be set to high level representing 0 and low level representing 1 as needed, which is not limited herein.

In accordance with an embodiment of the present disclosure, it is noted that a <3> and B <3> need to be compared to determine if a <3> is less than B <3> before comparing a <2> and BN <2>. The exclusive OR value can be calculated for A <3> and B <3>, and in the case of a low output level, i.e., A <3> and B <3> are the same, the comparison can be continued for A <2> and BN <2 >; in the case where the output is high, that is, a <3> and B <3> are different, since the output is performed in the case where a <3> greater than B <3> has been excluded, the high output, that is, the comparison result representing a <3> less than B <3> and a <0:3> less than B <0:3> can be obtained since the conventional digital comparator can obtain three cases of "greater than", "equal to" and "less than" by comparing the two inputs sequentially from the high to the low, only one case of "greater than" is reserved, and the case of "equal to" and "less than" is directly complemented, so that the array area of the digital comparator can be reduced by more than half.

For example, in the case of f=1, it is possible to obtain a <0:3> greater than B <0:3>; conversely, it is possible to obtain that A <0:3> is not greater than B <0:3>, equal to or less than the threshold, without distinguishing between them, and without affecting the result.

Fig. 3 schematically illustrates a structural diagram of a 3-bit digital comparator according to an embodiment of the present disclosure.

As shown in fig. 3, in the 3-bit digital comparator 300 of this embodiment, the two input data are a <0:2> and B <0:2>, respectively, and a <0:2> and B <0:2> may be three bits of data of the partition statistics.

According to embodiments of the present disclosure, A <2> and B <2> may characterize the leading values of A <0:2> and B <0:2>, with BN <2> being the result of the inverse of B <2>. When the outputs are high, that is, when both A <2> and BN <2> are high, the results of A <2> being high and B <2> being low, that is, when A <2> is greater than B <2>, can be obtained, and the comparison result can be obtained directly: a <0:2> is greater than B <0:2>, and the output result F is 1, so that the comparison of low-order numerical values is not needed; on the other hand, when the sum outputs of A <2> and BN <2> are low, it is possible to obtain that A <2> and B <2> are both high or both low or A <2> is low and B <2> is high, that is, A <2> and B <2> are equal in value or A <2> is smaller than B <2>, and A <0:2> and B <0:2> cannot be distinguished according to the first bits, it is necessary to further compare the second bit values of the two data, namely A <1> and BN <1>, and before A <1> and BN <1> are compared, it is necessary to compare A <2> and B <2>, and determine whether A <2> is smaller than B <2>.

The first set of data A <0:2> is 110 and B <0:2> is 011; the second set of data A <0:2> is 110 and B <0:2> is 101, and the third set of data A <0:2> is 110 and B <0:2> is 101 are illustrated.

For the first set of data, the first bit A <2> of A <0:2> is 1, the first bit B <2> of B <0:2> is 0, the inversion of B <2> results in BN <2> being 1, and the ANDed outputs are high, i.e. A <2> and BN <2> are both high, and BN <2> is B <2> being inverted, so that B <2> is low, so that A <2> is greater than B <2>, resulting in A <0:2> being greater than B <0:2>.

For the second set of data, the first bit A <2> of A <0:2> is 1, the first bit B <2> of B <0:2> is 1, the second bits A <1> and B <1> of A <0:2> and B <0:2> are inverted to obtain BN <2> as 0, the second bits A <0:2> and B <0:2> need to be continuously compared when the and output is low, the exclusive OR value of A <2> and B <2> is obtained before the second bits A <0:2> and B <0:2> are compared, namely A <2> and B <2> are the same, the second bits A <1> and B <1> of A <0:2> and B <0:2> can be continuously compared to obtain BN <1> as 1, the second bits A <1> and B <1> are both high, namely A <1> and BN <1> are required to be high, and BN <1> is required to be low, namely A <2> and B <1> is lower than B <0:2> is obtained when the and B <1> is lower than A <2> is greater than 0:2>.

For the third set of data, the first bit A <2> of A <0:2> is 0, the first bit B <2> of B <0:2> is 0, the B <2> is inverted to obtain BN <2> as 1, and the second bits of A <0:2> and B <0:2> need to be continuously compared when the AND output of A <2> and BN <2> is low, the OR value can be obtained for A <2> and B <2> before the second bits of A <0:2> and B <0:2> are compared, and the output is high, namely A <2> and B <2> are different, and because the comparison result that A <2> is smaller than B <2> can be obtained when A <2> and B <2> are different under the condition that A <2> is larger than B <2> is already eliminated.

According to an embodiment of the present disclosure, the multiplexer array may include at least one multiplexer, each of which may be connected to an output of one of the digital comparators of the digital comparator array. The multiplexer array may be configured to obtain a final position corresponding to the peak according to a result of each comparator, and output a histogram peak of the histogram data according to a target path of the target partition statistical data in the tree structure digital comparator array.

According to the embodiment of the disclosure, the digital comparator is matched with the use of the multi-path gate, and the histogram peak value of the histogram data can be finally obtained through multiple times of comparison, and the two-step histogram peak value processing can improve the processing time and avoid affecting the image frame rate.

According to an embodiment of the present disclosure, the multi-way gate array is further configured to output a peak position of the histogram data according to a target path of the target partition statistics in the tree structure digital comparator array; and determining target partition time corresponding to the target partition statistical data according to the target path, determining a target counter corresponding to the target partition time from N counters, and outputting the peak value of the histogram data according to the target counter.

According to embodiments of the present disclosure, the histogram peak may include a peak position and a peak size.

According to the embodiment of the disclosure, the multi-path gate array can determine the target partition time according to the target path of the target partition statistical data in the tree structure digital comparator array, determine the target counter corresponding to the target partition time, and output the peak value size and the peak value position of the histogram data according to the target counter.

According to embodiments of the present disclosure, a target path may characterize a path corresponding to the position encoding of target partition statistics in a tree structure digital comparator array. The target counter may represent a counter corresponding to a maximum value obtained by comparing the digital comparator array.

Fig. 4 schematically shows a structural schematic diagram of a tree-structured digital comparator array according to an embodiment of the present disclosure.

As shown in fig. 4, the tree structure digital comparator array 400 of this embodiment takes 8 partition statistics as an example, and 8 partition statistics are input into the tree structure digital comparator array respectively as BINX (x=1, 2 … …, 8), and a value with a larger output result of the digital comparator is input into the next stage.

For example: taking the case of BIN4 as the maximum value as an example, the comparison is performed with BIN3 for the first time, since BIN4> BIN3, BIN4 is used as the input of the next comparison, and the following positions are recorded: BIN4 position code 1 and BIN3 position code 0; for the second comparison with BIN2, since BIN4> BIN2, BIN4 is taken as the input for the next comparison, and its position is recorded as: BIN4 position code 1 and BIN2 position code 0; finally, compared to BIN7, BIN4 is taken as the final output, i.e., peak size, since BIN4> BIN7, while recording its position as: the BIN4 position code is 0, the BIN7 position code is 1, the peak value size is BIN4, the code of the position where the BIN4 is located is 011, and the target path of the BIN4 can be determined according to the code of the position where the peak value is located. Meanwhile, for the case of more inputs, a similar manner can be adopted, and the peak size and the peak position of the histogram peak can be determined through log2 (N) times of comparison (N is the number of input data).

According to the embodiment of the disclosure, the multiplexer can obtain the peak value while obtaining the peak value position, so that the further processing is facilitated, the problem that in the prior art, a code value is required to be stored in an SRAM1, address and data are obtained, and then the peak value is stored in an SRAM2 after the code value extraction and peak value detection circuit, and the peak value size and position are obtained is solved. I.e. the problem of requiring corresponding control circuitry for call of units and data allocation.

Fig. 5 schematically illustrates a schematic diagram of a digital comparator array and a multiplexer array according to an embodiment of the present disclosure.

As shown in fig. 5, the multi-way gate is respectively connected to the output end A1-1 of the first comparator, the output end A1-2 of the second comparator, and the output end A2-1 of the third comparator, the first input end of the first comparator is connected to bin1, the second input end of the first comparator is connected to bin2, the first input end of the second comparator is connected to bin3, the second input end of the second comparator is connected to bin4, the output end Q1-1 of the first comparator is connected to the first input end of the third comparator, the output end Q1-2 of the second comparator is connected to the second input end of the third comparator, the output end Q2-1 of the third comparator outputs the peak value, the output end A2-1 of the third comparator outputs the peak value position <1>, and the output end of the multi-way gate outputs the peak value position <0>.

According to the embodiments of the present disclosure, in order to further reduce the influence of ambient light, a multiple event mode is generally adopted, that is, SPAD responds multiple times in a detection interval, so as to suppress a "stacking effect", and avoid the problem that it is difficult to detect signal light due to ambient light interference in a single photon mode. Thus, to accommodate the multiple event mode, the counter unit is set up in an asynchronous mode. Asynchronous counters are of an asynchronous structure, wherein counting pulses are only applied to clock pulse input ends of part of the flip-flops, and trigger signals of other flip-flops are provided by the circuit.

According to the embodiments of the present disclosure, because of the existence of false counts and dark counts generated by ambient light, the measurement result of the counter corresponding to some partitions may be 0, and the counts of the measured target objects are relatively concentrated, so that the statistics of the target counter corresponding to the target partition is the largest.

According to the embodiment of the disclosure, compared with a synchronous counter, the asynchronous counter reduces the number of logic gates and area occupation while guaranteeing the counting rate.

Fig. 6 schematically illustrates a schematic diagram of an asynchronous counter array according to an embodiment of the present disclosure.

As shown in fig. 6, the count pulse clk of the asynchronous counter array 600 of this embodiment is applied to the first counter clock input only, and is an asynchronous counter array.

According to an embodiment of the present disclosure, the count pulses clk of the synchronous counters need to be applied to the clock pulse input of each counter. The asynchronous counter array shown in fig. 6 is only needed at the first counter clock input. Compared with a synchronous counter, the input unit with fewer clock pulses can reduce the number of logic gates and the complexity of a circuit structure.

According to an embodiment of the present disclosure, the peak processing circuit for a histogram further includes: the data processing unit is configured to acquire histogram data obtained by measuring the distance of the target object by using the measuring equipment, and process the histogram data according to N partition times of the histogram data to obtain preset partition distance measurement data corresponding to the N partition times in the histogram data.

According to embodiments of the present disclosure, the measuring device may be a device capable of laser emission as well as photo-sensing. The distance between the target object and the measuring device can be determined by the measuring device transmitting laser light to the target object and receiving laser light reflected back by the target object, based on the difference between the time of transmitting the laser light and the time of returning the laser light.

According to embodiments of the present disclosure, the histogram data may be obtained over multiple ToF measurements. The histogram data may be data having time as the abscissa axis and the number of pulses as the ordinate axis. The origin may be the starting time of the laser light emission to the object to be measured in each ToF measurement. The preset partition distance measurement data may characterize the partitioning of the histogram data by time, the data within each time partition. The size of each partition time can be preset manually according to actual measurement requirements.

Fig. 7 schematically illustrates an architectural diagram of a peak processing circuit with respect to histograms according to an embodiment of the disclosure.

As shown in fig. 7, the peak processing circuit 700 of this embodiment includes histogram data 710 that can be processed by the digital processing unit to obtain preset partition distance measurement data corresponding to each of the N partition times in the histogram data. The preset partition distance measurement data corresponding to each of the N partition times in the histogram data is passed through the peak processing circuit 720, and the peak size and the peak position of the histogram peak are output. .

According to the embodiment of the disclosure, the histogram data 710 represents data obtained by one distance measurement, the abscissa t represents time, after START, signals STOP1, STOP2 and STOP3 are respectively preset partition distance measurement data in three intervals, a series of code values 0 or 1 are obtained through code value acquisition, a counter unit storing the code values in the peak processing circuit 720 obtains N partition statistical data, namely, code values corresponding to N partitions according to preset partition distance measurement data corresponding to N partition times in the histogram data, specifically, in the case that the code value in the corresponding partition time is 1, the count of the counter is increased by 1, and the final measurement result of the counter is the accumulated value of the code values obtained by multiple measurements.

Fig. 8 schematically illustrates a schematic diagram of a digital comparator array according to yet another embodiment of the present disclosure.

As shown in fig. 8, the digital comparator array 800 of this embodiment includes a 4bit digital comparator 810 and a 3bit digital comparator 820.

According to embodiments of the present disclosure, to solve the problem that the scale of the digital comparator array may exhibit an exponential increase as the number of input bits increases, the 7-bit digital comparator 200 may be split into a form of a combination of 4 bits and 3 bits. Meanwhile, the comparison result of the low 4bit is used as the lowest bit input of the high 3bit, multiplexing of the 4bit module, namely adding the comparison result of the low 4bit when the high 3bit is compared, is equivalent to 4bit. The calculation of the 4-bit digital comparator may be referred to the description of the embodiments of the present disclosure with respect to fig. 2, and the calculation of the 3-bit digital comparator may be referred to the description of the embodiments of the present disclosure with respect to fig. 3.

According to the embodiment of the disclosure, the Q digital comparators are split to form P digital comparator groups, so that the area can be further reduced, and the multiplexing of the modules is realized.

Based on the peak processing circuit related to the histogram, the disclosure also provides a chip. The device will be described in detail below in connection with fig. 9.

Fig. 9 schematically shows a block diagram of a chip according to an embodiment of the disclosure.

As shown in fig. 9, the chip 900 of this embodiment includes a peak processing circuit 910.

The peak processing circuit 910 may include any of the circuits described above, according to embodiments of the present disclosure.

Fig. 10 schematically illustrates a block diagram of an electronic device adapted to implement a peak processing circuit with respect to a histogram, in accordance with an embodiment of the disclosure.

As shown in fig. 10, an electronic device 1000 according to an embodiment of the disclosure includes a chip 1010.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Those skilled in the art will appreciate that the features recited in the various embodiments of the disclosure and/or in the claims may be provided in a variety of combinations and/or combinations, even if such combinations or combinations are not explicitly recited in the disclosure. In particular, the features recited in the various embodiments of the present disclosure and/or the claims may be variously combined and/or combined without departing from the spirit and teachings of the present disclosure. All such combinations and/or combinations fall within the scope of the present disclosure.

The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.

Claims

1. A peak processing circuit for a histogram, comprising:

the digital comparator array is configured to compare the N partition statistical data and determine the largest partition statistical data in the N partition statistical data as target partition statistical data; and

and the multi-path gate array is connected with the digital comparator array and is configured to output the histogram peak value of the histogram data according to the target partition statistical data.

2. The circuit of claim 1, wherein the counter unit comprises N counters, each of the N counters corresponding to one of the N partition times, each of the N partition times corresponding to one of the N counters.

3. The circuit of claim 2, wherein the digital comparator array comprises Q digital comparators, Q being an integer greater than 0;

and the Q digital comparators are configured to form a tree structure digital comparator array, compare the N partition statistical data by utilizing the tree structure digital comparator array, and determine the largest partition statistical data in the N partition statistical data as target partition statistical data.

4. The circuit of claim 3, wherein the multiplexer array is further configured to output a histogram peak of the histogram data based on a target path of the target partition statistics in the tree structured digital comparator array.

5. The circuit of claim 4, wherein the histogram peak includes a peak position and a peak size;

the multi-way selector array is further configured to output a peak position of the histogram data according to the target path of the target partition statistics in the tree structure digital comparator array;

and determining target partition time corresponding to the target partition statistical data according to the target path, determining a target counter corresponding to the target partition time from the N counters, and outputting the peak value of the histogram data according to the target counter.

6. The circuit of claim 2, wherein the N counters constitute a counter array, the counter array being an asynchronous counter array.

7. The circuit of any of claims 1-4, further comprising:

the data processing unit is configured to acquire the histogram data obtained by measuring the distance of the target object by using the measuring equipment, and process the histogram data according to the N partition times of the histogram data to obtain the preset partition distance measurement data corresponding to the N partition times in the histogram data.

8. The circuit of claim 3, wherein the Q digital comparators are further configured to group the Q digital comparators into P digital comparator sets, compare the N partition statistics with the P digital comparator sets, and determine a largest partition statistic from the N partition statistics if Q is greater than a preset threshold.

9. A chip, comprising:

a circuit as claimed in any one of claims 1 to 8.

10. An electronic device, comprising: the chip of claim 9.