CN117555768A

CN117555768A - Test method, device, system, equipment and medium for computing quick link equipment

Info

Publication number: CN117555768A
Application number: CN202311575775.7A
Authority: CN
Inventors: 刘俊; 王彦伟; 岳龙; 李霞
Original assignee: Inspur Beijing Electronic Information Industry Co Ltd
Current assignee: Inspur Beijing Electronic Information Industry Co Ltd
Priority date: 2023-11-23
Filing date: 2023-11-23
Publication date: 2024-02-13

Abstract

The application discloses a test method, a device, a system, a device and a medium for computing fast link equipment, which relate to the technical field of computers, wherein a performance test system for computing fast link equipment comprises a host, computing fast link equipment connected with the host and high-speed peripheral equipment interconnection bus standard equipment connected with the host, and the method comprises the following steps: acquiring performance indexes corresponding to basic test items according to data transmission among different components; the component comprises a host, a computing fast link device and a high-speed peripheral device interconnection bus standard device; and comparing performance indexes corresponding to different basic test items to generate a performance test result of the computing quick link equipment. The method and the device realize comprehensive performance test of the computing quick link equipment in each scene.

Description

Test method, device, system, equipment and medium for computing quick link equipment

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a test method, apparatus, system, device, and medium for computing a fast link device.

Background

CXL (computational fast link, compute Express Link) is a high-performance, low-latency interconnect technology for connecting processors, accelerators, and memory devices. The Type3 device of CXL is a set of memory modules that provide persistent, volatile, or a combination of memory.

Due to the lack of a real physical device, the current ways of obtaining performance characteristics of the CXL device include simulating and physically implementing the CXL type3 device, and the performance of the CXL device is not necessarily accurately represented by using the access performance of the remote numa node to approximate the performance of the CXL device, and in addition, the implementation of the physical device with respect to the CXL is limited to the type3 device, and the performance of the CXL device in each scene cannot be systematically represented.

Therefore, how to perform performance testing on the computing fast link device in each scenario is a technical problem that needs to be solved by those skilled in the art.

Disclosure of Invention

The purpose of the application is to provide a performance test method, a device, equipment and a medium for computing quick link equipment, which realize comprehensive performance test of the computing quick link equipment in various scenes.

In order to achieve the above object, the present application provides a performance test method of a computing fast link device, which is applied to a performance test system of the computing fast link device, wherein the performance test system of the computing fast link device includes a host, the computing fast link device connected with the host, and a high-speed peripheral device interconnection bus standard device connected with the host, and the method includes:

Acquiring performance indexes corresponding to basic test items according to data transmission among different components; the basic test item comprises any one or a combination of a plurality of the memory of the host, the computing fast link device and the PCI express standard device, wherein the basic test item comprises any one or more of the memory of the computing fast link device, the memory of the PCI express standard device, the memory of the first computing fast link device and the memory of the second computing fast link device, the memory of the PCI express standard device, the memory of the first PCI express standard device and the memory of the second PCI express standard device, the memory of the host and the memory of the computing fast link device, the memory of the host and the memory of the PCI express standard device, the memory of the PCI express standard device and the memory of the first host and the memory of the second host;

and comparing performance indexes corresponding to different basic test items to generate a performance test result of the computing quick link equipment.

The calculating the memory access of the fast link device comprises: the computing unit in the computing quick link equipment accesses memories of different memory types in the computing quick link equipment under the condition that the computing quick link equipment is connected with the host through different computing quick links and the computing quick link equipment is in different control modes and different bias modes;

the high-speed peripheral device interconnection bus standard device accessing the internal memory thereof comprises: the computing unit in the peripheral interconnect express bus standard device accesses its own memory.

Wherein the first computing fast link device accessing the memory of the second computing fast link device comprises: the first computing fast link device is connected with the host through different computing fast links, and the first computing fast link device accesses the memory of the second computing fast link device under the condition that the second computing fast link device is in different control modes and different bias modes;

the computing the memory of the PCI express standard device accessed by the PCI express device comprises: and the computing quick link equipment is connected with the host computer through different computing quick links, and accesses the high-speed peripheral equipment interconnection bus standard equipment under the condition that the computing quick link equipment is in different control modes.

Wherein the host accessing the memory of the computing fast link device comprises: and under the condition that the computing quick link equipment is in different control modes, the host accesses the memory of the computing quick link equipment.

Wherein the computing the access of the fast link device to the memory of the host comprises: the computing fast link device accesses the memory of the host through the computing fast link;

the high-speed peripheral device interconnection bus standard device accessing the memory of the host comprises: the PCI express standard device accesses the memory of the host through the PCI express standard.

Wherein the performance index includes latency and/or bandwidth.

Wherein the performance indexes corresponding to the basic test items with different contrasts comprise:

comparing the performance indexes corresponding to the device memory managed by the host in the computing quick link device with the performance indexes corresponding to the device memory managed by the host in the computing quick link device which is accessed by the computing unit in the computing quick link device under the conditions of the host bias mode and the device bias mode.

Comparing the performance indexes corresponding to the device memory managed by the host in the computing quick link device with the performance indexes corresponding to the device memory managed by the host in the computing quick link device when the computing quick link device is in different control modes.

and comparing the performance indexes corresponding to the device memory and the device private memory managed by the host in the computing quick link device with the performance indexes corresponding to the device private memory accessed by the computing unit in the computing quick link device.

and comparing the performance indexes corresponding to the memory of the second computing quick link equipment with the performance indexes corresponding to the memory of the second computing quick link equipment when the second computing quick link equipment is in different control modes.

comparing the performance index corresponding to the memory of the device managed by the host in the first computing fast link device accessing the second computing fast link device with the performance index corresponding to the memory of the first PCI express standard device accessing the second PCI express standard device.

and comparing the performance index corresponding to the memory of the second computing quick link device accessed by the first computing quick link device through a memory copy mode with the performance index corresponding to the memory of the second peripheral device interconnection bus standard device accessed by the first peripheral device interconnection bus standard device.

and comparing the performance indexes corresponding to the memory of the second computing quick link equipment accessed by the first computing quick link equipment under the condition that the first computing quick link equipment is in different control modes.

and comparing the performance indexes corresponding to the device memory managed by the host in the computing quick link device with the performance indexes corresponding to the device memory managed by the host in the computing quick link device under the condition that the computing quick link device is in different control modes.

and comparing the performance index corresponding to the memory of the device managed by the host in the computing quick link device accessed by the host with the performance index corresponding to the memory of the high-speed peripheral device interconnection bus standard device accessed by the host.

and comparing the performance index corresponding to the device memory managed by the host in the computing fast link device accessed by the host with the performance index corresponding to the memory accessed by the first host to the second host.

The host is controlled to access the memory of the computing quick link device through the memory access instruction without temporary storage and/or the memory access instruction stored and written back;

and controlling the host to access the memory of the high-speed peripheral device interconnection bus standard device through a loading/storing memory access instruction in the form of a memory mapping port.

Wherein comparing the performance indexes corresponding to the different basic test items to generate a performance test result of the computing fast link device includes:

comparing performance indexes corresponding to different basic test items under different influencing factors to generate a performance test result of the computing quick link equipment; the influence factors comprise any one or a combination of a plurality of memory access threads, access modes, whether the memory access threads belong to the same non-uniform memory access node or not, and data quantity, wherein the access modes comprise sequential access and random access.

To achieve the above object, the present application provides a performance test apparatus for a computing fast link device, applied to a performance test system for a computing fast link device, where the performance test system for a computing fast link device includes a host, a computing fast link device connected to the host, and a high-speed peripheral device interconnection bus standard device connected to the host, the apparatus includes:

the acquisition module is used for acquiring performance indexes corresponding to the basic test items according to data transmission among different components; the basic test item comprises any one or a combination of a plurality of the memory of the host, the computing fast link device and the PCI express standard device, wherein the basic test item comprises any one or more of the memory of the computing fast link device, the memory of the PCI express standard device, the memory of the first computing fast link device and the memory of the second computing fast link device, the memory of the PCI express standard device, the memory of the first PCI express standard device and the memory of the second PCI express standard device, the memory of the host and the memory of the computing fast link device, the memory of the host and the memory of the PCI express standard device, the memory of the PCI express standard device and the memory of the first host and the memory of the second host;

And the comparison module is used for comparing the performance indexes corresponding to the different basic test items so as to generate a performance test result of the computing quick link equipment.

In order to achieve the above object, the present application provides a performance test system for computing a fast link device, for executing the performance test method for computing a fast link device as described above;

the performance test system of the computing fast link device comprises a host, the computing fast link device connected with the host, and a high-speed peripheral device interconnection bus standard device connected with the host.

To achieve the above object, the present application provides an electronic device, including:

a memory for storing a computer program;

and a processor for implementing the steps of the performance test method of the computing fast link device as described above when executing the computer program.

To achieve the above object, the present application provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the performance test method of a computing fast link device as described above.

According to the scheme, the performance test method of the computing fast link device is applied to a performance test system of the computing fast link device, the performance test system of the computing fast link device comprises a host, the computing fast link device connected with the host, and a high-speed peripheral device interconnection bus standard device connected with the host, and the method comprises the following steps: acquiring performance indexes corresponding to basic test items according to data transmission among different components; the basic test item comprises any one or a combination of a plurality of the memory of the host, the computing fast link device and the PCI express standard device, wherein the basic test item comprises any one or more of the memory of the computing fast link device, the memory of the PCI express standard device, the memory of the first computing fast link device and the memory of the second computing fast link device, the memory of the PCI express standard device, the memory of the first PCI express standard device and the memory of the second PCI express standard device, the memory of the host and the memory of the computing fast link device, the memory of the host and the memory of the PCI express standard device, the memory of the PCI express standard device and the memory of the first host and the memory of the second host; and comparing performance indexes corresponding to different basic test items to generate a performance test result of the computing quick link equipment.

According to the performance test method for the computing quick link equipment, basic test items are designed according to data transmission scenes among different components, and meanwhile, more comprehensive performance tests are achieved by comparing performance indexes corresponding to different basic test items. The application also discloses a performance testing device and system for computing the quick link device, an electronic device and a computer readable storage medium, and the technical effects can be achieved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate the disclosure and together with the description serve to explain, but do not limit the disclosure. In the drawings:

FIG. 1 is a block diagram illustrating a performance testing system for computing a fast link device according to an exemplary embodiment;

FIG. 2 is a flow chart illustrating a method of computing a performance test of a fast link device according to an exemplary embodiment;

FIG. 3 is a diagram illustrating a memory path for a computing fast link device to access itself, according to an example embodiment;

FIG. 4 is a diagram illustrating a transmission path for computing memory data between fast link devices according to an exemplary embodiment;

FIG. 5 is a transmission path diagram of a host access computing fast link device memory data, according to an example embodiment;

FIG. 6 is a transmission path diagram illustrating a computing fast link device accessing host memory data according to an example embodiment;

FIG. 7 is a block diagram illustrating a performance testing apparatus for computing a fast link device according to an exemplary embodiment;

fig. 8 is a block diagram of an electronic device, according to an example embodiment.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application. In addition, in the embodiments of the present application, "first," "second," and the like are used to distinguish similar objects, and are not necessarily used to describe a particular order or sequence.

A performance test system for a computing fast link device provided by the application is shown in fig. 1, and comprises a host, the computing fast link device connected with the host, and a high-speed peripheral interconnection bus standard device connected with the host.

An endpoint device (EP) may be a computing fast link (CXL) device or a peripheral component interconnect bus standard (PCIe, peripheral Component Interconnect Express) device, with multiple endpoint devices connected by Root Complex (Root Complex) components. In a CXL device or PCIe device, the computing unit is an optional unit. For CXL devices, the extended memory may be HDM (Host-managed Device Memory) or PDM (device private memory, private Device Memory). Considering the basic performance characteristics of feasible data access or transmission in CXL environment and PCIe environment, the operations are basic operations for forming upper-layer application, and the advantages brought by CXL are better utilized.

The characteristics of consistent access brought by CXL protocol can be tested by a specific tool, because the hit rate of the cache is related to the characteristics of different applications when the memory data of CXL equipment is loaded into the cache of CPU, only the cost brought by different paths of access data due to different protocols is considered when designing a test scheme. In addition, the differences of time delay and bandwidth caused by different stored media are not in the consideration range of the scheme, and the same storage media are required to be unified during testing.

The embodiment of the application discloses a performance test method of computing quick link equipment, which realizes comprehensive performance test of computing quick link equipment in various scenes.

Referring to fig. 1, a flowchart of a method for computing a performance test of a fast link device is shown according to an exemplary embodiment, as shown in fig. 1, comprising:

s101: acquiring performance indexes corresponding to basic test items according to data transmission among different components; the basic test item comprises any one or a combination of a plurality of the memory of the host, the computing fast link device and the PCI express standard device, wherein the basic test item comprises any one or more of the memory of the computing fast link device, the memory of the PCI express standard device, the memory of the first computing fast link device and the memory of the second computing fast link device, the memory of the PCI express standard device, the memory of the first PCI express standard device and the memory of the second PCI express standard device, the memory of the host and the memory of the computing fast link device, the memory of the host and the memory of the PCI express standard device, the memory of the PCI express standard device and the memory of the first host and the memory of the second host;

In a specific implementation, according to data transmission among different components, performance indexes corresponding to basic test items are obtained, wherein the basic test items comprise memory accessed by a computing fast link device, memory accessed by a peripheral device interconnection bus standard device, memory accessed by a first computing fast link device, memory accessed by a second computing fast link device, memory accessed by the peripheral device interconnection bus standard device, memory accessed by a host, memory accessed by the peripheral device interconnection bus standard device, memory accessed by the host, and the performance indexes can comprise time delay and bandwidth.

As a possible implementation manner, the calculating the access of the fast link device to the own memory includes: the computing unit in the computing quick link equipment accesses memories of different memory types in the computing quick link equipment under the condition that the computing quick link equipment is connected with the host through different computing quick links and the computing quick link equipment is in different control modes and different bias modes; the high-speed peripheral device interconnection bus standard device accessing the internal memory thereof comprises: the computing unit in the peripheral interconnect express bus standard device accesses its own memory.

In a specific implementation, the memory path of the endpoint device for accessing itself is shown by a dashed arrow in fig. 3, where the first case is that the endpoint device is a CXL device, the CXL device is connected to the host through a cxl.cache+cxl.mem protocol channel, the device memory is in an HDM-D mode, and the basic test item includes an HDM data performance accessed by the CXL device computing unit under the host bias and an HDM data performance accessed by the CXL device computing unit under the device bias. The second case is that the endpoint device is a CXL device, the CXL device is connected with the host computer through a CXL.cache+CXL.mem protocol channel, the device memory is in an HDM-DB mode, the device memory is in a PDM mode, and the basic test items comprise the HDM data performance accessed by the CXL device computing unit and the PDM data performance accessed by the CXL device computing unit. The third case is that the endpoint device is a PCIe device, and the basic test item includes the PCIe device computing unit accessing the device's own memory data performance.

As a possible implementation manner, the accessing, by the first computing fast link device, the memory of the second computing fast link device includes: the first computing fast link device is connected with the host through different computing fast links, and the first computing fast link device accesses the memory of the second computing fast link device under the condition that the second computing fast link device is in different control modes and different bias modes; the computing the memory of the PCI express standard device accessed by the PCI express device comprises: and the computing quick link equipment is connected with the host computer through different computing quick links, and accesses the high-speed peripheral equipment interconnection bus standard equipment under the condition that the computing quick link equipment is in different control modes.

In a specific implementation, a transmission path of memory data between endpoint devices is shown by a dashed arrow in fig. 4, where in the first case, the CXL device accesses a memory of the CXL device, and there are an HDM and a possible computing unit in the device, if the first computing fast link device directly accesses, through a cxl.cache protocol channel, the HDM data of the second computing fast link device, the basic test item includes a performance in a different bias mode when the HDM data of the second computing fast link device is in an HDM-D mode, the HDM data of the second computing fast link device is in an HDM-DB mode, and the HDM data of the second computing fast link device is in an HDM-H mode, and if both the first computing fast link device and the second computing fast link device are connected to the host through a cxl.mem protocol channel, the basic test item includes a performance of transmitting data between the first computing fast link device and the second computing fast link device through memcpy (memory copy function). The second case is that the CXL device accesses the PCIe device, if the computing fast link device is connected with the host through the CXL.cache protocol channel, the basic test item comprises memory data performance of the computing fast link device directly accessing the PCI express standard device through the CXL.cache protocol channel, data transmission performance of the memory data of the PCI express standard device and the computing fast link device in the HDM-D mode, and data transmission performance of the memory data of the PCI express standard device and the computing fast link device in the HDM-DB mode, if the computing fast link device is connected with the host through the CXL.mem protocol channel, the basic test item comprises memory data of the PCI express standard device and data transmission performance of the computing fast link device in the HDM-H mode. The third case is that the PCIe device accesses a memory of the PCIe device, and the basic test item includes data transmission performance of the memory of the first PCIe device and the memory of the second PCIe device.

As a possible implementation, the accessing, by the host, the memory of the computing fast link device includes: and under the condition that the computing quick link equipment is in different control modes, the host accesses the memory of the computing quick link equipment.

In a specific implementation, the transmission path of the memory data of the host access endpoint device is shown by a dashed arrow in fig. 5, where the first case is that the endpoint device is a CXL device, and the basic test items include the performance of the host access HDM data in the HDM-H mode, the performance of the host access HDM data in the HDM-D mode, and the performance of the host access HDM data in the HDM-DB mode. The first case is that the endpoint device is a PCIe device, and the basic test items include host access to memory capabilities of the PCIe device.

As a possible implementation manner, the computing the access of the fast link device to the memory of the host includes: the computing fast link device accesses the memory of the host through the computing fast link; the high-speed peripheral device interconnection bus standard device accessing the memory of the host comprises: the PCI express standard device accesses the memory of the host through the PCI express standard.

In a specific implementation, the transmission path of the endpoint device accessing the host memory data is shown by a dashed arrow in fig. 6, and the basic test item includes that the CXL device accesses the host memory data performance through the cxl.cache protocol, and the PCIe device accesses the host memory data performance through the PCIe protocol.

The first host accesses the memory of the second host, i.e. the data transmission between different num nodes between the hosts.

S102: and comparing performance indexes corresponding to different basic test items to generate a performance test result of the computing quick link equipment.

In the step, more comprehensive performance test is realized by comparing performance indexes corresponding to different basic test items.

As a possible implementation manner, the performance indexes corresponding to the basic test items with different contrasts include: comparing the performance indexes corresponding to the device memory managed by the host in the computing quick link device with the performance indexes corresponding to the device memory managed by the host in the computing quick link device which is accessed by the computing unit in the computing quick link device under the conditions of the host bias mode and the device bias mode.

In particular implementations, since the data accesses in the two bias modes have different paths, the performance of the device in accessing HDM data by the device computing unit is compared under the host bias and the device bias.

As a possible implementation manner, the performance indexes corresponding to the basic test items with different contrasts include: comparing the performance indexes corresponding to the device memory managed by the host in the computing quick link device with the performance indexes corresponding to the device memory managed by the host in the computing quick link device when the computing quick link device is in different control modes.

In a specific implementation, since the consistency of the HDM-DB mode and the HDM-D mode of the CXL device memory is maintained by the CXL.cache and the CXL.mem respectively, and the maintenance overheads of different protocols are different, the performance of the device for accessing HDM data by the device computing unit in the HDM-DB mode and the HDM-D mode can be compared.

As a possible implementation manner, the performance indexes corresponding to the basic test items with different contrasts include: and comparing the performance indexes corresponding to the device memory and the device private memory managed by the host in the computing quick link device with the performance indexes corresponding to the device private memory accessed by the computing unit in the computing quick link device.

In implementations, since CXL device memory may be partially used as HDM, while still partially memory is device private, i.e., PDM, the device computing unit may be compared to the performance of HDM and PDM, respectively.

As a possible implementation manner, the performance indexes corresponding to the basic test items with different contrasts include: and comparing the performance indexes corresponding to the memory of the second computing quick link equipment with the performance indexes corresponding to the memory of the second computing quick link equipment when the second computing quick link equipment is in different control modes.

In a specific implementation, since the CXL device can access the host memory space using the cxl.cache protocol channel, and the memory on the CXL device is addressed uniformly to the host memory, the cxl.cache protocol can access the HDM data of another CXL device, so the performance of EP1 accessing the HDM data in different modes in EP2 using the cxl.cache can be compared.

As a possible implementation manner, the performance indexes corresponding to the basic test items with different contrasts include: comparing the performance index corresponding to the memory of the device managed by the host in the first computing fast link device accessing the second computing fast link device with the performance index corresponding to the memory of the first PCI express standard device accessing the second PCI express standard device.

In a specific implementation, since HDM data of another CXL device may be accessed using the cxl.cache protocol, the two may be compared for performance, unlike the P2P data transfer between existing devices.

As a possible implementation manner, the performance indexes corresponding to the basic test items with different contrasts include: and comparing the performance index corresponding to the memory of the second computing quick link device accessed by the first computing quick link device through a memory copy mode with the performance index corresponding to the memory of the second peripheral device interconnection bus standard device accessed by the first peripheral device interconnection bus standard device.

In a specific implementation, the CXL.mem protocol channel can address the memory of the CXL device and the memory of the host in a unified way, and at the moment, the data transmission between the two CXL devices can be realized through memcpy operation, and the two CXL devices are different from the existing P2P data transmission mode between the two CXL devices, so that the two CXL devices can be compared in performance.

As a possible implementation manner, the performance indexes corresponding to the basic test items with different contrasts include: and comparing the performance indexes corresponding to the memory of the second computing quick link equipment accessed by the first computing quick link equipment under the condition that the first computing quick link equipment is in different control modes.

In a specific implementation, since the cxl.mem protocol channel can address the CXL device memory and the host memory in a unified manner, the data transmission mode between the CXL device memory and the PCIe device is different from the P2P data transmission mode between the existing devices, but the HDM in the CXL device has a different mode: HDM-H, HDM-DB, HDM-D, so that performance comparisons can be made for data transfers between devices in different host management device memory data modes.

As a possible implementation manner, the performance indexes corresponding to the basic test items with different contrasts include: and comparing the performance indexes corresponding to the device memory managed by the host in the computing quick link device with the performance indexes corresponding to the device memory managed by the host in the computing quick link device under the condition that the computing quick link device is in different control modes.

In a specific implementation, different protocol overheads are caused by different consistency maintenance protocols, so that the performance of the host accessing HDM data in different modes is compared.

As a possible implementation manner, the performance indexes corresponding to the basic test items with different contrasts include: and comparing the performance index corresponding to the memory of the device managed by the host in the computing quick link device accessed by the host with the performance index corresponding to the memory of the high-speed peripheral device interconnection bus standard device accessed by the host.

In an implementation, the performance of a host to access HDM data and PCIe device memory is compared.

As a possible implementation manner, the performance indexes corresponding to the basic test items with different contrasts include: and comparing the performance index corresponding to the device memory managed by the host in the computing fast link device accessed by the host with the performance index corresponding to the memory accessed by the first host to the second host.

In an implementation, performance between host access device HDM data and a remote numa node is compared.

For the above test items or the use of a comparison experiment, an application of a CXL type3 device may be used as an example, where the performance of the host accessing the memory data of the type3 device may be obtained by using a basic test item of the performance of the host accessing the HDM data in the HDM-H mode, and the performance of data transmission between different numa nodes relative to the host is low, and then when considering the application, an application with a high cache hit rate may be considered, where the hit rate is high enough to compensate for the disadvantage of the performance of the host accessing the HDM data in the HDM-H mode. In addition, as the performance of the host for accessing HDM data in HDM-H mode and the performance of data transmission between different numa nodes between hosts have no order of magnitude difference, CXL type3 equipment can be used as an exchange area of a host memory, and a novel page exchange mechanism is designed between the host memory and the CXL memory to improve the utilization rate of the application in the host memory, thereby improving the application performance.

According to the performance test method of the computing quick link equipment, basic test items are designed according to data transmission scenes among different components, the basic test items comprise memory accessed by the computing quick link equipment, memory accessed by the first computing quick link equipment to the second computing quick link equipment, memory accessed by the host to the computing quick link equipment, memory accessed by the computing quick link equipment to the host, memory accessed by the first host to the second host, and meanwhile, more comprehensive performance test is realized by comparing performance indexes corresponding to different basic test items.

On the basis of the above embodiment, as a possible implementation manner, the host accesses the memory of the computing fast link device through no temporary memory access instruction and/or memory access instruction storage and write-back; and controlling the host to access the memory of the high-speed peripheral device interconnection bus standard device through a loading/storing memory access instruction in the form of a memory mapping port.

In implementations, because CXL devices differ from PCIe devices in that CXL device memory may be cached by the host cache, it is desirable to consider using different instruction types to control whether accesses pass through the cache, load/Store memory access instructions transfer data between ARM registers and memory. The No-temporal Store instruction (No temporary storage memory access instruction) indicates that the host does not need to write data directly to memory via the cache, and the Store and Write back instruction (Store and write-back memory access instruction) indicates that the host writes data to memory via the cache. Memory access to PCIe devices is accomplished by Load/Store instructions in the form of MMIO (Memory-Mapped I/O).

On the basis of the foregoing embodiment, as a possible implementation manner, the comparing performance indexes corresponding to different basic test items to generate a performance test result of the computing fast link device includes: comparing performance indexes corresponding to different basic test items under different influencing factors to generate a performance test result of the computing quick link equipment; the influence factors comprise any one or a combination of a plurality of memory access threads, access modes, whether the memory access threads belong to the same non-uniform memory access node or not, and data quantity, wherein the access modes comprise sequential access and random access.

In a specific implementation, when the test host accesses to calculate the memory performance of the fast link device, the following influencing factors need to be considered:

1. the number of threads accessing the CXL memory.

2. Bandwidth discrimination for sequential access and random access to CXL memory.

3. CXL memory accesses with and across NUMA nodes.

4. CXL memory and host memory transfers with NUMA nodes and CXL memory and host memory transfers across NUMA nodes, at which time the impact of the size of the transferred data volume on performance is further considered.

For performance testing between extended memory devices, DMA and memcpy may be used to perform data transfer between the devices, where the DMA and memcpy differ in that the memcpy operation needs to be performed by the CPU, the DMA does not pass through the CPU, and since CXL device memory is regarded as system memory, not only DMA may be used to perform data transfer, but also memcpy may be used to perform data transfer, and at this time, the performance index of the bandwidth needs to consider the size of the transferred data. DMA may be used for data transfers between PCIe devices.

When the comparison test is carried out, performance indexes corresponding to different basic test items under different influence factors can be compared to generate a performance test result.

The following describes a performance testing apparatus for computing a fast link device according to an embodiment of the present application, and the performance testing apparatus for computing a fast link device and the performance testing method for computing a fast link device described in the following may be referred to with each other.

Referring to fig. 7, a block diagram of a performance testing apparatus for computing a fast link device according to an exemplary embodiment is shown, as shown in fig. 7, including:

the acquiring module 701 is configured to acquire performance indexes corresponding to basic test items according to data transmission between different components; the basic test item comprises any one or a combination of a plurality of the memory of the host, the computing fast link device and the PCI express standard device, wherein the basic test item comprises any one or more of the memory of the computing fast link device, the memory of the PCI express standard device, the memory of the first computing fast link device and the memory of the second computing fast link device, the memory of the PCI express standard device, the memory of the first PCI express standard device and the memory of the second PCI express standard device, the memory of the host and the memory of the computing fast link device, the memory of the host and the memory of the PCI express standard device, the memory of the PCI express standard device and the memory of the first host and the memory of the second host;

And the comparison module 702 is configured to compare performance indexes corresponding to different basic test items to generate a performance test result of the computing fast link device.

According to the performance testing device for computing the quick link equipment, basic test items are designed according to data transmission scenes among different components, and meanwhile, more comprehensive performance testing is achieved by comparing performance indexes corresponding to different basic test items.

Based on the foregoing embodiment, as a preferred implementation manner, the calculating the access of the fast link device to the own memory includes: the computing unit in the computing quick link equipment accesses memories of different memory types in the computing quick link equipment under the condition that the computing quick link equipment is connected with the host through different computing quick links and the computing quick link equipment is in different control modes and different bias modes;

Based on the foregoing embodiment, as a preferred implementation manner, the accessing, by the first computing fast link device, the memory of the second computing fast link device includes: the first computing fast link device is connected with the host through different computing fast links, and the first computing fast link device accesses the memory of the second computing fast link device under the condition that the second computing fast link device is in different control modes and different bias modes;

Based on the foregoing embodiment, as a preferred implementation, the accessing, by the host, the memory of the computing fast link device includes: and under the condition that the computing quick link equipment is in different control modes, the host accesses the memory of the computing quick link equipment.

Based on the foregoing embodiment, as a preferred implementation manner, the calculating the access of the fast link device to the memory of the host includes: the computing fast link device accesses the memory of the host through the computing fast link;

Based on the above embodiments, as a preferred implementation, the performance index includes a delay and/or a bandwidth.

Based on the above embodiment, as a preferred implementation, the comparing module 702 is specifically configured to: comparing the performance indexes corresponding to the device memory managed by the host in the computing quick link device with the performance indexes corresponding to the device memory managed by the host in the computing quick link device which is accessed by the computing unit in the computing quick link device under the conditions of the host bias mode and the device bias mode.

Based on the above embodiment, as a preferred implementation, the comparing module 702 is specifically configured to: comparing the performance indexes corresponding to the device memory managed by the host in the computing quick link device with the performance indexes corresponding to the device memory managed by the host in the computing quick link device when the computing quick link device is in different control modes.

Based on the above embodiment, as a preferred implementation, the comparing module 702 is specifically configured to: and comparing the performance indexes corresponding to the device memory and the device private memory managed by the host in the computing quick link device with the performance indexes corresponding to the device private memory accessed by the computing unit in the computing quick link device.

Based on the above embodiment, as a preferred implementation, the comparing module 702 is specifically configured to: and comparing the performance indexes corresponding to the memory of the second computing quick link equipment with the performance indexes corresponding to the memory of the second computing quick link equipment when the second computing quick link equipment is in different control modes.

Based on the above embodiment, as a preferred implementation, the comparing module 702 is specifically configured to: comparing the performance index corresponding to the memory of the device managed by the host in the first computing fast link device accessing the second computing fast link device with the performance index corresponding to the memory of the first PCI express standard device accessing the second PCI express standard device.

Based on the above embodiment, as a preferred implementation, the comparing module 702 is specifically configured to: and comparing the performance index corresponding to the memory of the second computing quick link device accessed by the first computing quick link device through a memory copy mode with the performance index corresponding to the memory of the second peripheral device interconnection bus standard device accessed by the first peripheral device interconnection bus standard device.

Based on the above embodiment, as a preferred implementation, the comparing module 702 is specifically configured to: and comparing the performance indexes corresponding to the memory of the second computing quick link equipment accessed by the first computing quick link equipment under the condition that the first computing quick link equipment is in different control modes.

Based on the above embodiment, as a preferred implementation, the comparing module 702 is specifically configured to: and comparing the performance indexes corresponding to the device memory managed by the host in the computing quick link device with the performance indexes corresponding to the device memory managed by the host in the computing quick link device under the condition that the computing quick link device is in different control modes.

Based on the above embodiment, as a preferred implementation, the comparing module 702 is specifically configured to: and comparing the performance index corresponding to the memory of the device managed by the host in the computing quick link device accessed by the host with the performance index corresponding to the memory of the high-speed peripheral device interconnection bus standard device accessed by the host.

Based on the above embodiment, as a preferred implementation, the comparing module 702 is specifically configured to: and comparing the performance index corresponding to the device memory managed by the host in the computing fast link device accessed by the host with the performance index corresponding to the memory accessed by the first host to the second host.

Based on the above embodiment, as a preferred implementation manner, the host accesses the memory of the computing fast link device by using no temporary memory access instruction and/or storing and writing back the memory access instruction; and controlling the host to access the memory of the high-speed peripheral device interconnection bus standard device through a loading/storing memory access instruction in the form of a memory mapping port.

Based on the above embodiment, as a preferred implementation, the comparing module 702 is specifically configured to: comparing performance indexes corresponding to different basic test items under different influencing factors to generate a performance test result of the computing quick link equipment; the influence factors comprise any one or a combination of a plurality of memory access threads, access modes, whether the memory access threads belong to the same non-uniform memory access node or not, and data quantity, wherein the access modes comprise sequential access and random access.

The specific manner in which the various modules perform the operations in the apparatus of the above embodiments have been described in detail in connection with the embodiments of the method, and will not be described in detail herein.

Based on the hardware implementation of the program modules, and in order to implement the method of the embodiments of the present application, the embodiments of the present application further provide an electronic device, fig. 8 is a block diagram of an electronic device according to an exemplary embodiment, and as shown in fig. 8, the electronic device includes:

A communication interface 1 capable of information interaction with other devices such as network devices and the like;

and the processor 2 is connected with the communication interface 1 to realize information interaction with other devices, and is used for executing the performance test method of the computing quick link device provided by one or more technical schemes when running the computer program. And the computer program is stored on the memory 3.

Of course, in practice, the various components in the electronic device are coupled together by a bus system 4. It will be appreciated that the bus system 4 is used to enable connected communications between these components. The bus system 4 comprises, in addition to a data bus, a power bus, a control bus and a status signal bus. But for clarity of illustration the various buses are labeled as bus system 4 in fig. 8.

The memory 3 in the embodiment of the present application is used to store various types of data to support the operation of the electronic device. Examples of such data include: any computer program for operating on an electronic device.

It will be appreciated that the memory 3 may be either volatile memory or nonvolatile memory, and may include both volatile and nonvolatile memory. Wherein the nonvolatile Memory may be Read Only Memory (ROM), programmable Read Only Memory (PROM, programmable Read-Only Memory), erasable programmable Read Only Memory (EPROM, erasable Programmable Read-Only Memory), electrically erasable programmable Read Only Memory (EEPROM, electrically Erasable Programmable Read-Only Memory), magnetic random access Memory (FRAM, ferromagnetic random access Memory), flash Memory (Flash Memory), magnetic surface Memory, optical disk, or compact disk Read Only Memory (CD-ROM, compact Disc Read-Only Memory); the magnetic surface memory may be a disk memory or a tape memory. The volatile memory may be random access memory (RAM, random Access Memory), which acts as external cache memory. By way of example, and not limitation, many forms of RAM are available, such as static random access memory (SRAM, static Random Access Memory), synchronous static random access memory (SSRAM, synchronous Static Random Access Memory), dynamic random access memory (DRAM, dynamic Random Access Memory), synchronous dynamic random access memory (SDRAM, synchronous Dynamic Random Access Memory), double data rate synchronous dynamic random access memory (ddr SDRAM, double Data Rate Synchronous Dynamic Random Access Memory), enhanced synchronous dynamic random access memory (ESDRAM, enhanced Synchronous Dynamic Random Access Memory), synchronous link dynamic random access memory (SLDRAM, syncLink Dynamic Random Access Memory), direct memory bus random access memory (DRRAM, direct Rambus Random Access Memory). The memory 3 described in the embodiments of the present application is intended to comprise, without being limited to, these and any other suitable types of memory.

The method disclosed in the embodiments of the present application may be applied to the processor 2 or implemented by the processor 2. The processor 2 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in the processor 2 or by instructions in the form of software. The processor 2 described above may be a general purpose processor, DSP, or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The processor 2 may implement or perform the methods, steps and logic blocks disclosed in the embodiments of the present application. The general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed in the embodiments of the present application may be directly embodied in a hardware decoding processor or implemented by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium in the memory 3 and the processor 2 reads the program in the memory 3 to perform the steps of the method described above in connection with its hardware.

The processor 2 implements corresponding flows in the methods of the embodiments of the present application when executing the program, and for brevity, will not be described in detail herein.

In an exemplary embodiment, the present application also provides a storage medium, i.e. a computer storage medium, in particular a computer readable storage medium, for example comprising a memory 3 storing a computer program executable by the processor 2 for performing the steps of the method described above. The computer readable storage medium may be FRAM, ROM, PROM, EPROM, EEPROM, flash Memory, magnetic surface Memory, optical disk, CD-ROM, etc.

Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the above method embodiments may be implemented by hardware associated with program instructions, where the foregoing program may be stored in a computer readable storage medium, and when executed, the program performs steps including the above method embodiments; and the aforementioned storage medium includes: a removable storage device, ROM, RAM, magnetic or optical disk, or other medium capable of storing program code.

Alternatively, the integrated units described above may be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product. Based on such understanding, the technical solutions of the embodiments of the present application may be embodied in essence or a part contributing to the prior art in the form of a software product stored in a storage medium, including several instructions for causing an electronic device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a removable storage device, ROM, RAM, magnetic or optical disk, or other medium capable of storing program code.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A performance test method of a computing fast link device, applied to a performance test system of a computing fast link device, the performance test system of the computing fast link device including a host, the computing fast link device connected to the host, and a high-speed peripheral device interconnect bus standard device connected to the host, the method comprising:

2. The performance testing method according to claim 1, wherein the computing the access of the fast link device to the own memory comprises: the computing unit in the computing quick link equipment accesses memories of different memory types in the computing quick link equipment under the condition that the computing quick link equipment is connected with the host through different computing quick links and the computing quick link equipment is in different control modes and different bias modes;

3. The performance testing method of claim 1, wherein the first computing fast link device accessing a memory of a second computing fast link device comprises: the first computing fast link device is connected with the host through different computing fast links, and the first computing fast link device accesses the memory of the second computing fast link device under the condition that the second computing fast link device is in different control modes and different bias modes;

4. The method of claim 1, wherein the host accessing the memory of the computing fast link device comprises: and under the condition that the computing quick link equipment is in different control modes, the host accesses the memory of the computing quick link equipment.

5. The performance testing method of claim 1, wherein the computing a flash link device access to a memory of the host comprises: the computing fast link device accesses the memory of the host through the computing fast link;

6. The performance testing method according to claim 1, wherein the performance indicators comprise latency and/or bandwidth.

7. The performance testing method according to claim 1, wherein the performance indexes corresponding to the basic test items with different contrasts comprise:

8. The performance testing method according to claim 1, wherein the performance indexes corresponding to the basic test items with different contrasts comprise:

9. The performance testing method according to claim 1, wherein the performance indexes corresponding to the basic test items with different contrasts comprise:

10. The performance testing method according to claim 1, wherein the performance indexes corresponding to the basic test items with different contrasts comprise:

11. The performance testing method according to claim 1, wherein the performance indexes corresponding to the basic test items with different contrasts comprise:

12. The performance testing method according to claim 1, wherein the performance indexes corresponding to the basic test items with different contrasts comprise:

13. The performance testing method according to claim 1, wherein the performance indexes corresponding to the basic test items with different contrasts comprise:

14. The performance testing method according to claim 1, wherein the performance indexes corresponding to the basic test items with different contrasts comprise:

15. The performance testing method according to claim 1, wherein the performance indexes corresponding to the basic test items with different contrasts comprise:

16. The performance testing method according to claim 1, wherein the performance indexes corresponding to the basic test items with different contrasts comprise:

17. The performance testing method according to claim 1, wherein the host is controlled to access the memory of the computing fast link device by having no temporary memory access instruction and/or storing and writing back memory access instructions;

18. The performance testing method according to claim 1, wherein comparing the performance indexes corresponding to the different basic test items to generate the performance test result of the computing fast link device includes:

19. A performance testing apparatus for a computing fast link device, the performance testing system for a computing fast link device comprising a host, a computing fast link device coupled to the host, and a high speed peripheral interconnect bus standard device coupled to the host, the apparatus comprising:

20. A performance testing system for a computing fast link device, configured to perform the performance testing method for a computing fast link device according to any one of claims 1 to 19;

21. An electronic device, comprising:

a memory for storing a computer program;

a processor for implementing the steps of the method for computing a performance test of a fast link device according to any one of claims 1 to 19 when executing said computer program.

22. A computer readable storage medium, characterized in that it has stored thereon a computer program which, when executed by a processor, implements the steps of the method for testing the performance of a computing fast link device according to any of claims 1 to 19.