CN117548318A - PMUT structure with support layer and manufacturing method thereof - Google Patents
PMUT structure with support layer and manufacturing method thereof Download PDFInfo
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 2
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Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
- B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
- B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
- B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
- B06B1/06—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
- B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
- B06B3/00—Methods or apparatus specially adapted for transmitting mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
- B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
- B06B2201/00—Indexing scheme associated with B06B1/0207 for details covered by B06B1/0207 but not provided for in any of its subgroups
- B06B2201/50—Application to a particular transducer type
- B06B2201/55—Piezoelectric transducer
Landscapes
- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to a PMUT structure and a manufacturing method thereof, wherein the PMUT structure comprises: a transistor unit, one side of which includes a transistor; and a PMUT unit including a PMUT and a support layer, wherein the PMUT includes a first electrode layer, a second electrode layer and a piezoelectric layer, one side and the other side of the piezoelectric layer are respectively provided with the first electrode layer and the second electrode layer, wherein: the PMUT structure further includes a cavity for a PMUT; and one side of the supporting layer is bonded to one side of the transistor unit, and the other side of the supporting layer includes a flat surface portion bonded to the other side of the piezoelectric layer. The invention also relates to a PMUT structure array comprising the PMUT structure and electronic equipment comprising the PMUT structure or the PMUT structure array.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductors, and in particular, to a PMUT structure with a supporting layer, a method for manufacturing the PMUT structure, a PMUT structure array, and an electronic device having the PMUT structure or the PMUT structure array.
Background
The piezoelectric micromachined ultrasonic transducer Piezoelectric Micromachined Ultrasonic Transducer, PMUT, is a MEMS device that vibrates a piezoelectric film by using the positive and negative piezoelectric effects of a piezoelectric material, thereby transmitting or receiving an ultrasonic signal. When the PMUT is used as both an actuator (transmitting acoustic waves) and a sensor (receiving acoustic waves). The PMUT based on MEMS standard technology is produced in batches and packaged in a wafer level, so that the cost is greatly reduced, and the PMUT is very suitable for large-scale commercial application. The PMUT has good application prospects in the aspects of ultrasonic ranging, ultrasonic imaging, ultrasonic nondestructive testing, ultrasonic fingerprint identification, ultrasonic drivers and the like.
Ultrasonic ranging is one of the important applications of PMUTs, and mainly uses Time of Flight (TOF), i.e., detecting the Time between transmission and reception of ultrasonic waves to determine the distance. Based on the principle, the PMUT ultrasonic ranging can be used in the scenes of car reversing radar, underwater sonar detection, sweeping robots, ultrasonic smoke alarms and the like. In addition, the PMUT ultrasonic fingerprint sensor mainly based on Time of Flight (TOF) can detect fingerprints of the dermis of the finger, can identify fake fingerprints made of resin, can enable people with epidermis fingerprint damage caused by mechanical abrasion to smoothly read the fingerprints, is another important application of PMUT, and has very important effects in the fields of information security and the like. In addition, nondestructive inspection is a typical application of PMUT in industrial fields, and ultrasound is used for detecting object damage by detecting the time of flight and the intensity of a return signal, and has very wide and urgent demands in the fields of power grid, rail, chemical industry and the like. The PMUT array full-focusing imaging has the potential of realizing 3D imaging, and is hopeful to break through the limitation that the existing detection technology cannot detect fine damage; meanwhile, the small size of the non-destructive inspection device can completely meet the requirements of industrial fields on nondestructive inspection in the fields of portability and low power consumption. The PMUT ultrasonic medical imaging aims at the limitations of larger size, low detection precision, large propagation loss, long detection time and the like of the existing ultrasonic probe by detecting the flight time and the intensity of the return signal, so that the diagnosis speed and the diagnosis precision are greatly improved by the PMUT high-density array full-focusing phased array imaging, and the PMUT high-density array full-focusing phased array imaging has strong application capability in the medical diagnosis field. In addition, the PMUT can also be used as an energy source, and can be applied to the fields of ultrasonic excitation, energy transmission and the like.
The integration of the existing PMUT with CMOS (Complementary Metal-Oxide-Semiconductor) is mainly achieved by two schemes:
scheme 1. CMOS wafers are used as substrates for various thin film deposition and etching processes, however, PMUT fabrication processes include deposition of various thin films (such as piezoelectric thin films, electrode thin films, etc.) at different temperatures and etching of the corresponding thin films in different atmospheres and liquid environments, which requires that the process does not damage CMOS circuits. In the piezoelectric materials, only a few MEMS manufacturing processes of piezoelectric films such as AlN-based piezoelectric materials are compatible with CMOS, so that the scheme is mainly used for developing corresponding piezoelectric material-based integrated ultrasonic transducers. However, the piezoelectric property of the piezoelectric film is a critical determining part of PMUT performance, such as piezoelectric materials with very excellent piezoelectric properties, such as polycrystalline lead zirconate titanate (PZT), liNbO3, etc., and the processing technology is more severe than AlN and has poor compatibility with CMOS, so the development of CMOS integrated PMUT based on the above process flow is more limited and is difficult to realize.
And 2, respectively processing the PMUT wafer and the CMOS wafer, setting one side of the PMUT wafer, on which the piezoelectric film is arranged, and one side of the CMOS wafer, on which the transistor is arranged, as the front surface of the corresponding wafer, and bonding the front surface of the PMUT wafer and the front surface of the CMOS to construct the CMOS integrated PMUT. This approach has less limitations on the piezoelectric material than the above-described approach 1, however, the effective vibration of the PMUT mechanical vibration unit is critical for efficient emission and reception of ultrasound waves, which requires a cavity structure below the vibration unit, providing space for the vibration unit to vibrate effectively, which requires a corresponding cavity on the CMOS. However, cavity size is a central factor in determining PMUT ultrasound frequency, and variations in cavity size will result in variations in PMUT ultrasound frequency. When bonding two wafers of PMUT and CMOS, there is an unavoidable misalignment, resulting in random misalignment between the vibrating cell area and the design itself, causing frequency fluctuations of the developed CMOS integrated PMUT. It is worth noting that PMUT resonators used in the field of ultrasound imaging are very small in diameter, typically tens of microns or even less, and even a misalignment of 1 micron will have a significant adverse effect.
There is therefore a need in the art to develop CMOS and PMUT integration schemes as follows: the method has strong universality on the piezoelectric material, and/or the integration process of the CMOS unit and the PMUT unit has no influence on the size of the cavity.
The existing integration of the PMUT and the CMOS mainly uses a CMOS wafer as a substrate, and various thin film depositions (including but not limited to a supporting layer, an electrode layer, a piezoelectric layer and the like) and etching processing flows are carried out on the substrate, so that the integration of the PMUT on the CMOS wafer is realized.
Typically, PMUT cells integrated on CMOS exhibit flexural vibration modes, i.e. the vibration cells flexural vibrate in a direction perpendicular to the thickness of the membrane, emitting ultrasound waves outwards. In order to realize effective bending vibration of the PMUT unit, one side of the CMOS facing the PMUT vibration unit (namely the front side of the CMOS) needs to be provided with a cavity, meanwhile, the whole thickness of the films at two sides of the PMUT piezoelectric film is inconsistent, one side is thicker than the other side, so that the mass center of the whole vibration unit is not positioned at the center of the piezoelectric film, and vibration of the diaphragm in a thickness stretching mode is avoided.
One of the key factors determining PMUT performance is the piezoelectric material itself. When the PMUT and CMOS integrated chip is built based on the scheme, the growth of the piezoelectric film is carried out on a CMOS base wafer with a very complex surface, for example, the material type of the surface of the CMOS wafer for growing the piezoelectric film is not single, the surface unevenness has steps and the like, so that the deposition of the piezoelectric film with high quality, particularly the single crystal piezoelectric film, is difficult to realize.
There is therefore a need to develop an integration scheme of PMUT cells with conventional CMOS cells that facilitates the formation of high quality piezoelectric films.
Disclosure of Invention
The present invention has been made to alleviate or solve at least one of the above-mentioned problems of the prior art.
Embodiments of the present invention relate to a PMUT structure comprising:
a transistor unit, one side of which includes a transistor; and
a PMUT unit comprising a PMUT and a supporting layer, wherein the PMUT comprises a first electrode layer, a second electrode layer and a piezoelectric layer, one side and the other side of the piezoelectric layer are respectively provided with the first electrode layer and the second electrode layer,
wherein:
the PMUT structure further includes a cavity for a PMUT; and is also provided with
One side of the supporting layer is bonded to one side of the transistor unit, and the other side of the supporting layer includes a flat surface portion bonded to the other side of the piezoelectric layer.
Embodiments of the present invention also relate to a method of manufacturing a PMUT structure including a cavity for a PMUT, the method comprising the steps of:
providing a transistor unit, wherein one side of the transistor unit comprises a transistor; and
a PMUT unit is arranged to be jointed with the transistor unit, the PMUT unit comprises a PMUT and a supporting layer, the PMUT comprises a first electrode layer, a second electrode layer and a piezoelectric layer, one side and the other side of the piezoelectric layer are respectively provided with the first electrode layer and the second electrode layer,
wherein:
one side of the supporting layer is bonded to one side of the transistor unit, and the other side of the supporting layer includes a flat surface portion bonded to the other side of the piezoelectric layer.
Embodiments of the present invention also relate to a PMUT structure array comprising a plurality of PMUT structures as described above, or a PMUT structure fabricated by a plurality of fabrication methods as described above.
The embodiment of the invention also relates to an electronic device, comprising the PMUT structure, or the PMUT structure manufactured by the manufacturing method, or the PMUT structure array.
Drawings
These and other features and advantages of the various embodiments of the disclosed invention will be better understood from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate like parts throughout the several views, and wherein:
fig. 1 is a schematic structural diagram of a PMUT structure according to an exemplary embodiment of the present invention;
fig. 2-9 are cross-sectional schematic diagrams illustrating a method of fabricating a PMUT structure, according to an example embodiment of the invention;
fig. 10 is a schematic structural view of a PMUT structure according to another exemplary embodiment of the present invention;
fig. 11 is a schematic structural view of a PMUT structure according to yet another exemplary embodiment of the present invention;
fig. 12 is a schematic diagram of a PMUT structure array in accordance with an exemplary embodiment of the invention.
Detailed Description
The technical scheme of the invention is further specifically described below through examples and with reference to the accompanying drawings. In the specification, the same or similar reference numerals denote the same or similar components. The following description of embodiments of the present invention with reference to the accompanying drawings is intended to illustrate the general inventive concept and should not be taken as limiting the invention. Some, but not all embodiments of the invention. All other embodiments, which are derived by a person skilled in the art based on the embodiments of the invention, fall within the scope of protection of the invention.
First, reference numerals in the drawings of the present invention are explained as follows:
1000: CMOS cells or transistor cells (see fig. 1 and 2).
100: the CMOS substrate or transistor substrate can be made of monocrystalline silicon, gallium nitride, gallium arsenide, sapphire, quartz, silicon carbide, diamond, etc.
101: a source and a drain of the transistor.
110: the circuit protection layer is an insulating material layer, and may be silicon dioxide, silicon nitride, or the like.
111: a gate of the transistor.
113A: the material of the electrical connection layer in the transistor unit layer corresponds to the first electrical connection layer, and is selected from molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or the composite of the above metals or the alloy thereof, and the like, and the material is also applicable to other electrical connection layers.
113B: the transistor unit layer is internally provided with an electric connection layer corresponding to the second electric connection layer.
113. 115: and other transistor unit layers are electrically connected.
112 and 114: and a transistor cell interlayer electrical connection layer.
2000: PMUT cells.
200: the material of the support protection layer (support protection layer) can be one of aluminum nitride, silicon carbide, polysilicon, monocrystalline silicon, silicon dioxide, amorphous silicon and doped silicon dioxide.
201: a cavity.
210: the material of the sacrificial material layer can be silicon dioxide, doped silicon dioxide and the like.
220: and the supporting layer is made of one of silicon, silicon dioxide, silicon nitride, aluminum nitride, molybdenum, platinum and the like. In an alternative embodiment, the thickness of the support layer 210 is in the range of 0.1 μm-10 μm. As can be appreciated, when the material of the support layer 210 is metal, an electrical isolation layer (optionally an insulating film material) needs to be provided between the support layer 210 and the conductive layer 260A/260B mentioned later.
230. 250: the electrode layer is made of molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or a composite or alloy of the above metals. The materials of the two electrode layers may be the same or different.
240: the piezoelectric layer or piezoelectric film layer is made of polycrystalline aluminum nitride (AlN), polycrystalline zinc oxide, polycrystalline lead zirconate titanate (PZT), and polycrystalline lithium niobate (LiNbO) 3 ) Polycrystalline lithium tantalate (LiTaO) 3 ) Materials such as polycrystalline potassium niobate (KNbO 3), or materials such as single crystal aluminum nitride, single crystal gallium nitride, single crystal lithium niobate, single crystal lead zirconate titanate, single crystal potassium niobate, single crystal quartz thin film, or single crystal lithium tantalate, wherein the single crystal or the polycrystalline materials can also comprise rare earth element doped materials with a certain atomic ratio, and the single crystal or the polycrystalline materials belong to piezoelectric layers which can be used in the invention. .
240a,500 b: and a hole for conducting electricity.
260a,260b: the conductive layer may be made of a material selected from materials for forming the electrode layer.
270: the device protection layer is typically a dielectric material such as silicon dioxide, aluminum nitride, silicon nitride, etc.
300: a bonding material layer (see, e.g., fig. 1) for bonding the support layer 200 to the circuit protection layer 110, which may be, for example, a metal bonding layer.
400: the auxiliary substrate is made of monocrystalline silicon, gallium nitride, gallium arsenide, sapphire, quartz, silicon carbide, diamond and the like.
3000: PMUT structure (see fig. 1 and 12).
4000: PMUT structure array (see fig. 12).
Fig. 1 is a schematic structural diagram of a PMUT structure according to an exemplary embodiment of the present invention, and as shown in fig. 1, the PMUT structure 3000 includes:
a transistor unit 1000 (see fig. 1 and 2), the transistor unit 1000 including a transistor (which includes source and drain electrodes 101, a gate electrode 111), first and second electrical connection layers 113A and 113B electrically insulated from each other, a circuit protection layer 110, the circuit protection layer 110 covering the transistor, the first and second electrical connection layers 113A and 113B;
a PMUT cell 2000 (see fig. 1) comprising a supporting layer 200 and a PMUT comprising a first electrode layer 250, a second electrode layer 230 and a piezoelectric layer 240; and
the first conductive layer 260A and the second conductive layer 260B, which are electrically insulated from each other, see fig. 1,
wherein:
the PMUT structure further comprises a cavity 201 for PMUT, a supporting layer 220 is disposed on the upper side of the cavity 201, and a second electrode layer 230 is disposed on the supporting layer 220, as shown in fig. 1, it can be seen that in fig. 1, the cavity 201 is disposed in the supporting layer 200;
as shown in fig. 1, the piezoelectric layer 240 is a single crystal thin film layer, a bonding material layer 300 is disposed between one side (lower side as shown in fig. 1) of the supporting layer 200 and one side (upper side as shown in fig. 1) of the circuit protecting layer 110, and a flat portion of the other side (upper side of the supporting layer 200 in fig. 1) of the supporting layer 200 is bonded to the other side (lower side of the piezoelectric layer 240 in fig. 1) of the piezoelectric layer 240.
It should be noted that, in the present invention, "bonding" includes not only the case of directly bonding both as shown in fig. 1, for example, direct bonding, the bonding scheme may take various forms including silicon-silicon bonding, silicon-SiO 2 bonding, etc., but also the case of providing other bonding layers or films therebetween, which are within the scope of the present invention.
In the embodiment shown in fig. 1, the bonding between the supporting layer 200 and the circuit protection layer 110 passes through the material bonding layer 300, but the present invention is not limited thereto. As shown in fig. 11, the supporting layer 200 is directly bonded to the circuit protection layer 110. These are included in the scope of "one side of the coverlay 200 is bonded to one side of the circuit protective layer 110", i.e., the bonding includes not only the direct bonding of the coverlay 200 to the circuit protective layer 110 as shown in fig. 11, but also the case where other layers or film layers (e.g., bonding material layer 300) are provided therebetween as shown in fig. 1.
In addition, as shown in fig. 1, 10 and 11, the other side of the supporting layer 200 (the upper side of the supporting layer 200 in the drawing) is bonded to the piezoelectric layer 240, and the surface contact may be a direct surface contact or an indirect surface contact, similar to the "bonding of one side of the supporting layer 200 to one side of the circuit protection layer 110", which is within the scope of the present invention.
It should be noted that, in the specific embodiment of the present invention, the connection between the supporting layer 200 and the circuit protection layer 110 is exemplified, however, the connection between the PMUT cell 2000 and the CMOS cell 1000 may be a circuit protection layer defining the surface of the CMOS cell, or other layers defining the surface of the CMOS cell, which is within the scope of the present invention.
In the embodiment shown in fig. 1, the CMOS cell 1000 further includes a CMOS substrate 100, one side of the circuit protection layer 110 is bonded to the PMUT cell 2000, and the other side of the circuit protection layer 110 is bonded to the CMOS substrate 100. Alternatively, in some cases, the PMUT cell may be bonded to the CMOS substrate 100, which is also within the scope of the present invention.
It is also to be noted that, in the present invention, CMOS is taken as one example of a transistor and thus a CMOS cell is taken as one example of a transistor cell, but the present invention is not limited thereto, and the transistor may also be a BiMOS (BI-polar Metal-Oxide Semiconductor, bipolar Metal oxide semiconductor) cell or BCD (bipolarcmos-DMOS) or the like, and thus the transistor cell may also be a BiMOS cell or BCD cell or the like.
As shown in fig. 1, 10 and 11, the cavity 201 is provided in the supporting layer 200, and includes not only a case where the lower side of the cavity 201 is defined by the supporting layer 200 but also a case where the cavity 201 abuts against the lower side of the supporting layer 200 so that the lower side of the cavity 201 is defined by the bonding material layer 300 or the circuit protection layer 110, which is within the scope of the present invention.
For PMUT cells, a support layer is typically included. The support layer may be located on a side of the piezoelectric layer facing the transistor cell, for example, on the underside of the second electrode layer 230 as shown in fig. 1; or may be located on a side of the piezoelectric layer remote from the transistor cells, i.e. on an upper side of the first electrode layer 250. It should also be noted that the support layer 220 may not be provided by the structural design of the electrode layer itself, as shown in fig. 10 and 11. The difference between fig. 10 and 11 is that in fig. 11, the bonding material layer 300 is not provided, whereas in the structure shown in fig. 10, the bonding material layer 300 is provided between the supporting layer 200 and the circuit bonding layer 110.
In the embodiment shown in fig. 1, the PMUT structure is provided with a first conductive via 500A, a second conductive via 500B, and a third conductive via 240A (see, e.g., fig. 1 and 9), the first conductive via 500A extending through the piezoelectric layer 240, the supporting layer 200, and the bonding material layer 300 to reach the first electrical connection layer 113A within the circuit protection layer 110, the second conductive via 500B extending through the piezoelectric layer 240, the supporting layer 200, and the bonding material layer 300 to reach the second electrical connection layer 113B within the circuit protection layer 110, and the third conductive via 240A extending through the piezoelectric layer 240 to reach the second electrode layer 230. The first conductive layer 260A electrically connects the first electrode layer 250 to the first electrical connection layer 113A through the first conductive via 500A, and the second conductive layer 260B electrically connects the second electrode layer 230 to the second electrical connection layer 113B through the second conductive via 500B and the third conductive via 240A.
Although not shown, it is within the scope of the present invention that the first conductive layer 260A and the second conductive layer 260B may be electrically connected to the first electrical connection layer 113A and the second electrical connection layer 113B, respectively, exposed at the sides of the PMUT structure.
In an alternative embodiment, the first electrical connection layer 113A is electrically connected to one of the electrodes (e.g., the source) of the transistor, and the second electrical connection layer 113B is electrically connected to the other one of the electrodes (e.g., the gate) of the transistor. However, it is within the scope of the present invention that the first electrical connection layer 113A and/or the second electrical connection layer 113B may be electrically connected thereto, as needed and desired, in the case of other electrical connection structures present in the transistor cell.
In the embodiment shown in fig. 1, 10 and 11, the transistor unit 1000 includes a transistor, first and second electrical connection layers 113A and 113B electrically insulated from each other, and a circuit protection layer 110, the circuit protection layer 110 covering the transistor, the first and second electrical connection layers 113A and 113B. In alternative embodiments, the first electrical connection layer 113A and the second electrical connection layer 113B may not be disposed in the circuit protection layer 110 of the transistor cell, or the electrode power of the PMUT cell may be supplied in other manners without using the first electrical connection layer 113A and the second electrical connection layer 113B, which are also within the scope of the present invention.
Based on the above, the present invention proposes a PMUT structure comprising:
a transistor unit, one side of which includes a transistor; and
a PMUT unit comprising a PMUT and a supporting layer, wherein the PMUT comprises a first electrode layer, a second electrode layer and a piezoelectric layer, one side and the other side of the piezoelectric layer are respectively provided with the first electrode layer and the second electrode layer,
wherein:
the PMUT structure further includes a cavity for a PMUT; and is also provided with
One side of the supporting layer is bonded to one side of the transistor unit, and the other side of the supporting layer includes a flat surface portion bonded to the other side of the piezoelectric layer.
In the present invention, the side where the supporting layer 200 is bonded to the piezoelectric layer 240 is a flat surface, which is advantageous to solve the technical problem of low quality of the piezoelectric film layer caused by the fact that the material type of the CMOS wafer surface on which the piezoelectric film is grown is not single, the surface is uneven and has steps in the prior art.
In the structures shown in fig. 1, 10 and 11, the piezoelectric film of the PMUT is of monocrystalline structure, i.e., the piezoelectric layer 240 is a monocrystalline piezoelectric film layer. Compared with the polycrystalline piezoelectric film, the corresponding monocrystalline piezoelectric film in the structure has higher piezoelectric constant and electromechanical coupling coefficient, and better heat conduction performance, so that the vibration element density and the filling factor are improved. The high filling factor and the array element density can improve the transmitting acoustic intensity, the receiving sensitivity and the resolution ratio, obtain the ultrasonic imaging image with high contrast ratio and reduce the energy loss. In addition, the single-crystal piezoelectric film can realize uniform stress of the film in the whole wafer range in the manufacturing process, and reduce the influence of non-uniform stress on PMUT frequency, so that more stable and uniform PMUT devices can be obtained, and the yield of large-scale manufacturing is improved.
Furthermore, for imaging applications: in the aspect of imaging performance, the array element density can be improved due to good thermal conductivity of the monocrystalline piezoelectric material, so that the imaging resolution is improved; the uniformity of stress brought by the single crystal piezoelectric material can improve the frequency consistency, so as to optimize the imaging consistency; the high coupling coefficient brought by the single crystal piezoelectric material can improve the transmitting and receiving sensitivity of array elements, thereby improving the imaging contrast.
However, in alternative embodiments, the piezoelectric layer 240 may be a flat polycrystalline piezoelectric film layer, which is also within the scope of the present invention.
The method of fabricating the PMUT structure shown in fig. 1 is exemplarily described below with reference to fig. 2-9.
As shown in fig. 2, a transistor unit 1000 is provided, the transistor unit 1000 including a transistor (in fig. 2, 101 is a source and a drain of the transistor, 111 is a gate of the transistor), first and second electrical connection layers 113A and 113B electrically insulated from each other, and a circuit protection layer 110, the circuit protection layer 110 covering the transistor, the first and second electrical connection layers 113A and 113B. In fig. 2, 113, 115 are other CMOS intra-layer electrical connection layers, and 112 and 114 are CMOS inter-layer electrical connection layers. It should be noted that the structure shown in fig. 2 is exemplary, and the transistor unit 1000 may include the transistor and circuit protection layer 110, and may optionally include the first electrical connection layer 113A and the second electrical connection layer 113B for the present invention.
As shown in fig. 3, a single crystal piezoelectric film layer 240 is fabricated on a secondary wafer or secondary substrate 400. A layer of other thin film material may be provided between the single crystal piezoelectric film layer or the single crystal piezoelectric layer 240 and the auxiliary substrate 400, such as in a SOI (Silicon On Insulator) wafer, with an insulating layer provided between the single crystal piezoelectric film layer and the auxiliary substrate. As mentioned previously, 240 may also be a polycrystalline piezoelectric layer.
As shown in fig. 4, in the structure shown in fig. 3, a second electrode layer 230, a support layer 220, and a sacrificial material layer 210 are prepared on a single crystal piezoelectric film layer 240. The second electrode layer 230, the support layer 220, and the sacrificial material layer 210 are sequentially disposed on the single crystal piezoelectric film layer 240.
As shown in fig. 5, a support protective material is deposited over the structure shown in fig. 4 and planarized to form a support layer 200.
As shown in fig. 6, the structure shown in fig. 5 and the structure shown in fig. 2 are bonded to each other, for example, by using an additional layer of bonding material (which forms the bonding material layer 300) to bond the support layer 200 and the circuit protection layer 110. As mentioned previously, the supporting layer 200 may also be directly bonded to the circuit protection layer 110. The bonding scheme may take a variety of forms including silicon-silicon bonding, silicon-SiO 2 bonding, metal bonding, and the like.
As shown in fig. 7, the auxiliary substrate 400 is removed to expose the upper side of the single crystal piezoelectric film layer 240.
As shown in fig. 8, a first electrode layer 250 is provided on the upper side of the single crystal piezoelectric film layer 240.
As shown in fig. 9, the first conductive via 500A, the second conductive via 500B, the third conductive via 240A may be formed based on an etching process, and the sacrificial material layer in fig. 8 may be released to form the cavity 201. The first conductive via 500A penetrates the piezoelectric layer 240, the supporting layer 200, and the bonding material layer 300 to reach the first electrical connection layer 113A in the circuit protection layer 110, the second conductive via 500B penetrates the piezoelectric layer 240, the supporting layer 200, and the bonding material layer 300 to reach the second electrical connection layer 113B in the circuit protection layer 110, and the third conductive via 240A penetrates the piezoelectric layer 240 to reach the second electrode layer 230.
Next, as shown in fig. 1, a conductive material is deposited to form a first conductive layer 260A and a second conductive layer 260B. The first conductive layer 260A electrically connects the first electrode layer 250 to the first electrical connection layer 113A through the first conductive via 500A, and the second conductive layer 260B electrically connects the second electrode layer 230 to the second electrical connection layer 113B through the second conductive via 500B and the third conductive via 240A.
The device protection layer 270 may also be provided after the first and second conductive layers 260A and 260B are deposited.
In the embodiments shown in fig. 1-9 above, the fabrication process of the PMUT structure is illustrated in the form of a single PMUT cell with a single transistor cell, but as can be appreciated, the process described above may also be implemented on a wafer level. Specific: providing the transistor cells includes providing a transistor wafer formed with a plurality of transistor cells based on a MEMS process; in the step of providing the piezoelectric layer initial structure, the auxiliary substrate is a PMUT auxiliary wafer, and the single crystal piezoelectric layer is a single crystal piezoelectric film layer; forming a second electrode layer, a sacrificial material layer, and a first electrode layer corresponding to the plurality of PMUT cells based on the MEMS process; after the step of providing the first conductive layer and the second conductive layer electrically insulated from each other, the method further comprises the step of: dicing is performed to form PMUT structures comprising a single PMUT cell and a single CMOS cell.
Based on the manufacturing process shown in fig. 1-9, the present invention proposes a method for manufacturing a PMUT structure comprising cavities for PMUTs, the method comprising the steps of:
providing a transistor unit, wherein one side of the transistor unit comprises a transistor; and
a PMUT unit is arranged to be jointed with the transistor unit, the PMUT unit comprises a PMUT and a supporting layer, the PMUT comprises a first electrode layer, a second electrode layer and a piezoelectric layer, one side and the other side of the piezoelectric layer are respectively provided with the first electrode layer and the second electrode layer,
wherein:
one side of the supporting layer is bonded to one side of the transistor unit, and the other side of the supporting layer includes a flat surface portion bonded to the other side of the piezoelectric layer.
In summary, the present invention proposes an integrated solution of PMUT with single crystal piezoelectric film and conventional transistor wafer and its manufacturing method. In the case that the PMUT piezoelectric film is in a single crystal structure, the invention provides a scheme for transferring the piezoelectric single crystal film with the size equivalent to that of a transistor wafer to the transistor wafer and a manufacturing method of the transistor integrated PMUT based on the scheme, so as to overcome various limitations and difficulties of growing the single crystal piezoelectric film on the transistor wafer.
Fig. 12 is a schematic diagram of a PMUT structure array in accordance with an exemplary embodiment of the invention. As shown in fig. 12, the PMUT structure 3000 described above may be just one element of the array 4000. In fig. 12, the hollow circles represent PMUT vibration regions of the PMUT structure 3000, which may be any desired shape other than circles, including ellipses, polygons, combinations thereof, and the like. The black filled circles represent that the PMUT cells are electrically connected to the CMOS cells, as at the first electrical connection layer 113A and the second electrical connection layer 113B shown in fig. 1, which may also be of any desired shape. The PMUT structures 3000 combine to form a PMUT structure array 4000.
Each PMUT cell 2000 may be individually controlled by a matched CMOS circuit to form a two-dimensional PMUT structure array 4000.
Multiple PMUT structures 3000 may also be connected together, such as electrodes of PMUT structures 3000 on the same column are interconnected to form a one-dimensional line array, where the electrical connection points between the circuits of the CMOS cells and the PMUT cells are reduced, and the electrical connection points between a pair of CMOS cells and the PMUT cells control multiple PMUT cells simultaneously.
The ultrasonic transducer may be formed based on a PMUT structure or an array of PMUT structures, which may be used on an ultrasonic imager, but also on other electronic devices such as ultrasonic range finders, ultrasonic fingerprint sensors, nondestructive inspection instruments for industrial applications, etc.
Based on the above, the invention provides the following technical scheme:
1. a PMUT structure, comprising:
a transistor unit, one side of which includes a transistor; and
a PMUT unit comprising a PMUT and a supporting layer, wherein the PMUT comprises a first electrode layer, a second electrode layer and a piezoelectric layer, one side and the other side of the piezoelectric layer are respectively provided with the first electrode layer and the second electrode layer,
wherein:
the PMUT structure further includes a cavity for a PMUT; and is also provided with
One side of the supporting layer is bonded to one side of the transistor unit, and the other side of the supporting layer includes a flat surface portion bonded to the other side of the piezoelectric layer.
2. The PMUT structure of claim 1, wherein:
the piezoelectric layer is a monocrystalline film layer.
3. The PMUT structure of claim 1, wherein:
the transistor unit includes the transistor, a first electrical connection layer and a second electrical connection layer electrically insulated from each other;
the PMUT structure further includes a first conductive layer and a second conductive layer electrically insulated from each other;
the first electrode layer is electrically connected to the first electrical connection layer via at least the first conductive layer, and the second electrode layer is electrically connected to the second electrical connection layer via at least the second conductive layer.
4. The PMUT structure of claim 3, further comprising:
a first conductive via penetrating the piezoelectric layer, the supporting layer, and the first electrical connection layer reaching the transistor unit, a second conductive via penetrating the piezoelectric layer, the supporting layer, and the second electrical connection layer reaching the transistor unit, and a third conductive via penetrating the piezoelectric layer and reaching the second electrode layer,
wherein:
the first conductive layer electrically connects the first electrode layer to the first electrical connection layer through the first conductive hole, and the second conductive layer electrically connects the second electrode layer to the second electrical connection layer through the second conductive hole and the third conductive hole.
5. The PMUT structure of claim 3, wherein:
the first electrical connection layer is electrically connected to one of the electrodes of the transistor, and the second electrical connection layer is electrically connected to the other one of the electrodes of the transistor.
6. The PMUT structure of claim 1, wherein:
one side of the supporting layer is directly bonded to one side of the transistor cell.
7. The PMUT structure of claim 1, wherein:
one side of the supporting layer is bonded to one side of the transistor cell by an additional layer of bonding material.
8. The PMUT structure of claim 1, wherein:
the cavity is arranged in the supporting layer.
9. The PMUT structure of claim 8, further comprising:
and the supporting layer is arranged in the supporting layer and is contacted with the second electrode layer surface, and the supporting layer defines one side of the cavity far away from the transistor unit.
10. The PMUT structure of claim 8, wherein:
the second electrode layer defines a side of the cavity remote from the transistor cell.
11. The PMUT structure of claim 1, wherein:
the transistor cell includes one of a CMOS cell, a BiMOS cell, and a BCD cell.
12. A method of manufacturing a PMUT structure, the PMUT structure comprising a cavity for a PMUT, the method comprising the steps of:
providing a transistor unit, wherein one side of the transistor unit comprises a transistor; and
a PMUT unit is arranged to be jointed with the transistor unit, the PMUT unit comprises a PMUT and a supporting layer, the PMUT comprises a first electrode layer, a second electrode layer and a piezoelectric layer, one side and the other side of the piezoelectric layer are respectively provided with the first electrode layer and the second electrode layer,
wherein:
one side of the supporting layer is bonded to one side of the transistor unit, and the other side of the supporting layer includes a flat surface portion bonded to the other side of the piezoelectric layer.
13. The method according to claim 12, wherein:
the piezoelectric layer is a monocrystalline film layer.
14. The method according to claim 12, wherein:
the transistor unit includes the transistor, a first electrical connection layer and a second electrical connection layer electrically insulated from each other;
the method further comprises the steps of: the first conductive layer and the second conductive layer are electrically insulated from each other, the first electrode layer is electrically connected with the first electrical connection layer at least through the first conductive layer, and the second electrode layer is electrically connected with the second electrical connection layer at least through the second conductive layer.
15. The method according to claim 14, wherein:
before the step of providing the first conductive layer and the second conductive layer electrically insulated from each other, the method further comprises the step of: forming a first conductive hole, a second conductive hole and a third conductive hole, wherein the first conductive hole penetrates through the piezoelectric layer, the supporting layer and the first electric connection layer in the transistor unit, the second conductive hole penetrates through the piezoelectric layer, the supporting layer and the second electric connection layer in the transistor unit, and the third conductive hole penetrates through the supporting layer and reaches the second electrode layer;
in the step of providing the first conductive layer and the second conductive layer electrically insulated from each other, the first conductive layer electrically connects the first electrode layer and the first electrical connection layer via the first conductive via, and the second conductive layer electrically connects the second electrode layer and the second electrical connection layer via the second conductive via and the third conductive via.
16. The method of claim 12, wherein providing a PMUT cell engaged with a transistor cell comprises the steps of:
providing a piezoelectric layer initial structure, wherein the piezoelectric layer initial structure comprises an auxiliary substrate and a piezoelectric layer;
providing a second electrode layer and a sacrificial material layer, wherein the second electrode layer is arranged on one side of the piezoelectric layer, and the sacrificial material layer is arranged on one side of the second electrode layer;
providing a support layer, covering the piezoelectric layer, the second electrode layer and the sacrificial material layer with a support material, and flattening the support material to form the support layer;
bonding one side of the support layer with one side of the transistor unit;
removing the auxiliary substrate to expose the other side of the supporting layer;
a first electrode layer is arranged on the other side of the supporting layer; and
releasing the layer of sacrificial material to form the cavity.
17. The method according to claim 16, wherein:
providing the transistor cells includes providing a transistor wafer formed with a plurality of transistor cells based on a MEMS process;
in the step of providing the initial structure of the piezoelectric layer, the auxiliary substrate is a PMUT auxiliary wafer, and the piezoelectric layer is a piezoelectric film layer;
forming a second electrode layer, a sacrificial material layer, and a first electrode layer corresponding to the plurality of PMUT cells based on the MEMS process;
after the step of providing the first conductive layer and the second conductive layer electrically insulated from each other, the method further comprises the step of: a cut is performed to form a PMUT structure comprising a single PMUT cell and a single transistor cell.
18. The method of claim 17, wherein:
the piezoelectric layer is a single crystal piezoelectric film layer.
19. The method according to claim 16, wherein:
the piezoelectric layer initial structure is an SOI structure.
20. The method according to claim 16, wherein:
in the step of disposing the second electrode layer and the sacrificial material layer, the second electrode layer is disposed on one side of the piezoelectric layer, the support layer is disposed on one side of the second electrode layer, and the sacrificial material layer is disposed on one side of the support layer.
21. The method of claim 14, further comprising the step of:
and depositing a device protection layer, wherein the device protection layer covers the PMUT, the first conductive layer and the second conductive layer.
22. The method according to claim 14, wherein:
the first electrical connection layer is electrically connected to one of the electrodes of the transistor, and the second electrical connection layer is electrically connected to the other one of the electrodes of the transistor.
23. The method according to claim 12, wherein:
the transistor cell includes one of a CMOS cell, a BiMOS cell, and a BCD cell.
24. A PMUT structure array comprising a plurality of PMUT structures according to any one of claims 1-11, or a plurality of PMUT structures manufactured according to the manufacturing method of any one of claims 12-23.
25. An electronic device comprising a PMUT structure according to any one of claims 1-11, or a PMUT structure manufactured according to the manufacturing method of any one of claims 12-23, or a PMUT structure array according to claim 24.
26. The electronic device of claim 25, wherein:
the electronic device includes at least one of: ultrasonic imaging instrument, ultrasonic range finder, ultrasonic fingerprint sensor, nondestructive inspection instrument, flowmeter, force sense feedback equipment and smoke alarm.
Although embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.
Claims (26)
1. A PMUT structure, comprising:
a transistor unit, one side of which includes a transistor; and
a PMUT unit comprising a PMUT and a supporting layer, wherein the PMUT comprises a first electrode layer, a second electrode layer and a piezoelectric layer, one side and the other side of the piezoelectric layer are respectively provided with the first electrode layer and the second electrode layer,
wherein:
the PMUT structure further includes a cavity for a PMUT; and is also provided with
One side of the supporting layer is bonded to one side of the transistor unit, and the other side of the supporting layer includes a flat surface portion bonded to the other side of the piezoelectric layer.
2. The PMUT structure of claim 1, wherein:
the piezoelectric layer is a monocrystalline film layer.
3. The PMUT structure of claim 1, wherein:
the transistor unit includes the transistor, a first electrical connection layer and a second electrical connection layer electrically insulated from each other;
the PMUT structure further includes a first conductive layer and a second conductive layer electrically insulated from each other;
the first electrode layer is electrically connected to the first electrical connection layer via at least the first conductive layer, and the second electrode layer is electrically connected to the second electrical connection layer via at least the second conductive layer.
4. The PMUT structure of claim 3, further comprising:
a first conductive via penetrating the piezoelectric layer, the supporting layer, and the first electrical connection layer reaching the transistor unit, a second conductive via penetrating the piezoelectric layer, the supporting layer, and the second electrical connection layer reaching the transistor unit, and a third conductive via penetrating the piezoelectric layer and reaching the second electrode layer,
wherein:
the first conductive layer electrically connects the first electrode layer to the first electrical connection layer through the first conductive hole, and the second conductive layer electrically connects the second electrode layer to the second electrical connection layer through the second conductive hole and the third conductive hole.
5. The PMUT structure of claim 3, wherein:
the first electrical connection layer is electrically connected to one of the electrodes of the transistor, and the second electrical connection layer is electrically connected to the other one of the electrodes of the transistor.
6. The PMUT structure of claim 1, wherein:
one side of the supporting layer is directly bonded to one side of the transistor cell.
7. The PMUT structure of claim 1, wherein:
one side of the supporting layer is bonded to one side of the transistor cell by an additional layer of bonding material.
8. The PMUT structure of claim 1, wherein:
the cavity is arranged in the supporting layer.
9. The PMUT structure of claim 8, further comprising:
and the supporting layer is arranged in the supporting layer and is contacted with the second electrode layer surface, and the supporting layer defines one side of the cavity far away from the transistor unit.
10. The PMUT structure of claim 8, wherein:
the second electrode layer defines a side of the cavity remote from the transistor cell.
11. The PMUT structure of claim 1, wherein:
the transistor cell includes one of a CMOS cell, a BiMOS cell, and a BCD cell.
12. A method of manufacturing a PMUT structure, the PMUT structure comprising a cavity for a PMUT, the method comprising the steps of:
providing a transistor unit, wherein one side of the transistor unit comprises a transistor; and
a PMUT unit is arranged to be jointed with the transistor unit, the PMUT unit comprises a PMUT and a supporting layer, the PMUT comprises a first electrode layer, a second electrode layer and a piezoelectric layer, one side and the other side of the piezoelectric layer are respectively provided with the first electrode layer and the second electrode layer,
wherein:
one side of the supporting layer is bonded to one side of the transistor unit, and the other side of the supporting layer includes a flat surface portion bonded to the other side of the piezoelectric layer.
13. The method according to claim 12, wherein:
the piezoelectric layer is a monocrystalline film layer.
14. The method according to claim 12, wherein:
the transistor unit includes the transistor, a first electrical connection layer and a second electrical connection layer electrically insulated from each other;
the method further comprises the steps of: the first conductive layer and the second conductive layer are electrically insulated from each other, the first electrode layer is electrically connected with the first electrical connection layer at least through the first conductive layer, and the second electrode layer is electrically connected with the second electrical connection layer at least through the second conductive layer.
15. The method according to claim 14, wherein:
before the step of providing the first conductive layer and the second conductive layer electrically insulated from each other, the method further comprises the step of: forming a first conductive hole, a second conductive hole and a third conductive hole, wherein the first conductive hole penetrates through the piezoelectric layer, the supporting layer and the first electric connection layer in the transistor unit, the second conductive hole penetrates through the piezoelectric layer, the supporting layer and the second electric connection layer in the transistor unit, and the third conductive hole penetrates through the supporting layer and reaches the second electrode layer;
in the step of providing the first conductive layer and the second conductive layer electrically insulated from each other, the first conductive layer electrically connects the first electrode layer and the first electrical connection layer via the first conductive via, and the second conductive layer electrically connects the second electrode layer and the second electrical connection layer via the second conductive via and the third conductive via.
16. The method of claim 12, wherein providing a PMUT cell engaged with a transistor cell comprises the steps of:
providing a piezoelectric layer initial structure, wherein the piezoelectric layer initial structure comprises an auxiliary substrate and a piezoelectric layer;
providing a second electrode layer and a sacrificial material layer, wherein the second electrode layer is arranged on one side of the piezoelectric layer, and the sacrificial material layer is arranged on one side of the second electrode layer;
providing a support layer, covering the piezoelectric layer, the second electrode layer and the sacrificial material layer with a support material, and flattening the support material to form the support layer;
bonding one side of the support layer with one side of the transistor unit;
removing the auxiliary substrate to expose the other side of the supporting layer;
a first electrode layer is arranged on the other side of the supporting layer; and
releasing the layer of sacrificial material to form the cavity.
17. The method according to claim 16, wherein:
providing the transistor cells includes providing a transistor wafer formed with a plurality of transistor cells based on a MEMS process;
in the step of providing the initial structure of the piezoelectric layer, the auxiliary substrate is a PMUT auxiliary wafer, and the piezoelectric layer is a piezoelectric film layer;
forming a second electrode layer, a sacrificial material layer, and a first electrode layer corresponding to the plurality of PMUT cells based on the MEMS process;
after the step of providing the first conductive layer and the second conductive layer electrically insulated from each other, the method further comprises the step of: a cut is performed to form a PMUT structure comprising a single PMUT cell and a single transistor cell.
18. The method according to claim 17, wherein:
the piezoelectric layer is a single crystal piezoelectric film layer.
19. The method according to claim 16, wherein:
the piezoelectric layer initial structure is an SOI structure.
20. The method according to claim 16, wherein:
in the step of disposing the second electrode layer and the sacrificial material layer, the second electrode layer is disposed on one side of the piezoelectric layer, the support layer is disposed on one side of the second electrode layer, and the sacrificial material layer is disposed on one side of the support layer.
21. The method of claim 14, further comprising the step of:
and depositing a device protection layer, wherein the device protection layer covers the PMUT, the first conductive layer and the second conductive layer.
22. The method according to claim 14, wherein:
the first electrical connection layer is electrically connected to one of the electrodes of the transistor, and the second electrical connection layer is electrically connected to the other one of the electrodes of the transistor.
23. The method according to claim 12, wherein:
the transistor cell includes one of a CMOS cell, a BiMOS cell, and a BCD cell.
24. A PMUT structure array comprising a plurality of PMUT structures according to any one of claims 1-11, or a plurality of PMUT structures manufactured according to the manufacturing method of any one of claims 12-23.
25. An electronic device comprising a PMUT structure according to any one of claims 1-11, or a PMUT structure manufactured according to the manufacturing method of any one of claims 12-23, or a PMUT structure array according to claim 24.
26. The electronic device of claim 25, wherein:
the electronic device includes at least one of: ultrasonic imaging instrument, ultrasonic range finder, ultrasonic fingerprint sensor, nondestructive inspection instrument, flowmeter, force sense feedback equipment and smoke alarm.
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| PCT/CN2023/110643 WO2024027729A1 (en) | 2022-08-05 | 2023-08-02 | Pmut structure having support layer, and manufacturing method therefor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9096422B2 (en) * | 2013-02-15 | 2015-08-04 | Fujifilm Dimatix, Inc. | Piezoelectric array employing integrated MEMS switches |
| EP4071589A1 (en) * | 2013-12-12 | 2022-10-12 | QUALCOMM Incorporated | Micromechanical ultrasonic transducers and display |
| US10497748B2 (en) * | 2015-10-14 | 2019-12-03 | Qualcomm Incorporated | Integrated piezoelectric micromechanical ultrasonic transducer pixel and array |
| US10562070B2 (en) * | 2016-05-10 | 2020-02-18 | Invensense, Inc. | Receive operation of an ultrasonic sensor |
| CN113497593B (en) * | 2020-04-08 | 2023-05-12 | 诺思(天津)微***有限责任公司 | Single crystal acoustic resonator, filter and electronic device |
-
2022
- 2022-08-05 CN CN202210959224.XA patent/CN117548318A/en active Pending
-
2023
- 2023-08-02 WO PCT/CN2023/110643 patent/WO2024027729A1/en unknown
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| Publication number | Publication date |
|---|---|
| WO2024027729A1 (en) | 2024-02-08 |
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