CN117546072A

CN117546072A - MEMS device and design and fabrication of micromirrors with reduced moment of inertia

Info

Publication number: CN117546072A
Application number: CN202280044483.8A
Authority: CN
Inventors: 斯科特·A·米勒
Original assignee: Kaliant Technology Co
Current assignee: Kaliant Technology Co
Priority date: 2021-06-22
Filing date: 2022-06-20
Publication date: 2024-02-09

Abstract

Methods, apparatus and methods of manufacture are described that provide for: one or more stationary blades mounted to the frame or substrate, one or more movable blades mounted to each structure to be moved, and a flexure on which the structures are suspended and which reduces moment of inertia during use.

Description

MEMS device and design and fabrication of micromirrors with reduced moment of inertia

RELATED APPLICATIONS

The present application claims priority from U.S. patent application Ser. No. 17/807,441, filed on 6/17, 2022, which claims the benefit of U.S. provisional application Ser. No. 63/213,489, entitled "design and fabrication of micromirrors with reduced moment of inertia," filed on 22, 6/2021, the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to the design and manufacture of micromirrors with reduced moment of inertia.

Background

MEMS (microelectromechanical systems) devices are micro-scale mechanical structures with electrical circuits and are fabricated using various Integrated Circuit (IC) fabrication methods. One type of MEMS device is a micro-gimbal device. The gimbal mirror device includes a mirror member suspended from a substrate and pivotable about a gimbal due to electrostatic actuation. The electrostatic actuation generates an electric field, thereby pivoting the mirror element. By allowing the mirror part to pivot, the mirror part can have a range of angles of movement in which the mirror part can redirect the light beam to different positions.

An optical switch is a switching device that couples a light beam from an input optical fiber to an output optical fiber. Typically, the beam from the input fiber is collimated and directed to a desired location (such as the output fiber). A movable mirror (e.g., a gimbal mirror) in the switched mirror array redirects the light beam to a desired location. The maximum device switching speed is limited mainly by the resonant frequency at which the mirror element oscillates. The natural resonant frequency (f _o ) Obtained by the following formula:where k is torsional stiffness and I is moment of inertia about the axis of rotation. What is needed is a MEMS mirror array and method of manufacturing the array that reduces the moment of inertia of the mirrors in the array to increase the resonant frequency of the mirrors and increase the maximum device switching speed.

Disclosure of Invention

One aspect of the present disclosure provides a method of manufacturing a micromirror. The method includes forming a first photoresist layer on a first silicon-on-insulator (SOI) substrate. A first silicon-on-insulator (first Silicon On Insulator) (SOI) substrate includes a first silicon layer, a second silicon layer, and a first oxide layer between the first silicon layer and the second silicon layer. The method further includes forming a honeycomb recess pattern by etching the first photoresist layer and the second silicon layer. The method includes removing the first photoresist layer and disposing a second silicon-on-insulator (SOI) substrate on the first SOI substrate. A second silicon-on-insulator (SOI) substrate includes a third silicon layer, a fourth silicon layer, and a second oxide layer positioned between the third silicon layer and the fourth silicon layer. The method further includes removing the second oxide layer and the fourth silicon layer.

Another aspect of the present disclosure provides a movable mirror. The movable mirror includes: a fixed frame comprising a cavity; a movable frame disposed in the cavity; and a center stage disposed in the cavity. The center stage includes a plurality of recessed areas.

Implementations of the disclosure may include one or more of the following optional features. The movable mirror may comprise a mirror located on a central stage (e.g., on the opposite side of the surface having the recessed region). In addition, the recessed areas may form a honeycomb pattern on the surface of the center stage. The plurality of recessed regions may have a variety of shapes including, but not limited to, at least one of a circular recessed region, an elliptical recessed region, a rectangular recessed region, a parallelogram recessed region, a triangular recessed region, and a hexagonal recessed region. The movable mirror may also comprise a plurality of blades, i.e. a plurality of blades with a first blade and a second blade. The first blade may also overlap a center stage that includes a plurality of recessed regions. The movable mirror may further comprise a mirror cavity between the first blade and the second blade. A cover substrate and a base substrate may also be included in the movable mirror, the cover substrate and the base substrate including a plurality of recessed areas. The plurality of recessed areas may also overlap the mirror.

Incorporated by reference

All publications, patents, and patent applications mentioned in this specification are herein incorporated by reference to the same extent as if each individual publication, patent, or patent application was specifically and individually indicated to be incorporated by reference.

U.S. Pat. No. 5,501,893A, 1993, 26 to Laermer et al;

U.S. Pat. No. 6,538,799 B2, 3.25.2003 to McClelland et al;

U.S. Pat. No. 6,704,132 B2, 3/9/2004 to Dewa;

U.S. Pat. No. 6,903,860 B2, 6/7 2005 to Ishii;

US 6,912,078 B2, 6.28.2005 to kudrae et al;

U.S. Pat. No. 7,057,784 B2, 6/2006 to Miyajima et al;

US 7,261,826 B2, 8 months of 2007 to Adams et al;

US 7,403,338 B2, granted to Wu et al at month 7, 22 of 2008;

US 7,567,367 B2, 7/28 of 2009 granted Ji;

US 7,782,514 B2, 8 months 2010, 24 grants moisu;

US 8,345,336 B2, 1 st 2013 to Krastev et al;

US 8,636,911 B2, month 1, 28 of 2014 to Chen et al;

US 8,691,099 B2, 4/2014/8 to Gritters et al;

US 8,873,128 B2, 10 month 28 of 2014 to Conrad et al;

US 9,036,231 B2, granted to Zhou at 5, month 19 of 2015;

US 9,086,571 B2, 21 st 2015 to Zhou;

US2005/0139542 Al, published by Dickensheets et al, 6.30.2005;

US2007/0053044 Al, published by Kawakami et al at month 3 and 8 of 2007;

MARXER et al, "vertical mirror fabricated by deep reactive ion etching for fiber switching applications" (Vertical mirrors fabricated by deep reactive ion etching for fiber-optic switching applications), J.MEMS Systems,6 (3), 277-285 (1997); and

HALL et al, J.Micro/Nanolith MEMS MOEMS15 (4): 145501 (2016): pattern of mass reduction of silicon-based micro-mirrors on silicon oxide (Mass reduction patterning of silicon-on-oxide-base micromirrors).

Drawings

The novel features of the invention are set forth with particularity in the appended claims. A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description that sets forth illustrative embodiments, in which the principles of the invention are utilized, the accompanying drawings of which:

FIG. 1 illustrates a portion of a prior art mirror array;

FIG. 2 illustrates a cross-section of the prior art mirror array of FIG. 1 taken along line 2-2;

FIG. 3 illustrates an exemplary single mirror from a mirror array;

FIGS. 4A-4D illustrate various configurations for MEMS having recessed regions operable to reduce moment of inertia;

FIGS. 5A through 5R illustrate process steps for fabricating a micromirror with honeycomb grooves;

FIG. 6 illustrates an SOI wafer having a cavity; and

fig. 7 shows an optical (circuit) switch implemented with a mirror array.

Detailed Description

MEMS mirror arrays and methods of making such arrays are disclosed, the MEMS mirror arrays providing reduced micromirror moments of inertia for MEMS to achieve higher resonant frequencies. The higher resonant frequency creates a smaller coupling with ambient vibrations, such as accelerations from shock, seismic or other vibration sources. Furthermore, the higher resonant frequency reduces the requirement to isolate the MEMS-containing system from vibrations. Furthermore, a faster switching speed is possible when the mirror is used for an optical switch. All of these results can be achieved by integrating the honeycomb pattern into the backside of the mirror during the manufacturing process.

Fig. 1 shows a top-level view of a portion of a prior art MEMS mirror array 100. The MEMS mirror array 100 has a metal layer 110, a mirror cavity 112, and a support 120.

As will be appreciated by those skilled in the art, the MEMS array 100 has multiple stages of actuators. Each actuator in the array includes a center stage, a movable frame, and a fixed frame. The fixed frame may form a cavity within which the center stage and the movable frame are disposed. A reflective element (e.g., mirror) may be coupled to the center stage and suspended from the movable frame by a first center stage flexure and a second center stage flexure. The reflective element may be used to redirect the light beam along a light path different from the light path of the received light beam. The actuator comprising a mirror on the central carrier is also called mirror unit or MEM actuator with a mirror.

The rotation of the center stage may be independent of the rotation of the movable frame. Thus, the actuator may allow for an uncoupling movement. For example, the center stage may rotate relative to the fixed frame while the movable frame remains parallel and stationary relative to the fixed frame. Further, the movable frame may rotate relative to the fixed frame while the center stage remains parallel (and stationary) relative to the movable frame. The movable frame engages the fixed frame via the first fixed frame bend and the second fixed frame bend. Furthermore, the center stage and the movable frame may be rotated, for example, simultaneously, but independently of each other. Thus, for example, the center stage, the movable frame, and the fixed frame may be non-parallel at the same time and decoupled from one another during actuation.

The first and second center stage flexures are coupled to the movable frame via first and second end bars. The first and second end bars are in turn attached to the body of the movable frame with a plurality of support members. The support members are silica beams that provide tension. The support member provides tension by expanding an amount different from the material system used in the movable frame, center stage, first end bar, second end bar, and fixed frame. A system of differently expanded materials may be placed into the moveable frame to place the first and second central flexures in tension. In particular, the expansion provided by the connecting members acting on the movable frame and the first and second end bars creates a tension force on each pair of the center stage bending portion and the fixed frame bending portion. The support member is used to apply a tensioning force in order to minimize the possibility of positional deformation due to buckling of the flexure under compressive force. In general, if any of the bends is subjected to excessive compressive forces, the bends may buckle. In this way, the support member may be coupled between the body of the moveable frame and the first and second end bars at a non-perpendicular angle so as to pull the center stage bend to place the center stage bend in tension. Because the fixed frame bend is perpendicular to the center stage bend, the non-perpendicular attachment angle of the support members causes a pulling force on the movable frame body and thus a pulling and tensioning of the fixed frame bend.

The support member may be coupled between the bodies of the movable frames, and the first and second end bars may be positioned at an angle of about 45 degrees. Alternatively, the support member may be coupled between the body of the movable frame and the first and second end bars at an angle less than or greater than 45 degrees.

The center stage flexure allows the center stage to pivot. The center stage curvature also provides some torsional resistance proportional to the angle of rotation, but much less resistance than all other directions. In other words, there is a great resistance to undesired twisting movements of the center stage in other directions (e.g., left-right or about an axis perpendicular to the surface of the center stage). In addition, the center stage curvature extends into a corresponding slot formed in the center stage to provide the curvature with sufficient length to achieve proper flexibility and torsion resistance. The center stage bend may have a length of about 100 microns, a height of about 10 microns, and a width of about 1 micron, resulting in an aspect ratio of 10:1. Such an aspect ratio may provide greater compliance in the desired direction of motion and greater stiffness in the undesired direction. In alternative implementations, other lengths, heights, widths, and aspect ratios may be used.

Similarly, the fixed frame curvature enables the movable frame to pivot while providing resistance to undesired twisting movement of the movable frame in other directions (e.g., side-to-side, or about an axis perpendicular to the movable frame surface). The fixed frame bends extend into the slots and a corresponding slot is formed into the movable and fixed frames to provide the bends with sufficient length to achieve proper flexibility and torsion resistance.

One or more of the center stage flexure and the fixed frame flexure may include a pair of torsion beams. The use of multiple torsion beams may provide increased resistance to undesired twisting movement of the frame or carrier compared to a single beam bend. The pair of torsion beams may have different configurations. The torsion beam may be a non-parallel beam having ends adjacent the movable frame that are substantially parallel and spaced apart by a gap. The gap between the torsion beams decreases along the length of the beams such that the ends of the beams near the fixed frame are closer than the ends of the beams near the movable frame. The angular adjustment of the torsion beams relative to each other may help the flexure resist unstable torsional modes. In alternative implementations, the torsion beam may be configured such that the ends of the torsion beam near the fixed frame are spaced farther apart than the ends of the torsion beam near the movable frame. In yet another implementation, the torsion beams may be substantially parallel to each other such that the gap is substantially uniform along the length of the beam.

Fig. 2 illustrates a partial cross-section of a prior art MEMS mirror array 100 having a top side 10 and a bottom side 20, taken along line 2-2 in fig. 1, wherein each layer within the MEMS mirror array 100 has a layer top surface oriented toward the top side 10 and a bottom surface oriented toward the bottom side 20. The array has a base wafer 210 and a lid wafer 250. The base wafer 210 has first bonding elements 212, 212' at either end of the base wafer layer, which bond the base wafer 210 to the device wafer 220. The bonding elements 212, 212' may provide an airtight seal when bonded. The second bonding elements 222, 222' bond the device wafer 220 to the cap wafer 250.

The structure release is accomplished on the upper surface (topside 10) of the cap wafer 250 using a dry etch that penetrates the plurality of structure trenches 226 to suspend the movable elements of the mirror 224 and frame 230. Furthermore, the release etch promotes electrical isolation by, for example, separating the silicon of the frame 230 from the silicon of the surrounding members 238, 238'. The via 225 is used to connect a region of silicon to the metal interconnect 240. In order to completely seal the mirror from the external environment, the cap wafer 250 is bonded to the device wafer 220 by means of a second bonding element 222, 222', for example as a frit seal. The cap wafer 250 is typically glass to allow incident light to be transmitted into the mirror cavity 232 with low loss, reflected from the upper surface of the mirror 236, and transmitted out of the mirror cavity. The isolation trench 228 is filled with a dielectric material such as silicon dioxide. After mirror release, the isolation trenches 228 provide electrical isolation between the blades once filled.

Fig. 3 illustrates a layout of a single mirror configured with an actuator 300 according to some embodiments of the present disclosure. As shown in fig. 3, in some embodiments, the actuator 300 uses a single movable blade (e.g., first side blade 322) and two corresponding stationary blades (e.g., first side wing blades 324, 324') as the actuating mechanism structure to effect rotation. As illustrated, in some implementations, actuator 300 uses two such actuation mechanism structures per stage and two such actuation mechanism structures per frame. Thus, a plurality of blades are provided.

In some implementations, the first blade 312 is coupled to the carrier 302 and flanked on both sides by a pair of first side wing blades 314, 314' coupled to the movable frame 304 on opposite ends of the first blade 312. As shown, the carrier 302 is pivotally coupled to the movable frame 304 such that the first blade 312 is configured to move relative to the first wing blades 314, 314'. When a potential difference is applied between the first blade 312 and one of the first wing blades 314, 314', an attractive force is created between the two blades, thereby pivoting the carrier 302. For example, the first blade 312 may be maintained at ground potential when an active voltage is applied to either of the first side wing blades 314, 314'. For example, application of an active voltage to the first wing blade 314 will attract the first blade 312, thereby rotating the carrier 302 in a corresponding direction. Similarly, application of an active voltage to first side blade 314' will attract first blade 312 and rotate carrier 302 in a direction opposite to that generated by the attraction of first side blade 314.

A second blade 316 may also be coupled to an end of the carrier 302 opposite the position of the first blade 312, with a pair of second wing blades 318, 318' coupled to the movable frame 304 on opposite ends of the second blade 316. The second blade 316 moves relative to the second flanking blades 318, 318'. To provide the desired movement of the carrier 302 and resist undesired rotation, an actuation voltage is applied to both the first blade 312 and the second blade 316. When a potential difference is applied between the second blade 316 and one of the second flanking blades 318, 318', an attractive force is created between the two blades, causing the carrier 302 to rotate in a manner similar to that discussed above with respect to the first blade 312. The use of an in-line actuation mechanism on each end of the stage 302 reduces or minimizes unwanted twisting of the stage 302 to provide more uniform rotation.

A similar actuation mechanism structure may be used to rotate the movable frame 304. The first side blade 322 may also be coupled to the movable frame 304, and the first side wing blades 324, 324' are coupled to the fixed frame 340 on opposite ends of the first side blade 322.

The movable frame 304 is pivotally coupled to the fixed frame 340 such that the first side blade 322 is configured to move relative to the first side wing blades 324, 324'. When a potential difference is applied between the first side blade 322 and one of the first side wing blades 324, 324', an attractive force is created between the two blades, causing the movable frame 304 to pivot in a manner similar to that discussed above with respect to the carrier 302.

Second side blades 326 are coupled to opposite ends of the movable frame 304, and second side blades 328, 328' are coupled to the fixed frame 340 on opposite ends of the second side blades 326. The second side blade 326 moves relative to the second side blade 328, 328'. When a potential difference is applied between the second side blade 326 and one of the second side wing blades 328, 328', an attractive force is created between the blades, thereby facilitating rotation of the movable frame 304. The use of a series of actuation mechanisms on each end of the movable frame 304 reduces or minimizes undesirable twisting of the frame to provide more uniform rotation.

Alternatively, the carrier 302 or frame may have an actuation mechanism structure on only a single end. For another implementation, the actuator 300 may have other actuation mechanism structures without departing from the scope of the present disclosure.

Fig. 4A-4D illustrate the configuration of recessed areas 410 or a honeycomb comprising recessed areas and non-recessed areas. As will be appreciated by those of skill in the art, the patterns presented are representative and other patterns may be employed without departing from the scope of the present disclosure. The recessed region 410 in fig. 4A has four separate sections that have a circular or oval shape in two dimensions, with each section being a quarter of a two-dimensional shape according to some implementations of the present disclosure. The recessed areas are shown as one quarter of a circle or oval, while the non-recessed areas are shown as an X-shape transverse to the recessed areas. As shown, the non-recessed regions may be symmetrical or substantially symmetrical.

Turning to fig. 4B, in some implementations, the recessed areas 410 further divide the quarter section in fig. 4A into subsections with additional dividers 412 between the recessed areas. The additional spacers 412 create non-recessed regions having a concentric pattern, such as concentric circles, recessed into the non-recessed regions. In fig. 4C, in some implementations, additional breaks are provided that provide a partition 414 between the recessed region and the square non-recessed region. In fig. 4D, in some implementations, additional hexagonal breaks are provided that provide a divider 416 between the recessed region and the non-recessed region, which may be circular or elliptical. Other shapes such as rectangular, parallelogram, triangle, etc. may be used without departing from the scope of the present disclosure. The number of recessed areas may range from, for example, two or more, three or more, four or more, six or more, eight or more to two hundred or more.

Fig. 5A-5R illustrate process steps for fabricating a micromirror having the recessed or honeycomb regions shown in fig. 4A-4D, as well as other recessed patterns within the scope of the present disclosure. As shown in fig. 5A, the process starts with a silicon-on-insulator (SOI) wafer 510 (hereinafter also referred to as a "first silicon wafer" or "first substrate"). As shown in fig. 5A, in some implementations, the first silicon wafer 510 includes a top silicon layer 514 between 10 and 35 μm thick and a bottom silicon layer between 250 and 500 μm thick. As shown in fig. 5A, in some implementations, the substrate includes a buried oxide layer (buried oxide layer) 522 disposed between the top silicon layer 514 and the bottom silicon layer 512 and having a thickness between 0.5 μm and 2.0 μm.

Fig. 5A illustrates a cross-section of a first silicon wafer 510 selected to be in the thickness range of 300 to 600 micrometers (μm) according to some implementations of the present disclosure. The first silicon wafer 510 has a top side 10 (or device side or simply top) and a back or bottom side 20 and forms multiple layers. Each layer within the MEMS mirror array is formed from a first silicon wafer 510 having a top surface oriented toward the top side 10 and a bottom surface oriented toward the bottom side 20. As discussed above, in some implementations, the first silicon wafer 510 includes: a top silicon layer 514 having a thickness between 10 μm and 35 μm; a bottom silicon layer 512 having a thickness between 250 μm and 500 μm; the buried oxide layer 522 is disposed between the top silicon layer 514 and the bottom silicon layer 512 and has a thickness between 0.5 μm and 2.0 μm.

Fig. 5B illustrates a photoresist layer 516 disposed on a top surface of a first silicon wafer 510 in a MEMS mirror array in accordance with some implementations of the disclosure. As shown in fig. 5C, in some implementations, the photoresist layer 516 is patterned using photolithography. In some implementations, the etched pattern in fig. 5C is further etched using a suitable etching technique (e.g., deep reactive ion etching) to achieve the pattern shown in fig. 5D. As shown in fig. 5D, etching stops on buried oxide layer 522. This etching back creates recessed areas 410 (e.g., multiple recessed areas) of the honeycomb pattern as shown in fig. 4A-4D. The pattern of etched portions of the top silicon layer 514 (i.e., the recessed regions 410) may have various shapes including elliptical recessed regions, rectangular recessed regions, parallelogram recessed regions, triangular recessed regions, or hexagonal recessed regions. The photoresist layer 516 is then stripped or removed as shown in fig. 5E.

Fig. 5F illustrates a second silicon-on-insulator (SOI) wafer 550 (hereinafter "second silicon wafer" or "second substrate") disposed on the first silicon wafer 510 in fig. 5E according to some implementations of the present disclosure. In some implementations, similar to the first silicon wafer 510, the second silicon wafer 550 includes: a second top silicon layer 584 having a thickness between 5 μm and 35 μm; a second bottom silicon layer 582 having a thickness between 250 μm and 500 μm; a second buried oxide layer 552 is disposed between the second top silicon layer 584 and the second bottom silicon layer 582 and has a thickness between 0.5 μm and 2.0 μm. As shown in fig. 5F, the second top silicon layer 584 of the second silicon die 550 is closest to the upper surface of the first silicon die 510. In some implementations, as shown in fig. 5F, a silicon-silicon bond is formed between the top surface of the first silicon wafer 510 and the top surface of the second silicon wafer 550 that is flipped to face the top surface of the first silicon wafer 510. As a result, the top silicon layer 514 includes a second top silicon layer 584.

In some implementations, as shown in fig. 5G, the second bottom silicon layer 582 and the second buried oxide layer 552 of the second silicon wafer 550 are removed through a series of grinding, polishing, and etching steps.

The fabrication of the mirror follows the steps outlined in fig. 5H to 5R.

Fig. 5I-5L illustrate the upper left portion 502 shown in fig. 5H of the first silicon wafer 510 in the MEMS mirror array 100, which illustrates techniques for fabricating isolation trenches 520 on the top side 10 of the first silicon wafer 510 in accordance with some implementations of the present disclosure. The isolation trenches 520 are filled with a dielectric material (e.g., silicon dioxide). Once filled with dielectric material, the isolation trenches 520 provide electrical isolation between the blades after mirror release. The dielectric layer 518 also remains on the surface of the first silicon wafer 510 and is planarized after the isolation trench fill process to simplify subsequent photolithographic patterning and eliminate surface discontinuities.

Referring to fig. 5I, a first silicon wafer 510 is provided with a dielectric layer 518 according to some implementations of the present disclosure. Dielectric layer 518 may be silicon dioxide (e.g., an oxide layer). The first silicon wafer 510 may have any doping, resistivity, and crystal orientation, as the process relies solely on reactive ion etching to engrave and form the structure. In this embodiment, the dielectric layer 518 serves to protect the upper surface of the first silicon wafer 510 during the isolation trench etching process, and thus represents a masking layer. The masking layer may be formed by any number of techniques, including thermal oxidation of silicon or Chemical Vapor Deposition (CVD). In some implementations, the thickness of the dielectric layer 518 is between 0.5 μm and l μm. In some implementations, the photoresist is then etched, as shown in FIG. 5I Layer 516 is spun onto first silicon wafer 510 and the photoresist layer is exposed and developed using standard photolithographic techniques to define the isolation trench pattern of isolation trenches 520. In some implementations, reactive ion etching is used to transfer the photoresist pattern to the dielectric layer 518, exposing the top surface of the top silicon layer 514 of the first silicon wafer 510. Typically, the silicon dioxide mask is in a freon gas mixture (e.g., CHF ₃ Or CF (CF) ₄ ) Is etched. High etch rates for silicon dioxide etching are achieved using high density plasma reactors such as inductively coupled plasma ("ICP") chambers. These ICP chambers use a high power RF source to sustain a high density plasma and a low power RF bias on the wafer to achieve high etch rates at low ion energies. For such hardware configurations, it is common for the oxide etch rate of 200nm/min and the selectivity to photoresist to be greater than 1:1.

As shown in fig. 5J, in some implementations, isolation trenches 520 are formed in the first silicon wafer 510 by deep reactive ion etching of silicon using a high etch rate, high selectivity etch. As described in U.S. Pat. No. 5,501,893, sulfur hexafluoride (SF) is typically used for the trenches ₆ ) The gas mixture is etched in a high density plasma. Preferably, the etching is controlled such that the profile of the isolation trench 520 is concave or tapered and the top 524 of the isolation trench 520 is narrower than the bottom 519 of the isolation trench 520. The tapering of the isolation trenches 520 ensures that good electrical isolation is achieved in subsequent processing. In reactive ion etching, profile tapering can be achieved by adjusting the degree of passivation, or by varying parameters of the discharge (e.g., power, gas flow, pressure) during the etching process. In some implementations, because the isolation trenches 520 are filled with a dielectric material, the opening width at the top 524 of the isolation trenches 520 is typically less than 2 μm. In some implementations, the depth of the isolation trenches 520 is typically in a range between 10 μm and 50 μm. In some implementations, the process for etching the isolation trenches 520 is to alternate etching Steps (SF) in ICP plasma ₆ And argon mixture) and passivation steps (freon and argon) to photoresist @>50:1) and oxide%>100:1) high selectionAn etch rate exceeding 2 μm/min is selectively achieved. As the trench deepens, the power and time of the etching cycle increases to achieve a tapered profile. Although the trench geometry is preferably re-entrant, any trench profile can be accommodated by adjustments in the microstructured processing. Good isolation results can be obtained with any of a number of known trench etch chemistries. After etching the silicon trenches, in some implementations, the photoresist layer 516 is removed using wet chemical or dry ashing techniques, and the dielectric layer 518 is removed using reactive ion etching ("RIE") or buffered hydrofluoric acid.

Referring to fig. 5K, the isolation trenches 520 are then filled with an insulating dielectric material, typically silicon dioxide, according to some implementations of the present disclosure. The filling process causes a majority of the solid isolation segments in the isolation trenches 520 and serves to deposit a layer of dielectric material on the top side 10 (upper surface) of the silicon wafer 510 and a layer of dielectric on the sidewalls 528 and bottom 519 of the isolation trenches 520. The thickness of the deposited layer is typically in excess of l μm. Such filling may be accomplished using chemical vapor deposition ("CVD") techniques or preferably using silicon oxidation at elevated temperatures. In thermal oxidation, the wafer is exposed to an oxygen-rich environment at a temperature between 900 ℃ and 1150 ℃. This oxidation process consumes the silicon surface to form silicon dioxide. The volumetric expansion resulting from this process erodes the sidewalls of the trench from one another, eventually closing the trench opening. In CVD filling some dielectric is deposited on the walls, but filling also occurs due to deposition on the trench bottom. CVD dielectric fill of trenches has been demonstrated using TEOS or silane mixtures in plasma enhanced CVD chambers and low pressure CVD furnace tubes.

During the isolation trench 520 filling process, most of the isolation trench profile is typically not completely filled, such that an interface 532 and void 530 are formed in the isolation trench 520. The localized stress concentrations in the void 530 can cause electrical and mechanical failure of some devices, but this is generally not important for micromechanical devices due to the closed geometry of the isolation trench 520. By shaping the isolation trench 520 to be wider at the isolation trench opening at the top of the isolation trench 520 than at the bottom 519 of the isolation trench 520, the interface 532 and void 530 may be eliminated. However, good electrical isolation will require additional tapering of the microstructured trench etch in later steps. Another drawback of the isolation trench filling process is the imprint 526 created in the surface of the dielectric layer 538 centered over the isolation trench 520. Such indentations are unavoidable in most trench filling processes and can be as deep as 0.5 μm, depending on the thickness of the deposit. To remove the indentations 526, in some implementations, the surface is planarized to form a planar or substantially planar surface, as shown in fig. 5L, for subsequent photolithography and deposition steps. Planarization is performed using Chemical Mechanical Polishing (CMP). Planarization may also be performed by depositing an adhesive material (which may be photoresist, spin-on glass, or polyimide) and flowing the material to fill the indentations 526 to a smooth finish. During the etch back, which is the second step of planarization, the surface is uniformly etched, including filled indentations. Thus, by removing portions of the surface oxide layer, the indentations 526 are removed to create a layer of uniform thickness. For example, if the original dielectric layer 538 is 2 μm, the planarization of the removal indentation 526 leaves a dielectric layer 538 with a final thickness of less than l μm. The top side 10 (upper) surface of the first silicon wafer 510 is free of defects and ready for further lithography and deposition.

Fig. 5M shows a first silicon wafer 510 having the dielectric layer 538 and isolation trenches 520 described above. After the isolation trenches 520 are fabricated, the mask layer is lithographically patterned using standard front-to-back alignment for forming the blades on the bottom side 20 (backside) of the first silicon wafer 510, according to some implementations of the present disclosure. The blade pattern 572 is exposed and etched into the dielectric layer 539. Dielectric layer 539 is typically a masking layer composed of a combination of thermally grown silicon oxide and oxide deposited by chemical vapor deposition. The lithographic pattern is transferred in the mask layer by reactive ion etching, however the silicon blade etching is not completed until a later stage of the process. Without the etching blade, the wafer is easily processed through the remaining device layers. The backside of the blade pattern 572 is generally aligned to within a few microns of the topside isolation trench 520.

Then, according to some implementations of the present disclosure, metallization is performed on the top side 10 of the first silicon wafer 510, as shown in fig. 5N. To contact the underlying first silicon wafer 510, the vias 552 are patterned and etched into the dielectric layer 518 using standard photolithography and reactive ion etching. After the vias 552 are etched, metal is deposited to form the metal layer 540 and patterned to form interconnects 556 and contacts 554 to the first silicon wafer 510 through the vias 552. In some implementations, the metal is aluminum and is patterned using wet etching techniques. In mirror arrays with high interconnect densities, it is advantageous to pattern the metal using dry etching or evaporative metal lift-off techniques to achieve finer line widths. In some implementations, the metal layer 540 is used to provide bond pads and interconnects that connect electrical signals from the control circuitry to each mirror to control mirror actuation.

As shown in fig. 5N, in some implementations, the deposition of the second metal layer 560 provides a mirror surface. As will be appreciated by those skilled in the art, the second metal layer 560 may be the same metal as the first metal layer 540, such as aluminum. Alternatively, the second metal layer 560 may be a different metal, such as a metal that is more reflective than aluminum for certain wavelengths of light (e.g., gold). Such metals are tuned to provide high specular reflectivity for the wavelengths of light of interest, and are typically evaporated and patterned using lift-off techniques to allow for a wider choice of metallization. In some implementations, the metallization layer is composed of 500 μm aluminum. However, in some implementations, additional metal stacks (such as Cr/Pt/Au) may be used to increase reflectivity in the wavelength band common to the fibers. Since the metal is deposited under stress and affects the final mirror flatness, it is advantageous to reduce the thickness of the dielectric layer 538 in the mirror region. This can be achieved by using dry etching of the underlying dielectric prior to evaporation.

In fig. 5O, topside patterning is accomplished according to some implementations of the present disclosure. In some implementations, a passivation dielectric 542 (not shown) may be applied over the metal surface during subsequent processes to protect the metallization. Passivation is removed at the bond pad areas. In some implementations, the mirror structure, including the frame, the mirror, and the support, is defined by the channel 521 separating the structural elements. The lithographic pattern is transferred in the mask layer by reactive ion etching, whereas the silicon etching is not completed until a later stage of the process. The etching is self-aligned and through the various metals, dielectrics, and various layers of the first silicon wafer 510.

As shown in fig. 5P, in some implementations, the backside silicon etch transfers the blade pattern 572 into the first silicon wafer 510 to obtain the blade 570. In some implementations, the techniques disclosed in U.S. Pat. No. 5,501,893 are used to perform etching using deep silicon etching with high selectivity to oxide. Deep silicon etching achieves a near vertical profile in the blade 570, which may typically have a width of between 5 μm and 20 μm and a depth exceeding 300 μm. Etching is stopped on buried oxide layer 522 to provide a uniform depth over the wafer while not penetrating the top side 10 surface of silicon wafer 510. In some implementations, all of the blades 570 can be etched on both the mirror elements and the mirror array at the same time. The buried oxide layer 522 exposed by the deep silicon etch is then removed using a reactive ion etch that stops on the silicon.

Referring to fig. 5Q, because the first silicon wafer 510 is now ready for microstructure release, the first silicon wafer 510 becomes more susceptible to yield loss due to process shock or air flow. To facilitate processing and to aid in hermetically sealing the mirror array, in some implementations, a first silicon wafer 510 is disposed on a base wafer 210 (also referred to hereinafter as a "base" or "base substrate"). Then, the base wafer 210 is bonded to the first silicon wafer 510 to protect the blade after release. As shown in fig. 5Q, in some implementations, the base wafer 210 is bonded to the dielectric layer 539 of the first silicon wafer 510. In some implementations, bonding is accomplished by using a frit bonding element (bottom bonding element) that is heated to its flow temperature and then cooled. In this way, a temperature bond of 400 ℃ is created such that the bonding elements 212, 212' create a hermetic seal that encloses the entire mirror array. The separation between the first silicon wafer 510 and the base wafer 210 using the frit material bonding element allows the blade 570 to swing through high rotation angles without resistance. Typically, the required spacing is greater than 25 μm. As shown in fig. 5Q, in some implementations, the base wafer 210 overlaps the blade 570 in a first direction (e.g., a vertical direction).

Final structure release is accomplished on the top side of the wafer using dry etching in fig. 5R, according to some implementations in the present disclosure, through trench 521 to suspend the movable elements of mirror 236 and frame 230. Furthermore, the release etch facilitates electrical isolation by, for example, separating the silicon of the frame 230 from the silicon of the surrounding components and the device wafer 220. The via 552 is used to connect the silicon region to a metal interconnect 556 (shown in fig. 5N). To completely seal the mirror from the external environment, in some implementations, a cap wafer 250 (also referred to hereinafter as a "cap" or "cap substrate") is disposed on the first silicon wafer 510. The cap wafer 250 is then bonded to the first silicon wafer 510, preferably by bonding elements 222, 222' (e.g., a top bonding element such as a frit seal). As shown in fig. 5R, in some implementations, the cap wafer 250 is bonded to the metal layer 540 of the first silicon wafer 510. Similar to the base wafer 210, in some implementations, heat is applied to the bonding elements 222, 222' (such as frit seals) to fuse or couple the cap wafer 250 to the first silicon wafer 510. In some implementations, the cap wafer 210 overlaps the first silicon wafer 510 in a first direction (e.g., a vertical direction). In some implementations, the lid wafer 210 (e.g., lid) overlaps the base wafer 210 in a first direction. As shown in fig. 5R, in some implementations, the cap wafer 250 overlaps the first silicon wafer 510 and the base wafer 210 in a first direction. The cap wafer 250 may include: glass (and/or other suitable material) that allows incident light to be transmitted into the mirror cavity 232 with low loss, reflected from the upper surface of the mirror 236, and transmitted out of the mirror cavity 232. As shown in fig. 5R, in some implementations, the mirror cavity 232 is disposed between the blades 234, and at least one blade 234 overlaps the mirror 236 in the first direction. In some implementations, the mirror 236 overlaps the recessed region 410 in the first direction.

The resulting process provides an additional buried oxide layer, deeper vias and honeycomb grooves. Thus, MEMS has a higher resonant frequency and the association of the mirror with external vibrations is smaller. This provides an optical switching system or optical circuit switch which is less prone to errors in switching and which may have a faster switching time. As will be appreciated by those skilled in the art, the mirror cavity may be disposed between the first blade and the second blade. Further, a plurality of blades may be provided, wherein the first blade overlaps the center stage (including the plurality of recessed regions), the cover substrate and the base substrate may overlap the center stage (including the plurality of recessed regions), and/or the plurality of recessed regions may overlap the mirror.

Fig. 6 illustrates a cavity SOI wafer 600. In this configuration, the wafer manufacturer pre-etches the pattern of honeycomb grooves 610 into the wafer in the manufacturing process, according to some implementations of the present disclosure. Then, buried oxide layer 522 is positioned above the recess instead of below the recess, as shown in fig. 5. As will be appreciated by those skilled in the art, when the deep reactive ion etching process described above is performed to define the blade electrode (as shown in fig. 5P), the etching stops when reaching the buried oxide layer 522. Thus, in this configuration, the etching process will be time controlled to allow the blade electrode to be etched. Furthermore, the mirror structure will have an oxide layer positioned between the two silicon layers, which may warp or bend the mirror.

Fig. 7 illustrates an optical (circuit) switch 700 implemented with an array of switch mirrors 730, 740. The optical switch 700 may be configured to couple the light beam 750 from one of the input fibers 712 in the input fiber optic module 710 to a switching device of one of the output fibers 722 in the output fiber optic module 720. As shown, the beam 750 from the input fiber 712 is collimated and directed toward the desired output fiber 722. The movable mirrors 732, 742 in the switched mirror arrays 730, 740 redirect the light beam 750 to a desired position (one of the output fibers 722 in this example). Each of the switched mirror arrays 730, 740 in fig. 7 may be configured with a plurality of movable mirrors 732, 742 that are operable to direct (and redirect) the light beam 750. In addition, the optical switch 700 may also include at least one switched mirror array 730, 740, and at least one movable mirror 732, 742 is operable to implement the features discussed in fig. 3-6.

While preferred implementations of the present invention have been shown and described herein, it will be obvious to those skilled in the art that such implementations are provided by way of example only. Numerous variations, changes, and substitutions will now occur to those skilled in the art without departing from the invention. It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention. It is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.

Claims

1. A method of fabricating a micromirror, the method comprising:

forming a first photoresist layer on a first silicon-on-insulator (SOI) substrate comprising a first silicon layer, a second silicon layer, and a first oxide layer between the first silicon layer and the second silicon layer;

forming a honeycomb pattern by etching the first photoresist layer and the second silicon layer;

removing the first photoresist layer;

providing a second silicon-on-insulator (SOI) substrate on the first SOI substrate, the second SOI substrate comprising a third silicon layer, a fourth silicon layer, and a second oxide layer between the third silicon layer and the fourth silicon layer; and

and removing the second oxide layer and the fourth silicon layer.

2. The method of claim 1, further comprising forming a fifth silicon layer by bonding the second silicon layer and the third silicon layer together.

3. The method of claim 2, further comprising forming an isolation trench in the fifth silicon layer.

4. The method of claim 3, wherein forming the isolation trench in the fifth silicon layer comprises:

Forming a first dielectric layer on the fifth silicon layer;

forming a second photoresist layer on the first dielectric layer; and

the second photoresist layer, the first dielectric layer, and the fifth silicon layer are etched.

5. The method of claim 4, further comprising filling the isolation trench in the fifth silicon layer.

6. The method of claim 5, wherein filling the isolation trench in the fifth silicon layer comprises:

removing the first dielectric layer and the second photoresist layer; and

a second dielectric layer is deposited over the fifth silicon layer.

7. The method of claim 6, further comprising planarizing a surface of the second dielectric layer.

8. The method of claim 7, further comprising forming a first via and a second via, the first via passing through the second dielectric layer, the second via passing through the second dielectric layer.

9. The method of claim 8, further comprising:

forming a first contact associated with the first via; and

a second contact associated with the second via is formed.

10. The method of claim 9, further comprising forming a metal layer between the first contact and the second contact.

11. The method of claim 10, further comprising:

the second dielectric layer and the fifth silicon layer are etched between the first contact and the metal layer and between the second contact and the metal layer.

12. The method of claim 11, further comprising disposing a cap substrate on the first silicon-on-insulator (SOI) substrate.

13. The method of claim 12, wherein disposing a cap substrate on the first silicon-on-insulator (SOI) substrate comprises: a top bonding element is disposed between the cap substrate and the first silicon-on-insulator (SOI) substrate.

14. The method of claim 1, further comprising forming a backside blade pattern on the first silicon layer.

15. The method of claim 14, wherein forming a backside blade pattern on the first silicon layer comprises:

forming a third dielectric layer on the first silicon layer; and

the third dielectric layer and the first silicon layer are etched.

16. The method of claim 1, further comprising disposing the first silicon-on-insulator (SOI) substrate on a base substrate.

17. The method of claim 16, wherein disposing the first silicon-on-insulator (SOI) substrate on the base substrate comprises: a bottom bonding element is disposed between the first silicon-on-insulator (SOI) substrate and the base substrate.

18. A movable mirror, comprising:

a fixed frame comprising a cavity;

a movable frame disposed in the cavity; and

a center stage disposed in the cavity,

wherein the center stage includes a plurality of recessed areas.

19. The movable mirror of claim 18, further comprising a mirror positioned on the center stage.

20. The movable mirror of claim 18, wherein the recessed region forms a honeycomb pattern on a surface of the center stage.

21. The movable mirror of claim 18, wherein the plurality of recessed regions comprises at least one of a circular recessed region, an elliptical recessed region, a rectangular recessed region, a parallelogram recessed region, a triangular recessed region, and a hexagonal recessed region.

22. The movable mirror of claim 18, further comprising a plurality of blades including a first blade and a second blade, wherein the first blade overlaps a center stage comprising the plurality of recessed regions.

23. The movable mirror of claim 22, further comprising a mirror cavity between the first blade and the second blade.

24. The movable mirror of claim 18, further comprising a cover substrate and a base substrate, the cover substrate and the base substrate overlapping a center stage comprising the plurality of recessed regions.

25. The movable mirror of claim 19, wherein the plurality of recessed regions overlap the mirror.

26. A mirror array comprising the movable mirror of claim 18.

27. An optical circuit switch comprising the mirror array of claim 26.