CN117544162A - Signal input detection circuit - Google Patents

Signal input detection circuit Download PDF

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Publication number
CN117544162A
CN117544162A CN202311542000.XA CN202311542000A CN117544162A CN 117544162 A CN117544162 A CN 117544162A CN 202311542000 A CN202311542000 A CN 202311542000A CN 117544162 A CN117544162 A CN 117544162A
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CN
China
Prior art keywords
mos tube
capacitor
signal input
detection circuit
mos
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Pending
Application number
CN202311542000.XA
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Chinese (zh)
Inventor
田畅
孙彪
丁万新
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Shanghai Chuantu Microelectronics Co ltd
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Shanghai Chuantu Microelectronics Co ltd
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Priority to CN202311542000.XA priority Critical patent/CN117544162A/en
Publication of CN117544162A publication Critical patent/CN117544162A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The invention discloses a signal input detection circuit which comprises a counting module, a first capacitor, a first MOS tube, a second capacitor, a second MOS tube and an inverter. The first end of the first capacitor is connected with the output end of the counting module; the grid electrode of the first MOS tube is respectively connected with the second end of the first capacitor and the drain electrode of the first MOS switch, the drain electrode of the first MOS tube is connected with the system power supply voltage, and the source electrode of the first MOS tube is grounded; the first end of the second capacitor is connected with the source electrode of the first MOS tube, and the second end of the second capacitor is grounded; the grid electrode of the second MOS tube is respectively connected with the source electrode of the first MOS tube and the first end of the second capacitor, the source electrode of the second MOS tube is connected with the system power supply voltage, and the drain electrode of the second MOS tube is grounded through a first current source; the input end of the inverter is connected with the drain electrode of the second MOS tube. The invention solves the problems that the prior clock detection technology can detect the result after the counter counts for a certain time and has slower response.

Description

Signal input detection circuit
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a signal input detection circuit.
Background
As shown in fig. 1, in clock detection, a reference clock counter, a measured clock counter and a comparison detection module are generally required to be used. The counter is a unidirectional non-cyclic counter, i.e. it is reset and counts again from 0, and once it is full, it remains unchanged. If the clock signal under test is present, the counter starts counting after the system is reset, remaining unchanged after the expiration. The comparison detection module is realized by a comparator, and when the counting result is larger than a preset value, the output result of the detection module is high, which indicates that a clock exists; if the clock does not exist, the output result is kept to be 0, which indicates that no clock is input.
The existing clock detection technology needs a high-frequency reference clock, a counter and a comparison detection module, the complexity of the system is high, and the occupied area of a circuit is large. In addition, the existing clock detection technology can detect the result after acquiring the clock signal, and the counter is required to count for a certain time, so that the existing clock detection and counting response speed is low, and whether the clock signal exists cannot be detected immediately.
Based on this, a new solution is needed.
Disclosure of Invention
In view of this, the embodiments of the present disclosure provide a signal input detection circuit to at least solve the drawbacks and disadvantages of the existing clock detection technology.
The embodiment of the specification provides the following technical scheme:
the embodiment of the present specification provides a signal input detection circuit, including:
the counting module is used for acquiring input signals;
the first end of the first capacitor is connected with the output end of the counting module;
the grid electrode of the first MOS tube is connected with the second end of the first capacitor and the drain electrode of the first MOS switch respectively, the drain electrode of the first MOS tube is connected with the system power supply voltage, and the source electrode of the first MOS tube is grounded;
the first end of the second capacitor is connected with the source electrode of the first MOS tube, and the second end of the second capacitor is grounded;
the grid electrode of the second MOS tube is respectively connected with the source electrode of the first MOS tube and the first end of the second capacitor, the source electrode of the second MOS tube is connected with the system power supply voltage, and the drain electrode of the second MOS tube is grounded through a first current source;
and the input end of the inverter is connected with the drain electrode of the second MOS tube, and the output end of the inverter is used for outputting a detection result.
Further, the signal input detection circuit further includes:
the source electrode of the third MOS tube is connected with the grid electrode of the first MOS tube, the grid electrode of the third MOS tube is connected with the drain electrode of the third MOS tube, and the drain electrode of the third MOS tube is connected with the system power supply voltage.
Further, the drain electrode of the third MOS tube is connected with the system power supply voltage through a resistor.
Further, the source electrode of the first MOS tube is grounded through a second current source.
Further, the counting module is a D trigger.
Further, the D input of the D flip-flop is connected to the Q output of the D flip-flop to form a ring counter.
Further, the first MOS tube is an NMOS tube.
Further, the second MOS tube is a PMOS tube.
Further, the third MOS tube is an NMOS tube.
The embodiment of the invention also provides a signal input detection system which comprises the signal input detection circuit.
Compared with the prior art, the beneficial effects that above-mentioned at least one technical scheme that this description embodiment adopted can reach include at least:
according to the signal input detection circuit, a clock input signal is obtained through the counting module; the first end of the first capacitor is connected with the output end of the counting module; the grid electrode of the first MOS tube is connected with the second end of the first capacitor, the drain electrode of the first MOS tube is connected with the system power supply voltage, and the source electrode of the first MOS tube is grounded; the first end of the second capacitor is connected with the source electrode of the first MOS tube, and the second end of the second capacitor is grounded; the grid electrode of the second MOS tube is respectively connected with the source electrode of the first MOS tube and the first end of the second capacitor, the source electrode of the second MOS tube is connected with the system power supply voltage, and the drain electrode of the second MOS tube is grounded through a first current source; the input end of the inverter is connected with the drain electrode of the second MOS tube, and the output end of the inverter is used for outputting a detection result, so that whether the signal detection circuit receives an input signal or not can be known according to the output result of the output end of the inverter, and the problem that the counter is required to count for a certain time to detect the result and the response is slower in the existing clock detection technology is solved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a prior art clock detection circuit;
FIG. 2 is a circuit diagram of a signal input detection circuit according to an embodiment of the present invention;
the reference numerals of the present invention are as follows:
10. a counting module; 20. a first capacitor; 30. a first MOS tube; 40. a second capacitor; 50. a second MOS tube; 60. a first current source; 70. an inverter; 80. a third MOS tube; 90. and a second current source.
Detailed Description
Embodiments of the present application are described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present application, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, apparatus may be implemented and/or methods practiced using any number and aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concepts of the application by way of illustration, and only the components related to the application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details.
The following describes the technical solutions provided by the embodiments of the present application with reference to the accompanying drawings.
As shown in fig. 2, the embodiment of the present disclosure provides a signal input detection circuit, which includes a counting module 10, a first capacitor 20, a first MOS transistor 30, a second capacitor 40, a second MOS transistor 50, and an inverter 70. Wherein the counting module 10 is used for acquiring an input signal; a first end of the first capacitor 20 is connected with the output end of the counting module 10; the grid electrode of the first MOS tube 30 is respectively connected with the second end of the first capacitor 20 and the drain electrode of the first MOS tube 30, the drain electrode of the first MOS tube 30 is connected with the system power supply voltage, and the source electrode of the first MOS tube 30 is grounded; a first end of the second capacitor 40 is connected with the source electrode of the first MOS tube 30, and a second end of the second capacitor 40 is grounded; the grid electrode of the second MOS tube 50 is respectively connected with the source electrode of the first MOS tube 30 and the first end of the second capacitor 40, the source electrode of the second MOS tube 50 is connected with the system power supply voltage, and the drain electrode of the second MOS tube 50 is grounded through the first current source 60; the input end of the inverter 70 is connected to the drain electrode of the second MOS transistor 50, and the output end of the inverter 70 is configured to output a detection result.
Wherein the counting module 10 is used for acquiring a clock input signal.
Preferably, the counting module 10 is a D flip-flop, and the D input of the D flip-flop is connected with the Q output of the D flip-flop to form a ring counter.
Specifically, in the case where the counting module 10 is a D flip-flop, the clock input terminal of the D flip-flop is used to acquire the clock signal.
In some of these embodiments, the counting module 10 may also be a counter or the like.
In some embodiments, the first capacitor 20 is a polar capacitor, the negative electrode of which is connected to the output terminal of the D flip-flop, and the positive electrode of which is connected to the gate of the first MOS transistor 30.
Wherein, the first MOS tube 30 is an NMOS tube; the second MOS transistor 50 is a PMOS transistor.
In some of these embodiments, the second capacitor 40 is a polarized capacitor.
Specifically, the positive electrode of the second capacitor 40 is connected to the source electrode of the first MOS transistor 30 and the gate electrode of the second MOS transistor 50, and the negative electrode of the second capacitor 40 is grounded.
Further, the signal input detection circuit further includes a third MOS transistor 80, a source of the third MOS transistor 80 is connected to a drain of the first MOS transistor 30, a gate of the third MOS transistor 80 is connected to a drain of the third MOS transistor 80, and a drain of the third MOS transistor 80 is connected to a system power supply voltage.
The third MOS transistor 80 is an NMOS transistor.
Further, the drain electrode of the third MOS transistor 80 is connected to the system power voltage through a resistor.
Further, the source of the first MOS transistor 30 is grounded via the second current source 90.
The following is a specific implementation of the embodiment of the present invention:
as shown in fig. 2, the signal input detection circuit includes a D-flip-flop (counting module 10), an NMOS transistor M1 (third MOS transistor 80), an NMOS transistor M2 (first MOS transistor 30), a PMOS transistor M3 (second MOS transistor 50), a capacitor C1 (first capacitor 20), a capacitor C2 (second capacitor 40), a resistor R, an inverter 70, and a current source I 1 (second current source 90) and current source I 2 (first current source 60).
The working principle is as follows:
for the convenience of explanation of the working principle of the present invention, in this embodiment, the connection point between the source of the third MOS transistor 80 and the gate of the first MOS transistor 30 is set as node a, the connection point between the source of the first MOS transistor 30 and the second capacitor 40 is set as node B, and the connection point between the inverter 70 and the drain of the second MOS transistor 50 is set as node C.
In the case where no clock is input in the initial state, the voltages VA 'and VB' at the node a and the node B can be expressed as:
VA′＝VDD-Vgs1-I 1 ·R
VB′＝VA′-Vgs2
where Vges1 is the gate-source voltage of the NMOS transistor M1, vges2 is the gate-source voltage of the NMOS transistor M2, I 1 Is a current source I 1 Is set in the above-described range).
Under the condition that the clock input end of the D trigger has a clock input signal, the output end Q of the D trigger is changed from low level to high level Vh, and the voltage at the node A can be raised by Vh because the voltage at the two ends of the capacitor C1 cannot be suddenly changed, namely the Vges2 of the NMOS tube M2 can be raised, and the current I flowing out of the NMOS tube M2 can be known by a square law formula M2 Will become larger and eventually the current charges the capacitor C2, as seen by charge conservation, for a time t of the clock high level 1 Thereafter, the voltage VB' at node B becomes:
under the condition that the voltage at the node B is charged high, the |Vgs3| at the PMOS tube M3 is reduced until the current I flowing out of the PMOS tube M3 ＜I 2 Node C is driven by current source I 2 Pulled down to ground and after passing through inverter 70 the output of the signal input detection circuit goes high, i.e. has a clock input.
At clock level t 2 During the period, capacitor C2 is connected to current source I 1 Discharging occurs and the voltage at node B begins to drop, at t 2 In the time, only the current I flowing out of the PMOS tube M3 M3 ＞I 2 The clock can be stably detected; if the current I M3 ＜I 2 There is no clock input, and the output terminal v_det of the signal input detection circuit will remain low at this time, indicating no clock input.
The frequency range of the detected clock of the invention is as follows:
thus, detection of the input clock may be achieved by adjusting the parameters to configure a minimum value of the detected frequency.
The signal input detection circuit disclosed by the invention does not need a high-frequency reference clock, is low in circuit complexity and high in detection speed, and can detect whether a clock exists in real time.
The embodiment of the invention also provides a signal input detection system which comprises the signal input detection circuit.
In this specification, identical and similar parts of the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the description is relatively simple, and reference is made to the description of parts of the system embodiments.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily conceivable by those skilled in the art within the technical scope of the present application should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A signal input detection circuit, comprising:
the counting module is used for acquiring input signals;
the first end of the first capacitor is connected with the output end of the counting module;
the grid electrode of the first MOS tube is connected with the second end of the first capacitor and the drain electrode of the first MOS switch respectively, the drain electrode of the first MOS tube is connected with the system power supply voltage, and the source electrode of the first MOS tube is grounded;
the first end of the second capacitor is connected with the source electrode of the first MOS tube, and the second end of the second capacitor is grounded;
the grid electrode of the second MOS tube is respectively connected with the source electrode of the first MOS tube and the first end of the second capacitor, the source electrode of the second MOS tube is connected with the system power supply voltage, and the drain electrode of the second MOS tube is grounded through a first current source;
and the input end of the inverter is connected with the drain electrode of the second MOS tube, and the output end of the inverter is used for outputting a detection result.
2. The signal input detection circuit of claim 1, further comprising:
the source electrode of the third MOS tube is connected with the drain electrode of the first MOS tube, the grid electrode of the third MOS tube is connected with the drain electrode of the third MOS tube, and the drain electrode of the third MOS tube is connected with the system power supply voltage.
3. The signal input detection circuit according to claim 2, wherein a drain of the third MOS transistor is connected to the system power supply voltage through a resistor.
4. The signal input detection circuit of claim 3, wherein the source of the first MOS transistor is grounded via a second current source.
5. The signal input detection circuit of claim 1, wherein the counting module is a D flip-flop.
6. The signal input detection circuit of claim 5, wherein a D input of the D flip-flop is connected to a Q output of the D flip-flop to form a ring counter.
7. The signal input detection circuit of claim 1, wherein the first MOS transistor is an NMOS transistor.
8. The signal input detection circuit of claim 1, wherein the second MOS transistor is a PMOS transistor.
9. The signal input detection circuit of claim 2, wherein the third MOS transistor is an NMOS transistor.
10. A signal input detection system comprising a signal input detection circuit as claimed in any one of claims 1 to 9.
CN202311542000.XA 2023-11-17 2023-11-17 Signal input detection circuit Pending CN117544162A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311542000.XA CN117544162A (en) 2023-11-17 2023-11-17 Signal input detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311542000.XA CN117544162A (en) 2023-11-17 2023-11-17 Signal input detection circuit

Publications (1)

Publication Number Publication Date
CN117544162A true CN117544162A (en) 2024-02-09

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311542000.XA Pending CN117544162A (en) 2023-11-17 2023-11-17 Signal input detection circuit

Country Status (1)

Country Link
CN (1) CN117544162A (en)

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