CN1175421C

CN1175421C - Logic circuit

Info

Publication number: CN1175421C
Application number: CNB001083511A
Authority: CN
Inventors: 平入孝二
Original assignee: Sony Corp
Current assignee: Sony Corp
Priority date: 1999-12-22
Filing date: 2000-02-29
Publication date: 2004-11-10
Anticipated expiration: 2020-02-29
Also published as: JP2001186009A; KR20010082496A; CN1301023A; EP1111615A1; US6374393B1; TW463166B; KR100613738B1

Abstract

The logic circuit includes a logic circuit portion comprised of a dual-rail type logic tree, a synchronization type sensing latch means comprised of a sense amplifier for differentially amplifying results of evaluation of the logic circuit portion in synchronization with a clock, a logic tree disconnection controlling circuit, and a group of switches for disconnection of the logic tree, and a set and reset latch means for holding a logic for one cycle of the synchronization signal. In an idle stage, the sense amplifier is deactivated, the dual-rail type logic tree unit and sensing latch are connected, and the output terminals of the dual-rail type logic tree are short-circuited. In the drive stage, the sense amplifier is activated and the output terminals of the dual-rail logic tree are opened. In the final determination stage, the sense amplifier is activated and the logic tree and sensing latch unit are disconnected.

Description

Logical circuit

Technical field

The present invention relates to a kind of logical circuit that in integrated circuit etc., uses at cmos semiconductor, particularly as have be used for with a synchronizing signal, be the logical circuit of trigger of embedding logic function of the synthetic unit of function packing group of the function of trigger pip 1 memory element of synchronousing working and a series of logic gates that are positioned at its data input pin.

Background technology

Integrated circuit stores in the trigger to be used for the work of next cycle by the result who makes up the work of a plurality of logic gate actuating logic and will generate usually.

For example, very general structure also is to constitute by a trigger with in one or more logic gates of its data input pin arrangement in such as the integrated circuit of sequential circuit and streamline.

Below, will explain first to the 4th traditional example of the circuit that constitutes by a trigger and one or more logic gates of arranging at its data input pin.

First traditional example

Fig. 1 shows trigger utilizing that static cmos logic circuit 10 realizes and the general structure of the logic gate of arranging at its data input pin.

As shown in Figure 1, desirable logic function realizes by combinational logic circuit LC11.Its logic function output terminal F11 is provided for the data input pin D of trigger FF11.

In trigger FF11 and synchronizing signal CLK synchronously take out the value of input D and export from data output end Q.

The circuit of Fig. 2 shows the transistor layer of trigger F11.

Trigger FF11 shown in Figure 2 is so that be used in John p.Uyemura, the cmos circuit design, and kluwer Academic Publishers, pp.278-281, the MS master-slave D-flip flop of the 1999 CMOS transistor gates that disclose is widely used for the basis and current.

Specifically, trigger FF11 shown in Figure 2 has phase inverter INV11 to INV18 and cmos transmission gate TMG11 and TMG12.

In addition, the circuit of Fig. 3 shows an example of combinational logic circuit LC11 structure.

Logical circuit LC11 has 2-input XOR gate (EXOR) ER11,2-input biconditional gate (EXNOR) ENR11 and a 2-input nand gate NA11.

Logical circuit shown in Figure 3 shows following situation,, realizes logic function F=A (+) that is) { the situation of (B (+) C) D}.

Second traditional example

In addition, disclosed the thought of a trigger with function combinations to a bag of a series of logic gates that are arranged in its data input pin.

The same with first example, exist the PDN (pulldown network) of a kind of AMD.co the mount type trigger (below be simply referred to as " PDN-F/F " (referring to people's such as Dteven Hesley " 7th-Generationx86 Microprocessor ", ISSCC Digest of Technical papers, pp.92-93, February 1999, or people such as Alisa Scherer " An Out-of order Three-WaySuperscalar Multimedia Floating-Point ", ISSCC Digest of Technicalpapers, pp.282-283, February 1999).

The circuit of Fig. 4 shows the general structure of PDN-F/F, and the circuit of Fig. 5 shows the example of structure of the PDN-F/F logical circuit of a logic function that is used to install a multiplexer.

PDN-F/F logical circuit 20 is by comprising that p-channel MOS (PMOS) transistor PT21 and PT22 and n-channel MOS (NMOS) transistor NT11 are to the dynamic circuit unit 21 of NT13 and comprise that its input and output are interconnected each other and constitute with the phase inverter INV21 that constitutes a latch and the static circuit unit 22 of INV22 and the phase inverter INV23 that output is used.

As mentioned above, PDN is the abbreviation of " pulldown network " and is referred to as NMOS usually and goes alone line style logic tree 23.

In this system, the described logic of dynamic logic unit 21 assessments, its value is preserved by the latch of static circuit unit 22.

Described PDN-F/F logical circuit 20 is characterised in that the pulse clock PCLK that will be transfused to PMOS transistor PT21 and nmos pass transistor NT21 must be one and the synchronous short pulse of global synchronizing signal CLK rising edge.

Described pulse clock PCLK is produced by pulse producer shown in Figure 5 24.

Described pulse producer 24 is by being transfused to phase inverter INV24 that inversion clock signal CLK_X is arranged, being connected in series in supply voltage V _DDPower lead and ground between and its grid be provided with the output of phase inverter INV24 PMOS transistor PT23 and nmos pass transistor NT24 and NT25, be transfused to drain electrode tie point current potential that PMOS transistor PT23 and nmos pass transistor NT24 are arranged and enable signal ENB 2-input nand gate NA21, be transfused to that the 2-input rejection gate NR21 of output that Sheffer stroke gate NA21 is arranged and inversion clock signal CLK_X constitutes.

When described pulse clock PCLK had logical zero, inner node F was initialized to " 1 ".

When described pulse clock PCLK becomes logical one, the described logic of assessment in logic tree (PDN) 23, and node F changes.This dynamic inverter that changes through being made of PMOS transistor PT22 and nmos pass transistor NT23 and NT24 is transferred to the latch 22a that comprises phase inverter INV21 and INV22.During this cycle, described input signal must not change.

Important thing is accurately to control the time that described pulse clock PCLK becomes logical zero in described PDN-F/F logical circuit 20.

This time must be a current potential that is enough to make node F becomes logical zero from logical one shortest time.

If this time is too short, so, the current potential of node F can turn back to logical one once more when fully not being varied to logical zero, and therefore, described logic can not correctly be assessed.But if this time is oversize, so, the cycle length that input signal can not change is oversize.

Time cycle as changing,, also exist one time and retention time are set even in general trigger working time place's input.It has been generally acknowledged that the short time means preferable performance.

In PDN-F/F logical circuit 20, the time cycle that pulse clock PCLK becomes logical one is directly with that time and retention time are set is relevant, so the width of described pulse clock PCLK is preferably shorter.

The pulse producer of generation pulse clock PCLK shown in Figure 5 is characterised in that the proper width of described pulse clock PCLK obtains by nmos pass transistor NT24 and NT25.

As PDN, be logic tree 23 when aspect size, having become 3 NMOS, if promptly except nmos pass transistor NT24 and NT25 also series connection added another nmos pass transistor, so, the delayed-action that in described pulse producer 24, can produce three NMOS.

Can think that the main target of PDN-F/F logical circuit 20 is to realize the high speed logic circuit.

Usually, the speed of the circuit of being realized by dynamic logic circuit will be higher than the speed of the circuit of being realized by static logic circuit.

In addition, in PDN-F/F logical circuit 20, in order to shorten be provided with time and the retention time relevant with described logic function input end, described main latch and described logic tree are together with each other.

The 3rd traditional example

Be combined into second example of the thought of a bag mutually as the function of a trigger that will be positioned at its data input pin and a series of logic gates, described a trigger (after this being simply referred to as " SA-F/F ") and (seen people such as Borivoje Nikolic " based on the trigger of sensor amplifier " based on sensor amplifier, ISSCC Digest of Technical papers, PP.282-283, people's such as February 1999 or R.Stephany " 200MHZ 32b 0.5W CMOS risc microcontroller ", TSSCC Digest of Technical papers, PP.238-239 February1998).

The circuit of Fig. 6 shows the general structure of SA-F/F, and the circuit of Fig. 7 shows the object lesson of structure of the SA-F/F logical circuit of the logic function that a multiplexer is installed.

SA-F/F logical circuit 30 is by comprising that nmos pass transistor NT301 is used to control nmos pass transistor NT31, one that two main line type logic trees 31 of described NMOS and clock signal clk synchronously are connected to ground to the two main line type logic tree of the NMOS of NT316 31, one and is made of to sensor amplifier 32 and type SR latch 33 that be made of Sheffer stroke gate NA31 and NA32 and non-that NT34 constitutes to PT34 and nmos pass transistor NT32 PMOS transistor PT31.

Notice that the grid of the nmos pass transistor NT34 in described sensor amplifier 32 is connected to supply voltage V _DDPower lead and always be in conducting state

In SA-F/F logical circuit 30, when synchronizing signal CLK is logical zero, give charging by the PMOS transistor PT31 and the PT32 execution of sensor amplifier 32.Whereby, logic input node TH and TH_X become logical one and keep its output with respect to SR latch 33.

Logic tree 31 is through nmos pass transistor NT32 and logic is imported F to NT33 and F_X gives the amount that is lower than logical one current potential nmos pass transistor threshold value that is charged to.

At this moment, NT31 is cut off by nmos pass transistor, so the electric current of not flowing through flows through.

When clock signal clk became logical one, PMOS transistor PT31 and PT32 became and end, and nmos pass transistor NT31 becomes conducting, the assessment of beginning actuating logic.

According to described input signal, the logic input node TF relevant and the path of a ground connection among the TF-X in logic tree 31, have been formed with sensor amplifier 32.Here, suppose that it is a logic input node TF side.

In this case, the current potential of logic input node TF quickly falls to logical zero.

Here, the nmos pass transistor NT34 of sensor amplifier 32 always is in conducting state and is similar to the resistance of a reality, and therefore, the electric charge at logic input node TF_X place flows to logic input node TF side through nmos pass transistor NT34.

Therefore, the current potential of logic input node F_X has lingeringly slightly after logic input F and also drops to " 0 ".

At last, the current potential of logic input F and F_X all drops to the logical zero current potential, and still, logic output H and H_X do not drop to the logical zero current potential.Here, suppose H=0 and H_X=1.

When logic input F at first became logical zero, described logic output H also became logical zero through nmos pass transistor NT32.

But after described current potential had decline slightly, logic output node TH_X reverted to logical one.This is because logic input F drops to logic a little earlier " 0 ", PMOS transistor PT34 becomes conducting and electric charge is provided for logic input node TH_X.For this reason, PMOS transistor PT33 and nmos pass transistor NT33 end, and PMOS transistor PT34 and nmos pass transistor NT32 become conducting and keep the logic potential state of a stable period at logic output node TH and TH_X place.

These two logic output H and H_X also are transfused to SR latch 33, and therefore, the assessment result of described logic function is inserted into and exports to SR latch 33.

The path of ground connection is changed to F_X from logic input F even change in the input signal after this and in logic tree 31, also can not exert an influence to work.

This is will not flow to logic input node TF_X one side because nmos pass transistor NT33 has become by the electric charge with node TH_X.The grounding path that arrives logic input node TF_X still only is fixed on logical zero through nmos pass transistor NT34 and NT32 with the current potential of node TH.

Can think that the main target of described SA-F/F logical circuit 30 also is to realize the high speed logic circuit in the mode identical with PDN-F/F logical circuit 20.

Described SA-F/F logical circuit 30 utilizes described dynamic logic circuit to combine so that shorten be provided with time and the retention time relevant with the input end of described logic function with the mode evaluate logic function identical with described PDN-F/F logical circuit and with a sensor amplifier and main latch.

The 4th traditional example

Become the 3rd embodiment of thought of a bag identical with function combinations with a trigger that will be positioned at its data input and a series of logic gates, described a differential current switch logic (after this being referred to as " DCSL ") circuit and (seen people such as Dinesh Somasekhar " differential current switch logic: low-power consumption DCVS logic families ", IEEE JSSC vol.31, no.7, pp.981-991, July 1996).

The circuit of Fig. 8 shows the general structure of DCSL.

DCSL circuit 40 is by the two main line logic tree parts 41 of NMOS, be made of to PT43 and nmos pass transistor NT41 to sensor amplifier unit 42 that NT45 constitutes with by the or/no type SR latch 43 that rejection gate NR41 and NR42 constitute PMOS transistor PT41 in the mode identical with SA-F/F logical circuit 30.

In same text, (pp.983, Fig. 4 is to Fig. 6) three kinds of sensor amplifiers (DCSL1, DCSL2 and DCSL3) have been advised.Here, described DCSL3 will be described.In addition, as describing in the text, described DCSL itself is one and relates to the suggestion of new dynamic logic circuit, particularly a sensor amplifier constructive method and not to realize that having the trigger that embeds logic function is target.But the pp.986 of same text, Figure 12 have introduced " the DCSL output state that is latched " and suggestion realizes having the method for the trigger that embeds function.

Different with described SA-F/F logical circuit, in DCSL (DCSL3) circuit 40, as flip-flop operation original state, the current potential of the logic of sensor amplifier 41 output H and H_X be set at described nmos pass transistor threshold value near.Described current potential is used as logical zero and handles for use in the logic gate of back with their benchmark.

In the original state of described flip-flop operation, inversion clock signal CLK_X is provided as logical one, and PMOS transistor PT41 is by becoming conducting with nmos pass transistor NT45.

Because nmos pass transistor NT45 becomes conducting, inner node TH and TH_X are by short circuit.This means nmos pass transistor NT41, NT42, NT43 and NT44 grid and the drain electrode by short circuit.

Its grid and drain electrode are equivalent to a diode by the MOS transistor of short circuit.

Here, will consider that the logic current potential of node TH and TH_X is the situation of [0,1] before inversion clock CLK_X becomes logical one.In this case, positive charge is stored in node TH_X place.

When inversion clock signal CLK_X becomes logical one and during the short circuit that takes place to be caused by nmos pass transistor NT45, causes balanced distribution thereby the electric charge at node TH_X place begins to flow to node TH.

At this moment, if described electric charge does not flow to Anywhere, then the current potential of two node TH and TH_X becomes supply voltage V _DDHalf.

But as mentioned above, this moment, nmos pass transistor NT41, NT42, NT43 and NT44 were equivalent to a diode, therefore, had electric current to flow, up to the potential difference (PD) between the described diode two ends become equal the threshold value of described nmos pass transistor substantially till.

Specifically, electric current flows to ground through nmos pass transistor NT41 and NT42, and simultaneously, electric current flows to the logic output node TF and the TF_X of logic tree 41 through nmos pass transistor NT43 and NT44.

Utilize this mode, the current potential of node TH and TH_X becomes and equals the threshold value of described nmos pass transistor substantially.

At this moment, even a path that has to ground among the node TF of logic tree 41 and the TF_X does not have electric current to flow out from node TH and TH_X yet.

This is because the voltage that is added to the grid of nmos pass transistor NT43 and NT44 is positioned near the threshold value of nmos pass transistor and described transistor is cut off.

Therefore, the current potential at node TF and TF_X place becomes unstable.But in most of the cases, they become the value near logical zero.

The current potential of node TH and TH-X is positioned near the threshold value of described nmos pass transistor.They are used as logical zero and handle, thereby make or/no type SR latch 442 keep their output.

Inversion clock signal CLK_X becomes logical zero (this is equivalent to the rising of clock signal clk) and beginning logic evaluation.

In this case, nmos pass transistor NT45 ends, and therefore short-circuit condition can not occur, and PMOS transistor PT41 becomes conducting and electric current begins to flow.

Because near the voltage described nmos pass transistor threshold value is not added on the grid of PMOS transistor PT42 and PT43, so PMOS transistor PT42 and PT43 begin conducting state.

Therefore, electric charge offers node TH and TH_X through PMOS transistor PT41, PT42 and PT43.Because near the voltage described nmos pass transistor threshold value has been added to (being node TH and TH_X) on the described grid, so nmos pass transistor NT43 and NT44 begin cut-off state.

Electric charge is provided for node TH and TH_X, and the current potential of these nodes rises, and nmos pass transistor NT43 and NT44 begin faint conducting.

Utilize and the identical mode of described SA-F/F logical circuit, always can in the middle of the logic output node TF of described logic tree and TF_X one, be formed into the path on ground by making up described input signal.Here hypothesis is node TF.

Electric current flows to node TF from node TH through the nmos pass transistor NT43 that begins faint conducting.The current potential that has begun the node TH that rises drops to the current potential of complete logical zero.

Because node TH becomes complete logical zero current potential, complete conducting and nmos pass transistor NT42 and NT45 become and end fully so PMOS transistor PT43 becomes.

For this reason, node TH_X reaches complete logical one current potential rapidly.In addition, simultaneously, PMOS transistor PT42 becomes and ends fully, nmos pass transistor NT41 and the NT43 complete conducting that becomes.

Whereby, keep the potential state of stable period at node TH and TH_X place.Logic output H and the H_X corresponding with the current potential of these two nodes also are the inputs of described SR latch 43, and therefore, the assessment result of logic function is inserted into and exports to described SR latch 43.

TF_X is changed into from node TF in path to ground even change in input signal after this and in described logic tree 41, also can not exert an influence to described work.

Nmos pass transistor NT44 has become by will not flowing to node TF_X from node TH_X with electric current.In addition, even node TF no longer has the path to ground, nmos pass transistor NT41 has also become conducting and and node TH has been remained on complete logical zero.

One of target of DCSL circuit 40 is to realize the high speed logic circuit with the identical mode of described SA-F/F logical circuit.In addition, realize that simultaneously reducing power consumption also is one of main target.

In DCSL circuit 40, the electric current that flows into logic tree 41 is subjected to the control of nmos pass transistor NT43 and NT44.

As mentioned above, the nmos pass transistor that becomes logical one one side place in logic evaluation is handled becomes and ends.

For this reason, the current potential of the logic output node TF of logic tree 41 and TF_X only begins to have slightly rising from the logical zero current potential.The rising a little of the logic output node TF of logic tree 41 and TF_X current potential amplitude means that the current potential amplitude of node in the described logic tree is still less than this amplitude.

Square being directly proportional of power consumption and described logic amplitude, therefore, the power consumption of described logic tree part is compared very little with the power consumption of the SA-F/F logical circuit that uses same NMOS pair of main line type logic trees.

In addition, in described SA-F/F logical circuit, described logic tree is high more, and the time that arrives last definite described logic is just long more.

But, in the DCSL circuit, logic determine the time to the dependence of described logic tree height less (above-mentioned text, pp.948, Figure 18).This also is to become the cause of ending because of nmos pass transistor NT42 before flowing into logic tree 41 at too big electric current and NT44.

Before the logic output node TF of logic tree 41 and TF_X fluctuation are too big, determine described logic in sensor amplifier 42 1 sides, therefore, the SA-F/F logical circuit that has than great fluctuation process with the logic tree node compares, and the inherent characteristic of described DCSL circuit is exactly the influence that can bear described logic tree height.

But above-mentioned first to the 4th traditional circuit has following problems.

The problem of first conventional example

One of problem of the static cmos logic circuit of explaining as first conventional example is the big power consumption that causes owing to misoperation.

The thought of " misoperation " is meant the rub-out signal transmission that takes place moment at output node of described combinational logic circuit or intermediate node place.

In described CMOS logical circuit, its power consumption P is provided by following equation, and wherein, signal frequency is f, and gate capacitance, interconnect capacitance etc. is C, and the signal amplitude current potential is V:

P＝f·C·V ² ...(1)

When misoperation took place, described signal frequency looked and becomes very big that power consumption increases according to the relation of above-mentioned equation (1).

Below, referring to the situation after Fig. 9 A and the 9B explanation generation misoperation.

In Fig. 9 A and 9B, the initial logic current potential of supposing input signal A, B, C and D is " 0 ", " 0 ", " 1 " and " 1 ", and the logic current potential of logic function output F is fixed to " 1 ".Suppose that in addition described input signal does not take place simultaneously at A, B, C and D place, but occurring in sequence according to A, B, C and D.

When described input signal A became logical one, the logic function of logical circuit LC11 output F11 moved on to logical zero.Then, when input signal B became logical one, logic function output F11 moved on to logical one.In addition, when input signal C became logical zero, logic function output F11 moved on to logical zero.At last, when input signal D became logical zero, logic function output F11 moved on to logical one.

Here the signal transmission of performed logic function output F11 is according to the correct assessment result output of variation of input signal in this example.There is not the mistake that comprises in the independent signal transmission of per second.

But the initial value of logic function output F11 is " 1 " and also become " 1 " at last, and therefore, the signal transmission in this time is unwanted, and therefore, it still is referred to as the signal of mistake.

In addition, even input signals takes place simultaneously, also misoperation may take place.Suppose that the current potential of stating node in time t place is represented as A (t)=1.In addition, the output of supposing described logic gate is following being determined by the input that moves ahead:

R(t)＝B(t-1)(+)C(t-1) (2)

In equation (2), under the situation of original state t=0,

Input signal: A (0)=0, B (0)=0, C (0)=1, D (0)=1,

Intermediate node: R (0)=1, S (0)=0,

Output node: F (0)=1.

When t=1, input signal moves together,

Input signal: A (1)=1, B (1)=1, C (1)=0, D (1)=0,

Intermediate node: R (1)=1, S (1)=0,

Output node: F (1)=1.

When t=2,

Input signal: A (2)=1, B (2)=1, C (2)=0, D (2)=0,

Intermediate node: R (2)=1, S (2)=^ (R (1) D (1))=1,

Output node: F (2)=^ (A (1) (+) S (1))=0.

When t=3,

Input signal: A (3)=1, B (3)=1, C (3)=0, D (3)=0,

Intermediate node: R (3)=1, S (3)=^ (R (2) D (2))=1,

Output node: F (3)=^ (A (2) (+) S (2))=0.

After this, it becomes constant.Attention: ^ represents anti-phase.

As mentioned above, described logic function output is moved in the mode of 1-0-1.Even provide described input signal simultaneously, also described misoperation can take place.

This is because the quantity difference of described interior section logic gate causes.Doing as a whole input is A, B, C and D, and still, the input of logic gate ENR11 shown in Figure 3 itself is the output signal S of input signal A and logic gate NA11.Signal S changes after logic gate ER11 changes owing to the variation of input signal B and C, and therefore, the phase place that signal A and signal S change does not become equal.

Therefore, when watching the input of described door, described misoperation consequently takes place in the difference in that its side signal transmission face still exists signal to transmit.

In aforesaid example, aspect input signal, there is not misoperation.Described misoperation be because the mistiming that described input signal and M signal change causes.This misoperation will be referred to as " generation misoperation " especially.

On the contrary, the described misoperation that is referred to as " propagation misoperation " that exists certain to produce by the misoperation that is included in the described input signal.

In Fig. 9 A and 9B, when input signal D=1, the logic function that is implemented is become F11=A (+) B (+) C.Even two in three input signals are fixed to certain logical value, if having misoperation in a remaining input, also misoperation will take place at output F11 place.

For example, when misoperation taking place at the A place and have 0 → 1 → 0 variation, do not consider the situation of original A=B=C=0, output F11 also will change according to 0 → 1 → 0.

As mentioned above, the factor that produces misoperation at first is that the 3rd is because the misoperation that comprises in described input signal because secondly the variation in input signal transmission time is the variation because of the input transmission that causes in the inner delay difference that produces of combinational logic circuit.

Causing under the situation of misoperation that owing to these three kinds of factors described logical circuit is according to the correct logical value of input signal output in that moment.Logical circuit itself can not determine that it is exporting an incorrect value in that moment.

In order to eliminate above-mentioned first and second factors, need a kind of the insertion to be used to regulate so that make the method for the very accurate delay element that described signal changes according to all logic gates inputs of described interior section to described internal signal wire, and in order to eliminate the 3rd factor, considering a kind of judge described signal effectively/be used to represent to be used for the method for two signal wires of a logical value of definite described logic in invalid.

But, because implement very difficulty, hardware cost increases and power attenuation greater than the minimizing of described misoperation, so these methods all are very unpractiaca.

Therefore, in principle, the misoperation of eliminating fully in the general static cmos logic circuit is difficult, and does not accomplish.

The problem of second conventional example

Maximum characteristic in the PDN-F/F logical circuit characteristic of explaining as second conventional example be produce as described in the mechanism of pulse clock PCLK (pulse producer 23 among Fig. 3).

In principle, if the quantity (highly) of the nmos pass transistor that is connected in series of described pulse producer 24 be adjusted to described PDN, be that the height of described logic tree 23 is complementary, so, can obtain the optimum width of described pulse clock PCLK.

But in fact, even described height is identical, the size on the branch line direction also is different, therefore, can not correctly reappear the speed that node TF changes among the PDN in the pulse producer 24.The expansion of size means the expansion of described MOS junction capacity and interconnect capacitance on the branch line direction.

In addition, when pulse producer 24 as the body portion of an independent unit and PDN-F/F logical circuit from the time, also will have metal interconnection through an interconnection layer between the pulse clock input end of the pulse clock output terminal of pulse producer 24 and PDN-F/F logical circuit main body.

In the LSI design, utilize CAD to form the layout and the path of described unit automatically usually.At this moment, interconnected between the unit that is provided with by described CAD is not constant.Predict that in advance they are very difficult.

When this designing technique is applied to the PDN-F/F logical circuit, design for each, the interconnect length of the pulse clock PCLK that extends from pulse producer 24 changes.Metal interconnection has stray capacitance and its size and is directly proportional with interconnect length usually, therefore, designs for each, and the load that is connected on the pulse clock output terminal of pulse producer 24 changes.

As long as described interconnected load changes, the width of described pulse clock PCLK also changes forever.The amplitude of pulse clock PCLK is to determine that directly the PDN-F/F logical circuit is provided with the key element of time and retention time.

Therefore, when being carried out layout by described CAD and the path is set, the PDN-F/F logical circuit will not have the constant time that is provided with and retention time.Design for the LSI that is used for timing analysis, describedly is set and the retention time is very important value the time.If can not find correct value, just realize described circuit till the ass ascends the ladder in practical layout with before the path is set.

On the contrary, thereby make up mutually when forming a logical block when pulse producer 24 and described PDN-F/F logical circuit, the large scale of the circuit of pulsing circuit 24 has become a problem.

Except described logic tree is not to go alone line style but the two logic trees of two main line type, the SA-F/F logical circuit does not have anything corresponding with pulse producer 24.

Under the situation of SA-F/F logical circuit, it approximately is the twice of described size that the circuit of described logic tree becomes, and still, if consider the circuit size of pulse producer 24, described SA-F/F logical circuit becomes tightr through regular meeting.

The problem of the 3rd conventional example

As the problem of the SA-F/F logical circuit explained in the 3rd conventional example be final determine as described in time before the logic be too dependent on the charge discharge speed of NMOS logic tree.

Node TF shown in Figure 6 and TF_X are given being charged to be lower than the logical one current potential and to be accurate to a current potential of described threshold quantity before the described logic evaluation of beginning.

With the described logic evaluation of beginning, electric charge is through described NMOS logic tree 31 discharges.The current potential of two node TF and TF_X finally all becomes the logical zero current potential, but in them one always arrives described logical zero early than another.The node that early becomes logical zero is one relevant with final definite described logic.

When the nmos pass transistor that will become conducting was simply regarded a resistance as, the time that described node arrives the logical zero current potential was to be determined by the resistance R of nmos pass transistor on the grounding path and the capacitive component C in the logic tree 31.

Briefly, the time that is used to arrive the logical zero current potential is directly proportional with (C that total R is total).When the grid width of nmos pass transistor is Wn and grid length when being Ln, conducting resistance R is directly proportional with (Ln/Wn).

When from the terminal point of described logic tree to the path on ground transistorized quantity, be the height of described logic tree when being h, can think that total R is proportional to (h/Wn).Here, usually, Ln is a fixed value of being determined by the manufacturing processing, omits the description to it here.

Described total C comprises the NMOS diffusion capacitance of inside such as logic tree 31 and is in according to the dull relation that increases of the height of described logic tree.

Therefore, be used for finally determining that the time of the logic of described SA-F/F logical circuit is proportional to the height of described NMOS logic tree usually and is inversely proportional to grid width Wn usually.

The height of described logic tree equals the input signal amount of the logic function that will be implemented substantially.For example, if it is a 5-input EXOR, then the height of described logic tree becomes 5.

Therefore, described logic function complicated more (input signal quantity is big more) is used for then finally determining that time of logic of described SA-F/F logical circuit is just long more.

When the hope minimizing was used for finally determining the time-lag of described logic in this manner, what the grid width of nmos pass transistors was made in the described logic tree 31 was bigger, thereby makes conducting resistance R smaller.When gate terminal one side that drives it is watched, the capacitive component that described nmos pass transistor had is proportional to (WnLn).As mentioned above, power consumption is proportional to the capacitive component of described system.

Therefore, in SA-F/F logical circuit 30, can not realize the increase and the reduction in power consumption of speed simultaneously.

The problem of the 4th conventional example

As in above-mentioned reference, pointing out, significantly be subjected to the influence of fluctuation, noise etc. in the circuit constancy easily as the DCSL circuit 40 of the 4th conventional example by itself.

In the original state of flip-flop operation, node TH and TH_X are by short circuit and be initialized to voltage near described NMOS threshold value in the sensor amplifier 32.

When inversion clock signal CLK_X becomes logical zero (when described CLK rises), described two nodes are cut off, poor according to the magnitude of current of node TF that flows into described logic tree and TF_X taken place in the current potential of node TH and TH_X, and this difference is comprised the phase inverter of PMOS transistor PT42 and PT43 and nmos pass transistor NT41 and NT42 to expansion, final then definite described logical value.

If the incorrect potential fluctuation that causes owing to coupled noise or other noise takes place at node H or H_X place, just may finally determine the logical value of a mistake in this is handled.Even that incorrect potential fluctuation very faint (about described logic amplitude 1/10 to 1/20), node TH that described work begins to locate and the potential fluctuation of TH_X are also very little, and therefore, described node is easy to be subjected to their influence.

For example, consider that correct logical value determines to become H=0 and H_X=1 and be added to situation above it at the noise that node TH stays current potential.

Logic tree node TF has the path of ground connection.Electric charge on the node TH flows through nmos pass transistor NT43.

But the voltage that is added on the grid of this nmos pass transistor NT43 does not have other current potential and this voltage to be slightly larger than the threshold value of described nmos pass transistor except the current potential of node TH_X.

For this reason, nmos pass transistor NT43 does not become sufficient conducting and can think that its conduction resistance is very big.Therefore, the incorrect potential fluctuation that rises owing to noise can be reduced immediately.Under the situation of the current potential of node TH greater than the current potential of node TH_X, utilize the function of sensor amplifier 42 that described logical value is defined as H=0 and T_X at that time.

Even when not having coupled noise, because the logical value of a mistake also can be finally determined in the variation of circuit stability sometimes.

For example, consider to determine to become to be connected to the situation of the stray capacitance of node TH under H=0 and the H_X=1 situation less than the stray capacitance that is connected to node TH_X in described correct logical value.

When described trigger is started working, because the electric charge that provides to PT43 through PMOS transistor PT41 makes the current potential of two nodes that rising all be arranged slightly.

Because the node TF of logic tree has the path of a ground connection, so when finally having determined a correct logic, the rising of node TH current potential is slower than the rising of node TH_X.

In sensor amplifier 42, amplify the potential difference (PD) that produces by this way and it is confirmed as a correct logical value.

But when the stray capacitance that is connected to node TH and TH_X existed tangible difference and node TH_X very big, the rising of node TH_X was slower than node TH.

The electric charge that offers node TH at first flows to logic tree 41 through nmos pass transistor NT43, so it must be maintained at the current potential that is lower than node TH_X.

But as mentioned above, nmos pass transistor NT43 is not by abundant conducting, and it is very big that its conduction resistance is considered to, so the difference of stray capacitance can not fully be absorbed.

In this manner, there is a kind of node phenomenon,, should slowly rises mistakenly and the final logical value of determining a mistake by zooming current potential originally at this node place.

Even under the situation about changing in network constant or coupled noise, its basic problem is that still nmos pass transistor NT43 and NT44 have the function of cutting apart sensor amplifier 42 and logic tree 41.

Determine in the work disposal that in logic be added to the threshold value that voltage on nmos pass transistor NT43 and the NT44 grid is slightly larger than described nmos pass transistor, therefore, the conduction resistance of these nmos pass transistors is considered to the conduction resistance greater than the nmos pass transistor of conducting.

The value of described impedance can not absorb because the incorrect potential fluctuation that coupled noise produces.

Summary of the invention

An object of the present invention is to provide a kind of logical circuit, this circuit is applicable to that the characteristic of a dynamic logic circuit that is obtained by combinational logic tree, sensor amplifier and SR latch by good use eliminates the misoperation that takes place to reduce power consumption and can realize high speed operation in the static cmos logic circuit.

In addition, second purpose of the present invention provides a kind of logical circuit, and this logical circuit provides two main line type logic trees so that give up being used to produce the mechanism with short pulse width and can passing through the CAD autoplacement and the wiring simplified design such as the PND-F/F logical circuit.

In addition, the 3rd purpose of the present invention provides a kind of logical circuit, this circuit makes operating rate to the degree of dependence of the grid width of MOS in described logic tree height and the described logic tree corresponding degree of dependence less than described SA-F/F logical circuit, even and also can realize high speed operation under the situation of the complex logic function that realizes having a lot of input signals.

In addition, the 4th purpose of the present invention provides a kind of logical circuit, and this circuit can bear the variation of network constant and coupled noise and can realize the work more stable than DCSL circuit.

According to a first aspect of the invention, provide a kind of logical circuit that is used for the synchronous output logic functional assessment of a synchronizing signal result, having comprised:

Two main line type logic trees that are used to form a path and realize desired logic function wherein, have only a main line to arrive a reference potential through described path according to input signal;

A sensing latch unit has:

Be used to receive first logic input node and second logic input node that described pair of main line type is connected to output of first logic and the output of second logic;

The first logic output node;

The second logic output node;

A sensor amplifier, this sensor amplifier are pointed out in reception to work on the basis of the described synchronizing signal that drives and finally are set to the first different level and second level according to the logic current potential that the conduction resistance difference that is had by first logic input that inputs to the described first logic output node and the second logic output node and the input of second logic will described first logic be exported and second logic is exported;

First conversion equipment is used for the short circuit first logic output node and the second logic output node when the synchronizing signal of dummy status is pointed out in one of reception;

Second conversion equipment is used for connecting or disconnecting described first logic input node and the first logic output node according to the potential point of a control end;

The 3rd conversion equipment is used for connecting or disconnecting described second logic input node and the second logic output node according to the potential point of described control end; With

A logic tree disconnects control device, has:

First setting device, the current potential that is used for being connected to the control node on the control end of described second conversion equipment and the 3rd conversion equipment be set at least comprise wherein in sensor amplifier does not also have finally to determine the state of dummy status of described logic, be connected described second and two ends of the 3rd conversion equipment between the current potential that connects; With

Second setting device is used for being electrically connected or disconnecting described first logic input node and the first logic output node according to the current potential of a control end;

The set and the latch units that resets, be used for receiving first logic output of described sensing latch unit in its set termination, reset terminal at it receives second logic output of described sensing latch unit, and keeps the logic of described sensing latch unit to export the time cycle that reaches described synchronizing signal one-period.

In addition, in the present invention, first setting device that described logic tree disconnects control device comprise be connected can described second conversion equipment and the 3rd conversion equipment be incorporated between first power supply potential of connection status and the described control node and receive the 4th conversion equipment that becomes conducting on the basis of the synchronizing signal of pointing out described dummy status at its control end, second setting device of described logic tree disconnection control device comprises and is connected and described second conversion equipment and the 3rd conversion equipment can be incorporated between the second source current potential and described control node of off-state, have the control end that is connected to the described first logic output node and when the described first logic output potential is in described first level, become the 5th conversion equipment of conducting and be connected described second source current potential and described control node between, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 6th conversion equipment of conducting.

In addition, in the present invention, first setting device that described logic tree disconnects control device comprise be connected can described second conversion equipment and the 3rd conversion equipment be incorporated between first power supply potential of connection status and the described control node and point out to become on the basis of synchronizing signal of dummy status the 4th conversion equipment of conducting in its control end reception, second setting device that described logic tree disconnects control device comprises and being connected between an intermediate node and the described control node, have the control end that is connected to the described first logic output node and when the described first logic output potential is in described first level, become the 5th conversion equipment of conducting, be connected between described intermediate node and the described control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 6th conversion equipment of conducting, and be connected between the second source current potential that described second conversion equipment and the 3rd conversion equipment can be incorporated into off-state and the described intermediate node and when described the 4th conversion equipment conducting, remain on nonconducting state, when remaining on nonconducting state, described the 4th conversion equipment becomes the 7th conversion equipment of conducting state.

In addition, in the present invention, first setting device that described logic tree disconnects control device comprises that be connected in series in can described second conversion equipment and the 3rd conversion equipment is incorporated into that first power supply potential of connection status and one control between the node and become the 4th conversion equipment and the 5th conversion equipment of conducting by the current potential that receives the current potential of the described first logic output node and the described second logic output node at their control end under dummy status, and described logic tree second setting device that disconnects control device comprises and is connected and described second conversion equipment and the 3rd conversion equipment can be incorporated between the second source current potential and described control node of off-state, have the control end that is connected to the described first logic output node and when the described first logic output potential is in described first level, become the 6th conversion equipment of conducting, and be connected between described second source current potential and the described control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 7th conversion equipment of conducting.

According to a second aspect of the invention, provide a kind of and the logical circuit synchronous output logic functional assessment of a synchronizing signal result, comprise the two main line type logic trees that are used to form a path and realize desirable logic function, through described path, have only a main line to arrive described reference potential according to input signal; Have the output of first logic and first logic input node of second logic output and the sensing latch unit of second logic input node that receive described pair of main line type logic tree; The first logic output node; The second logic output node; Point out in reception to work on the basis of synchronizing signal of described driving and the final logic current potential that described first logic of difference is exported and second logic is exported according to first logic input that inputs to described first logic input node and second logic input node and the conduction resistance that the input of second logic has is set to the first different level and the sensor amplifier of second level; First conversion equipment is used for the described first logic output node of short circuit and the second logic output node when receiving synchronizing signal pointing out dummy status; Second conversion equipment is used for being electrically connected or disconnecting described first logic input node and the described first logic output node according to the current potential of described control end; The 3rd conversion equipment is used for being electrically connected or disconnecting described second logic input node and the described second logic output node according to the current potential of described control end; Disconnect control device with a logic tree, this device have be used for comprise wherein said logic also not the current potential that sensor amplifier is connected to the described control node on the control end of described second conversion equipment and the 3rd conversion equipment under by the state of the final dummy status of determining be set at least can be connected described second and two ends of the 3rd conversion equipment between first setting device of the current potential that connects, and be used for described therein logic sensor amplifier be set to according to the current potential of the described control node of current potential of the first logic output node or the second logic output node under by the final state of determining at least can be connected described second and two ends of the 3rd conversion equipment between carry out second setting device of the current potential that disconnects; The set and the latch units that resets are used at it termination being set and receive first logic output of described sensing latch unit, receive second logic output of described sensing latch unit and the time cycle that the logic output of described sensing latch unit is kept the one-period of described synchronizing signal at its reset terminal; The 4th conversion equipment is used under dummy status electricity and disconnects the path of the reference potential that arrives described pair of main line logic tree and reference potential and locate to be connected them in the time except that described dummy status.

In addition, in the present invention, first setting device that described logic tree disconnects control device comprise be connected can described second conversion equipment and the 3rd conversion equipment be incorporated between first power supply potential of connection status and the described control node and point out to become on the basis of synchronizing signal of described dummy status the 5th conversion equipment of conducting in its control end reception, second setting device that described logic tree disconnects control device comprises and is connected and described second conversion equipment and the 3rd conversion equipment can be incorporated between the second source electric potential and described control node of off-state, have the control end that is connected to the described first logic output node and when the described first logic output potential is in described first level, become the 6th conversion equipment of conducting, and be connected between described second source current potential and the described control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 7th conversion equipment of conducting.

In addition, in the present invention, first setting device that described logic tree disconnects control device comprise be connected can described second conversion equipment and the 3rd conversion equipment be incorporated between first power supply potential of connection status and the described control node and point out to become on the basis of synchronizing signal of described dummy status the 5th conversion equipment of conducting in its control end reception, second setting device that described logic tree disconnects control device comprises and being connected between an intermediate node and the described control node, have the control end that is connected to the described first logic output node and when the described first logic output potential is in described first level, become the 6th conversion equipment of conducting, be connected between described intermediate node and the described control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 7th conversion equipment of conducting, and be connected and described second conversion equipment and the 3rd conversion equipment can be incorporated between the second source current potential and described intermediate node of off-state, when described the 5th conversion equipment conducting, be in nonconducting state and when described the 5th conversion equipment is in nonconducting state, become the 8th conversion equipment of conducting.

In addition, in the present invention, first setting device that described logic tree disconnects control device comprises the 5th conversion equipment and the 6th conversion equipment that is connected in series between first power supply potential that described second conversion equipment and the 3rd conversion equipment can be incorporated into connection status and the described control node and becomes conducting on the basis at the current potential of the current potential of their control ends first logic output node and the second logic output node under the described dummy status, second setting device that described logic tree disconnects control device comprises and is connected and described second conversion equipment and the 3rd conversion equipment can be incorporated between the second source current potential and described control node of off-state, have the control end that is connected to the described first logic output node and when the described first logic output potential is in described first level, become the 7th conversion equipment of conducting, and be connected between described second source electric potential and the described control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 8th conversion equipment of conducting.

According to a third aspect of the invention we, a kind of logical circuit that is used for the synchronous output logic functional assessment of a synchronizing signal result is provided, comprise the two main line type logic trees that are used to form a path and realize desired logic function, have only a main line to arrive described reference potential through described path according to input signal; Have the output of first logic and first logic input node of second logic output and the sensing latch unit of second logic input node that are used to receive described pair of main line type logic tree; The first logic output node; The second logic output node; Point out in reception to work on the basis of the synchronizing signal that drives and finally to be defined as the first different level and the sensor amplifier of second level according to poor current potential with the described first logic output node and the second logic output node by first logic input that inputs to described first logic input node and second logic input node and the conduction resistance that the input of second logic has; First conversion equipment is used for the described first logic output node of short circuit and the second logic output node when receiving the synchronizing signal of pointing out dummy status; Second conversion equipment is used for being electrically connected or disconnecting described first logic input node and the described first logic output node according to the current potential of described control end; The 3rd conversion equipment is used for being electrically connected or disconnecting described second logic input node and the described second logic output node according to the current potential of described control end; Disconnect control device with a logic tree, have be used for the current potential that is included in described sensor amplifier and does not also have finally to determine to be connected under the state of dummy status of described logic a control node on the control end of described second conversion equipment and the 3rd conversion equipment be set at least can be connected described second and two ends of the 3rd conversion equipment between the current potential that connects first setting device and be used for being set to can disconnect at least according to the current potential of the described control node of current potential of the described first logic output node and the second logic output node under by the final state of determining being connected described second and second setting device of the current potential of two ends of the 3rd conversion equipment at described sensor amplifier in described logic; The set and the latch units that resets, be used for receiving first logic output of described sensing latch unit, receive second logic output of described sensing latch unit and the logic of described sensing latch unit is exported the time cycle that keeps described synchronizing signal one-period at its reset terminal in its set termination; The 4th conversion equipment is used under dummy status electricity and is disconnected to the path of the reference potential of described pair of main line type logic tree and described reference potential and locates to be connected them in the time except that dummy status; The 5th conversion equipment, be used to force the reference potential that is connected to described pair of main line type logic tree and the path of described reference potential to reach a time cycle, in this cycle, utilize the 4th conversion equipment under the dummy status and be disconnected to the path of described pair of main line type logic tree reference potential and described reference potential when when described synchronizing signal is pointed out described dummy status itself, being stopped.

In addition, in the present invention, first setting device that described logic tree disconnects control device comprise be connected can described second conversion equipment and the 3rd conversion equipment be incorporated between first power supply potential of connection status and the described control node and point out to become on the basis of synchronizing signal of described dummy status the 6th conversion equipment of conducting in its control end reception, second setting device that described logic tree disconnects control device comprises and is connected and described first conversion equipment and second conversion equipment can be incorporated between the second source current potential and described control node of off-state, have the control end that is connected to the described first logic output node and when the described first logic output potential is in described first level, become the 7th conversion equipment of conducting, and be connected between described second source current potential and the described control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 8th conversion equipment of conducting.

In addition, in the present invention, first setting device that described logic tree disconnects control device comprise be connected can described second conversion equipment and the 3rd conversion equipment be incorporated between first power supply potential of connection status and the described control node and point out to become on the basis of synchronizing signal of described dummy status the 6th conversion equipment of conducting in its control end reception, second setting device that described logic tree disconnects control device comprises and being connected between an intermediate node and the described control node, have the control end that is connected to the described first logic output node and when the described first logic output potential is in described first level, become the 7th conversion equipment of conducting, be connected between described intermediate node and the described control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 8th conversion equipment of conducting, and be connected between the second source current potential that described second conversion equipment and the 3rd conversion equipment can be incorporated into off-state and the described intermediate node and when described the 6th conversion equipment is switched on, remain on nonconducting state and when described the 6th conversion equipment is maintained at nonconducting state, become the 9th conversion equipment of conducting.

In addition, in the present invention, first setting device that described logic tree disconnects control device comprises and being connected in series between first power supply potential that described second conversion equipment and the 3rd conversion equipment can be incorporated into the connection status state and the described control node and at the 6th conversion equipment and the 7th conversion equipment that become conducting under the described dummy status on their control ends receive the basis of the first logic output node current potential and the second logic output node current potential, second setting device that described logic tree disconnects control device comprises and is connected and described second conversion equipment and the 3rd conversion equipment can be incorporated between the second source current potential and described control node of off-state, have the control end that is connected to the described first logic output node and when the described first logic output potential is in described first level, become the 8th conversion equipment of conducting, and be connected between described second source current potential and the described control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 9th conversion equipment of conducting.

In addition, in each logical circuit according to the present invention, the sensor amplifier of described sensing latch unit has first phase inverter and second phase inverter, the input of the output of first phase inverter and second phase inverter is interconnected, their tie point is connected to the described first logic output node, the output of the input of first phase inverter and second phase inverter is interconnected, their tie point is connected to the described second logic output node, and described first conversion equipment is connected between the input of the input of first phase inverter and second phase inverter.

According to the present invention, have in the sensing latch unit of the logical zero of pointing out described dummy status in for example described synchronizing signal, described sensor amplifier does not have driving force, first conversion equipment, second conversion equipment and the 3rd conversion equipment become conducting state.

The result is, in described sensing latch unit, present and be transfused to the first logic output node that the output of described logic tree is arranged, be transfused to and second logic of described logic tree output input node is arranged, be used for exporting the first logic output node of described first logic output and being used for exporting the second logic output node of second logic output all by the state of short circuit to the described set and the latch units that resets to described set and the latch units that resets.

Under this dummy status the driving condition of described synchronizing signal after logical zero becomes logical one, described sensor amplifier has driving force, described first conversion equipment becomes nonconducting state, described second with the 3rd conversion equipment and the same conducting state that remains on originally.

Therefore, in this driving condition, the first logic output node, first logic input node and the second logic output node, second logic input node are all by short circuit.Therefore, present the first logic output node and first logic input node and the second logic output node and all d/d state of second logic input node that is under the short-circuit condition.

Final determine synchronizing signal after the described logical value have cycle of logical one during in (finally definite state), described sensor amplifier has driving force, presents the state that the first logic output node and first logic input node and the second logic output node and second logic input node all are disconnected.

In addition, according to the present invention, become logical zero (dummy status) and electric charge in described synchronizing signal and flow to from sensing latch unit and the described pair of main line type logic tree in described reference potential, promptly time cycle and utilize the 4th conversion equipment to avoid described logic tree and described reference potential to be disconnected by electricity.

For this reason, can realize reduction in power consumption.

In addition, according to the present invention, stop at logical zero and the 4th conversion equipment continues to become under the situation of nonconducting state in for example described synchronizing signal, described the 5th conversion equipment remains on conducting state.

For this reason, the inside node in described sensing latch unit and the two main line type logic tree can be fixed on the current potential of complete logical zero.The result is the leakage current that can reduce in the set and the latch units that resets.

Description of drawings

By below in conjunction with the description of accompanying drawing to most preferred embodiment, it is clearer that these and other objects of the present invention and characteristic will become.Wherein

Fig. 1 show utilize that the static cmos logic circuit realizes comprise a trigger and in the general structure of first conventional example of a plurality of logic gates of its input end;

The circuit of Fig. 2 shows the transistor layer of trigger shown in Figure 1;

The circuit of Fig. 3 shows combinational logic circuit example of structure shown in Figure 1;

The circuit of Fig. 4 shows the general structure of PDN-F/F logical circuit;

The circuit of Fig. 5 shows the example of the PDN-F/F logical circuit concrete structure of the logic function that is used for installing a multiplexer thereon;

The circuit of Fig. 6 shows the general structure of SA-F/F logical circuit;

The circuit of Fig. 7 shows the example of the SA-F/F logical circuit concrete structure of the logic function that is used for installing a multiplexer thereon;

The circuit of Fig. 8 shows the general structure of DCSL circuit;

Fig. 9 A and 9B are used to explain the problem of first conventional example;

The block diagram of Figure 10 shows first most preferred embodiment of the logical circuit according to the present invention;

The circuit of Figure 11 shows in logical circuit shown in Figure 10 the example of the concrete structure of two main line type logic trees parts and SR latch units;

Figure 12 is used to explain the basic structure of the sensing latch unit according to the present invention;

Figure 13 is used for explaining according to the present invention the groundwork of described sensing latch unit under " dummy status ".

Figure 14 is used for explaining according to the present invention the groundwork of described sensing latch unit under " driving condition ";

Figure 15 is used for explaining according to the present invention the groundwork of described sensing latch unit under " finally determining state ";

The circuit of Figure 16 shows first object lesson according to sensing latch of the present invention unit;

The circuit of Figure 17 shows second object lesson according to sensing latch of the present invention unit;

The circuit of Figure 18 shows the 3rd object lesson according to sensing latch of the present invention unit;

Figure 19 shows the described traditional cmos logical circuit of Fig. 4 and according to the current waveform of logical circuit of the present invention;

Figure 20 shows the work time-delay characteristics of described static cmos logic circuit;

Figure 21 shows the work time-delay characteristics of the logical circuit according to the present invention;

Figure 22 show at the SA-F/F logical circuit and in a circuit according to the invention with respect to the TCQ characteristic of described logic tree height;

Figure 23 show at the SA-F/F logical circuit and in a circuit according to the invention with respect to the TCQ characteristic of the NMOS size (Wn) of described logic tree;

Figure 24 shows a kind of processing, handle by means of this, according to sensing latch of the present invention unit absorb incorrect potential fluctuation and the most at last current potential be set to correct logical value;

The block diagram of Figure 25 shows second most preferred embodiment of the logical circuit according to the present invention;

The circuit of Figure 26 shows the example of two main line type logic tree parts of NMOS described in the described logical circuit of Figure 25 and SR latch units concrete structure;

The block diagram of Figure 27 shows the 3rd most preferred embodiment of the logical circuit according to the present invention;

The circuit of Figure 28 shows the example of two main line type logic tree parts of NMOS described in the logical circuit shown in Figure 27 and SR latch units concrete structure; With

Figure 29 shows the potential waveform at the work of SLEEP pattern and inner node TH in leakage current value analog result place and TH_X.

Embodiment

Below, most preferred embodiment is described in conjunction with the accompanying drawings.

First embodiment

The block diagram of Figure 10 shows first most preferred embodiment of the logical circuit according to the present invention.

Have the two main line type logic tree part of main structure element, NMOS as shown in figure 10 110, a SR latch units 120 and a sensing latch unit 130 that comprises sensor amplifier according to the logical circuit 100 of current first most preferred embodiment.

In the two main line type logic tree parts 110 of described NMOS, when the input signal of logic of propositions function be A1, A2 ..., An and their inversion signal A1_X, A2_X ..., when An_X provides together, a path that always has ground connection among described logic tree end TF and the TF_X, and another always presents high impedance status.

As long as the two main line type logic tree parts 110 of described NMOS satisfy this specific character, the method that realizes it so is unessential, and its structure can be shown in the example of Figure 11.

Specifically, the two main line type logic tree parts 110 of NMOS shown in Figure 11 show 4 input C, B, C and D and have nmos pass transistor NT1101 to NT1112.

In the two main line type logic tree parts 110 of NMOS, nmos pass transistor NT1101, NT1107 and NT1111 are connected in series between logic function output node TF1 and the ground.

In addition, nmos pass transistor NT1104, NT1106, NT1110 and NT1112 are connected in series between logic function output node TF_X1 and the ground.

Nmos pass transistor NT1102 is connected between the tie point of logic output node TF_X1 and nmos pass transistor NT1101 and NT1107, and nmos pass transistor 1103 is connected between the tie point of logic output node and nmos pass transistor NT1104 and NT1106.

In addition, the inversion signal A_X that obtains by the anti-phase described signal A at phase inverter INV101 place is provided for the grid of nmos pass transistor NT1101 and NT1104, and signal A is provided for the grid of nmos pass transistor NT1102 and NT1103.

Nmos pass transistor NT1105 is connected between the tie point of the tie point of nmos pass transistor NT1101 and NT1107 and nmos pass transistor NT1106 and NT1110.

In addition, be provided for the grid of nmos pass transistor NT1105 by the inversion signal D_X that obtains at the inversion signal D of phase inverter INV102 place, and signal D is provided for the grid of nmos pass transistor NT1106.

Nmos pass transistor NT1108 is connected between the tie point of the tie point of nmos pass transistor NT1106 and NT1110 and nmos pass transistor NT1107 and NT1111, and nmos pass transistor NT1109 is connected between the tie point of nmos pass transistor NT1101 and NT1107 and nmos pass transistor NT1110 and NT1112.

In addition, be provided for the grid of nmos pass transistor NT1107 and NT1110 by the inversion signal C_X that obtains at the inversion signal C of phase inverter INV103 place, and signal C is provided for the grid of nmos pass transistor NT1108 and NT1109.

In addition, be provided for the grid of nmos pass transistor NT1111 by the inversion signal B_X that obtains at the inversion signal B of phase inverter INV104 place, and signal B is provided for the grid of nmos pass transistor NT1112.

Described SR latch units 120 is at the logic output H of its set (S) termination receipts from the output node TH of described sensing latch unit 130, in its logic output of (R) termination receipts that resets from the output node TH_X of sensing latch unit 130, keep the logic output of described sensing latch unit 130 and hold output data from Q.

As long as described SR latch units 120 has such as the common set and the latch functions that reset by two Sheffer stroke gates or two rejection gate realizations, implementation method is unessential.

From the maintenance pattern that is used for S end and R end (with non-type) is that logical one and the maintenance pattern that is used for two ends (or/no type) are the logical zero this point, and exists difference between non-type and the or/no type.

For this reason, must suitably use them according to the output node TH of described sensing latch unit 130 and the polarity of TH_X.

The output node that is used for node TH and THZ-X under the dummy status (original state of flip-flop operation) that the polarity of described sensing latch unit 130 is pointed out to be installed in the back is the logical one or the difference of logical zero.

In logical circuit shown in Figure 11 100, described SR latch units 120 is realized by rejection gate NR121 and NR122.

In addition, in logical circuit shown in Figure 11 100, the two main line type logic tree parts 110 of described NMOS realize such as F=A (+) { logic function of (B (+) C) D}.

The current potential that is fixed to complete logical zero under with described dummy status in the existence of the irrelevant grounding path of logical value combination that exist in the middle of described logic tree node TF1 and TF_X1 one and input signal A, B, C and D is distributed to the output node TH and the TH_X of sensing latch unit 130.

As shown in figure 12, sensing latch unit 130 has a sensor amplifier 131 of working under drive controlling; One is used as the switch 132 that is used for being used for by this drive controlling short circuit described first conversion equipment of the node TH of logic output H and H_X and TH_X; A logic tree disconnects control module 133; One is used as and is used for disconnecting at described logic tree that the described node TH of short circuit and the input of described logic use node TF2 and node TH_X and logic input to use the switch 134 of described second conversion equipment of node TF_X under the control of control module 133; With the switch 135 that is used as the 3rd conversion equipment of described main structure element.

Here said drive controlling refers to described clock signal (synchronizing signal) CLK and its inversion signal CLK_X.

As mentioned above, there is not specified in more detail to realize the method for two main line type logic trees 110 of described NMOS and described SR latch units 120.Maximum characteristics of the present invention are described sensing latch unit 130.

Below, explain that with reference to the accompanying drawings the work of described sensing latch unit 130 defines and concrete 26S Proteasome Structure and Function.

Note, for the purpose of explaining, suppose that described logic function is to carry out synchronously with the rising edge of clock signal (synchronizing signal) CLK.

Shown in Figure 13,14 and 15, the work of sensing latch unit 130 can be divided into three grades, promptly described " dummy status ", described " driving condition " and described " finally determining state ".

As shown in figure 13, the time cycle of described clock signal clk with logical zero is referred to as " dummy status ".This is corresponding to so-called " original state of flip-flop operation ".

In this dummy status, utilize clock signal clk and its inversion signal CLK_X to point out that work does not begin, sensor amplifier 131 does not have driving force and irrelevant mutually with the current potential of node TH and TH_X.Switch 132 short circuit node TH and TH_X.

When the logical value on node TH and the TH_X was finally determined, logic tree disconnected control module 133 and points out

switch

134 and 135 be connected.

Whereby, node TH and TF2 and node TH_X and TF_X2 are by short circuit.

Here, even the logical value on node TH and the TH_X is not meaned that by the final time of determining the current potential of node H and H_X equates or they are different, so the also very little described logical value of its difference is unclear state.

In this dummy status, present node TH, TH_X, TF2 and TF_X2 all by the state of described switch short circuit.The logical value of node TH and TH_X points out to be used for the maintenance pattern of described SR latch units 120 at this moment.

Begin to be referred to as " driving condition " by the time cycle of the final time of determining from described clock signal clk from logical zero to the moment of logical one conversion to the logical value of node TH and TH_X.

As shown in figure 14, in this case, switch 132 become by and disconnect node TH and TH_X, simultaneously sensor amplifier 131 have driving force and with the current potential of node TH and TH_X mutually mutual interference and attempting make one in the middle of them to become logical zero and make another become logical one.

But the logical value of node TH and TH_X also is not determined.Formerly after the state, logic tree disconnects control module 133 and points out

switch

134 and 135 be connected and short circuit node TH and TF2 and node TH_X and TF_X2.

Therefore, between sensor amplifier 131 and logic tree node TF1 and TF_X1, disturb.Always there is one to have the path of ground connection and attempt and be drawn into logical zero among logic tree node TF1 and the TF_X1 with one among node TH and the TH_X.On the basis that receives this interference, node TH that has become identical and the current potential of TH_X begin to change to different directions.

Be referred to as " finally determining state " from being begun to turn back to the time cycle of the time of logical zero by the final moment of determining to clock signal clk from logical one in the logical value of node TH that preceding state, begins to change and TH_X.

As shown in figure 15, in this case, sensor amplifier 131 has driving force, and switch 132 becomes and ends, so, the maintenance that the current potential of node TH and TH_X is stabilized.

Under the logical value of node TH and TH_X became clearly situation, logic tree disconnects control module 133 to be pointed out that

switch

134 and 135 disconnects and is connected.

Whereby,

switch

134 and 135 becomes disconnection, and sensor amplifier 131 and logic tree 110 are disconnected by electricity.For this reason, even the grounding path of input signal after this and logic tree 110 changes, can not exert an influence to node TH and TH_X yet.

Therefore, under this state, even variation has taken place input signal, the current potential of node TH and TH_X also can not change and keep with being stabilized.

As mentioned above, only under driving condition, just need input signal to keep constant with respect to described logic function.

Even input signal has taken place to change under dummy status and described grounding path has become TF_X2 (TF_X1) from TF2 (TF1), node TF2 and TF_X2 also pass through switch 132,134 and 135 by short circuit, so, needn't consider it.

In addition, as described in front, logic tree 110 and sensor amplifier 131 are disconnected by electricity in final definite state, so also do not influence.In addition, disconnect control device 133 at approximate and described logic tree and point out that same timing place that disconnects carries out the insertion to described SR latch units.

As described in front, in described final definite state, the logical value of node TH and THX keeps with being stabilized.Even described circuit enters described dummy status after this, SR latch units 120 also is in the maintenance pattern, therefore continues to keep that value.

Therefore, this has guaranteed that the output of SR latch units 120 will become the steady state value from the rising edge of described clock signal clk to next rising edge.

In this manner, can realize having the work of the trigger of following embedding logic function, promptly in the extremely short time cycle that the rising edge from described clock signal (synchronizing signal) begins to input signal sampling, output this assessment of maintenance to its logic evaluation and in during the one-period of described clock signal (synchronizing signal).

Below, 16 to 18 detailed explanations comprise three concrete examples of the sensor amplifier 130 of above-mentioned principle of work with reference to the accompanying drawings.

Note, in the explanation below, suppose node TH and TH_X output logic " 0 " in described dummy status.In addition, suppose that also ground connection with described logic tree does not resemble the mode of being eliminated as shown in Figure 10 and uses described sensing latch unit.

First object lesson of sensing latch unit

The circuit of Figure 16 shows first object lesson according to sensing latch of the present invention unit.

As shown in figure 16, this sensing latch unit 130A have PMOS transistor PT1301 to PT1304, nmos pass transistor NT1301 to NT1307, first logic input node TF2, second logic input node TF_X2, the first logic output node TH, the second logic output node TH_X and input end of clock TCLK and TCLKX.

The grid of PMOS transistor PT1301 is connected to supply voltage V _DDPower lead, its drain electrode is connected on the source electrode of PMOS transistor PT1302 and PT1303.

The drain and gate of PMOS transistor PT1302 and nmos pass transistor NT1301 is interconnected each other to constitute phase inverter INV131.

The output node ND131 of phase inverter INV131 is made of the drain electrode tie point of PMOS transistor PT1302 and nmos pass transistor NT1301, and the input node ND132 of phase inverter INV131 is made of the tie point of their grids.

Similarly, the drain and gate of PMOS transistor PT1303 and nmos pass transistor NT1302 is interconnected each other to constitute phase inverter INV132.

The output node ND133 of phase inverter 132 is made of the drain electrode tie point of PMOS transistor PT1303 and nmos pass transistor NT1302, and the input node ND134 of phase inverter INV132 is made of their grid tie point.

In addition, the source ground of nmos pass transistor NT1301 and NT1302.

The output node NF131 of phase inverter INV131 is connected to input node ND134 and the logic output terminal TH of phase inverter INV132, and the output node ND133 of phase inverter INV132 is connected to input node ND132 and the logic output terminal TH_X of phase inverter INV131.

Sensor amplifier 131 is made of to PT1303 and NT1301 and NT1302 the PMOS transistor PT1301 with above-mentioned annexation.

Constitute the input node ND134 of the input node ND132 of phase inverter INV131 of sensor amplifier 131 and phase inverter 132, in other words the grid of nmos pass transistor NT1301 and the grid of nmos pass transistor NT1302 are connected through nmos pass transistor NT1303.

Nmos pass transistor NT1303 is used as switch 132.

Nmos pass transistor NT1304 is connected between logic output node TH and the logic input node TF2, and nmos pass transistor NT1305 is connected between logic output node TH_X and the logic input node TF_X2.

In addition, nmos pass transistor NT1304 is used as switch 134 and nmos pass transistor NT1305 is used as switch 135.

In addition, the source ground of nmos pass transistor NT1306 and NT1307, and their drain electrode is connected to the drain electrode of grid and the PMOS transistor PT1304 of nmos pass transistor NT1304 and NT1305 jointly.In addition, the source electrode of PMOS transistor PT1304 is connected to supply voltage V _DDPower lead on.

Logic tree disconnects control device 133 and is made of PMOS transistor PT1304 and nmos pass transistor NT1306 and NT1307.

Notice that described first setting device is made of PMOS transistor PT1304 and described second setting device is made of nmos pass transistor NT1306 and NT1307.

In addition, the grid of PMOS transistor PT1301 and the grid that is used as the nmos pass transistor NT1303 of switch 132 are connected to output terminal of clock TCLKX, and the grid of PMOS transistor 1304 is connected to output terminal of clock TCLK.

The grid of nmos pass transistor NT1306 is connected on the tie point of logic output terminal TH and nmos pass transistor NT1304, and the grid of nmos pass transistor NT1307 is connected on the tie point of logic output terminal TH_X and nmos pass transistor NT1305.

In having the sensing latch unit 130A of structure shown in Figure 16, in described dummy status, clock signal clk has logical zero, and inversion clock signal CLK_X has logical one.Therefore, PMOS transistor PT1301 become by and turn-off the electric current of sensor amplifier part 131, thereby make sensor amplifier 131 not have any driving force.

On the contrary, the PMOS transistor PT1304 of logic tree disconnection control module 133 becomes conducting and provides electric charge to node G.

In described initial conditions, the logic current potential of node TH and TH_X is " 0 ", so nmos pass transistor NT1306 and NT1307 become and end.

Therefore, described control node G is initialized to the current potential of logical one.

This makes logic tree disconnect control module 133 can point out to be used as the nmos pass transistor NT1304 of switch 134 and being connected of the nmos pass transistor NT1305 that is used as switch 135.

In addition, the nmos pass transistor NT1303 that is used as switch 132 becomes conducting by means of inversion clock signal CLK_X, and is used as the control of Electric potentials of the nmos pass transistor NT1304 of switch 134 and the controlled node G of nmos pass transistor NT1305 that is used as switch 135 and becomes conducting.

Whereby, node TH, TH_X, TF2 and TF_X2 are by short circuit.

At this moment, a path that always has ground connection among logic tree node TF1 and the TF_X1, therefore, the current potential of node TH, TF2 and TF_X2 is fixed to the current potential of complete logical zero.

In described driving condition, clock signal clk becomes logical one and inversion clock signal CLK_X becomes logical zero.

For this reason, PMOS transistor PT1301 becomes conducting, and nmos pass transistor NT1303 becomes and ends, and sensor amplifier 131 has driving force.

On the contrary, PMOS transistor NT1304 becomes and ends, and stopping to provide electric charge to control node G.

But in the initial conditions of described driving condition, the current potential of node TH and TH_X is complete logical zero, and nmos pass transistor NT1306 and NT1307 become and end.

For this reason, the electric charge on the control node G is saved, and the current potential of described control node G is maintained at logical one completely.Check definite state of described logic, make logic tree disconnect control module 133 and can still point out to be used as the nmos pass transistor NT1304 of switch 134 and being connected of the nmos pass transistor NT1305 that is used as switch 135.

Therefore, between sensor amplifier 131 and described logic interference has taken place, whereby, node TH and TH_X begin to change.

In described final definite state, one among node TH and the TH_X becomes logical one.Here suppose that it is node TH_X.

In this case, the nmos pass transistor NT1307 that logic tree disconnects control module 133 becomes conducting and goes up the leakage electric charge to node G, and whereby, the current potential of control node G becomes complete logical zero.

For this reason, the nmos pass transistor NT1305 that is used as the nmos pass transistor NT1304 of switch 134 and is used as switch 135 becomes and ends, and described sensor amplifier 131 and logic tree are turned off.

By checking the state of described logic, this makes described logic disconnect the disconnection that control module 133 can be pointed out to be used as the nmos pass transistor NT1304 of switch 134 and be used as the nmos pass transistor NT1305 of switch 135.

After this, circuit enters into dummy status, and clock signal clk becomes logical zero, and inversion clock signal CLK_X becomes logical one.

Whereby, the nmos pass transistor NT1303 that is used as switch 132 becomes conducting, and the charge balance on node TH and the TH_X distributes.

Simultaneously, thus the grid of nmos pass transistor NT1301 and NT1302 and the drain electrode be equivalent to a diode by short circuit.

Therefore, the current potential of node TH and TH_X is pulled down to rapidly near the threshold value of described nmos pass transistor.

Near the nmos pass transistor threshold value current potential is used as logical zero basically and handles, and therefore, nmos pass transistor NT1306 and NT1307 become and end.

Therefore, PMOS transistor PT1304 offers control node G with electric charge, and the current potential of described control node G is again initialised as complete logical one.

Receiving on this current potential electricity basis, the nmos pass transistor NT1304 that is used as switch 134 becomes conducting with the nmos pass transistor NT1305 that is used as switch 135, and sensor amplifier 131 is connected once more with described logic tree.

Be present in the electric charge that node TH and TH_X went up and be arranged near the current potential the nmos pass transistor threshold value and pulled down to ground through described logic tree 110.

In this manner, the current potential of node TH, TH_X, TF2 and TF_X2 is fixed as the current potential of complete logical zero once more.

Second object lesson of sensing latch unit

The circuit of Figure 17 shows second concrete example of the sensing latch unit according to the present invention.

The difference of this sensing latch unit 130B and sensing latch shown in Figure 16 unit 130A is that nmos pass transistor NT1308 is connected and is used as between the intermediate node MG and ground that described logic tree disconnects the source electrode tie point of nmos pass transistor NT1306 and NT1307 in the control module that the grid of this nmos pass transistor NT1308 is connected on the input end of clock TCLK.

Basic functional principle is identical with first concrete example shown in Figure 16, repeats no more here.

Owing to having added slightly different that nmos pass transistor NT1308 causes is the conversion process of determining state to dummy status from final.

In this switch process, ending of the conducting of PMOS transistor PT1304 and nmos pass transistor NT1306 and NT1307 takes place simultaneously.

For nmos pass transistor NT1306 and NT1307 are ended, utilize described NMOS diode balanced distribution electric charge on node TH and TH_X to become needs with the step that flows out electric charge.

For this reason, in the shown in Figure 16 first concrete example, there is a moment, at this place moment, whole electric current flow through nmos pass transistor NT1306 or NT1307 after PMOS transistor PT1304 conducting.

In contrast, in the shown in Figure 17 second concrete example, do not produce above-mentioned circulating current.

This is because with PMOS transistor PT1304 conducting the time, and nmos pass transistor NT1308 and same clock signal clk synchronously become and end.

The 3rd object lesson of sensing latch unit

The circuit of Figure 18 shows the 3rd concrete example of according to the present invention sensing latch unit.

The difference of this sensing latch unit 130C and Figure 16 and sensing latch shown in Figure 17 unit 130A and 130B is that described logic tree disconnects control module and has a static NOR logic circuit structure and replaced described dynamic NOR logic circuit structure with this.

Specifically, supply voltage V _DDPower lead and described control node G be connected with PT1306 to replace by two PMOS transistor PT1305 that are connected in series and describedly give charging and use PMOS transistor PT1304, the grid of PMOS transistor PT1305 is connected to logic output node TH, the grid of PMOS transistor PT1306 is connected to logic output node TH_X, and described logic tree disconnects control circuit and is made of static NOR circuit S-NOR.

In this sensing latch unit 130C, clock signal (synchronizing signal) CLK of node TH and TH_X current potential determines the disconnection of current potential and the described logic tree of control of switch node G according to the observation.

That is, in dummy status, node TH and TH_X have logical zero, and therefore, control node G is set to logical one.In described driving condition, a time point place that becomes logical one in node TH or TH_X, control node G is set to logical zero.

Because PMOS transistor PT1305 and PT1306 are connected in series, thus there is not electric current to flow, till node TH and TH_X turn back to logical zero and do not produce circulating current,

In addition, current the 3rd object lesson is that with respect to the advantage of first and second object lessons described logic tree disconnects control module clock signal (synchronizing signal) CLK when not required, so, can reduce additional clock signal (synchronizing signal) CLK.

To explain according to static cmos logic circuit of the present invention and a logical circuit concrete property result relatively by simulating below.

Misoperation in the static cmos logic circuit is the problem that exists in the described conventional example.Use the logic function and the input signal pattern (those signal patterns that described therein timing vicinity A, B, C and D change) that are used as example this moment to carry out the SPICE simulation.

Figure 19 shows traditional cmos logical circuit shown in Figure 4 and according to the current waveform of logical circuit of the present invention.

In Figure 19, horizontal ordinate express time, ordinate are represented electric current and voltage.

In addition, in Figure 19, the family curve of being pointed out by solid line is the current waveform of circuit of the present invention, and is the current waveform of traditional circuit by the family curve that dotted line is pointed out.

Can clearly be seen that from Figure 19 in described static cmos logic circuit, described logical circuit all will be worked when input signal changes, therefore expended electric current.

In contrast, clearly, with traditional circuit comparison, circuit of the present invention has reduced power consumption.

Below will more described static cmos logic circuit and the time-delay characteristics of logical circuit of the present invention.

Figure 20 shows the work time-delay characteristics of described static cmos logic circuit, and Figure 21 shows the work time-delay characteristics of the logical circuit according to the present invention.

In Figure 20 and 21, the horizontal ordinate express time, ordinate is represented voltage.

This has studied the be provided with time relevant with clock signal (synchronizing signal) CLK with input signal C, with input signal A and clock signal (synchronizing signal) CLK relevant retention time and with the relevant time-delay of output Q and clock signal (synchronizing signal) CLK (to the clock of Q: be called for short Tcq).

Different with common trigger, all input signals of described logic function all have the time that is provided with and the retention time based on clock signal clk.Most important signal is to be transferred to the signal of logic function output F and the signal that transmits the most slowly the soonest.

In traditional circuit shown in Figure 4, as seeing from Figure 20, the fastest transmission signals is that " A " the slowest transmission signals is " C ".

Have three kinds with the relevant measured value of described trigger time-delay characteristics: time, retention time and above-mentioned Tcq are set.These measured values all use clock signal (synchronizing signal) CLK as benchmark.

When using other trigger to realize logical circuit of the present invention and described logical circuit, in principle, the synchronization timing of relative time clock signal (synchronizing signal) is different.Occurred for this reason describedly being set and the retention time becomes negative situation the time.This is inappropriate for comparing.Therefore, in order to compare, preferably with described that time and retention time be set and be defined as described sample time (being Sample in the drawings) and time and Tcq will be set and be set to described time delay (being FFDelay in the drawings).

Described " sample time " only means not allowing the input signal sampling of input signal variation.

Described " time delay " mean the time that in one-period, consumes by described trigger and described logic function.In this two times, the time is short more, and performance is good more.

When on the basis of the above relatively during the time-delay characteristics of traditional cmos logical circuit and circuit of the present invention, become 427ps sample time in traditional circuit shown in Figure 20, and in circuit of the present invention shown in Figure 21 sample time become 711ps.

With regard to this two times, circuit of the present invention is better.

Therefore, according to logical circuit of the present invention, thereby first purpose of the present invention, promptly the characteristic by the described dynamic logic circuit of good utilization reduces power consumption and realizes that high speed operation has been implemented to eliminate misoperation.

In addition, second purpose of the present invention is that deletion is used to produce mechanism with the same short width-pulse with the PDN-F/F logical circuit and is convenient to design by utilizing CAD to carry out place and route automatically.

As described above, the two main line type logic tree parts 110 of sensing latch unit 130 and NMOS have been used in the present invention.

Utilize this two mechanisms, can detect the final of described logic automatically and determine and the obstruction input signal.In principle, do not need pulse producer.

Therefore realized described second purpose.

Say below and describe the advantage of circuit of the present invention with respect to the SA-F/F logical circuit of explaining as the 3rd object lesson.

The problem of described SA-F/F logical circuit is finally to determine that the required time of described logical organization is depended on the height of described logic tree substantially and the size of MOS transistor in this logic tree.

Because the height of logic tree is represented the quantity of described logic function input signal,, determine that finally the time of described logic is just long more so logic function is complicated more.

Under the situation of complex logic function, what described transistorized grid width can be provided with is bigger, and makes its conduction resistance less to shorten the logical definition time.But the size of logic tree will become bigger at that time.

Be used for finally determining that the time of described logic directly appears at Tcq.

Therefore, studied described Tcq with respect to the variation of logic tree height and Tcq variation with respect to NMOS size in the logic tree.

Figure 22 shows the characteristic with respect to the logic tree height at Tcq described in SA-F/F logical circuit and the logical circuit of the present invention, and Figure 23 shows the characteristic with respect to logic tree NMOS size at Tcq described in SA-F/F logical circuit and the logical circuit of the present invention.

In Figure 22, horizontal ordinate is represented the height of described logic tree, and ordinate is represented described Tcq, in Figure 23, and the size of horizontal ordinate presentation logic tree NMOS, ordinate is represented the fluctuation speed of described Tcq.

In addition, in the drawings, density bullet is pointed out the characteristic of SA-F/F logical circuit, and white marking is pointed out the characteristic of circuit of the present invention.

Can clearly be seen that from Figure 22 circuit Tcq of the present invention is little to the degree of dependence of logic tree height.When described logic tree became higher, circuit of the present invention was then with higher speed operation.

In addition, Figure 23 shows the fluctuation speed at 0.64 μ m described Tcq when 0.36 μ m changes as the size Wn of nmos pass transistor in the logic tree especially.This moment, the height of logic tree was 5.

Can find out obviously that from this circuit of the present invention is less to the degree of dependence of size Wn.Be not only this point, and also have following trend, promptly size Wn is more little, and speed is high more.

In the SA-F/F logical circuit, the current potential of node and logic tree node begins and pulled down to the current potential of complete logical zero in the sensor amplifier from logical one current potential or the current potential that approaches it.

On the contrary, in circuit of the present invention, they begin and are thus lifted to the current potential of logical one from logical zero current potential or the current potential that approaches it.

By drop-down, therefore, the SA-F/F logical circuit depends on the height or the Wn of described logic tree to described current potential by the light of nature through logic tree.

But the height of logic tree is irrelevant with the described current potential of lifting.Size Wn is more little, and the capacitive component that logic tree has is few more, and therefore, less Wn size has more advantage for promoting described voltage.

Therefore, circuit of the present invention is tangible with respect to the advantage of SA-F/F logical circuit when realizing complex logic circuit.Even the 3rd purpose of the present invention, promptly under the situation of the complex logic function that realizes having a plurality of input signals, can realize that also high speed operation has been implemented.

In addition, the 4th purpose of the present invention is that realize can the reactive circuit constant and coupled noise changes and work that can be more stable than DCSL circuit.

Causing that the DCSL circuit is to impose on to comprise that the actuating logic tree is connected with sensor amplifier and the voltage of the nmos pass transistor grid that disconnects is very low to one of reason of incorrect potential fluctuation sensitivity, promptly approximately is the threshold value of described nmos pass transistor.

Because these nmos pass transistors do not become conducting fully,, thereby make because the caused incorrect potential fluctuation of variation of described network constant and coupled noise can not be absorbed so conduction resistance is very high.

In logical circuit according to the present invention, logic tree 110 and sensor amplifier 131 be connected and disconnection is to be carried out by the control node G in sensing latch unit 130.

In control node G, electric charge is provided by the PMOS transistor, and gives the current potential of the complete logical zero in place.For this reason, the nmos pass transistor NT1304 and the NT1305 that are used as

switch

134 and 135 become abundant conducting, and have less conduction resistance and can easily absorb incorrect potential fluctuation.

In addition, the another one reason is to think that the current potential that is added to the nmos pass transistor grid that is used as described switch is different node.

That is, in circuit shown in Figure 9, node TH_X is connected to the grid of nmos pass transistor NT43, and node TH is connected to the grid of nmos pass transistor NT44.

When described sensor amplifier was in driving condition (CLK_X=0), node TH was disconnected with TH_X and does not become identical current potential.Potential difference (PD) between node TH and the TH_X is amplified by described sensor amplifier immediately, and described logic tree and sensor amplifier are disconnected.

Therefore, the incorrect current potential that produces between node TH and TH_X is exaggerated and and finally to be confirmed as be the logical value of a mistake.

In contrast, in sensing latch circuit 130 of the present invention, be used as the nmos pass transistor NT1304 of

switch

134 and 135 and 1305 conducting and by by public control node G control.

Even incorrect potential fluctuation takes place at node TH and TH_X place, as long as described current potential does not become highly must be enough to be identified as logical one, the current potential of control node G will be retained in logical one, and sensor amplifier 131 and logic tree 110 can not disconnect.

In this time cycle, between logic tree 110 grounding paths and sensor amplifier 131, disturb, logic tree 110 absorbs described incorrect potential fluctuation, thereby makes sensor amplifier be guided correct logical value.

Figure 24 shows a processing, handles by this, absorbs described incorrect potential fluctuation and correct logical value finally is set according to sensing latch of the present invention unit.

In Figure 24, the horizontal ordinate express time, ordinate is represented voltage.

Figure 24 shows the situation that provides the noise that reduces node TH current potential in described processing particularly, handles by this, and node TH finally is defined as original logical one.

In Figure 24, there is a time cycle, in this time cycle,, the noise effect that begins to locate at driving condition is lower than the current potential of node TH_X owing to making the current potential of node TH.

But, the current potential that this situation is restored subsequently and the current potential of node TH becomes is higher than node TH_X and finally be defined as logical one.In described DCSL circuit, this work is impossible.

Therefore, realized the 4th purpose.

In addition, in logical circuit according to the present invention, in described dummy status, sensor amplifier and logic tree are connected, and all nodes in the sensor amplifier and all nodes of logic tree are all by short circuit and be initialized to identical current potential.

Therefore, according to logical circuit of the present invention, has the advantage that to avoid causing fault owing to the imbalance of stray capacitance in the described logic tree.

Explain as top, because first embodiment provides the structure of two main line type logic trees 110 of a kind of NMOS of having and SR latch units 120, and, in described pair of main line type logic tree 110, when providing the input signal of described logic function, a path that always has ground connection among terminal TF of logic tree and the TF_X always becomes high impedance status with another, export H_X from the logic output H of the output node TH of sensing latch unit 130 and in its (R) termination receipts that reset from the logic of the output node TH_X of sensing latch unit 130 in its set (S) termination receipts with described SR latch units 120, the logic output that keeps described sensing latch unit 130, export described data from the Q output terminal, has sensor amplifier 131 with described sensing latch unit 130 by drive controlling work, utilize this drive controlling short circuit to be used for logic output H and the node TH of H_X and the switch 132 of TH_X, logic tree disconnects control module 133, be used for the node TH and the node TF2 of described logic input and be used for the node TH_X of described logic input and the switch 134 and 135 of node TF_X by 133 controls of logic tree disconnection control module and short circuit, wherein, in sensing latch unit 130, have in the dummy status of logical zero in synchronizing signal (CLK), sensor amplifier 131 does not have driving force, switch 132,134 and 135 become conducting, present all the inner node TH of sensing latch device and TH_X and logic tree node TF and TF_X all by the state of short circuit, wherein, in synchronizing signal (CLK) from the driving condition that logical zero begins after logical one changes immediately, described sensor amplifier has driving force, present switch 134 and 135 ground conductings as original, switch 132 becomes and ends, thereby node TH and TF are made this two d/d states of node by short circuit, wherein, determine that final the synchronizing signal (CLK) that begins after the described logical value had in the time cycle of logical one, sensor amplifier 131 has driving force, present switch 132,134 and 135 become by and node TH, TH_X, the state that TF and TF_X are disconnected, so have following effect:

The first, thus the misoperation that takes place in the static cmos logic circuit is eliminated and has reduced power consumption, and can realize high speed operation by the characteristic of using dynamic logic circuit well.

The second, can be so that by utilizing CAD to carry out autoplacement and wiring elimination and be designed for to produce to have the mechanism that is shorter than such as the pulse of SA-F/F logical circuit.

The 3rd, even operating rate to the dependence of mos gate utmost point width in the height of logic tree and the logic tree less than described SA-F/F logical circuit and also can high speed operation under the situation of the complex logic function that realizes having a plurality of input signals.

The 4th, can realize more can reactive circuit constant and the work of coupled noise variation and higher stability than DCSL circuit.

Second embodiment

The block diagram of Figure 25 shows second embodiment of the logical circuit according to the present invention, and the circuit of Figure 26 shows the object lesson of two main line type logic tree parts of NMOS shown in Figure 25 and SR latch units.

The difference of second embodiment and first embodiment has been to add a nmos pass transistor NT101 who is used for synchronously controlling with synchronizing signal (clock signal) the two main line type logic tree ground connection of NMOS.

In the original state of described flip-flop operation, this nmos pass transistor NT101 becomes and ends.

Notice that the concrete structure of two main line type logic trees of NMOS shown in Figure 26 and SR latch units is similar to circuit shown in Figure 11, therefore, omits about their detailed explanation here.

According to second embodiment, when clock signal (synchronizing signal) when CLK has logical one, nmos pass transistor NT101 becomes conducting.

For this reason, in clock signal (synchronizing signal) CLK becomes the state of logical one, promptly determine in the state final, its work with based on the structure of Figure 10, be that the work of structure shown in Figure 11 is identical.

Difference is that clock signal (synchronizing signal) CLK therein becomes the work in the dummy status of logical zero.

When clock is believed (synchronizing signal) when CLK has logical zero, irrelevant with the combination of input signal A, B, C, D logical value, be all not have grounding path at logic tree node TF or in the middle of TF_X.

In first embodiment, situation about being explained is to utilize logic tree with grounding path that the current potential of node TH, TH_X, TF and TF_X is fixed as complete logical zero current potential in dummy status.But, under the situation of structure shown in Figure 25 and 26, can not present this state.

Even logic tree 110 does not have the path of ground connection, also can make described sensing latch unit 130 itself have current potential with node TH and TH_X and pull down near the nmos pass transistor threshold value function that is connected the nmos pass transistor NT1304 that is used as switch 134 of described logic tree 110 and sensor amplifier 131 with conducting and is used as the nmos pass transistor NT1305 of switch 135.

When these

switches

134 and 135 become conducting and node TH and TH_X and are shorted to node TF and TF_X, in logic tree, be present on node TH and the TH_X and near electric charge that its current potential is arranged on the described nmos pass transistor threshold value is balanced distribution according to its electric capacity.

As the result of balanced distribution, the current potential of node TH, TH_X, TF and TF_X becomes and is slightly less than the threshold value of described nmos pass transistor, but is slightly larger than the current potential of complete logical zero.

That is, under the situation of structure shown in Figure 25 and 26, in described dummy status (position, Kongxiang), do not export complete logical zero current potential from node TH and TH_X.

The current potential that is slightly less than the nmos pass transistor threshold value but is slightly larger than complete logical zero current potential is output.The value that these current potentials have is low as to be enough to presentation logic " 0 ", therefore, does not have contradiction on principle of work.

Second embodiment is the increase of reduction in power consumption and speed with respect to the advantage of first embodiment.

In first embodiment, in described dummy status, all electric charges in sensing latch unit 130 and the logic tree 110 are all destroyed.

In contrast, in a second embodiment, the Partial charge that provides in driving condition is saved and reuses in next driving condition.For this reason, power consumption can be reduced manyly.

In addition, in described driving condition, the current potential of node TH and TH_X begins to rise from the current potential near the nmos pass transistor threshold value, therefore, determines finally that time that described logic needs becomes to be shorter than described current potential shown in Figure 10 from required time of structure that complete logical zero begins to rise.

The 3rd embodiment

The block diagram of Figure 27 shows the 3rd embodiment of the logical circuit according to the present invention, and the circuit of Figure 28 shows the object lesson of two main line type logic tree parts of the described NMOS of Figure 27 and SR latch units.

The difference of the 3rd embodiment and second embodiment is to be connected in parallel one with described nmos pass transistor NT101 and is used to control the two main line type logic trees of described NMOS and a transistor NT102 who is different from the synchronous grounding NMOS of control signal SLEEP of described clock signal (synchronizing signal).

Notice that the concrete structure of two main line type logic tree parts of NMOS shown in Figure 28 and SR latch units and circuit structure shown in Figure 11 are similar, therefore, omit the detailed explanation to them here.

According to the 3rd embodiment, when control signal SLEEP had logical zero, nmos pass transistor NT102 ended.The work of this moment shown in Figure 26 identical with according to second embodiment.

On the contrary, in control signal SLEEP becomes the time durations of logical one, do not consider described clock signal (synchronizing signal) CLK, in logic tree 110, have reliable grounding path.

That is, electric charge was not saved or reused this moment.

Finally be set in the dummy status of logical one at control signal SLEEP, node TH and TH_X become complete logical zero.

When clock signal (synchronizing signal) when CLK stops at logical zero, need make described control signal SLEEP become logical one.

Current, in order to reduce power consumption, stop to provide the method for clock to become very common to idle circuit block.

The clock that is stopped becomes constant logical zero or logical one.Then depend on design as for becoming which steady state value, still, in case design finishes, described clock just always stops at identical logical value place.

Problem according to structure shown in Figure 25 and 26 of second embodiment is the situation that described clock signal (synchronizing signal) CLK stops at logical zero.

At this moment, because dummy status, the current potential of node TH and TH_X becomes and is slightly less than the threshold value of described nmos pass transistor.

SR latch units 120 is received and is worked in the maintenance pattern with it as logical zero.There is not logical problem in this.

But the magnitude of leakage current when ending becomes problem.

Have in SR latch units 120 the node TH at their grid places and the NMOS of TH_X this moment and be in cut-off state.Usually, described MOS has electric current to flow through, although this magnitude of current is very little under cut-off state.This electric current is referred to as leakage current.

The value of described leakage current is to be determined by the exponential function of described grid potential.Therefore, the current potential of described node TH and TH_X be the situation of complete logical zero V and their near the leakage current value between the situation of the threshold value of described nmos pass transistor in, the difference that has the about order of magnitude to two order of magnitude is although their absolute value is very little.For this reason, when stopping to cause long dummy status owing to clock, its power consumption also is dropped the situation that drops to complete logical zero current potential with the current potential of node TH and TH_X less than the electric charge that is used to reuse.

Structure according to third embodiment of the invention shown in Figure 27 and 28 exactly is used to realize this function.

As mentioned above, when clock signal (synchronizing signal) when being stopped at logical zero, becoming very big according to leakage current described in the structure shown in Figure 25 of second embodiment.

In contrast, in the structure according to the 3rd embodiment shown in Figure 27, SLEEP is set to logical one by control signal, and the current potential of node TH and TH_X can drop to complete logical zero under the dummy status.For this reason, described leakage current can become very little.

Figure 29 shows inner node TH and the potential waveform of TH_X and the analog result of leakage current value when the SLEEP pattern is worked.

In Figure 29, the horizontal ordinate express time, ordinate is represented voltage.

In current simulation, use circuit shown in Figure 27, the pulse of clock signal (synchronizing signal) CLK is presented, and carries out to be used for determining that finally the work of described logic and clock signal clk stop at logical zero.

At this moment, control signal SLEEP still is in logical zero.Therefore, node TH and TH_X do not have the current potential of complete logical zero.

Shown in the cycle leakage current be 557.3nA.

Then, when control signal SLEEP was set to logical one, the current potential of node TH and TH_X quickly fell to 0V.Shown in leakage current in the cycle be 24.6nA.

In this manner, the influence of SLEEP control is very big.

Summarize effect of the present invention as mentioned above, according to the present invention, thereby the misoperation that takes place in the static cmos logic circuit can be eliminated and reduced power consumption and the characteristic by good use dynamic logic circuit can realize high speed operation.

In addition, according to the present invention, can eliminate to be used to produce have to be shorter than and design such as the mechanism of PDN-F/F logical circuit pulse and CAD autoplacement easy to use and wiring.

In addition, according to the present invention, operating rate is less than the SA-F/F logical circuit for the degree of dependence of the grid width of MOS in the height of logic tree and the described logic tree, even also can realize high speed operation under the situation of the complex logic function that realizes having a lot of input signals.

In addition, according to the present invention, realized that work and the stability that can bear network constant and coupled noise variation will be higher than the DCSL logical circuit.

In addition, according to the present invention, by providing described SLEEP pattern to use switch and the inside node in the described logic tree being fixed to complete logical zero current potential, can reduce described leakage current when synchronizing signal has to force when continuing to set up described grounding path in logical zero and two main lines at described logic tree.

The specific embodiments of selecting being combined into illustration purpose is when invention has been described, and clearly, the those of ordinary skill in this professional skill field can be made a lot of modifications under the prerequisite that does not break away from key concept of the present invention and spirit.

Claims

1. logical circuit that is used for the synchronous output logic functional assessment of a synchronizing signal result comprises:

A sensing latch unit has:

The first logic output node;

The second logic output node;

A logic tree disconnects control device, has:

2. logical circuit according to claim 1, it is characterized in that, the sensor amplifier of described sensing latch unit has first phase inverter and second phase inverter, the input of the output of described first phase inverter and described second phase inverter is interconnected, its tie point is connected to the described first logic output node, the output of the input of first phase inverter and second phase inverter is interconnected, its tie point be connected to the described second logic output node and

Wherein, described first conversion equipment is connected between the input of the input of first phase inverter and second phase inverter.

3. logical circuit according to claim 1, it is characterized in that, first setting device that described logic tree disconnects control device comprise be connected can described second conversion equipment and the 3rd conversion equipment be incorporated between first power supply potential of connection status and the described control node and point out in its control end reception to become on the basis of synchronizing signal of described dummy status conducting the 4th conversion equipment and

Wherein, described logic tree disconnects control device and comprises and be connected and described second conversion equipment and the 3rd conversion equipment can be incorporated between the second source current potential and described control node of off-state, have the control end that is connected to the described first logic output node and when the described first logic output potential is in one first level, become the 5th conversion equipment of conducting, and be connected between described second source current potential and the described control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 6th conversion equipment of conducting.

4. logical circuit according to claim 2, it is characterized in that, first setting device that described logic tree disconnects control device comprise be connected can described second conversion equipment and the 3rd conversion equipment be incorporated between first power supply potential of connection status and the described control node and point out in its control end reception to become on the basis of synchronizing signal of described dummy status conducting the 4th conversion equipment and

Wherein, second setting device that described logic tree disconnects control device comprises and is connected and described second conversion equipment and the 3rd conversion equipment can be incorporated between the second source current potential and described control node of off-state, have the control end that is connected to the described first logic output node and when the described first logic output potential is in described first level, become the 5th conversion equipment of conducting, and be connected between described second source current potential and the described control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 6th conversion equipment of conducting.

5. logical circuit according to claim 1, it is characterized in that, first setting device that described logic tree disconnects control device comprise be connected can described second conversion equipment and the 3rd conversion equipment be incorporated between first power supply potential of connection status and the described control node and point out in its control end reception to become on the basis of synchronizing signal of described dummy status conducting the 4th conversion equipment and

Wherein, second setting device that described logic tree disconnects control device is included between intermediate node and the control node, have the control end that is connected to the described first logic output node and when the described first logic output potential is in described first level, become the 5th conversion equipment of conducting, and connect between intermediate node and the control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 6th conversion equipment of conducting, and be connected between the second source current potential that described second conversion equipment and the 3rd conversion equipment can be incorporated into off-state and the intermediate node, when the 4th conversion equipment conducting, remain on nonconducting state, when remaining on nonconducting state, the 4th conversion equipment becomes the 7th conversion equipment of conducting.

6. logical circuit according to claim 2, it is characterized in that, described be connected to disconnect control device first setting device comprise be connected can described second conversion equipment and the 3rd conversion equipment be incorporated between first power supply potential of connection status and the described control node and point out in its control end reception to become on the basis of synchronizing signal of dummy status conducting the 4th conversion equipment and

Wherein, second setting device that described logic tree disconnects control device comprises and being connected between an intermediate node and the described control node, have the control end that is connected to the described first logic output node and when the described first logic output potential is in described first level, become the 5th conversion equipment of conducting, be connected between described intermediate node and the described control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 6th conversion equipment of conducting, be connected and described second conversion equipment and the 3rd conversion equipment can be incorporated between the second source current potential and described intermediate node of off-state, when the 4th conversion equipment conducting, remain on nonconducting state, when remaining on nonconducting state, the 4th conversion equipment becomes the 7th conversion equipment of conducting.

7. logical circuit according to claim 1, it is characterized in that, first setting device that described logic tree disconnects control device comprise be connected in series in can described second conversion equipment and the 3rd conversion equipment be incorporated into first power supply potential of connection status and one control between the node and in described dummy status, on described control end receives the basis of current potential of the current potential of the first logic output node and the second logic output node, become the 4th conversion equipment of conducting and the 5th conversion equipment and

Wherein, second setting device that described logic tree disconnects control device comprises and is connected and described second conversion equipment and the 3rd conversion equipment can be incorporated between the second source current potential of off-state, have the control end that is connected to the described first logic output node and when the described first logic output potential is in described first level, become the 6th conversion equipment of conducting, and be connected between described second source current potential and the described control node, have the control end that is connected to the second logic output node and when the described second logic output potential is in described first level, become the 7th conversion equipment of conducting.

8. logical circuit according to claim 2, it is characterized in that, first setting device that described logic tree disconnects control device comprise be connected in series in can described second conversion equipment and the 3rd conversion equipment be incorporated into first power supply potential of connection status and one control between the node and in dummy status, on its control end receives the basis of the described first logic output node current potential and the second logic output node current potential, become the 4th conversion equipment of conducting and the 5th conversion equipment and

Wherein, second setting device that described logic tree disconnects control device comprises and is connected and described second conversion equipment and the 3rd conversion equipment can be incorporated between the second source current potential and described control node of off-state, have the control end that is connected to the described first logic output node and when the described first logic output potential is in described first level, become the 6th conversion equipment of conducting, and connect between second source current potential and the control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 7th conversion equipment of conducting.

9. logical circuit that is used for the synchronous output logic functional assessment of a synchronizing signal result comprises:

Form a path and realize two main line type logic trees of desired function, wherein have only a main line to arrive described reference potential through described path according to input signal;

A sensing latch unit has:

Be used to receive first logic input node and second logic input node of described pair of main line type logic tree first logic output and the output of second logic;

The first logic output node;

The second logic output node;

A sensor amplifier, this sensor amplifier is pointed out in reception to work on the basis of the synchronizing signal that drives, and is set to the first different level and second level according to the logic current potential of being exported by first logic input that inputs to described first logic input node and second logic input node and the most described first logic output of conduction resistance difference that the input of second logic has and second logic;

First conversion equipment is used for the short circuit first logic output node and the second logic output node when receiving the synchronizing signal of pointing out a dummy status;

Second conversion equipment is used for being electrically connected or disconnecting described first logic input node and the first logic output node according to the current potential of described control end;

The 3rd conversion equipment is used for being electrically connected or disconnecting described second logic input node and the second logic output node according to the current potential of described control end; With

A logic tree disconnects control device, has

First setting device, be used for comprise wherein described sensor amplifier also do not have finally to determine current potential that a state place of the dummy status of described logic is connected to the control node on the control end of described second conversion equipment and the 3rd conversion equipment be set at least can be connected described second and two ends of the 3rd conversion equipment between the current potential that connects; With

Second setting device, be used for the state place that has finally determined described logic at described sensor amplifier be set to according to the current potential of described first logic output node or the described control node of the described second logic output node at least can be connected described second and two ends of the 3rd conversion equipment between carry out the current potential that disconnects;

The set and the latch units that resets, be used for receiving first logic output of described sensing latch unit in its set termination, receive second logic output of described sensing latch unit at its reset terminal, and the time cycle that the output of described sensing latch unit is kept described synchronizing signal one-period; With

The 4th conversion equipment is used for being disconnected to the path of described pair of main line type logic tree reference potential and described reference potential and being connected them at described dummy status time place in addition at described dummy status electricity.

10. logical circuit according to claim 9, it is characterized in that, the sensor amplifier of described sensing latch unit has the phase inverter and second phase inverter, the output of first phase inverter links to each other with the input of second phase inverter, its tie point is connected to the described first logic output node, the input of first phase inverter links to each other with the output of second phase inverter, and its tie point is connected to the described second logic output node; With

11. logical circuit according to claim 9, it is characterized in that first setting device of described logic tree disconnecting device comprises and is connected between first power supply potential that described second conversion equipment and the 3rd conversion equipment can be incorporated into connection status and the described control node and receives the 5th conversion equipment that becomes conducting on the basis of a synchronizing signal pointing out described dummy status at its control end; With

Second setting device that described logic tree disconnects control device comprises and is connected and described second conversion equipment and the 3rd conversion equipment can be incorporated between the second source current potential and described control node of off-state, have the control end that is connected to the described first logic output node and when the described first logic output potential is in described first level, become the 6th conversion equipment of conducting, and be connected between second source electric potential and the described control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 7th conversion equipment of conducting.

12. logical circuit according to claim 10, it is characterized in that, first setting device that described logic tree disconnects control device comprise be connected can described second conversion equipment and the 3rd conversion equipment be incorporated between first power supply potential of connection status and the described control node and point out to become on the basis of synchronizing signal of described dummy status the 5th conversion equipment of conducting in its control end reception; With

Wherein, second setting device that described logic tree disconnects control device comprises and is connected and described second conversion equipment and the 3rd conversion equipment can be incorporated between the second source current potential and described control node of off-state, have the control end that is connected to the described first logic output node and when the described first logic output potential be in described first level can the time become the 6th conversion equipment of conducting, and be connected between described second source current potential and the described control node, have the control end that is connected to described logic output node and when the described second logic output potential is in described first level, become the 7th conversion equipment of conducting.

13. logical circuit according to claim 9, it is characterized in that, first setting device that described logic tree disconnects control device comprise be connected can described second conversion equipment and the 3rd conversion equipment be incorporated between first power supply potential of connection status and the described control node and point out to become on the basis of synchronizing signal of described dummy status the 5th conversion equipment of conducting in its control end reception; With

Wherein, second setting device that described logic tree disconnects control device comprises and being connected between an intermediate node and the described control node, have the control end that is connected to the described first logic output node and when the described first logic output potential is in described first output level, become the 6th conversion equipment of conducting, be connected between described intermediate node and the described control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 7th conversion equipment of conducting, and be connected and described second conversion equipment and the 3rd conversion equipment can be incorporated between the second source current potential and described intermediate node of off-state, when described the 5th conversion equipment conducting, remain on nonconducting state and when described the 5th conversion equipment remains on nonconducting state, become the 8th conversion equipment of conducting.

14. logical circuit according to claim 10, it is characterized in that, first setting device that described logic tree disconnects control device comprise be connected can described second conversion equipment and the 3rd conversion equipment be incorporated between first power supply potential of connection status and the described control node and point out to become on the basis of synchronizing signal of described dummy status the 5th conversion equipment of conducting in its control end reception; With

Wherein, second setting device that described logic tree disconnects control device comprises and being connected between an intermediate node and the described control node, have the control end that is connected to the described first logic output node and when the described first logic output potential is in described first level, become the 6th conversion equipment of conducting, be connected between described intermediate node and the control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 7th conversion equipment of conducting, and be connected and described second conversion equipment and the 3rd conversion equipment can be incorporated between the second source current potential and described intermediate node of off-state, when described the 5th conversion equipment conducting, remain on nonconducting state and when described the 5th conversion equipment remains on nonconducting state, become the 8th conversion equipment of conducting.

15. logical circuit according to claim 9, it is characterized in that first setting device that described logic tree disconnects control device comprises the 5th conversion equipment and the 6th conversion equipment that is connected in series between first power supply potential that described second conversion equipment and the 3rd conversion equipment can be incorporated into connection status and the described control node and becomes conducting in described dummy status on their control ends receive the basis of the described first logic output potential and the second logic output potential; With

Wherein, second setting device that described logic tree disconnects control device comprises and is connected and described second conversion equipment and the 3rd conversion equipment can be incorporated between the second source current potential and described control node of off-state, have the control end that is connected to the described first logic output node and when the described first logic output potential is in described first level, become the 7th conversion equipment of conducting, and be connected between described second source current potential and the described control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 8th conversion equipment of conducting.

16. logical circuit according to claim 10, it is characterized in that, first setting device of described logic tree comprise be connected in series between first power supply potential that described second conversion equipment and the 3rd conversion equipment can be incorporated into connection status and the described control node and in described dummy status, on their control ends receive the basis of the described first logic output node current potential, become the 5th conversion equipment of conducting and the 6th conversion equipment and

Wherein, described logic tree second setting device that disconnects control device comprises and is connected between the second source current potential and described control node that described second conversion equipment and the 3rd conversion equipment can be incorporated into off-state, has the control end that is connected to the described first logic output node and becomes the 7th conversion equipment of conducting when the described first logic output potential is in described first level; And be connected between described second source current potential and the described control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 8th conversion equipment of conducting.

17. a logical circuit that is used for the synchronous output logic functional assessment of a synchronizing signal result comprises:

Be used to form a path and realize two main line type logic trees of desired logic function, wherein have only a main line to arrive described reference potential according to input signal;

The sensing latch unit has:

Be used to receive first logic input node and second logic input node of first output of described pair of main line type logic tree and second output;

The first logic output node;

The second logic output node;

A sensor amplifier, point out in reception to work on the basis of a synchronizing signal driving, and be set to the first different level and second level according to being transfused to first logic input of described first logic input node and second logic input node and the current potential that described first logic of conduction resistance difference is exported and second logic is exported that the input of second logic is had;

First conversion equipment is used for the short circuit first logic output node and the second logic output node when receiving synchronizing signal pointing out dummy status,

The 3rd conversion equipment, be used for according to described control current potential be electrically connected or disconnect second logic input node and the second logic output node; With

A logic tree disconnects control device, has:

First setting device is used for comprising wherein at described sensor amplifier not having finally to determine that the current potential of the control node that links to each other with the control end of second conversion equipment and the 3rd conversion equipment in the state of dummy status of described logic is set to can make at least and described second two current potentials that end is connected that link to each other with the 3rd conversion equipment;

Second setting device is used for therein that the current potential according to described first logic output node or the described control node of the second logic output node is set to can make at least the current potential that disconnects between two ends that are connected with described second conversion equipment and the 3rd conversion equipment at a state place that described sensor amplifier has finally been determined described logic; With

The set and the latch units that resets, be used for its set termination receive described sensing latch unit first logic output, receive second logic output of described sensing latch unit at its reset terminal, and time cycle that the logic output of described sensing latch unit is kept the synchronizing signal one-period;

The 4th conversion equipment is used for being disconnected to the path of the reference potential of described pair of main line type logic tree and described reference potential and being connected them in the state except that dummy status at dummy status electricity; With

The 5th conversion equipment, be used to force connect the time cycle of path that arrives described pair of main line type logic tree reference potential and described reference potential, disconnect the path that arrives described pair of main line type logic tree reference potential and described reference potential when in this time cycle, in dummy status, utilizing the 4th conversion equipment when synchronizing signal is being pointed out described dummy status, to stop.

18. logical circuit according to claim 17, it is characterized in that, the sensor amplifier of described sensing latch unit has first phase inverter and second phase inverter, the input of the output of first phase inverter and second phase inverter is interconnected, its tie point is connected to the described first logic output node, the output of the input of first phase inverter and second phase inverter is interconnected, its tie point be connected to the described second logic output node and

19. logical circuit according to claim 17, it is characterized in that, first setting device that described logic tree disconnects control device comprise be connected can described second conversion equipment and the 3rd conversion equipment be incorporated between first power supply potential of connection status and the described control node and point out to become on the basis of synchronizing signal of described dummy status the 6th conversion equipment of conducting in its control end reception; With

Wherein, second setting device that described logic tree disconnects control device comprises and is connected and described second conversion equipment and the 3rd conversion equipment can be incorporated between the second source current potential and described control node of off-state, have the control end that is connected to the first logic output node and when the described first logic output potential is in described first level, become the 7th conversion equipment of conducting, and be connected between described second source current potential and the described control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 8th conversion equipment of conducting.

20. logical circuit according to claim 18, it is characterized in that, first setting device that described logic tree disconnects control device comprise be connected can described second conversion equipment and the 3rd conversion equipment be incorporated between first power supply potential of connection status and the described control node and point out to become on the basis of synchronizing signal of described dummy status the 6th conversion equipment of conducting in its control end reception; With

21. logical circuit according to claim 17, it is characterized in that, first setting device that described logic tree disconnects control device comprise be connected can described second conversion equipment and the 3rd conversion equipment be incorporated between first power supply potential of connection status and the described control node and point out to become on the basis of synchronizing signal of described dummy status the 6th conversion equipment of conducting in its control end reception; With

Second setting device that wherein said logic tree disconnects control device comprises and being connected between an intermediate node and the described control node, have the control end that is connected to the first logic output node and when the described first logic output potential is in described first level, become the 7th conversion equipment of conducting, be connected between described intermediate node and the described control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 8th conversion equipment of conducting, be connected and described second conversion equipment and the 3rd conversion equipment can be incorporated between the second source current potential and intermediate node of living in of off-state, when described the 6th conversion equipment conducting, remain on nonconducting state and when described the 6th conversion equipment remains on nonconducting state, become the 9th conversion equipment of conducting.

22. logical circuit according to claim 18, it is characterized in that, first setting device that described logic tree disconnects control device comprise be connected can described second conversion equipment and the 3rd conversion equipment be incorporated between first power supply potential of connection status and the described control node and point out to become on the basis of synchronizing signal of described dummy status the 6th conversion equipment of conducting in its control end reception; And wherein said logic tree second setting device that disconnects control device comprises and being connected between an intermediate node and the described control node, have the control end that is connected to the first logic output node and when the described first logic output potential is in described first level, become the 7th conversion equipment of conducting, be connected between described intermediate node and the described control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 8th conversion equipment of conducting, be connected and described second conversion equipment and the 3rd conversion equipment can be incorporated between the second source current potential and intermediate node of living in of off-state, when described the 6th conversion equipment conducting, remain on nonconducting state and when described the 6th conversion equipment remains on nonconducting state, become the 9th conversion equipment of conducting.

23. logical circuit according to claim 17, it is characterized in that first setting device that described logic tree disconnects control device comprises the 6th conversion equipment and the 7th conversion equipment that is connected in series between first power supply potential that described second conversion equipment and the 3rd conversion equipment can be incorporated into connection status and the described control node and becomes conducting in described dummy status on their control ends receive the basis of current potential of the current potential of the described first logic output node and the described second logic output node; With

Wherein, second setting device that described logic tree disconnects control device comprises and is connected and described second conversion equipment and the 3rd conversion equipment can be incorporated between the second source current potential and described control node of off-state, have the control end that is connected to the described first logic output node and when the described first logic output potential is in described first level, become the 8th conversion equipment of conducting, and be connected between described second source current potential and the described control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 9th conversion equipment of conducting.

24. logical circuit according to claim 18, it is characterized in that, first setting device that described logic tree disconnects control device comprise be connected in series between first power supply potential that described second conversion equipment and the 3rd conversion equipment can be incorporated into connection status and the described control node and in described dummy status, on their control end receives the basis of current potential of the current potential of the described first logic output node and the described second logic output node, become the 6th conversion equipment of conducting and the 7th conversion equipment and

Second setting device that described logic tree disconnects control comprises and is connected and described second conversion equipment and the 3rd conversion equipment can be incorporated between the second source current potential and described control node of off-state, have the control end that is connected to the described first logic output node and when the described first logic output potential is in described first level, become the 8th conversion equipment of conducting, and be connected between described second source current potential and the described control node, have the control end that is connected to the described second logic output node and when the described second logic output potential is in described first level, become the 9th conversion equipment of conducting.