CN117539698A

CN117539698A - Detection circuit

Info

Publication number: CN117539698A
Application number: CN202311489907.4A
Authority: CN
Inventors: 潘志伟
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2023-11-09
Filing date: 2023-11-09
Publication date: 2024-02-09

Abstract

The embodiment of the application provides a detection circuit, wherein the detection circuit comprises: a power supply, a first prompt component, a second prompt component 103, a first intermediate relay and a connector; the first end of the first prompt component is electrically connected with the second end of the power supply through a first target switch in the first intermediate relay, and the second end of the first prompt component is electrically connected with the first end of the power supply; the first end of the second prompting component 103 is electrically connected with the first contact of the connector through a second target switch in the first intermediate relay, and the second end of the second prompting component 103 is electrically connected with the second end of the power supply; the first end of the first intermediate relay is electrically connected with the second end of the power supply, and the second end of the first intermediate relay is electrically connected with the second contact of the connector; the connector also includes a third contact electrically connected to the first end of the power source.

Description

Detection circuit

Technical Field

The embodiment of the application relates to the field of computers, in particular to a detection circuit.

Background

Currently, a personal computer (Personal Computer, abbreviated as a PC) and a memory of a server are manually installed with memory banks, so that personnel cannot install the memory banks according to a process flow specification, and the memory banks are not completely inserted into a main board memory socket. Therefore, the problem that the computer cannot be started, or the computer with the memory bank which is not installed in place flows to the client, and then the client complaints such as incapability of starting are exploded out. Currently, most production workshops are arranged with process quality control (Process Quality Control, abbreviated as PQC) and manual inspection such as shift inspection to manually inspect the installation of memory banks in place. This visual inspection is time consuming and laborious, inefficient, and has a high leak rate. And a high-precision pressure sensor is arranged in the memory slot, the pressure sensor transmits the pressure to the processing chip, the computer is started and electrified to judge the memory installation state, the detection is only carried out after the whole machine is assembled, the early prevention is not met, the product is manufactured at one time and the accurate requirement is met, and the high-precision pressure sensor has extremely high cost.

Aiming at the problem that the installation state of the memory bank on the main board cannot be determined efficiently in the related art, no effective solution is proposed at present.

Accordingly, there is a need for improvements in the related art to overcome the drawbacks of the related art.

Disclosure of Invention

The embodiment of the application provides a detection circuit, which at least solves the problem that the installation state of a memory bank on a main board cannot be determined efficiently.

According to one embodiment of the present application, there is provided a detection circuit including: the power supply, the first suggestion subassembly, the second suggestion subassembly, the first intermediate relay, connector; the first end of the first prompt component is electrically connected with the second end of the power supply through a first target switch in a first intermediate relay, and the second end of the first prompt component is electrically connected with the first end of the power supply; the first end of the second prompting component is electrically connected with the first contact of the connector through a second target switch in the first intermediate relay, and the second end of the second prompting component is electrically connected with the second end of the power supply; the first end of the first intermediate relay is electrically connected with the second end of the power supply, the second end of the first intermediate relay is electrically connected with the second contact of the connector, wherein the first target switch is in a closed state and the second target switch is in an open state when current exists in the first intermediate relay, and the first target switch is in an open state and the second target switch is in a closed state when current does not exist in the first intermediate relay; the connector further includes a third contact electrically connected to the first end of the power source; the connector is used for being electrically connected with a first end of a first designated switch on the main board through the first contact, electrically connected with a second end of the first designated switch through the second contact and electrically connected with the first end of the first designated switch through the third contact under the condition that the connector is connected with the main board; the opening and closing states of the first designated switch have a corresponding relation with the installation state of the memory bank at a position corresponding to the first designated switch in the memory socket.

In an exemplary embodiment, the first prompting component is configured to display a first prompting message when the first specified switch is in a closed state; under the condition that the first designated switch is in an off state, no prompt message is displayed; the first prompt message is used for prompting that the memory bank is successfully installed at a position corresponding to the first designated switch in the memory socket; the second prompting component is used for not displaying prompting information under the condition that the first specified switch is in a closed state; and displaying second prompt information when the first specified switch is in an off state, wherein the second prompt information is used for prompting that the memory bank is not successfully installed at a position corresponding to the first specified switch in the memory socket.

In an exemplary embodiment, the detection circuit further includes: a target prompting component, a target intermediate relay; the first end of the target prompt component is electrically connected with the first end of the power supply through a second target switch in the target intermediate relay, and the second end of the target prompt component is electrically connected with the second end of the power supply; the first end of the target intermediate relay is electrically connected with the second end of the power supply, the second end of the target intermediate relay is electrically connected with the first target contact of the connector, wherein the second target switch of the target intermediate relay is in an open state when current exists in the target intermediate relay, and the second target switch of the target intermediate relay is in a closed state when current does not exist in the target intermediate relay; the connector is further configured to electrically connect with the third contact through the first target contact when the connector is connected with the motherboard.

In an exemplary embodiment, the target prompt component is configured to not display a prompt message when the connector is connected to the motherboard; and displaying third prompt information under the condition that the connector is not connected with the main board, wherein the third prompt information is used for prompting that the detection circuit is not connected with the main board.

In an exemplary embodiment, the detection circuit further includes: a time relay; the first end of the time relay is electrically connected with the second end of the power supply, and the second end of the time relay is electrically connected with the second target contact of the connector; the connector is further configured to electrically connect with a first end of a detection switch on the motherboard through the third contact when the connector is connected with the motherboard; the connector is further used for being electrically connected with the second end of the detection switch on the main board and the first end of the switch of the time relay through the second target contact under the condition that the connector is connected with the main board; a second end of the switch of the time relay is used for being electrically connected with a first end of the first designated switch under the condition that the connector is connected with the main board; when the time relay has current, the switch of the time relay is in a closed state, and the open-close state of the detection switch has a corresponding relation with the installation state of the memory bar at the position corresponding to the detection switch in the memory socket.

In an exemplary embodiment, the time relay is configured to, when the time parameter is a preset time parameter, not conduct electricity for a preset time corresponding to the preset time parameter, and conduct electricity after the preset time corresponding to the preset time parameter.

In one exemplary embodiment, the detection circuit includes: 2N prompt components and N intermediate relays; the connector comprises n+2 contacts, i is a positive integer greater than or equal to 2; the first end of the 2i-1 prompting component is electrically connected with the second end of the power supply through a first target switch in a first intermediate relay, and the second end of the 2i-1 prompting component is electrically connected with the first end of the power supply; the first end of the 2 i-th prompt component is electrically connected with the first contact of the connector through a second target switch in the i-th intermediate relay, and the second end of the 2 i-th prompt component is electrically connected with the second end of the power supply; the first end of the ith intermediate relay is electrically connected with the second end of the power supply, the second end of the ith intermediate relay is electrically connected with the (i+2) th contact of the connector, wherein when the ith intermediate relay has current, the first target switch of the ith intermediate relay is in a closed state and the second target switch of the ith intermediate relay is in an open state, and when the ith intermediate relay does not have current, the first target switch of the ith intermediate relay is in an open state and the second target switch of the ith intermediate relay is in a closed state; the connector is further configured to electrically connect with a first end of an i-th specified switch on the motherboard through the first contact, electrically connect with a second end of the i-th specified switch through the i+2-th contact, and electrically connect with the first end of the i-th specified switch through the third contact when the connector is connected with the motherboard; the opening and closing states of the i-th designated switch have a corresponding relation with the installation state of the memory bank at a position corresponding to the i-th designated switch in the memory socket.

In one exemplary embodiment, the first prompting component includes: a first indicator light; the second prompting component comprises: the second warning light and the buzzer.

In an exemplary embodiment, the first indicator light is configured to be in a light-emitting state when the first specified switch is in a closed state; in an off state with the first specified switch in an off state; the second prompting lamp is used for being in a luminous state when the first designated switch is in an off state; in an off state with the first designated switch in a closed state; the buzzer is used for being in an on state under the condition that the first specified switch is in an off state; and the first designated switch is in a closed state when the first designated switch is in a closed state.

In one exemplary embodiment, the target cue component includes: the target prompting lamp is used for being in an extinguishing state under the condition that the connector is connected with the main board; and the connector is in a light-emitting state when not connected with the main board.

In this application, design a detection circuitry to under the condition of the state of needs detection memory bank, be connected above-mentioned detection circuitry to on the mainboard, because the mounted state of memory bank can influence the open-close state of first appointed switch, thereby influence the state of first suggestion subassembly and second suggestion subassembly, and then the user can confirm whether the memory bank on the mainboard is installed in place according to the state of first suggestion subassembly and second suggestion subassembly, the problem of the mounted state of memory bank on the mainboard of unable efficient determination has been solved, the defective rate and the test leakage rate that the memory bank of mainboard is installed in place have been reduced.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:

FIG. 1 is a schematic diagram (one) of a detection circuit according to an embodiment of the present application;

FIG. 2 is a schematic diagram (II) of a detection circuit according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a motherboard according to an embodiment of the present application;

FIG. 4 is a schematic view of a side boss mechanism of a memory socket according to an embodiment of the present application;

FIG. 5 is a schematic view of a front boss mechanism of a memory socket according to an embodiment of the present application;

fig. 6 is a schematic diagram of a 15PIN pad according to an embodiment of the present application;

FIG. 7 is a bottom cross-sectional view of a memory socket according to an embodiment of the present application;

FIG. 8 is a block diagram illustrating a memory installation status detection apparatus according to an embodiment of the present application;

FIG. 9 is a schematic diagram (III) of a detection circuit according to an embodiment of the present application;

FIG. 10 is a flowchart of detecting a memory bank installation status according to an embodiment of the present application;

FIG. 11 is a logic diagram illustrating memory installation status detection according to an embodiment of the present application.

Detailed Description

In order to make the present application solution better understood by those skilled in the art, the following description will be made in detail and with reference to the accompanying drawings in the embodiments of the present application, it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

In order to solve the above-mentioned problem, in the present embodiment, a detection circuit is provided, fig. 1 is a schematic diagram (a) of a detection circuit according to an embodiment of the present application, and as shown in fig. 1, the detection circuit 10 includes:

a power supply 101, a first prompt component 102, a second prompt component 103, a first intermediate relay 104 and a connector 105;

a first end (a) of the first prompting component 102 is electrically connected with a second end (-) of the power supply 101 through a first target switch 1041 in a first intermediate relay 104, and a second end (b) of the first prompting component 102 is electrically connected with a first end (+) of the power supply 101;

A first end (c) of the second prompting assembly 103 is electrically connected to the first contact 1051 of the connector 105 through a second target switch 1042 in a first intermediate relay 104, and a second end (d) of the second prompting assembly 103 is electrically connected to a second end (-) of the power supply 101;

a first end (e) of the first intermediate relay 104 is electrically connected to a second end (-) of the power source 101, and a second end (f) of the first intermediate relay 104 is electrically connected to a second contact 1052 of the connector 105, wherein the first target switch 1041 is in a closed state and the second target switch 1042 is in an open state when there is a current in the first intermediate relay 104, and the first target switch 1041 is in an open state and the second target switch 1042 is in a closed state when there is no current in the first intermediate relay 104;

the connector 105 further includes a third contact 1053 electrically connected to the first end (+) of the power supply 101; wherein, the connector 105 is configured to electrically connect with a first end (g) of a first designated switch 201 on the motherboard through the first contact 1051, electrically connect with a second end (h) of the first designated switch 201 through the second contact 1052, and electrically connect with the first end (g) of the first designated switch 201 through the third contact 1053 when the connector 105 is connected with the motherboard 20;

The open/close state of the first switch 201 corresponds to the installation state of the memory bank at a position corresponding to the first switch 201 in the memory socket.

When the memory bank is not mounted at the position corresponding to the first designated switch 201 in the memory socket, the first designated switch on the main board is in an off state, and when the memory bank is mounted at the position corresponding to the first designated switch 201 in the memory socket, the first designated switch on the main board is in an on state.

The first target switch in the first intermediate relay is KA-ON in the relay, and the first target switch in the first intermediate relay is KA-OC in the relay.

An intermediate relay is a relay used for a control circuit, and is generally used to transfer a control signal from one circuit to another. It typically has two inputs, one of which receives a control signal and the other of which receives a signal from the other circuit, and one output which passes the signal to the other circuit.

The KA-ON switch and the KA-OC switch are two common types of switches for an intermediate relay. The KA-ON switch is a normally open switch that will connect the input and output terminals when a control signal is input, delivering a signal from another circuit. The KA-OC switch is a normally closed switch that will disconnect the input from the output when a control signal is input, preventing the transfer of signals. The two switches can be selectively used according to the needs to realize different control functions. They function in the circuit to connect and disconnect the circuit, and can be used in the fields of automatic control systems, electronic equipment, industrial control and the like.

As an alternative example, the connector may be a 15PIN connector, wherein a 15PIN connector is a common electrical connector commonly used to connect a circuit board, cable or device to other devices or systems. It has 15 metal pins distributed at both ends of the connector for transmitting electric signals, data signals or power. The 15PIN connector is generally in a right angle or straight line shape, has good mechanical strength and stability, and is suitable for various industrial and consumer electronic devices. It can be used to connect displays, projectors, computers, audio devices, video devices, cameras, etc. The 15PIN connector may have different designations and uses depending on the particular standard and application. The most common 15PIN connector is the VGA connector used to connect a computer to a display for transmitting analog video signals. There are other types of 15PIN connectors, such as D-sub connectors, for serial communications and data transmission.

Generally, a 15PIN connector is a common electrical connector used to connect various devices and systems, transmit signals and power. It has wide application in the fields of computers, displays, audio and video equipment, etc.

In this application, can be connected above-mentioned detection circuitry to on the mainboard, because the mounted state of memory strip can influence the on-off state of first appointed switch to influence the state of first suggestion subassembly and second suggestion subassembly, and then the user can confirm whether the memory strip on the mainboard is installed in place according to the state of first suggestion subassembly and second suggestion subassembly, has solved the problem of unable efficient determination of the mounted state of memory strip on the mainboard, has reduced the not-in-place defective rate of mainboard memory strip installation and has checked the leakage rate.

In an exemplary embodiment, the first prompting component 102 is configured to display a first prompting message when the first specified switch 201 is in a closed state; in the case where the first specified switch 201 is in the off state, no prompt message is displayed; the first prompting message is configured to prompt that the memory bank is successfully installed at a position corresponding to the first designated switch 201 in the memory socket; the second prompting component 103 is configured to not display a prompting message when the first specified switch 201 is in a closed state; in the case that the first specified switch 201 is in the off state, a second prompting message is displayed, where the second prompting message is used to prompt that the memory bank is not successfully installed at a position corresponding to the first specified switch 201 in the memory socket.

It should be noted that, under the condition that the first designated switch is in the closed state, the first intermediate relay is connected with the positive electrode and the negative electrode of the power supply, namely, the first intermediate relay has current, the first target switch is in the closed state, the second target switch is in the open state, at this time, the first prompt component has current, the second prompt component does not have current, the first prompt component displays the first prompt information, and the second prompt component does not display the prompt information.

It should be noted that, under the condition that the first designated switch is in the off state, the first intermediate relay is not connected with the anode and the cathode of the power supply, that is, no current exists in the first intermediate relay, the first target switch is in the off state, the second target switch is in the on state, at this time, no current exists in the first prompt component, no current exists in the second prompt component, the first prompt component does not display prompt information, and the second prompt component displays second prompt information.

In this embodiment, the states of the first prompting component and the second prompting component determine whether the memory bank on the motherboard is installed in place or not, which is more accurate than the state of the first prompting component or the second prompting component alone.

Optionally, the first indicator light may be a green light, the second indicator light may be a red light, and the buzzer is a long-ringing buzzer.

That is, when the first specified switch is in the closed state, the first indicator light emits light (i.e., the first indicator message), the second indicator light does not emit light, and the buzzer does not sound, i.e., the memory bank in the main board is successfully installed at the first specified switch; under the condition that the first specified switch is in an end-on state, the first prompt lamp does not emit light, the second prompt lamp emits light, and the buzzer sounds for a long time (namely, second prompt information), namely, the fact that the memory bank in the main board is not successfully installed at the first specified switch is indicated.

In this embodiment, by selecting the prompting lamp and the long-ringing buzzer as the prompting component, the installation state of the memory bank in the memory socket of the user can be prompted simply and obviously.

In an exemplary embodiment, fig. 2 is a schematic diagram (two) of a detection circuit according to an embodiment of the present application, as shown in fig. 2, where the detection circuit further includes: a target cue component 106, a target intermediate relay 107;

a first terminal (k) of the target prompting component 106 is electrically connected to a first terminal (+) of the power supply 101 through a second target switch 1072 in the target intermediate relay 107, and a second terminal (j) of the target prompting component 106 is electrically connected to a second terminal (-) of the power supply 101;

the first end (m) of the target intermediate relay 107 is electrically connected to the second end (-) of the power source 101, and the second end (n) of the target intermediate relay 107 is electrically connected to the first target contact 1054 of the connector, wherein the second target switch 1072 of the target intermediate relay 107 is in an open state when there is a current in the target intermediate relay 107, and the second target switch 1072 of the target intermediate relay 107 is in a closed state when there is no current in the target intermediate relay 107;

Wherein, the connector 105 is further configured to electrically connect with the third contact 1054 through the first target contact 1054 when the connector 105 is connected with the motherboard 20.

It should be noted that, when the detection circuit is not connected to the motherboard through the connector, the target intermediate relay is not connected to the positive and negative poles of the power supply, and thus no current exists in the target intermediate relay, that is, the second target switch of the target intermediate relay is in the closed state at this time, and thus, current exists in the target prompt component.

Under the condition that the detection circuit is connected with the main board through the connector, the target intermediate relay is connected with the anode and the cathode of the power supply, and then current exists in the target intermediate relay, namely, at the moment, the second target switch of the target intermediate relay is in a disconnection state, and then no current exists in the target prompt component.

In this embodiment, the target prompt component and the target intermediate relay are set in the detection circuit, so that whether the detection circuit is successfully connected with the motherboard can be determined through the target prompt component, and in addition, because the target prompt component can display third prompt information when the connector is not connected with the motherboard, whether the detection circuit is normal can be automatically detected through the target prompt component.

Optionally, the target indicator light is a red light, i.e. the red light is turned on when the connector is not connected to the motherboard, and is turned off when the connector is connected to the motherboard.

As an alternative example, the target presenting component includes a long-ringing buzzer, and further, in a case where the connector is not connected to the main board, the long-ringing buzzer sounds, and in a case where the connector is connected to the main board, the long-ringing buzzer does not sound.

In an exemplary embodiment, as shown in fig. 2, the detection circuit further includes: a time relay 108;

A first end (o) of the time relay 108 is electrically connected to a second end (-) of the power source 101, and a second end (p) of the time relay 108 is electrically connected to a second target contact 1055 of the connector 105;

wherein the connector 105 is further configured to electrically connect with a first end (q) of a detection switch 202 on the motherboard via the third contact 1053 when the connector 105 is connected with the motherboard 20;

wherein the connector 105 is further configured to electrically connect with a second terminal (r) of the detection switch 202 on the motherboard 20 and a first terminal (x) of the switch 1081 of the time relay 108 through the second target contact 1055 when the connector 105 is connected with the motherboard 20,

a second terminal (y) of a switch 1081 of the time relay 108 for electrically connecting with a first terminal (g) of the first designated switch 201 in the case where the connector 105 is connected with the main board 20;

when the time relay has current, the switch of the time relay is in a closed state, and the open-close state of the detection switch has a corresponding relation with the installation state of the memory bar at the position corresponding to the detection switch in the memory socket.

The detection switch in the motherboard is a switch corresponding to a target designated position of the motherboard, and the target designated position is a position on a side surface of the memory card slot.

The time relay is an electrical control device for controlling the switching of the circuit according to a predetermined time delay. It consists of an electromagnetic relay and a timer. The time relay typically comprises an adjustable delay means, which can be set to a desired time delay, typically in seconds or minutes. When the circuit is activated, the time relay starts to count and switches the circuit state after a set time delay. The working principle of the time relay is realized by the attraction and release of the electromagnet. When the circuit is activated, the electromagnet is attracted, so that the contact of the relay is closed, and the circuit is in a conducting state. When the timer is finished, the electromagnet is released, the contact is opened, and the circuit is disconnected. Time relays are widely used in various fields such as automation control systems, power systems, electronic devices, and the like. The device can realize the functions of timing switch, timing alarm, timing start and stop and the like, and improves the automation degree and efficiency of the equipment.

It is noted that, as can be seen from the circuit diagram of fig. 2, when the time relay is conductive, the switch 1081 of the time relay is in a closed state, and thus the first designated switch can be detected.

In this embodiment, a time relay is added to the circuit, so that the detection circuit can control the detection time of the mounting state of the memory bank in the motherboard (i.e., how long later the mounting state of the memory bank in the motherboard starts to be detected).

In one exemplary embodiment, the detection circuit includes: 2N prompt components and N intermediate relays; the connector comprises n+2 contacts, i is a positive integer greater than or equal to 2;

the first end of the 2i-1 prompting component is electrically connected with the second end of the power supply through a first target switch in a first intermediate relay, and the second end of the 2i-1 prompting component is electrically connected with the first end of the power supply;

The first end of the 2 i-th prompt component is electrically connected with the first contact of the connector through a second target switch in the i-th intermediate relay, and the second end of the 2 i-th prompt component is electrically connected with the second end of the power supply;

the first end of the ith intermediate relay is electrically connected with the second end of the power supply, the second end of the ith intermediate relay is electrically connected with the (i+2) th contact of the connector, wherein when the ith intermediate relay has current, the first target switch of the ith intermediate relay is in a closed state and the second target switch of the ith intermediate relay is in an open state, and when the ith intermediate relay does not have current, the first target switch of the ith intermediate relay is in an open state and the second target switch of the ith intermediate relay is in a closed state;

the connector is further configured to electrically connect with a first end of an i-th specified switch on the motherboard through the first contact, electrically connect with a second end of the i-th specified switch through the i+2-th contact, and electrically connect with the first end of the i-th specified switch through the third contact when the connector is connected with the motherboard;

The opening and closing states of the i-th designated switch have a corresponding relation with the installation state of the memory bank at a position corresponding to the i-th designated switch in the memory socket.

As an optional example, N is equal to 3, that is, the on-off state of the first specified switch may be detected by the first prompting component, the second prompting component, and the first intermediate relay, so as to determine the installation state of the memory bank at the position corresponding to the first specified switch in the memory socket; the switch state of the second designated switch can be detected through the third prompting component, the fourth prompting component and the second intermediate relay, and then the installation state of the memory bank at the position corresponding to the second designated switch in the memory socket is determined; the switch state of the third designated switch can be detected through the fifth prompting component, the sixth prompting component and the third intermediate relay, and then the installation state of the memory bank at the position corresponding to the third designated switch in the memory socket is determined.

It will be apparent that the embodiments described above are only some, but not all, of the embodiments of the present application. For better understanding of the above method, the following description will explain the above process with reference to the examples, but is not intended to limit the technical solutions of the embodiments of the present application, specifically:

The application provides a memory bank detecting system mainly relates to PC, server memory bank manual work and automatic installation field, and is specific:

the memory bank detection system comprises: the memory comprises three main components, namely a memory socket on a main board, a memory installation state detection device (namely the detection circuit) and a memory detection 15PIN connector (the detection circuit is provided with a connector, and the main board is provided with an interface corresponding to the connector).

Wherein fig. 3 illustrates a schematic diagram of a motherboard, in which positions of a memory socket are marked, the memory socket includes a front side boss mechanism and a side boss mechanism, fig. 4 illustrates the side boss mechanism of the memory socket (corresponding to a target designated position corresponding to a detection switch in the memory socket), fig. 5 illustrates the front side boss mechanism of the memory socket (corresponding to a position corresponding to a first designated switch and an ith designated switch in the memory socket), fig. 7 illustrates a bottom cross-sectional view of the memory socket, and K1, K2, and K3 switches in fig. 7 correspond to the first designated switch, the second designated switch, and the third designated switch in the above embodiments.

It should be noted that, the memory installation state detection electronic device is connected with the memory socket on the motherboard through the memory detection 15PIN connector.

Fig. 8 is a block diagram schematically showing a structure of a memory mount state detection apparatus, as shown in fig. 8, including: 2001 L1 green light, 2002 L2 green light, 2003 L3 green light, 2004 L4 red light, 2005 L5 red light, 2006 L6 red light, 2007 zg1 buzzer, 2008 zg2 buzzer, 2009 zg3 buzzer, 2010 L7 red light, 2011 zg4 buzzer, 2012 intermediate relay KA1, 2013 intermediate relay KA2, 2014 intermediate relay KA3, 2015 time relay KT1, 2016 ac to dc module, 2017 power switch.

It should be noted that the memory detection 15PIN connector includes: memory detects 15PIN plug, cable, memory and detects 15PIN base, and fig. 6 shows 15PIN base schematic diagram.

The design of the memory detection 15PIN connector connection detection device is adopted, the electronic detection device is independent of a detected object, and can detect while producing, so that the efficiency is improved; the method can also realize that the self-detection of the in-place installation condition of the memory bank of the main board after the main board is electrified.

Optionally, the memory installation state detection device includes: the design of the side circular boss structure of the memory socket (shown in fig. 4, comprising 1001 a circular boss block, 1002 a movable contact, 1003 a fixed contact, 1004 a spring, 1005 a movable contact wiring and 1006 a fixed contact wiring) solves the problem that the memory bar is inserted into the memory socket without damaging the memory bar and the card memory bar.

It should be noted that the memory installation state detection device includes: the front T-shaped boss structure at the bottom of the memory socket (shown in fig. 5, comprising 1101T-shaped protruding blocks, 1102 upper (movable) contacts, 1102 lower (static) contacts, 1104 springs, 1105 upper contact wiring and 1106 lower contact wiring) solves the problem of detecting the in-place condition of 3 points of the memory strip and ensures that the whole memory strip is installed in place.

It should be noted that the memory installation state detection device includes: 2010 The L7 red light, 2011 ZG4 buzzer flashing light and short buzzing buzzer design can remind an operator to insert the 3 memory to detect the 15PIN connector, and guarantee that the memory is required to be in place to be detected every time.

L1 green light, 2002 L2 green light, 2003 L3 green light, 2004 L4 red light, 2005 L5 red light, 2006 L6 red light, 2007 ZG1 buzzer, 2008 ZZG2 buzzer, 2009 ZG3 buzzer, 3 groups of traffic lights and buzzer designs respectively correspond to 3 memory bank detection points, and can prompt an operator which part of a memory bank is not in place.

The 2012 intermediate relays KA1, 2013 intermediate relays KA2 and 2014 intermediate relays KA3 and 3 intermediate relays are adopted for interlocking design, so that the problem that a green light (in place) and a red light and a buzzer (not in place) work simultaneously and false alarm occurs is solved.

The 2015 time relay KT1 is adopted to be connected and then is used for supplying power to the power circuit design of the electric appliances such as the intermediate relay, the green light, the red light, the buzzer and the like, so that the problems of early warning and mess warning of the 2-memory installation state detection electronic device are solved.

As an optional example, the method for detecting the installation state of the memory bank in the motherboard by the memory installation state detection device includes the following steps:

step one: firstly, a power switch of the memory installation state detection electronic device 2017 is turned on, a memory detection 15PIN connector is not required to be inserted into a main board, and 2010 L7 red light flickering and 2011 ZZG4 buzzer dripping and ringing are observed, so that the detection device can work normally.

Step two: adjusting 2015 a time relay KT1 time scale knob, selecting seconds in units, rotating the knob to enable a scale pointer to point to 5, and representing: after the memory bar is inserted into the memory socket, the K4 side boss switch (corresponding to the detection switch) is closed to electrify KT1 for 5 seconds, and then the situation that the memory bar is installed in place is detected. Referring specifically to the circuit diagram of the memory mounted state detection apparatus shown in fig. 9.

Step three: the motherboard is placed on a leveling console (the motherboard referred to herein is a motherboard comprising a front side of the memory socket, a side boss mechanism, and a boss circuit), and the memory bank is inserted into the memory socket.

Step four: after waiting for 5 seconds, observing whether all the green lights of the memory installation state detection electronic devices 2001 L1, 2002L2 and 2003 L3 are on (refer to the flow chart shown in fig. 10 and the logic relation diagram shown in fig. 11), if so, the memory bank is installed in place, and the next motherboard can be continuously installed.

Step five: if not, 2004 L4 red light is on, 2007 ZZG1 buzzer sounds long, the front boss switch 1 is not closed, and the memory is not in place; after the staff is processed, 2004 L4 red light goes out, 2007 ZZG1 buzzer stops, 2001 L1 green light is on, and the staff is put into place.

Step six: if 2005 L5 red light is on and 2008 ZZG2 buzzer sounds, the front boss switch 2 is not closed, and the memory is not installed in place; after staff is processed, 2005 L5 red light goes out, 2008 ZZG2 buzzer stops, 2002L2 green light is on, and then the staff is installed in place.

Step seven: if 2006 L6 red light is on and 2009ZZG3 buzzer sounds long, the front boss switch 2 is not closed, and the memory is not installed in place; after staff is processed, 2006 L6 red light goes out, 2009ZZG buzzer stops, 2003 L3 green light is on, and then the staff is installed in place.

Step eight: after all the alarm fault points are processed and all the 2001 L1 green light, the 2002L2 green light and the 2003 L3 green light are lighted, the step three is skipped.

The following explanation will be made on the principle of the current diagram shown in fig. 9:

the current flows out from the positive electrode of the 24V alternating current-direct current module power supply of the memory installation state detection electronic device 2016, after the socket 1 pin is reached, after the memory bar is inserted into the slot, the boss switch on the k4 side is closed, one path of current returns to the device through the socket 2 pin, so that the time relay KT1 is closed; after the other current is closed at the normally open contact of KT1, two paths of currents are divided, wherein one current flows into the pin of the socket 8 from KT1 to the stationary contacts of the 3 front boss switches k1, k2 and k 3; the other path flows out of the device from the pin 8 of the socket, and the normally closed contacts of the 3 intermediate relays KA1, KA2 and KA3 are arranged.

If the memory inserting clamping groove presses the K1 front boss switch 1 in place, the k1 dynamic and static contacts are not contacted, current flows from the intermediate relay KA1-OC to the L4-long-lighting red lamp and the ZZG-long-ringing buzzer, and after the red lamp and the buzzer are powered on, the red lamp and the buzzer are always on to remind an employee that the memory pressing is not in place.

If the internal memory is pressed in place, the dynamic contact and the static contact of the k1 are contacted, positive current flows to the pin 5 of the socket from the back of the k1 and flows out to the coil of the intermediate relay KA1 of the device, the normally closed contacts of the coil closed KA1-OC are opened, and the normally open contacts of the KA1-ON are closed; the current flows from the KA1-ON normally open contact to L1-green, and L1 gets normally ON, telling the employee that the memory is pressed in place here. Since the normally closed contacts of KA1-OC are opened, the L4-long-lighting type red lamp and ZZG-long-ringing type buzzer are not operated when power is lost. The other two point front boss switches k2, k3 are the same.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application should be included in the protection scope of the present application.

Claims

1. A detection circuit, comprising:

the power supply, the first suggestion subassembly, the second suggestion subassembly, the first intermediate relay, connector;

the first end of the first prompt component is electrically connected with the second end of the power supply through a first target switch in a first intermediate relay, and the second end of the first prompt component is electrically connected with the first end of the power supply;

the first end of the second prompting component is electrically connected with the first contact of the connector through a second target switch in the first intermediate relay, and the second end of the second prompting component is electrically connected with the second end of the power supply;

the first end of the first intermediate relay is electrically connected with the second end of the power supply, the second end of the first intermediate relay is electrically connected with the second contact of the connector, wherein the first target switch is in a closed state and the second target switch is in an open state when current exists in the first intermediate relay, and the first target switch is in an open state and the second target switch is in a closed state when current does not exist in the first intermediate relay;

The connector further includes a third contact electrically connected to the first end of the power source; the connector is used for being electrically connected with a first end of a first designated switch on the main board through the first contact, electrically connected with a second end of the first designated switch through the second contact and electrically connected with the first end of the first designated switch through the third contact under the condition that the connector is connected with the main board;

the opening and closing states of the first specified switch have a corresponding relation with the installation state of the memory bar at a position corresponding to the first specified switch in the memory socket.

2. The detection circuit of claim 1, wherein the detection circuit comprises a logic circuit,

the first prompt component is used for displaying first prompt information under the condition that the first specified switch is in a closed state; under the condition that the first designated switch is in an off state, no prompt message is displayed; the first prompt message is used for prompting that the memory bank is successfully installed at a position corresponding to the first designated switch in the memory socket;

the second prompting component is used for not displaying prompting information under the condition that the first specified switch is in a closed state; and displaying second prompt information when the first specified switch is in an off state, wherein the second prompt information is used for prompting that the memory bank is not successfully installed at a position corresponding to the first specified switch in the memory socket.

3. The detection circuit of claim 1, wherein the detection circuit comprises a logic circuit,

the detection circuit further includes: a target prompting component, a target intermediate relay;

the first end of the target prompt component is electrically connected with the first end of the power supply through a second target switch in the target intermediate relay, and the second end of the target prompt component is electrically connected with the second end of the power supply;

the first end of the target intermediate relay is electrically connected with the second end of the power supply, the second end of the target intermediate relay is electrically connected with the first target contact of the connector, wherein the second target switch of the target intermediate relay is in an open state when current exists in the target intermediate relay, and the second target switch of the target intermediate relay is in a closed state when current does not exist in the target intermediate relay;

the connector is further configured to electrically connect with the third contact through the first target contact when the connector is connected with the motherboard.

4. The detection circuit of claim 3, wherein,

the target prompt component is used for not displaying prompt information under the condition that the connector is connected with the main board; and displaying third prompt information under the condition that the connector is not connected with the main board, wherein the third prompt information is used for prompting that the detection circuit is not connected with the main board.

5. The detection circuit of claim 1, wherein the detection circuit comprises a logic circuit,

the detection circuit further includes: a time relay;

the first end of the time relay is electrically connected with the second end of the power supply, and the second end of the time relay is electrically connected with the second target contact of the connector;

the connector is further configured to electrically connect with a first end of a detection switch on the motherboard through the third contact when the connector is connected with the motherboard;

the connector is further used for being electrically connected with the second end of the detection switch on the main board and the first end of the switch of the time relay through the second target contact under the condition that the connector is connected with the main board; a second end of the switch of the time relay is used for being electrically connected with a first end of the first designated switch under the condition that the connector is connected with the main board;

6. The detection circuit of claim 5, wherein the detection circuit comprises a logic circuit,

the time relay is used for being non-conductive in preset time corresponding to the preset time parameter and conductive after the preset time corresponding to the preset time parameter under the condition that the time parameter is the preset time parameter.

7. The detection circuit of claim 1, wherein the detection circuit comprises a logic circuit,

the detection circuit includes: 2N prompt components and N intermediate relays; the connector comprises n+2 contacts, i is a positive integer greater than or equal to 2;

8. The detection circuit of claim 1, wherein the detection circuit comprises a logic circuit,

the first prompting component comprises: a first indicator light;

the second prompting component comprises: the second warning light and the buzzer.

9. The detection circuit of claim 8, wherein the detection circuit comprises a logic circuit,

the first indicator light is used for being in a light-emitting state when the first specified switch is in a closed state; in an off state with the first specified switch in an off state;

the second prompting lamp is used for being in a luminous state when the first designated switch is in an off state; in an off state with the first designated switch in a closed state;

The buzzer is used for being in an on state under the condition that the first specified switch is in an off state; and the first designated switch is in a closed state when the first designated switch is in a closed state.

10. The detection circuit of claim 4, wherein the detection circuit comprises a logic circuit,

the target cue component comprises: the target prompting lamp is used for being in an extinguishing state under the condition that the connector is connected with the main board; and the connector is in a light-emitting state when not connected with the main board.