CN117539323A - MCU internal clock calibration method, system and chip based on ATE equipment - Google Patents
MCU internal clock calibration method, system and chip based on ATE equipment Download PDFInfo
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Abstract
The invention provides an MCU internal clock calibration method, a system and a chip based on ATE equipment, in particular to the technical field of semiconductors, and the scheme comprises the following steps: starting an internal clock of the MCU, and acquiring a target calibration frequency of the internal clock; determining the frequency of an ATE clock based on the target calibration frequency, wherein the frequency of the ATE clock is a reference frequency; obtaining a typical value based on the reference frequency and the target calibration frequency; capturing real-time frequency of an ATE clock by using an internal clock, initializing values of each bit of a register of the internal clock, constructing a binary operation rule based on the real-time frequency and typical values, and adjusting the values of corresponding bits from high bits to low bits in a bit-by-bit round robin manner to obtain the calibrated internal clock. According to the scheme, the calibration precision can be improved, the test cost and the chip manufacturing cost are reduced, the performance requirement on ATE equipment is low, and the application range of the ATE equipment can be improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an MCU internal clock calibration method, system and chip based on ATE equipment.
Background
At present, along with the rapid development of technology, the micro-controller chip (Microcontroller Unit, MCU), also called singlechip, is increasingly demanded in the fields of smart home, medical treatment, automobiles and the like, and the precision requirement on the MCU chip is also increasingly high. In order to operate properly without the need for an oscillator circuit external to the MCU, MCU manufacturers design one or more internal clock signals, i.e., internal RC oscillators. For reasons of manufacturing process, the accuracy and stability of the internal clock is lower than the external clock, and in order to meet the requirements of normal operation, the clock usually needs to be calibrated.
In the existing scheme based on Timer (TIM) capture, some of the scheme is to output the calibrated clock signal in the MCU through the frequency dividing circuit by adding the frequency dividing circuit. The MCU is internally started with two counting units by providing a clock signal source from the outside, the first counting unit is used for accumulating the number of external reference clocks, the second counting unit is used for accumulating the number of clocks of the clock generating component in the monitoring chip, then the difference value of the two clock numbers is calculated, and the internal register value is modified based on the difference value to calibrate. This solution requires the use of an external clock to generate a high frequency, high precision clock signal, which is costly and time consuming to calibrate.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a method, a system and a chip for calibrating an MCU internal clock based on ATE equipment, which aims to solve the problems of high cost and long calibration time consumption caused by the additional addition of a frequency dividing circuit or an external high-frequency high-precision clock in the existing scheme based on timer capture.
To achieve the above object, a first aspect of the present invention provides a method for calibrating an MCU internal clock based on ATE equipment, including:
starting an internal clock of an MCU (micro control Unit), and acquiring a target calibration frequency of the internal clock;
determining the frequency of an ATE clock based on the target calibration frequency, wherein the frequency of the ATE clock is a reference frequency;
obtaining a representative value based on the reference frequency and the target calibration frequency;
and capturing real-time frequency of the ATE clock by using the internal clock, initializing values of each bit of a register of the internal clock, constructing a binary operation rule based on the real-time frequency and the typical value, and adjusting the values of corresponding bits from high bits to low bits in a bit-by-bit round robin manner to obtain the calibrated internal clock.
Optionally, the initializing the value of each bit of the register of the internal clock, and constructing a binary operation rule based on the real-time frequency and the typical value, and adjusting the value of the corresponding bit from the high bit to the low bit in a bit-by-bit round robin manner, to obtain the calibrated internal clock, including:
Initializing the value of each bit of a register of the internal clock to obtain an intermediate value of the register under binary system;
capturing a real-time frequency of the ATE clock with the internal clock based on the intermediate value, and obtaining a captured value based on the real-time frequency and the target calibration frequency;
comparing the captured value with the typical value, and utilizing the binary operation rule to carry out bit-by-bit round robin adjustment on the value of the corresponding bit from the high bit to the low bit according to the comparison result of the captured value and the typical value until the captured value is equal to the typical value or is adjusted to the lowest bit of the register;
and if the adjusted bit is the lowest bit, respectively adjusting the value of the lowest bit to be 0 or 1, obtaining corresponding calibration errors under different values, determining the value of the lowest bit according to the calibration errors, and obtaining the calibrated internal clock.
Optionally, the step of using the binary operation rule to round-robin the value of the corresponding bit from the high bit to the low bit according to the comparison result of the captured value and the typical value until the captured value is equal to the typical value or is adjusted to the lowest bit of the register includes:
If the capture value is greater than the typical value, the current bit of the register is assigned to 0, and the next bit of the current bit is assigned to 1; if the capture value is smaller than the typical value, the next bit of the current bit of the register is assigned to be 1, the next bit is jumped to, and the round robin adjustment is continued until the capture value is equal to the typical value or is adjusted to the lowest bit of the register.
Optionally, the determining the value of the lowest bit based on the calibration error corresponding to the lowest bit under different values includes:
adjusting the lowest bit to be 1, and capturing the real-time frequency of the ATE clock by utilizing the internal clock to obtain a first capturing value; calculating an absolute value of a difference between the first captured value and the representative value to obtain a first absolute difference value;
adjusting the lowest bit to 0, and capturing the real-time frequency of the ATE clock by using the internal clock to obtain a second capturing value; calculating an absolute value of a difference between the second captured value and the representative value to obtain a second absolute difference;
comparing the first absolute difference value with the second absolute difference value, if the first absolute difference value is smaller than the second absolute difference value, assigning the lowest bit to be 1, otherwise, assigning the lowest bit to be 0.
Optionally, initializing a value of each bit of the register of the internal clock to obtain an intermediate value of the register under binary system includes:
acquiring all bits of a register of the internal clock, and determining a maximum value and a minimum value of the register under decimal;
determining a standard intermediate value of the register under decimal based on the maximum value and the minimum value;
and determining the value of each bit of the register under the binary system based on the standard intermediate value, and obtaining the intermediate value of the register under the binary system.
Optionally, capturing, based on the intermediate value, a real-time frequency of the ATE clock with the internal clock, and obtaining a captured value based on the real-time frequency and the target calibration frequency, including:
determining a clock cycle of the internal clock based on the intermediate value, and capturing a real-time frequency of the ATE clock with the internal clock based on the clock cycle;
and calculating the ratio of the real-time frequency to the target calibration frequency to obtain the capture value.
Optionally, the obtaining a typical value based on the reference frequency and the target calibration frequency includes:
Acquiring the stability and fine-tuning stepping proportion of the internal clock, and acquiring the precision of the ATE clock;
obtaining a representative value based on a ratio of the reference frequency to the target calibration frequency;
if the typical value is less than the fine-tuning step ratio, obtaining a typical value based on the stability, the fine-tuning step ratio, and the accuracy of the ATE clock;
if the typical value is greater than or equal to the fine-tuning step ratio, a typical value is obtained based on the stability, the typical value, and the accuracy of the ATE clock.
A second aspect of the present invention provides an MCU internal clock calibration system based on ATE equipment, the system comprising:
the target calibration frequency acquisition module is used for starting an internal clock of the MCU and acquiring the target calibration frequency of the internal clock;
the reference frequency acquisition module is used for determining the frequency of an ATE clock based on the target calibration frequency, wherein the frequency of the ATE clock is a reference frequency;
a typical value generation module, configured to obtain a typical value based on the reference frequency and the target calibration frequency;
and the calibration module is used for capturing the real-time frequency of the ATE clock by using the internal clock, initializing the values of all bits of a register of the internal clock, constructing a binary operation rule based on the real-time frequency and the typical value, and adjusting the values of the corresponding bits from high bits to low bits in a bit-by-bit round-robin manner to obtain the calibrated internal clock.
A third aspect of the present invention provides a chip comprising a memory, a processor, an internal clock, and an ATE device-based MCU internal clock calibration program stored on the memory and executable on the processor, the ATE device-based MCU internal clock calibration program implementing any one of the above-described ATE device-based MCU internal clock calibration methods steps when executed by the processor.
A fourth aspect of the present invention provides a computer readable storage medium, where an ATE device-based MCU internal clock calibration program is stored, where any one of the steps of the ATE device-based MCU internal clock calibration method described above is implemented when the ATE device-based MCU internal clock calibration program is executed by a processor.
Compared with the prior art, the beneficial effects of this scheme are as follows:
the method of the invention uses the internal clock of the calibrated MCU as the working clock of the timer to capture the high-precision clock generated by ATE, and obtains the calibrated reference object, i.e. typical value, based on the reference frequency and the target calibration frequency; and initializing the values of all bits of a register of the internal clock, constructing a binary operation rule based on the real-time frequency and typical value of the ATE clock captured by the timer, and adjusting the values of corresponding bits from high bits to low bits in a bit-by-bit round robin manner to obtain the calibrated internal clock. According to the scheme, on the premise of ensuring the calibration accuracy, the test cost can be reduced; the correction of the internal clock of the MCU without the frequency dividing circuit can be solved, the frequency dividing circuit is not required to be designed, and the manufacturing cost of the chip can be reduced; the performance requirement on the ATE equipment is low, and the application range of the ATE equipment is improved, so that the testing cost is further reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of an MCU internal clock calibration method based on ATE equipment;
FIG. 2 is a flowchart of an MCU internal clock calibration method based on ATE equipment according to the present invention;
FIG. 3 is a graph comparing calibrated clock signals, high precision clock signals and TIM capture counts for a TIM capture scheme of the prior art;
FIG. 4 is a graph showing the comparison of the calibrated clock signal, the high precision clock signal and the TIM capture count for the calibration method of the present invention;
FIG. 5 is a graph showing the successive correction results of the dichotomy of the invention;
FIG. 6 is a schematic diagram of the structure of bits of the register of the present invention;
FIG. 7 is a schematic diagram of an MCU internal clock calibration system based on ATE equipment according to the present invention;
fig. 8 is a functional block diagram of a chip of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in this specification and the appended claims, the term "if" may be interpreted in context as "when …" or "upon" or "in response to a determination" or "in response to detection. Similarly, the phrase "if a condition or event described is determined" or "if a condition or event described is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a condition or event described" or "in response to detection of a condition or event described".
The following description of the embodiments of the present invention will be made more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown, it being evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present invention is not limited to the specific embodiments disclosed below.
Because the stability of the internal clock of the MCU is poor, the clock frequencies of different MCUs can be different, and in order to ensure the precision of the internal clock of the MCU, MCU manufacturers need to calibrate the clock of each MCU before leaving the factory, so that the application prospect of calibrating the internal clock of the MCU is wide.
The invention is faced with the problems of high cost and long calibration time consumption existing in the existing scheme based on timer capture, when the scheme is used for calibrating an inaccurate clock, a clock with high precision is needed as a reference, the timer is required to realize counting, and a clock source is inevitably needed.
The embodiment of the invention provides an MCU internal clock calibration method based on ATE equipment, which is deployed on electronic equipment such as a computer, a server and the like, is applied to a scene of calibrating an MCU internal clock, and aims at capturing a high-precision clock signal generated by ATE by using a timer. The types of the MCUs are not limited, and may be various types of MCUs applied to the fields of intelligent home appliances, medical appliances, automotive electronics, computer networks and communications, smart cards, etc., and the types of internal clocks of the MCUs are not limited, including but not limited to internal high-speed clocks (HSIs), internal low-speed clocks (LSIs), etc. Specifically, as shown in fig. 1 and fig. 2, the steps of the method in this embodiment include:
step S1000: starting an internal clock of the MCU, and acquiring a target calibration frequency of the internal clock;
specifically, the internal clock of the MCU is started and tuned to the capture function mode, and the counting function is started. And determining a target calibration frequency according to factors such as the frequency of the internal clock and the like, and acquiring the target calibration frequency of the internal clock.
Step S2000: determining the frequency of an ATE clock based on the target calibration frequency, wherein the frequency of the ATE clock is a reference frequency;
specifically, initializing a timer, generating a high-precision clock matched with a target calibration frequency by using ATE (automatic test equipment), namely, an ATE clock for short, as a reference clock, and acquiring the frequency of the ATE clock, wherein the generating of the high-precision clock matched with the target calibration frequency by using ATE refers to generating a clock by using ATE, so that the clock can generate a frequency proportional to the target calibration frequency of an internal clock which is calibrated currently; and the frequency generated when initializing the ATE clock is used as the reference frequency for checking the MCU internal clock.
Step S3000: obtaining a typical value based on the reference frequency and the target calibration frequency;
specifically, since the internal clock of the MCU generally adopts an RC oscillator, in some cases, the internal oscillation frequency of the RC oscillator may drift, most commonly, drift caused by temperature drift and the air tightness of the MCU package, so that the stability of the internal clock of the MCU is not too high, when the internal clock of the MCU is calibrated, a certain range of calibration errors are allowed, that is, as long as the absolute difference between the calibrated frequency of the internal clock and the target calibration frequency is within a specified range, the calibration accuracy requirement is met.
Based on this, the invention takes the ratio of the reference frequency to the target calibration frequency as a typical value of the internal clock of the calibrated MCU.
Step S4000: capturing real-time frequency of an ATE clock by using an internal clock, initializing values of each bit of a register of the internal clock, constructing a binary operation rule based on the real-time frequency and typical values, and adjusting the values of corresponding bits from high bits to low bits in a bit-by-bit round robin manner to obtain the calibrated internal clock.
Specifically, initializing the value of each bit of a register of an internal clock, and capturing the real-time frequency of an ATE clock based on the internal clock of all bits of the register in the current value state; based on the real-time frequency and the typical value, constructing a binary operation rule by taking the principle that the real-time frequency approaches to the target calibration frequency; the binary operation rule is utilized to adjust the value of the corresponding bit in a bit-by-bit round-robin manner from the high bit to the low bit, so that the adjustment amplitude is gradually decreased from large to small, the effectiveness and the accuracy of each calibration can be effectively improved, and the obtained calibration accuracy of the calibrated internal clock can be improved.
In this embodiment, by using the internal clock of the calibrated MCU as the working clock of the timer, to capture the high-precision clock generated by the ATE, it is easy to provide a low-frequency high-precision reference clock by the ATE, and the signal period of this clock can be flexibly adjusted according to the requirement. By adjusting the clock period, the ratio of the real-time frequency of the ATE clock captured by the timer to the target calibration frequency is increased, the calibration step is reduced, and the accuracy is improved. Therefore, the scheme can reduce the test cost on the premise of ensuring the calibration precision; the correction of the internal clock of the MCU without the frequency dividing circuit can be solved, the frequency dividing circuit is not required to be designed, and the manufacturing cost of the chip can be reduced; the performance requirement on the ATE equipment is low, and the application range of the ATE equipment is improved, so that the testing cost is further reduced.
Referring to fig. 2, in one embodiment, initializing the values of the respective bits of the register of the internal clock in step S4000, and constructing a binary operation rule based on the real-time frequency and the typical value, and adjusting the values of the respective bits from the high order to the low order by the bit-wise round robin to obtain the calibrated internal clock specifically includes:
Step S4100: initializing the values of each bit of a register of an internal clock to obtain an intermediate value of the register under binary system;
specifically, according to the number of bits of the register, a standard intermediate value of the register in decimal is determined, and each bit of the register is assigned such that the value of the register is initialized to an integer closest to the standard intermediate value in decimal as the intermediate value of the register in binary. It will be readily appreciated that when there are two integers closest to the standard intermediate value in decimal, then the higher bit value of the register in binary is taken as the intermediate value.
Step S4200: capturing real-time frequency of an ATE clock by utilizing an internal clock based on the intermediate value, and obtaining a captured value based on the real-time frequency and a target calibration frequency;
specifically, the frequency of the internal clock changes due to the different bit values in the registers. The frequency of the internal clock is adjusted by changing the value of each bit of the register, the signal period of the internal clock after each adjustment is measured, and the real-time frequency of the ATE clock is captured by the internal clock, so that the current frequency of the internal clock is reflected through the captured real-time frequency. The embodiment takes the ratio of the real-time frequency to the target calibration frequency as the capture value to indirectly reflect the frequency of the internal clock.
Step S4300: comparing the captured value with the typical value, and utilizing a binary operation rule to round-robin the value of the corresponding bit from the high bit to the low bit according to the comparison result of the captured value and the typical value until the captured value is equal to the typical value or to the lowest bit of the register, so that the captured value is close to or equal to the typical value.
Specifically, based on the intermediate value and the typical value obtained by initializing the register, the intermediate value is adjusted so that the frequency of the internal clock is closer to the target calibration frequency, and an updated intermediate value is obtained, and it is easy to understand that the updated intermediate value obtained by each halving operation is closer to the value of the register corresponding to the internal clock at the target calibration frequency than the intermediate value obtained by the last halving operation.
With the change of the intermediate value, the real-time frequency of the ATE clock captured by the internal clock is also changed accordingly, so that the captured value is updated once every time a binary operation is performed.
Step S4400: if the adjusted bit is the lowest bit, respectively adjusting the value of the lowest bit to be 0 or 1, obtaining the corresponding calibration error under different values, determining the value of the lowest bit according to the calibration error, and obtaining the calibrated internal clock.
In this embodiment, the binary operation rule is utilized to perform the binary operation by adjusting the corresponding bit value from the high bit to the low bit in a bit-by-bit round-robin manner, the number of times of performing the binary operation is the same as the number of bits of the register, and in practical application, the actual calibration times are often smaller than the number of bits of the register, compared with the number of times of exponent power in the prior art, the number of times of calibration is greatly reduced, and the calibration efficiency and precision are effectively improved. Meanwhile, the algorithm complexity is reduced, the test time is shortened, the production cost is reduced, and the method has a wide application prospect.
Referring to fig. 2, in one embodiment, the comparing result of the captured value and the typical value in step S4300 is used to sequentially adjust the value of the corresponding bit from the high bit to the low bit by using the binary operation rule until the captured value is equal to the typical value or is adjusted to the lowest bit of the register, which specifically includes:
if the capture value is greater than the typical value, the current bit of the register is assigned to 0, and the next bit of the current bit is assigned to 1; if the capture value is smaller than the typical value, the next bit of the current bit of the register is assigned to be 1, and the next bit is jumped to, and the round robin adjustment is continued until the capture value is equal to the typical value or the lowest bit of the register is adjusted.
Specifically, if the capture value is greater than the typical value, the current bit of the register is assigned 0 and the next bit of the current bit is assigned 1. If the adjustment is successful, shifting to the next bit, namely, making N=N-1, returning to the signal period of the internal clock, capturing the real-time frequency of the ATE clock by using the internal clock, continuously executing the calibration operation according to the bit, and the like; if the adjustment is unsuccessful, a fault prompt message is sent out.
If the capture value is less than the typical value, the next bit of the current bit of the register is assigned a value of 1. If the adjustment is successful, shifting to the next bit, namely, making N=N-1, returning to the signal period of the internal clock, capturing the real-time frequency of the ATE clock by using the internal clock, continuously executing the calibration operation according to the bit, and the like; if the adjustment is unsuccessful, a fault prompt message is sent out.
In this embodiment, in the process of performing the round robin adjustment on the bits of the register from the high position to the low position in steps S4510 and S4520, the discrimination operation and the fault prompting function of the calibration bit are added, so that each calibration is ensured to be strictly performed according to the set rule, the bit number of each calibration is clearly grasped, and the accuracy of the calibration and the fault detection efficiency can be effectively improved.
Referring to fig. 2, in one embodiment, determining the value of the lowest bit in step S4400 based on the calibration error corresponding to the lowest bit under different values specifically includes:
step S4410: adjusting the lowest bit to be 1, and capturing the real-time frequency of an ATE clock by using an internal clock to obtain a first capturing value; calculating an absolute value of a difference between the first captured value and the representative value to obtain a first absolute difference value;
specifically, the lowest bit is adjusted to be 1, a timer is utilized to capture a signal period of an internal clock, the frequency corresponding to the signal period is regarded as the current real-time frequency of the ATE clock, and the ratio of the current real-time frequency to the target calibration frequency is used as a first capture value. Then, the absolute value of the difference between the first captured value and the representative value is calculated, and a first absolute difference value is obtained.
Step S4420: adjusting the lowest bit to 0, and capturing the real-time frequency of the ATE clock by using the internal clock to obtain a second capturing value; calculating the absolute value of the difference between the second captured value and the typical value to obtain a second absolute difference value;
specifically, the principle is the same as that of step S4410, and there is no sequential division between step S4410 and step S4420.
Step S4430: and comparing the first absolute difference value with the second absolute difference value, if the first absolute difference value is smaller than the second absolute difference value, assigning the lowest bit to be 1, and otherwise, assigning the lowest bit to be 0.
In this embodiment, since the lowest bit does not have the next bit, the rules of step S4510 and step S4520 are not met, so that in order to ensure that the accuracy of the calibrated internal clock is the highest, all possible values of the lowest bit are adjusted and pre-determined, and then the calibration errors corresponding to the lowest bit under different values are compared, and the value corresponding to the smaller calibration error is assigned to the lowest bit, so as to minimize the calibration error.
In one embodiment, initializing the values of the bits of the register of the internal clock in step S4100, obtaining the intermediate value of the register in binary, specifically includes:
step S4110: acquiring all bits of a register of an internal clock, and determining the maximum value and the minimum value of the register under decimal system;
step S4120: determining a standard intermediate value of the register under decimal based on the maximum value and the minimum value;
step S4130: based on the standard intermediate values, the values of the bits of the register in binary are determined, and the intermediate values of the register in binary are obtained.
Specifically, in order to improve the calibration efficiency, the embodiment initializes each bit of the register to obtain an approximate intermediate value, which is favorable for performing fine adjustment upwards or fine adjustment upwards based on the intermediate value in the calibration process, so as to accelerate the calibration speed. For example, a register is known to have 4 binary bits, and it is easy to know that the maximum value of the binary of the register is 1111, 15 after decimal conversion, 0000, 0 after decimal conversion, and then the intermediate value under decimal is 7.5, not an integer. Thus, the initialization register is an integer of 7 or 8 near 7.5, and 7 or 8 after the initialization assignment is approximated as an intermediate value. Similarly, if the register has N bits, its maximum value is 2 N -1, with the lowest order 0 and the middle value ofThe corresponding approximate binary number is 10..0, wherein the number of 0 is N-1. As can be seen from the above, regardless of the number of bits N of the register, initialization is performed such that the most significant bit is 1 and the remaining bits are 0, which is the case closest to the standard intermediate value in decimal, the initialization method is generally applicable to various types of internal clocks.
In the embodiment, the intermediate value of the register obtained by the initialization method is closer to the real frequency of the internal clock and closer to the actual situation, and the method can be suitable for different types of registers and internal clocks, has wide universality, is diversified in application scenes,
in one embodiment, capturing the real-time frequency of the ATE clock with the internal clock based on the intermediate value in step S4200 and obtaining the captured value based on the real-time frequency and the target calibration frequency specifically includes:
step S4210: determining a clock cycle of the internal clock based on the intermediate value, and capturing a real-time frequency of the ATE clock with the internal clock based on the clock cycle;
step S4220: and calculating the ratio of the real-time frequency to the target calibration frequency to obtain a capture value.
In this embodiment, the capture value is related to the real-time frequency and the target calibration frequency, and the typical value is related to the reference frequency and the target calibration frequency, so that the real-time frequency and the reference frequency of the ATE clock can be linked through the capture value and the typical value, thereby realizing indirect comparison of the real-time frequency and the reference frequency, and having simple implementation, small calculation amount, and convenience and rapidness.
In one embodiment, the obtaining a typical value in step S3000 based on the reference frequency and the target calibration frequency specifically includes:
step S3100: acquiring the stability of an internal clock and the fine-tuning stepping proportion, and acquiring the precision of an ATE clock;
step S3200: obtaining a typical value based on the ratio of the reference frequency to the target calibration frequency;
step S3300: if the typical value is less than the fine-tuning step ratio, obtaining the typical value based on the stability, the fine-tuning step ratio, and the accuracy of the ATE clock;
step S3400: if the typical value is greater than or equal to the fine-tuning step ratio, the typical value is obtained based on the stability, the typical value, and the accuracy of the ATE clock.
In this embodiment, in order to calibrate to as high an accuracy as possible, the following parameters need to be considered:
1) Internal clock stability, denoted by W;
2) The accuracy of the calibrated reference clock, denoted by Racc;
3) Fine tuning of step ratio of internal clockA representation;
4) The ratio of the reference frequency to the target calibration frequency of the calibrated clock, i.e. the typical value, is denoted vtyp= (fref/ftyp), where fref denotes the frequency value of the reference clock and ftyp denotes the target calibration frequency value of the calibrated clock.
Combining the above parameters, a simulation formula is obtained:
If it isCalibration error->
If it isCalibration error->
If the internal clock stability of the chip is designed to be high enough under ideal conditions, the frequency requirement is stable enough and no fluctuation exists, thenThe calibrated reference clock source is a low frequency high precision clock provided by the ATE equipment (usually with a precision error of about 20 ppm), whose deviation is negligible, i.e. +.>
Thus, the simulation formula can be reduced to:
if it isCalibration error->Indicating that the hardware design value limit has been reached at this time, the step value may be taken as the minimum deviation;
if it isCalibration error/>It is shown that the ratio of the reference frequency to the target calibration frequency cannot be scaled up due to the limitations of the external environment on the reference frequency of the ATE clock, so the inverse of the typical value can be taken as the minimum deviation.
The invention can output a low-frequency high-precision reference clock by adjusting ATE, so that the ratio of the reference frequency to the target calibration frequency is increased, and errors caused by external environment can be ignored, therefore,calibration error->At this time, the accuracy of the internal clock reaches the hardware design limit, and the deviation under the corresponding step value is minimum.
Further, after obtaining the calibrated internal clock in step S4000, the method further includes: the values of the respective bits of the calibrated register of the internal clock are stored into the nonvolatile region of the MCU.
Specifically, the values of each bit of the register after calibration are stored in a nonvolatile area in an internal memory area of the MCU, for example, an address corresponding to a FLASH area, so that the optimal value of each bit of the register is recorded, and meanwhile, the value can be used as a reference calibration value of the MCU of the same type to be shipped, so that the calibration efficiency is further improved, the cost is saved, and the economic benefit of MCU manufacturers is improved.
Further, the method repeatedly executes the re-power-off and then powers on, and outputs the periodic signal of the next calibrated MCU internal clock through the general purpose input/output (General Purpose Input Output, GPIO), namely the IO port.
The feasibility and effectiveness of the calibration method of the invention are respectively verified by adopting a mode of comparison analysis with the prior art, and the method is specifically as follows:
example one: known as a calibrated MCU chip incapable of frequency division, the output frequency of the internal clock (i.e., the target calibration frequency) is designed to be 10MHz, with a step ratio of 0.5%, where step ratio = target calibration frequency/TIM clock operating frequency.
(1) Using the TIM capture scheme of the prior art, the TIM clock employs an externally supplied high frequency high precision clock, which is set to XMHz, and x=2000 is found from 10:x=0.5%, which requires an externally supplied high frequency high precision clock signal of 2000MHz as a reference clock (i.e., ATE clock). In actual mass production, it is difficult to generate a stable 2000MHz clock by ATE equipment commonly used in the industry, and professional crystal oscillator is usually required to be provided externally. The calibrated clock signal, the high precision clock signal, and the TIM capture count versus graph of the prior art TIM capture scheme are shown in fig. 3, where the abscissa represents time in ns, the ordinate represents voltage value in mv, and the time period between the two vertical dashed lines intersecting the abscissa represents one clock cycle. It can be seen that the value of the TIM capture count reflects the current operating frequency of the internal clock, and that the frequency of the high precision clock signal is much higher than that of the calibrated clock signal, not easy to implement and is unstable, with low feasibility.
(2) The method adopts the calibrated internal clock output by the MCU as the working clock of the timer TIM; the ATE provides a low frequency high precision clock, which is given as YMHz, and if y=0.05 is found according to Y: 10=0.5%, then the ATE device is required to provide a 50KHz clock, which is easier for ATE devices commonly used in the industry, no additional circuitry is required to be externally connected, and the clock can be adjusted, which verifies the feasibility of the method of the present invention. The calibrated clock signal, the high-precision clock signal and the TIM capture count comparison chart of the calibration method are shown in fig. 4, wherein the abscissa represents time, the ordinate represents voltage value, and the time period between two vertical dashed lines intersecting the abscissa represents one clock period. The value of the TIM capture count can reflect the current operating frequency of the internal clock, and the frequency of the high-precision clock signal is far lower than that of the calibrated clock signal, so that the method is easy to realize, good in stability and high in feasibility.
Based on the above feasibility analysis of the method of the present invention, an MCU with an internal clock having a target calibration frequency of 10MHz (period 100 ns) is known, and assuming that the period T1 of the high precision clock generated by ATE is 1000ns, the period ratio of the clock to the target calibration frequency is 10:1. Assuming a TIM capture value of 900MHz at this time, the ratio of TIM capture to target calibration frequency is 9:1, and when the period T2 of the ATE-generated high precision clock is 2000ns, the ratio of TIM capture to target calibration frequency is 20:1, the ratio of TIM capture to target calibration frequency is 18:1. It can be seen that the larger the ratio of the captured value of the internal clock timer TIM to the target calibration frequency, the smaller the step. Thus, the clock frequency generated by the ATE is further controlled so that the ratio of the captured value of the internal clock timer TIM to the target calibration frequency is approximately 20:1; the accuracy of the calibration can be effectively improved.
Example two: the algorithm scheme of the dichotomy is adopted, a register of an internal clock of the MCU to be calibrated is known to have 12 bits, and if an adjustment method of gradually increasing or decreasing in the prior art is adopted, the maximum number of times of adjustment is 12 11 2047 times, but if the dichotomy proposed by the present invention is adopted, the adjustment is performed in a round-robin manner according to the successive approximation method from high order to low order, and at most 12 times, i.e., one adjustment is performed for each bit. Therefore, the dichotomy provided by the invention can greatly shorten the correction time, thereby reducing the test cost of the chip and effectively verifying the effectiveness of the method.
FIG. 5 is a schematic diagram of successive correction results of the dichotomy proposed by the present invention, wherein the abscissa represents the bits of the register, including coarse bits and fine bits, and the ordinate represents the frequency of the calibrated internal clock. Therefore, according to the sequential calibration from high level to low level, the calibrated amplitude is gradually reduced from large level, that is, the internal clock is firstly subjected to rough adjustment and then fine adjustment, so that the frequency of the internal clock is more and more close to the target calibrated frequency. FIG. 6 is a schematic diagram of the structure of each bit of the register, wherein, from the high order to the low order, coarse adjustment is achieved by calibrating the first six bits (i.e. 12 th to 7 th bits, denoted as [11:6 ]), fine adjustment is achieved by calibrating the last six bits (i.e. 6 th to 1 st bits, denoted as [5:0 ]), and the value of each bit is the result after calibration.
As shown in fig. 7, corresponding to the above method for calibrating an MCU internal clock based on ATE equipment, an embodiment of the present invention further provides an MCU internal clock calibration system based on ATE equipment, where the MCU internal clock calibration system based on ATE equipment includes:
the target calibration frequency acquisition module 710 is configured to start an internal clock of the MCU and acquire a target calibration frequency of the internal clock;
a reference frequency acquisition module 720, configured to determine, based on the target calibration frequency, a frequency of an ATE clock, where the frequency of the ATE clock is the reference frequency;
a typical value generation module 730 for obtaining a typical value based on the reference frequency and the target calibration frequency;
the calibration module 740 is configured to capture a real-time frequency of the ATE clock by using the internal clock, initialize values of bits of a register of the internal clock, construct a binary operation rule based on the real-time frequency and the typical value, and cycle the values of the corresponding bits from high to low bits, so as to obtain the calibrated internal clock.
Specifically, in this embodiment, the specific function of the above-mentioned MCU internal clock calibration system based on ATE equipment may also refer to the corresponding description in the above-mentioned MCU internal clock calibration method based on ATE equipment, which is not described herein again.
Based on the above embodiment, the present invention also provides a chip, and a functional block diagram thereof may be shown in fig. 8. The chip comprises a processor, a memory, an internal clock and a correction interface which are connected through a system bus. The internal clock comprises a timer and a register, wherein the timer is used for capturing the real-time frequency of the internal clock, and the register is used for storing clock information of the internal clock. The processor of the chip is used to provide computing and control capabilities. The memory of the chip comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and an MCU internal clock calibration program based on ATE equipment. The internal memory provides an environment for the operation of an operating system in a non-volatile storage medium and an MCU internal clock calibration program based on ATE equipment. The calibration interface of the chip is used for electrical connection with external ATE equipment. The MCU internal clock calibration program based on the ATE equipment realizes the steps of any one of the MCU internal clock calibration methods based on the ATE equipment when being executed by a processor.
It will be appreciated by those skilled in the art that the functional block diagram shown in FIG. 8 is merely a block diagram of some of the structures associated with the present inventive arrangements and is not limiting of the chip to which the present inventive arrangements may be applied, and that a particular chip may include more or less components than those shown, or may be combined with some components, or may have a different arrangement of components.
In one embodiment, a chip is provided, where the chip includes a memory, a processor, and an ATE device-based MCU internal clock calibration program stored in the memory and capable of running on the processor, where the ATE device-based MCU internal clock calibration program implements any one of the steps of the ATE device-based MCU internal clock calibration method provided in the embodiments of the present invention when executed by the processor.
The embodiment of the invention also provides a computer readable storage medium, on which an MCU internal clock calibration program based on the ATE equipment is stored, and when the MCU internal clock calibration program based on the ATE equipment is executed by a processor, the steps of any one of the MCU internal clock calibration methods based on the ATE equipment provided by the embodiment of the invention are realized.
It should be understood that the sequence number of each step in the above embodiment does not mean the sequence of execution, and the execution sequence of each process should be determined by its function and internal logic, and should not be construed as limiting the implementation process of the embodiment of the present invention.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, the specific names of the functional units and modules are only for distinguishing from each other, and are not used for limiting the protection scope of the present invention. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other manners. For example, the apparatus/terminal device embodiments described above are merely illustrative, e.g., the division of the modules or units described above is merely a logical function division, and may be implemented in other manners, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed.
The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will understand that; the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions are not intended to depart from the spirit and scope of the various embodiments of the invention, which are also within the spirit and scope of the invention.
Claims (10)
1. The MCU internal clock calibration method based on the ATE equipment is characterized by comprising the following steps of:
starting an internal clock of an MCU (micro control Unit), and acquiring a target calibration frequency of the internal clock;
determining the frequency of an ATE clock based on the target calibration frequency, wherein the frequency of the ATE clock is a reference frequency;
obtaining a representative value based on the reference frequency and the target calibration frequency;
and capturing real-time frequency of the ATE clock by using the internal clock, initializing values of each bit of a register of the internal clock, constructing a binary operation rule based on the real-time frequency and the typical value, and adjusting the values of corresponding bits from high bits to low bits in a bit-by-bit round robin manner to obtain the calibrated internal clock.
2. The method for calibrating an internal clock of an MCU based on an ATE device according to claim 1, wherein initializing the values of the bits of the register of the internal clock, and constructing a binary operation rule based on the real-time frequency and the typical value, and adjusting the values of the corresponding bits from a higher order to a lower order by a bit-by-bit round robin, to obtain the calibrated internal clock, comprises:
initializing the value of each bit of a register of the internal clock to obtain an intermediate value of the register under binary system;
capturing a real-time frequency of the ATE clock with the internal clock based on the intermediate value, and obtaining a captured value based on the real-time frequency and the target calibration frequency;
comparing the captured value with the typical value, and utilizing the binary operation rule to carry out bit-by-bit round robin adjustment on the value of the corresponding bit from the high bit to the low bit according to the comparison result of the captured value and the typical value until the captured value is equal to the typical value or is adjusted to the lowest bit of the register;
and if the adjusted bit is the lowest bit, respectively adjusting the value of the lowest bit to be 0 or 1, obtaining corresponding calibration errors under different values, determining the value of the lowest bit according to the calibration errors, and obtaining the calibrated internal clock.
3. The method according to claim 2, wherein the adjusting the value of the corresponding bit by bit from the high order to the low order by using the binary operation rule according to the comparison result of the captured value and the typical value until the captured value is equal to the typical value or the captured value is adjusted to the lowest order of the register comprises:
if the capture value is greater than the typical value, the current bit of the register is assigned to 0, and the next bit of the current bit is assigned to 1; if the capture value is smaller than the typical value, the next bit of the current bit of the register is assigned to be 1, the next bit is jumped to, and the round robin adjustment is continued until the capture value is equal to the typical value or is adjusted to the lowest bit of the register.
4. The method for calibrating an MCU internal clock based on an ATE device according to claim 2, wherein determining the value of the least significant bit based on the calibration error corresponding to the least significant bit at different values comprises:
adjusting the lowest bit to be 1, and capturing the real-time frequency of the ATE clock by utilizing the internal clock to obtain a first capturing value; calculating an absolute value of a difference between the first captured value and the representative value to obtain a first absolute difference value;
Adjusting the lowest bit to 0, and capturing the real-time frequency of the ATE clock by using the internal clock to obtain a second capturing value; calculating an absolute value of a difference between the second captured value and the representative value to obtain a second absolute difference;
comparing the first absolute difference value with the second absolute difference value, if the first absolute difference value is smaller than the second absolute difference value, assigning the lowest bit to be 1, otherwise, assigning the lowest bit to be 0.
5. The method according to claim 2, wherein initializing the values of the bits of the register of the internal clock to obtain the intermediate values of the register in binary comprises:
acquiring all bits of a register of the internal clock, and determining a maximum value and a minimum value of the register under decimal;
determining a standard intermediate value of the register under decimal based on the maximum value and the minimum value;
and determining the value of each bit of the register under the binary system based on the standard intermediate value, and obtaining the intermediate value of the register under the binary system.
6. The ATE device-based MCU internal clock calibration method of claim 2, wherein the capturing the real-time frequency of the ATE clock with the internal clock based on the intermediate value and obtaining the captured value based on the real-time frequency and the target calibration frequency comprises:
Determining a clock cycle of the internal clock based on the intermediate value, and capturing a real-time frequency of the ATE clock with the internal clock based on the clock cycle;
and calculating the ratio of the real-time frequency to the target calibration frequency to obtain the capture value.
7. The ATE-device-based MCU internal clock calibration method of claim 1, wherein the obtaining a typical value based on the reference frequency and the target calibration frequency comprises:
acquiring the stability and fine-tuning stepping proportion of the internal clock, and acquiring the precision of the ATE clock;
obtaining a representative value based on a ratio of the reference frequency to the target calibration frequency;
if the typical value is less than the fine-tuning step ratio, obtaining a typical value based on the stability, the fine-tuning step ratio, and the accuracy of the ATE clock;
if the typical value is greater than or equal to the fine-tuning step ratio, a typical value is obtained based on the stability, the typical value, and the accuracy of the ATE clock.
8. An ATE-device-based MCU internal clock calibration system, the system comprising:
the target calibration frequency acquisition module is used for starting an internal clock of the MCU and acquiring the target calibration frequency of the internal clock;
The reference frequency acquisition module is used for determining the frequency of an ATE clock based on the target calibration frequency, wherein the frequency of the ATE clock is a reference frequency;
a typical value generation module, configured to obtain a typical value based on the reference frequency and the target calibration frequency;
and the calibration module is used for capturing the real-time frequency of the ATE clock by using the internal clock, initializing the values of all bits of a register of the internal clock, constructing a binary operation rule based on the real-time frequency and the typical value, and adjusting the values of the corresponding bits from high bits to low bits in a bit-by-bit round-robin manner to obtain the calibrated internal clock.
9. A chip comprising a memory, a processor, an internal clock, and an ATE device-based MCU internal clock calibration program stored on the memory and executable on the processor, which when executed by the processor, implements the steps of the ATE device-based MCU internal clock calibration method of any one of claims 1-7.
10. A computer readable storage medium, wherein an ATE device based MCU internal clock calibration program is stored on the computer readable storage medium, and when the ATE device based MCU internal clock calibration program is executed by a processor, the steps of the ATE device based MCU internal clock calibration method according to any one of claims 1-7 are implemented.
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