CN117527151B - UCIE-based data retransmission method - Google Patents
UCIE-based data retransmission method Download PDFInfo
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Abstract
The application provides a data retransmission method based on UCIE, which is applied to a chip pair for data interaction based on UCIE, wherein an adaptation layer of a first chip in the chip pair comprises a data sending module, and an adaptation layer of a second chip in the chip pair comprises a data receiving module, and the method comprises the following steps: the data sending module stops sending the residual data in the current batch of data and sends the retransmission data corresponding to the latest retransmission request to the data receiving module if the retransmission request is received in the process of sending the retransmission data corresponding to the current retransmission request or the data from the protocol layer to the data receiving module; the data receiving module performs real-time effective head batch judgment on the received data, adjusts the decoding position based on the result of the effective head batch judgment so as to send target data in the received data to the protocol layer of the second chip, and can support any position to initiate retransmission, thereby improving the link utilization rate and the retransmission operation efficiency.
Description
Technical Field
The application relates to the technical field of high-speed interconnection, in particular to a data retransmission method based on UCIE.
Background
UCIE (Universal Chiplet Interconnect Express, universal core interconnection standard) is the fastest current solution in the high-speed interconnection field, and an Adapter Layer is used as a middle Layer of a three-Layer structure, so that the conversion from an FDI (Flit-Aware D2D Interface) Interface to an RDI (Raw D2D Interface) Interface needs to be realized, and the correct transmission of data to an opposite end is ensured through retransmission operation.
When the uci uses a 64B (B refers to Byte) Flit format to transmit data, the adaptation layer needs to transmit 17 data to the physical layer (i.e., PHY) per 16 valid data of the transmission protocol layer, since each data needs to add a header of 2B and a CRC (Cyclic Redundancy Check ) of 2B. Fig. 1 is a timing diagram of a conventional retransmission operation signal, as shown in fig. 1, assuming that the adaptation layer initiates a data retransmission operation (e.g., needs to transmit D0-D16) when the watchdog overflows, a late NAK signal is received when the adaptation layer retransmits D0 (informing D0-D16 has been properly resolved by the receiving module RX, and D17-D33 is in error and needs to be retransmitted). For this situation, the current industry performs data retransmission in a boundary alignment manner, that is, it is known that D0-D16 has been resolved correctly, and still sends D0-D16 out, and then initiates the retransmission operation corresponding to D17-D33. However, in the case where D0-D16 has been properly resolved by RX, it is not meaningful to continue to retransmit D0-D16 (which RX will discard) and waste the effective bandwidth, which in turn results in unnecessary overhead, reducing link utilization and retransmission efficiency.
Disclosure of Invention
The application provides a UCIE-based data retransmission method, which is used for solving the problem that the existing UCie-based data retransmission scheme cannot achieve the highest transmission efficiency.
The application provides a data retransmission method based on UCIE, the method is applied to a chip pair which carries out data interaction based on UCIE, an adaptation layer of a first chip in the chip pair comprises a data sending module, and an adaptation layer of a second chip in the chip pair comprises a data receiving module, and the method comprises the following steps:
the data sending module stops sending the residual data in the current batch of data and sends the retransmission data corresponding to the latest retransmission request to the data receiving module if the retransmission request is received in the process of sending the retransmission data corresponding to the current retransmission request or the data from the protocol layer to the data receiving module;
the data receiving module performs real-time effective head batch judgment on the received data, and adjusts the decoding position based on the result of the effective head batch judgment so as to send target data in the received data to a protocol layer of the second chip.
According to the uci-based data retransmission method provided in the present application, the performing real-time effective head-batch judgment on the received data, and adjusting the decoding position based on the result of the effective head-batch judgment to send the target data in the received data to the protocol layer of the second chip specifically includes:
Sequentially carrying out effective batch head judgment on the received data packets, and adjusting the value of a batch decoding polling register based on the result of the effective batch head judgment;
and determining a current decoding position based on the result of the effective head-of-batch judgment and the value of the batch decoding polling register, decoding target data in the received data based on the current decoding position, and transmitting the decoded target data to a protocol layer of the second chip.
According to the uci-based data retransmission method provided in the present application, the adjusting the value of the batch decoding polling register based on the result of the valid batch head determination specifically includes:
step S01, judging whether the last data packet is a valid head, if so, executing step S02, and if not, executing step S03;
step S02, setting the value of the batch decoding polling register to 2;
step S03, judging whether the current data packet is a potential head, if so, executing step S04, and if not, executing step S05;
step S04, setting the value of the batch decoding polling register to be 1;
step S05, judging whether the polling end zone bit, the check code error zone bit and the jump number zone bit are all 0, if so, executing step S06, otherwise, executing step S07;
step S06, setting the value of the batch decoding polling register as the sum of the current decoding position and 1;
In step S07, the value of the batch decode poll register is set to 0.
According to the uci-based data retransmission method provided in the present application, the determining the current decoding position based on the result of the valid batch head judgment and the value of the batch decoding polling register specifically includes:
step S11, judging whether the last data packet is a valid head, if so, executing step S12, otherwise, jumping to execute step S13;
step S12, setting the current decoding position to be 1, and decoding data from the beginning to be sent to a protocol layer of the second chip;
step S13, judging whether the previous data packet is an invalid head, if so, executing step S14, otherwise, jumping to execute step S15;
step S14, taking the sum of the last decoding position and 1 as the current decoding position;
step S15, the value of the batch decoding polling register is used as the current decoding position.
According to the uci-based data retransmission method provided in the present application, the determining whether the last data packet is an effective header specifically includes:
and under the condition that the previous data packet simultaneously meets all conditions in the potential batch first judging condition set, judging whether the current data packet simultaneously meets all conditions in the potential batch first judging condition set, and if so, judging that the previous data packet is a valid batch first.
According to the uci-based data retransmission method provided in the present application, the determining whether the previous data packet is an invalid header specifically includes:
and under the condition that the previous data packet simultaneously meets all conditions in the potential batch first judging condition set, judging whether the current data packet simultaneously meets all conditions in the potential batch first judging condition set, and if not, judging that the previous data packet is an invalid batch first.
According to the uci-based data retransmission method provided in the present application, the conditions in the potential batch head judgment condition set include: the protocol type is correct, the effective data is sent, and the serial number is the batch head number;
the conditions in the potential secondary batch first judgment condition set comprise: the protocol type is correct, the effective data is sent, the serial number is the first serial number of the next batch, and the comparison of the jump number and the check code is successful.
According to the UCIE-based data retransmission method provided by the application, the value of the polling end flag bit is determined based on the current decoding position, and when the value of the current decoding position is equal to the batch length, the polling end flag bit is 1, otherwise, the polling end flag bit is 0.
According to the UCIE-based data retransmission method provided by the application, the value of the error flag bit of the check code is determined based on the comparison result of the reference check code in the current data packet and the actual check code obtained based on the previous data calculation, and if the reference check code is different from the actual check code, the error flag bit of the check code is 1, otherwise, the error flag bit of the check code is 0.
According to the uci-based data retransmission method provided in the present application, the value of the skip number flag bit is determined based on the difference between the sequence number of the current data packet and the sequence number of the previous data packet, if the difference is not 1, the skip number flag bit is 1, otherwise, is 0.
The data retransmission method based on UCIE is applied to a chip pair for data interaction based on UCIE, wherein an adaptation layer of a first chip in the chip pair comprises a data sending module, and an adaptation layer of a second chip in the chip pair comprises a data receiving module, and the method comprises the following steps: the data sending module stops sending the residual data in the current batch of data and sends the retransmission data corresponding to the latest retransmission request to the data receiving module if the retransmission request is received in the process of sending the retransmission data corresponding to the current retransmission request or the data from the protocol layer to the data receiving module; the data receiving module performs real-time effective head-batch judgment on the received data, adjusts the decoding position based on the result of the effective head-batch judgment so as to send target data in the received data to the protocol layer of the second chip, can support retransmission at any position, avoids the waste of effective bandwidth, and further improves the link utilization rate and retransmission operation efficiency.
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For a clearer description of the present application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a timing diagram of a conventional retransmission operation signal;
fig. 2 is a flow chart of a uci-based data retransmission method provided in the present application;
fig. 3 is a schematic diagram of a principle of a data transmitting module provided in the present application to transmit data;
fig. 4 is a schematic diagram of a second principle of transmitting data by the data transmitting module provided in the present application;
fig. 5 is a schematic diagram of a principle of extracting data by the data receiving module provided in the present application;
FIG. 6 is a schematic diagram of a flow of adjustment of a batch decode poll register provided herein;
FIG. 7 is a schematic diagram of an adjustment flow of a current decoding position provided in the present application;
FIG. 8 is a schematic diagram of a data receiving module according to the present disclosure;
FIG. 9 is a schematic diagram of a second embodiment of a batch head detection performed by the data receiving module provided in the present application;
Fig. 10 is an effect schematic diagram of the uci-based data retransmission method provided in the present application;
fig. 11 is a schematic structural diagram of an electronic device provided in the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is apparent that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
Fig. 2 is a schematic flow chart of a method for retransmitting data based on uci, where the method is applied to a chip pair performing data interaction based on uci, an adaptation layer of a first chip (referred to as die 0) in the chip pair includes a data transmitting module (i.e., TX), and an adaptation layer of a second chip (referred to as die 1) in the chip pair includes a data receiving module (i.e., RX), as shown in fig. 2, the method includes:
step 101, in the process of sending retransmission data corresponding to a current retransmission request or data from a protocol layer to a data receiving module, if the retransmission request is received, the data sending module stops sending the rest data in the current batch of data and sends retransmission data corresponding to the latest retransmission request to the data receiving module;
And 102, the data receiving module performs real-time effective head judgment on the received data, and adjusts the decoding position based on the result of the effective head judgment so as to send target data in the received data to a protocol layer of the second chip.
Specifically, it can be understood that the adaptation layer of the first chip may further include a data receiving module, and correspondingly, the adaptation layer of the second chip may further include a data sending module, so that data interaction can be achieved based on the data receiving module and the data sending module. In the embodiment of the application, the data retransmission scheme is introduced by taking the first chip as the data transmitting end and the second chip as the data receiving end as an example.
Based on the foregoing and fig. 1, the current industry adopts a boundary alignment method to retransmit data, that is, it is known that D0-D16 has been correctly resolved, and still transmits D0-D16, and then initiates retransmission operation corresponding to D17-D33. However, in the case that D0-D16 has been correctly resolved by RX, continuing to retransmit D0-D16 has no meaning (RX discards it) and may cause waste of effective bandwidth, thereby causing unnecessary overhead, reducing link utilization and retransmission operation efficiency, and for this problem, the embodiment of the present application proposes a method for immediately initiating data retransmission based on uci e based on the characteristic that uci e protocol supports retransmission (i.e. retransmission) to be initiated immediately and waits for reinitiation after boundary alignment: taking the example of fig. 1, i.e., when a late NAK is received when D0 is sent (informing D0-D16 has been properly resolved by the RX, that D17-D33 is in error and needs to be retransmitted), the ongoing nonsensical retry operation is canceled and a new retry operation is performed.
Because retransmission is performed after boundary alignment, RX only needs to detect the first data in a batch (namely, the first data in a batch of data is used for finishing the data reorganization processing of a receiving side), and the first data is only required to be scanned according to a certain interval, so that the operation is simple, but the transmission efficiency is greatly reduced by the implementation scheme. On the contrary, retransmission is initiated at any position, the RX is required to be capable of detecting the head of the batch possibly occurring at any position in real time, processing the back-to-back condition of two continuous batches, filtering the condition of invalid head of the data stream, and timely processing the valid batch sent back-to-back immediately after discarding the previous invalid batch (including the whole batch and the residual batch) in time. In addition, the area and the speed of implementation are greatly different due to the difference of the level of designers (speed and area are two important indexes of chip design, and the faster the better the speed, the smaller the area the better).
Based on the above problems, the embodiment of the application provides a data retransmission method based on UCIE, which can support retransmission initiated at any position, comprehensively considers the problems of speed and area, and ensures the final implementation effect on a chip. Specifically, to achieve the highest efficiency of retry operations, an immediate execution mechanism is employed for the TX that receives the retry request and supports immediate discarding of the invalid retry in progress, i.e., the retry operations need not be aligned by batch length. Based on the mechanism, the data sending module stops sending the residual data in the current batch of data and sends the retransmission data corresponding to the latest retransmission request to the data receiving module if the retransmission request is received in the process of sending the retransmission data corresponding to the current retransmission request or the data from the protocol layer to the data receiving module. It can be appreciated that the data transmission module processes the retransmission request includes the following two scenarios: the first is that the data sending module receives a retransmission request in the process of sending data from a protocol layer to the data receiving module, the second is that the data sending module receives a new retransmission request in the process of sending retransmission data to the data receiving module, the scene supports cyclic retry (for example, the first retry needs to send batch 0-3 data, when sending batch 2 data, the response is received to inform batch 0 of successful batch 1 failure, the second retry is immediately initiated and batch 1-3 data is sent, when sending batch 3 data and not sending batch 1 of successful batch 2 failure is received to inform batch 1 of successful batch 2 failure, the third retry is immediately initiated and batch 2-3 data is sent). Therefore, in order to support the foregoing mechanism of immediately executing the received retry request and supporting immediately discarding the invalid retry in progress, the data sending module in the embodiment of the present application stops sending the remaining data in the current batch of data and sends the retransmission data corresponding to the latest retransmission request to the data receiving module if the retransmission request is received in the process of sending the retransmission data corresponding to the current retransmission request or the data from the protocol layer to the data receiving module.
Accordingly, to support the above mechanism, RX needs to detect valid lot and filter invalid lot in the running water, and at the same time, complete the analysis of the whole lot. RX needs to support that the lot first appears in any position and that the lot first is back to back, and can discard the residual lot in time and process the subsequent new lot at the same time. Based on this, the data receiving module in the embodiment of the present application may perform effective head-batch determination on the received data in real time, and adjust the decoding position based on the result of the effective head-batch determination to send the target data in the received data to the protocol layer of the second chip.
More specifically, the performing real-time effective head-batch judgment on the received data, and adjusting the decoding position based on the result of the effective head-batch judgment to send the target data in the received data to the protocol layer of the second chip specifically includes:
sequentially carrying out effective batch head judgment on the received data packets, and adjusting the value of a batch decoding polling register based on the result of the effective batch head judgment;
and determining a current decoding position based on the result of the effective head-of-batch judgment and the value of the batch decoding polling register, decoding target data in the received data based on the current decoding position, and transmitting the decoded target data to a protocol layer of the second chip.
Fig. 3 is a schematic diagram of the principle of transmitting data by the data transmitting module provided in the present application, as shown in fig. 3, TX is mainly used to implement the reorganization of the data packet (i.e. flit) from the protocol layer and transmit the reorganized data packet to the physical layer. As shown in fig. 3, for the 64B Flit received from the protocol layer, a 2B header (Flit Hdr in the figure) is added to the header, a 2B standard CRC is added to the tail, and the 64B standard CRC is aligned and sent out. Based on the above, to accurately judge the effective batch head, first, a potential batch head judgment needs to be performed, and the application obtains a potential batch head judgment condition set through research, where the conditions in the potential batch head judgment condition set include: the protocol type is correct, the valid data is sent, and the serial number is the head number. More specifically, all conditions in the set of potential head-of-lot judgment conditions include:
1. data [63] [7:6] is 01 (which is only an example, and can be set to other values because of different protocol types in practical application) to judge whether the protocol type is correct (corresponding to the protocol type is correct);
2. data [63] [4] is 0, and it is judged that valid data (corresponding to the above-described "valid data transmitted") is being transmitted;
3. data [62] [7:6] is 00, and it is judged that valid data (corresponding to the above-mentioned "valid data transmitted") is being transmitted;
4. data [62] [5:4] is 00, and normal data flit (corresponding to the above-mentioned "valid data transmitted") is judged to be being transmitted;
5. data [62] [3:0] is 0000, and judges that a batch head flit with a batch length of 16 is being sent (when the batch length is 16, the number of the batch head flit is 16 multiplied by n, and n is 0-15);
data [62] [2:0] is 000, and judging whether a batch head flit with a batch length of 8 is being transmitted (when the batch length is 8, the number of the batch head flit is 8 multiplied by n, and n is 0-31);
data [62] [1:0] is 00, and whether a batch head flit with a batch length of 4 is being transmitted or not is judged (when the batch length is 4, the number of the batch head flit is 4 multiplied by n, and n is 0-63) (corresponding to the sequence number is the batch head number);
and judging whether the five conditions are met simultaneously in parallel, if so, judging that the received data packet is a potential head. Fig. 4 is a second schematic diagram of the principle of transmitting data by the data transmitting module provided in the present application, as shown in fig. 4, the specific principle of determining the potential batch head is as follows:
at the RX point, when the pipeline detects the first flit, its data [63:62] corresponds to exactly the header, so there are two cases:
the first is to meet the five conditions, and then judge that the potential batch head is detected; the second is that the above five conditions are not met at the same time, and the reason for this situation may be that data distortion occurs on the link during data transmission, and the actual header sent by TX is broken, and this flit needs to be discarded.
When the second flit is detected by the pipeline, the data [63:62] corresponds to data (the data can be changed randomly, and the five conditions are easy to meet), so that two situations exist at the moment:
the first is to meet the five conditions, and then judge that the potential batch head is detected; the second is that the above five conditions are not met at the same time, i.e. no potential lot head is detected.
In summary, the detection of whether the above five conditions are satisfied is a necessary and insufficient condition for judging that a valid head of a batch is detected. In order to determine that the current data packet is a valid header, the following conditions are also required to be satisfied:
1. the CRC of the current packet is correct (i.e., the e portion of shift_flit when shift_cnt is 1 in fig. 4);
2. the header of the next batch head flit immediately follows detects correctly (a batch of data is discarded once there is an error, so it is known that the current data of the current batch has lost transmission meaning when the next batch of data of the current batch is in error); the header detection correctly includes no sequence number (i.e., sequence number) hop number (hop number indicates data loss).
Based on this, the embodiment of the application obtains the potential first batch judgment condition set through research, and the conditions in the potential first batch judgment condition set include: the protocol type is correct, the effective data is sent, the serial number is the first serial number of the next batch, and the comparison of the jump number and the check code is successful. More specifically, all conditions in the set of potential secondary batch first judgment conditions include:
1. data [59] [7:6] is 01 (which is only an example, and can be set to other values because of different protocol types in practical application) to judge whether the protocol type is correct (corresponding to the protocol type is correct);
2. data [59] [4] is 0, and it is judged that valid data (corresponding to the above-described "valid data transmitted") is being transmitted;
3. data [58] [7:6] is 00, and it is judged that valid data (corresponding to the above-mentioned "valid data transmitted") is being transmitted;
4. data [58] [5:4] is 00, and normal data flit (corresponding to the "valid data transmitted") is judged to be being transmitted;
5. data [58] [3:0] is 0001, and judges that the next batch head flit with the batch length of 16 is transmitted (when the batch length is 16, the number of the next batch head flit is 16 multiplied by n+1, and n is 0-15);
data [62] [2:0] is 001, and judging whether the next batch head flit with the batch length of 8 is being transmitted (when the batch length is 8, the number of the next batch head flit is 8 multiplied by n+1, and n is 0-31);
data [62] [1:0] is 01, and whether the next batch head flit with the batch length of 4 is being transmitted or not is judged (when the batch length is 4, the number of the next batch head flit is 4 multiplied by n+1, and n is 0-63) (corresponding to the serial number of the next batch head number);
6. the sequence number ({ data [59] [3:0], data [58] [3:0] }) currently extracted from the fixed position of the data (the position corresponding to the next lot head) is equal to the sum of the value of the previous sequence number and 1 (the sequence number representing the lot head and the non-occurrence number of the next lot head) (corresponding to the "non-occurrence number");
7. The CRC of the head currently extracted from the fixed position of the data (e part of shift_flit when shift_cnt is 1 in FIG. 4) ({ data [61] [7:0], data [60] [7:0] }) is equal to the CRC of the 64B flit corresponding to the head calculated based on the head data (indicating that the 64B data corresponding to the head is not distorted) (corresponding to the "check code comparison success") as described above.
And judging whether the seven conditions are met simultaneously in parallel, if so, judging that the received data packet is a potential secondary batch head.
In summary, the charging conditions for judging the current data packet as the valid header are as follows: under the condition that the current data packet simultaneously meets all conditions in the potential batch first judging condition set, the next data packet simultaneously meets all conditions in the potential batch first judging condition set.
Based on the detection principle, the data receiving module can accurately and effectively judge the head of the received data in real time. On this basis, the data receiving module also needs to adjust the decoding position based on the result of the valid head-of-batch judgment to send the target data in the received data to the protocol layer of the second chip. Specifically, fig. 5 is a schematic diagram of a data receiving module provided in the present application to extract data, as shown in fig. 5, where flit represents data sent by a protocol layer of die0 to an adapter layer thereof, and shift_buf represents a 62B cache of an adapter of die0 (used for caching data of the protocol layer to complete a reorganization operation of adding 2B headers and 2B CRCs to the data); shift_flit represents data transmitted by the adapter of die0 to its PHY layer; shift_cnt represents that 17 blocks are needed for a batch of data sent by the adapter of die0 to its PHY layer (i.e., physical layer), and together with shift_flit reflects mapping of different location reorganization; the extract_flit represents effective data extracted by the adapter of die1 when link delay from PHY layer of die0 to PHY layer of die1 and PHY layer of die1 to adapter layer of die1 is ignored, and together with shift_flit and shift_cnt, reflect mapping of decoding at different positions. As can be seen from fig. 5, the effective period of RX extraction data is a period in which shift_cnt is 1 to 16.
Based on the principle that the data receiving module extracts data, the embodiment of the application provides a complete data analysis scheme, specifically, fig. 6 is a schematic diagram of an adjustment flow of the batch decoding polling register provided by the application, and fig. 7 is a schematic diagram of an adjustment flow of a current decoding position provided by the application, where the embodiment of the application determines the current decoding position based on a result of the effective batch first judgment and a value of the batch decoding polling register, decodes target data in the received data based on the current decoding position, and sends the decoded target data to a protocol layer of the second chip. As shown in fig. 6-7, the adjusting the value of the batch decoding polling register based on the result of the valid batch head determination specifically includes:
step S01, judging whether the last data packet is a valid head, if so, executing step S02, and if not, executing step S03;
step S02, setting the value of a batch decoding polling register (hereinafter called polling_shift_cnt) to 2;
step S03, judging whether the current data packet is a potential head, if so, executing step S04, and if not, executing step S05;
step S04, setting the value of the batch decoding polling register to be 1;
step S05, judging whether the polling end zone bit, the check code error zone bit and the jump number zone bit are all 0, if so, executing step S06, otherwise, executing step S07;
Step S06, setting the value of the batch decoding polling register as the sum of the current decoding position (actual_shift_cnt) and 1;
in step S07, the value of the batch decode poll register is set to 0.
The determining the current decoding position based on the result of the effective head judgment and the value of the batch decoding polling register specifically comprises the following steps:
step S11, judging whether the last data packet is a valid head, if so, executing step S12, otherwise, jumping to execute step S13;
step S12, setting the current decoding position to be 1, and decoding data from the beginning to be sent to a protocol layer of the second chip;
step S13, judging whether the previous data packet is an invalid head, if so, executing step S14, otherwise, jumping to execute step S15;
step S14, taking the sum of the previous decoding position (called pre_actual_shift_cnt) and 1 as the current decoding position;
step S15, the value of the batch decoding polling register is used as the current decoding position.
Wherein, the judging whether the last data packet is a valid head, specifically includes:
and under the condition that the previous data packet simultaneously meets all conditions in the potential batch first judging condition set, judging whether the current data packet simultaneously meets all conditions in the potential batch first judging condition set, and if so, judging that the previous data packet is a valid batch first. Specifically, when the data packet simultaneously satisfies all conditions in the set of conditions for judging the potential batch head, the RX pulls a potential batch head indication bit (hereinafter referred to as batch_header_flag) high to indicate that the potential batch head is detected. The RX registers the batch_header_flag signal in a register pre_is_head_idex when it detects that the PHY is sending data to the Adapter, indicating that the previous data from the PHY was a potential head. Therefore, whether the previous data meets the judging condition of the potential batch head or not can be known when the next batch head is detected. Under the condition that the previous data packet simultaneously meets all conditions in the potential batch first judging condition set, further judging whether the current data packet simultaneously meets all conditions in the potential batch first judging condition set, and if so, pulling an indication signal second_data_valid high to indicate that the current data packet is the potential batch first; conversely, second_data_valid is not pulled high. Based on the foregoing, it can be seen that when the pre_is_head_idex is detected to be high, if the second_data_valid is pulled high, the information contained in the first batch and the first batch is correct so far (i.e. the last data packet is a valid first batch), the currently extracted data can be sent to the protocol layer, and meanwhile, the indication signal valid_head_idex is pulled high; if second_data_valid is not pulled high, the information contained in the first and second batches is erroneous so far (i.e. the last data packet is an invalid first batch), and the currently extracted data cannot be sent to the protocol layer, and meanwhile, the indication signal false_header_idex is pulled high. Based on this, the determining whether the previous data packet is an invalid header specifically includes:
And under the condition that the previous data packet simultaneously meets all conditions in the potential batch first judging condition set, judging whether the current data packet simultaneously meets all conditions in the potential batch first judging condition set, and if not, judging that the previous data packet is an invalid batch first.
In summary, in the uci-based data retransmission method provided in the embodiments of the present application, the adjustment mechanism of the batch decoding poll register is as follows:
1. immediately setting the register poling_shift_cnt to 2 upon detecting that valid_header_idex is pulled high means that the current decoding position is determined to be 1 and the next decoding position is determined to be 2. Thus, the RX will be ready to decode the second after decoding the first data.
2. Conversely, detecting that the batch_header_flag is pulled high (potential head is detected) immediately sets the register polling_shift_cnt to 1 indicating that the potential head is currently detected and applies for the next decode location to be 1 to further confirm whether it is a valid head. The specific cases are as follows:
A. the next position detects that valid_header_idex is pulled high (valid next batch head), and the actual_shift_cnt is set to 1 preferentially according to the fact that valid_header_idex is pulled high, namely the decoding process from the head is not influenced;
B. The next position does not detect valid_header_idex to be pulled high and detects false_header_idex to be pulled high, and then the actual_shift_cnt is set to be pre_actual_shift_cnt+1 preferentially according to the fact that false_header_idex is detected to be pulled high, that is, the current decoding process is not affected;
C. the next position does not detect valid_header_idex pulling high and false_header_idex pulling high, and at this time, actual_shift_cnt is set to poling_shift_cnt according to the descending principle; at this time, the first batch needs to be judged, so that the decoding position is only 1; i.e. a register polling _ shift _ cnt of 1 will now support a normal detection of whether the previous potential head is a valid head.
3. Conversely, in the event that valid_header_idex is not detected to be high and batch_header_flag is not detected to be high, the following event is detected:
A. detecting that shift_cnt_end (i.e., the end of poll flag bit) is pulled high (indicating that decoding of 1 batch of data has been completed), immediately setting the register polling_shift_cnt to 0 indicates that the current decoding position is determined to be 16 and the next decoding position is determined to be 0. Thus, the RX will be ready to decode the next batch of data after decoding the 16 th data.
It is noted that the value of the polling end flag is determined based on the current decoding position, and when the value of the current decoding position is equal to the batch length, the polling end flag is 1, otherwise, is 0. Based on this, the actual_shift_cnt signal is 16 when the batch length is 16 and shift_cnt_end is pulled high; the actual_shift_cnt signal is 8 with the batch length being 8 and the shift_cnt end being pulled high; the actual_shift_cnt signal is 4 when the batch length is 4 and the shift_cnt_end is pulled high.
B. Detecting flit_crc_error (i.e. check code error flag bit) to be high (indicating that crc comparison failure is detected during decoding), immediately setting a register polling_shift_cnt to 0 to indicate that data is found to be distorted in the current batch decoding process, stopping decoding and informing a protocol layer to discard the current batch; while the next decoding position is set to 0. Thus, the RX discards the current batch and then prepares to decode the next batch of data. It is noted that the value of the error flag bit of the check code is determined based on the comparison result of the reference check code in the current data packet and the actual check code calculated based on the previous data, if the reference check code is different from the actual check code, the error flag bit of the check code is 1, otherwise, is 0.
C. Detecting that the seq_num_jump (i.e. the jump number flag bit) is pulled up (indicating that the sequence number is detected to be jumped during decoding), immediately setting a register polling_shift_cnt to 0 to indicate that the decoding is stopped when data loss is found in the decoding process of the current batch, and informing a protocol layer to discard the current batch; while the next decoding position is set to 0. Thus, the RX discards the current batch and then prepares to decode the next batch of data. It is noted that the value of the skip number flag bit is determined based on the difference between the sequence number of the current data packet and the sequence number of the previous data packet, if the difference is not 1, the skip number flag bit is 1, otherwise, is 0.
4. Conversely, none of the above cases were detected: detecting that adpt2proc_valid is pulled high (indicating that the decoding of the current batch is in progress), immediately setting register poll_shift_cnt to actual_shift_cnt+1 indicates that the current decoding position is determined to be correct and the next decoding position is determined to be the next position of the previously used position. Thus, the RX will be ready to decode the next data after decoding the current data.
On the basis of the above, the mechanism of RX extract data is as follows:
1. immediately setting actual_shift_cnt to 1 upon detection of valid_header_idex pull-up represents determining that the current decoding position is 1 and decoding data from the beginning for transmission to the protocol layer on the receiving side. Thus, even if the RX receives two batches back-to-back, it can pull valid_header_idex only one clock high (the first 1 batch first will not pull valid_header_idex high because the next data does not meet the secondary batch first determination condition), thereby realizing immediately discarding the residual batch and simultaneously starting decoding the back-to-back later batch.
2. Conversely, detection of false_header_idex high (valid_header_idex and false_header_idex are mutually exclusive) indicates that the previous potential header proved to be an invalid header without decoding from scratch; at this time, the actual_shift_cnt is immediately set to pre_actual_shift_cnt+1. Therefore, the invalid batch head can be accurately identified and the current decoding process can be continued.
Wherein the RX detects that the PHY is sending data to the Adapter, registers an actual_shift_cnt signal in a register pre_actual_shift_cnt indicating the decoding position of the previous data from the PHY.
3. Conversely, if no valid_header_idex pull-up is detected and no false_header_idex pull-up is detected, the value of the batch decode poll register poll_shift_cnt is immediately assigned to actual_shift_cnt.
The event 1 and the event 2 can realize dynamic synchronization, find the starting point of data decoding (support the occurrence of the batch head at any position and support the batch head back to back), and effectively prevent erroneous judgment. Event 3 is used to complete subsequent decoding of a batch of data.
As for the mechanism of jump number and crc comparison failure during RX decision decoding, any feasible manner may be adopted, which is not specifically limited in the embodiments of the present application.
The principles and effects of the uci-based data retransmission method provided in the embodiments of the present application will be discussed below in connection with specific examples. It will be appreciated that RX will face 4 combinations of valid and invalid lot sizes when detecting valid and invalid lot sizes, namely valid and valid followed by invalid, invalid followed by valid and invalid. FIG. 8 is a schematic diagram of a data receiving module according to the present application for performing a lot-first detection, which corresponds to a case where an invalid lot-first is followed by an invalid lot-first and a valid lot-first is followed by an invalid lot-first; fig. 9 is a second schematic diagram of a data receiving module according to the second embodiment of the present application, where the second schematic diagram corresponds to a valid batch first followed by a valid batch first and a valid batch first followed by an invalid batch first.
As shown in fig. 8, the protocol layer initiates a retry operation immediately after transmitting 2 data; the header portion of the first shift_flit data is distorted across the link and the high 2B and header of the 2 nd shift_flit are much like and meet all the conditions for determining a potential head of the batch. The 19 blocks in FIG. 8 are designated as T0-T18 from front to back.
The RX side continuously detects 3 potential batch heads at T0-T2 and respectively sets the register polling_shift_cnt to 1;
the RX side respectively judges that the first 2 potential batch heads are invalid batch heads in the period of T1 and T2 (the 1 st potential batch head is judged to have failed in the crc comparison of the batch heads in the period of T1, the 2 nd potential batch head is judged to have failed in the crc comparison of the batch heads in the period of T2 and the occurrence of jump numbers is possibly judged to occur);
immediately setting actual_shift_cnt to 1 when the 3 rd potential lot head is determined to be a valid lot head in the period T3;
when the 3 rd potential batch head is judged to be a valid batch head in the period T3, the following conditions are judged:
A. part of 1 batch of data is sent to the protocol layer, and the protocol layer is immediately informed to discard the data of the current batch if the current batch operation is judged to not end normally (the batch ends normally when the batch length data of the protocol layer are sent to);
B. no part of the data of 1 batch is sent to the protocol layer, and no discard action is initiated.
Determining that data is normally sent to the protocol layer in a period of T3-T18 (no polling end/crc error/jump number is detected), so that the result of actual_shift_cnt+1 is assigned to a register polling_shift_cnt;
the valid head and the invalid head are not detected in the period T4, so that the result of the poling_shift_cnt is immediately used as the value of the actual_shift_cnt to continue the decoding work;
the same as T4 in the period of T5-T19; the period T19 will complete the decoding of a batch of data.
It follows that the above mechanism can detect the case of an invalid head followed by a valid head (including the case of an invalid head followed by an invalid head).
As shown in fig. 9, the protocol layer initiates a retry operation immediately after transmitting 1 data; the header portion of the first shift_flit data is normally transmitted on the link, and the high 2B and header of the 3 rd shift_flit are much like and satisfy all conditions that determine the potential head of the batch. The 18 blocks in FIG. 9 are designated from front to back as T0-T17.
The RX side continuously detects 3 potential batch heads at T0-T2 and respectively sets the register polling_shift_cnt to 1;
if the 1 st potential batch head is determined to be an invalid batch head at the time T1 (the 1 st potential batch head is determined to be failed in the crc comparison of the batch head at the time T1 and the occurrence of jump number is possibly determined), immediately assigning the result of the pre-actual-shift_cnt+1 to the actual-shift_cnt (the value of the actual-shift_cnt at the time T1 can be ignored without affecting the subsequent work);
Immediately setting actual_shift_cnt to 1 when the 2 nd potential batch head is determined to be a valid batch head at the time T2;
and when the 2 nd potential batch is judged to be the effective batch at the time T2, partial data of 1 batch of data is not sent to the protocol layer (when the time T1 judges that the crc comparison fails, the data is not sent to the protocol layer), and no discarding action is required to be initiated.
For other cases: when the valid batch head is detected, if the current batch operation is judged not to end normally (when the batch length data of the protocol layer is sent, the batch ends normally), the protocol layer is immediately informed to discard the current batch of data. I.e., active lot head followed by active lot head (back-to-back) and active lot head followed by non-active lot head followed by active lot head (non-back-to-back) are supported.
When detecting that the PHY is transmitting data to the Adapter at time T2, assigning a value of actual_shift_cnt to a register pre_actual_shift_cnt (the value of pre_actual_shift_cnt is 1 at time T3);
determining that the 3 rd potential lot is an invalid lot (the 3 rd potential lot is determined that the crc comparison of the lot fails and a jump number may be determined to occur at the time T3), so that the result of the pre_actual_shift_cnt+1 is assigned to the actual_shift_cnt (the value of the actual_shift_cnt is 2 at the time T3);
Determining that data is normally sent to the protocol layer at the time T3-T16 (no polling end/crc error/jump number is detected), so that the result of actual_shift_cnt+1 is assigned to a register polling_shift_cnt (the value of polling_shift_cnt at the time T4 is 3);
the valid head and the invalid head are not detected at the time T4, so that the result of the poling_shift_cnt is immediately used as the value of the actual_shift_cnt to continue the decoding work;
at the time T5-T17 with T4; decoding of a batch of data will be completed at time T17.
It can be seen that the above mechanism can detect the situation of an active lot head followed by an active lot head and the situation of an active lot head followed by an inactive lot head.
In summary, the uci-based data retransmission method according to the embodiment of the present application can detect an effective header (determining that the current decoding position is 1) and decode data from the header to send to the protocol layer of the receiving side based on valid_header_idex and actual_shift_cnt, and support the occurrence of the header in any position and support the back-to-back of the header; filtering the false batch head based on false_header_idex and pre_actual_shift_cnt, namely, the false batch head can be identified as erroneous judgment and the current decoding process can be continued; meanwhile, the implementation supports subsequent decoding work of a batch of data based on the polling_shift_cnt and the actual_shift_cnt. The whole circuit can realize all the schemes of the embodiment by using two 5-bit registers of poling_shift_cnt [4:0] and pre_actual_shift_cnt [4:0], the circuit area is very small, the speed of data decoding is not affected, namely the latency from the FDI interface to the RDI interface is not affected by the circuit area.
Fig. 10 is an effect diagram of the uci-based data retransmission method provided in the present application, where signal_a and signal_c are retransmission requests, signal_b is a data signal sent by an existing retransmission operation, and signal_b_2 is a data signal sent by a retransmission operation in the present application. As shown in fig. 10, according to the uci-based data retransmission method of the embodiment of the present application, when a delayed NAK is received (informing that D0-D16 has been properly resolved by RX, and that D17-D33 is in error and needs to be retransmitted) when D0 is transmitted, the ongoing nonsensical retry operation is canceled and a new retry operation is performed. Thus, a single retry operation will save 16 transmission time units, significantly improving the effective bandwidth (34 time units were originally required to complete a single meaningful retransmission operation, now 18 time units were required, i.e. only 9/17 of the original time was required, i.e. a performance improvement of 47%.
The method provided by the embodiment of the application is applied to a chip pair for data interaction based on UCIE, wherein the adaptation layer of a first chip in the chip pair comprises a data sending module, and the adaptation layer of a second chip in the chip pair comprises a data receiving module, and the method comprises the following steps: the data sending module stops sending the residual data in the current batch of data and sends the retransmission data corresponding to the latest retransmission request to the data receiving module if the retransmission request is received in the process of sending the retransmission data corresponding to the current retransmission request or the data from the protocol layer to the data receiving module; the data receiving module performs real-time effective head-batch judgment on the received data, adjusts the decoding position based on the result of the effective head-batch judgment so as to send target data in the received data to the protocol layer of the second chip, can support retransmission at any position, avoids the waste of effective bandwidth, and further improves the link utilization rate and retransmission operation efficiency.
Fig. 11 illustrates a physical structure diagram of an electronic device, as shown in fig. 11, which may include: the processor 201, the communication interface 202, the memory 203 and the communication bus 204, wherein the processor 201, the communication interface 202 and the memory 203 complete communication with each other through the communication bus 204. Processor 201 may invoke logic instructions in memory 203 to perform the uci-based data retransmission method provided by the methods described above, including: the data sending module stops sending the residual data in the current batch of data and sends the retransmission data corresponding to the latest retransmission request to the data receiving module if the retransmission request is received in the process of sending the retransmission data corresponding to the current retransmission request or the data from the protocol layer to the data receiving module; the data receiving module performs real-time effective head batch judgment on the received data, and adjusts the decoding position based on the result of the effective head batch judgment so as to send target data in the received data to a protocol layer of the second chip.
Further, the logic instructions in the memory 203 may be implemented in the form of software functional units and may be stored in a computer readable storage medium when sold or used as a stand alone product. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk, an optical disk, or other various media capable of storing program codes.
Of course, the above logical instructions may also be implemented in the form of hardware functional units. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a hardware product, which may be used as a hardware functional module of a chip to perform all or part of the steps of the methods described in the various embodiments of the present application, so as to achieve the efficiency maximization of data retransmission.
In another aspect, the present application also provides a computer program product, where the computer program product includes a computer program, where the computer program can be stored on a non-transitory computer readable storage medium, where the computer program, when executed by a processor, can perform the uci-based data retransmission method provided by the methods above, and the method includes: the data sending module stops sending the residual data in the current batch of data and sends the retransmission data corresponding to the latest retransmission request to the data receiving module if the retransmission request is received in the process of sending the retransmission data corresponding to the current retransmission request or the data from the protocol layer to the data receiving module; the data receiving module performs real-time effective head batch judgment on the received data, and adjusts the decoding position based on the result of the effective head batch judgment so as to send target data in the received data to a protocol layer of the second chip.
In yet another aspect, the present application further provides a non-transitory computer readable storage medium having stored thereon a computer program, which when executed by a processor is implemented to perform the uci-based data retransmission method provided by the methods above, the method comprising: the data sending module stops sending the residual data in the current batch of data and sends the retransmission data corresponding to the latest retransmission request to the data receiving module if the retransmission request is received in the process of sending the retransmission data corresponding to the current retransmission request or the data from the protocol layer to the data receiving module; the data receiving module performs real-time effective head batch judgment on the received data, and adjusts the decoding position based on the result of the effective head batch judgment so as to send target data in the received data to a protocol layer of the second chip.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as a ROM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions.
Claims (9)
1. The data retransmission method based on UCIE is characterized in that the method is applied to a chip pair which performs data interaction based on UCIE, an adaptation layer of a first chip in the chip pair comprises a data sending module, and an adaptation layer of a second chip in the chip pair comprises a data receiving module, and the method comprises the following steps:
the data sending module stops sending the residual data in the current batch of data and sends the retransmission data corresponding to the latest retransmission request to the data receiving module if the retransmission request is received in the process of sending the retransmission data corresponding to the current retransmission request or the data from the protocol layer to the data receiving module;
the data receiving module performs real-time effective head batch judgment on the received data, and adjusts the decoding position based on the result of the effective head batch judgment so as to send target data in the received data to a protocol layer of the second chip;
the method comprises the steps of performing real-time effective head batch judgment on received data, adjusting a decoding position based on the result of the effective head batch judgment to send target data in the received data to a protocol layer of a second chip, and specifically comprises the following steps:
sequentially carrying out effective batch head judgment on the received data packets, and adjusting the value of a batch decoding polling register based on the result of the effective batch head judgment;
And determining a current decoding position based on the result of the effective head-of-batch judgment and the value of the batch decoding polling register, decoding target data in the received data based on the current decoding position, and transmitting the decoded target data to a protocol layer of the second chip.
2. The uci-based data retransmission method according to claim 1, wherein the adjusting the value of the batch decoding poll register based on the result of the valid batch head determination specifically comprises:
step S01, judging whether the last data packet is a valid head, if so, executing step S02, and if not, executing step S03;
step S02, setting the value of the batch decoding polling register to 2;
step S03, judging whether the current data packet is a potential head, if so, executing step S04, and if not, executing step S05;
step S04, setting the value of the batch decoding polling register to be 1;
step S05, judging whether the polling end zone bit, the check code error zone bit and the jump number zone bit are all 0, if so, executing step S06, otherwise, executing step S07;
step S06, setting the value of the batch decoding polling register as the sum of the current decoding position and 1;
in step S07, the value of the batch decode poll register is set to 0.
3. The uci-based data retransmission method according to claim 2, wherein determining the current decoding position based on the result of the valid head-of-batch judgment and the value of the batch decoding polling register specifically comprises:
Step S11, judging whether the last data packet is a valid head, if so, executing step S12, otherwise, jumping to execute step S13;
step S12, setting the current decoding position to be 1, and decoding data from the beginning to be sent to a protocol layer of the second chip;
step S13, judging whether the previous data packet is an invalid head, if so, executing step S14, otherwise, jumping to execute step S15;
step S14, taking the sum of the last decoding position and 1 as the current decoding position;
step S15, the value of the batch decoding polling register is used as the current decoding position.
4. The uci-based data retransmission method according to claim 3, wherein the determining whether the last packet is a valid header specifically comprises:
and under the condition that the previous data packet simultaneously meets all conditions in the potential batch first judging condition set, judging whether the current data packet simultaneously meets all conditions in the potential batch first judging condition set, and if so, judging that the previous data packet is a valid batch first.
5. The uci-based data retransmission method according to claim 4, wherein the determining whether the previous packet is an invalid header specifically includes:
and under the condition that the previous data packet simultaneously meets all conditions in the potential batch first judging condition set, judging whether the current data packet simultaneously meets all conditions in the potential batch first judging condition set, and if not, judging that the previous data packet is an invalid batch first.
6. The uci-based data retransmission method according to claim 5, wherein the conditions in the set of potential head-of-lot judgment conditions include: the protocol type is correct, the effective data is sent, and the serial number is the batch head number;
the conditions in the potential secondary batch first judgment condition set comprise: the protocol type is correct, the effective data is sent, the serial number is the first serial number of the next batch, and the comparison of the jump number and the check code is successful.
7. The uci-based data retransmission method according to claim 2, wherein the value of the poll end flag is determined based on a current decoding position, and the poll end flag is 1 when the value of the current decoding position is equal to a batch length, and is 0 otherwise.
8. The uci-based data retransmission method according to claim 2, wherein the value of the check code error flag bit is determined based on a comparison result of a reference check code in a current data packet and an actual check code calculated based on a previous data packet, and if the reference check code is different from the actual check code, the check code error flag bit is 1, otherwise is 0.
9. The uci-based data retransmission method according to claim 2, wherein the value of the skip flag is determined based on a difference between a sequence number of a current packet and a sequence number of a previous packet, and the skip flag is 1 if the difference is not 1, and is 0 otherwise.
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| CN103141050A (en) * | 2011-12-28 | 2013-06-05 | 华为技术有限公司 | Data packet retransmission method and node in quick path interconnect system |
| CN103188059A (en) * | 2011-12-28 | 2013-07-03 | 华为技术有限公司 | Method, device and system for data packet retransmission in quick path interconnect system |
| WO2020034909A1 (en) * | 2018-08-11 | 2020-02-20 | 华为技术有限公司 | Communication method and communication device |
| WO2023098623A1 (en) * | 2021-12-03 | 2023-06-08 | 北京字跳网络技术有限公司 | Information processing method and apparatus, and electronic device and storage medium |
| CN115038115A (en) * | 2022-06-21 | 2022-09-09 | 美的集团股份有限公司 | Data transmission method, device, electronic equipment, storage medium and product |
| CN116743317A (en) * | 2023-06-29 | 2023-09-12 | 上海奎芯集成电路设计有限公司 | Data transmission method based on universal chip interconnection standard |
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