CN117520215A

CN117520215A - Page missing processing method and related equipment

Info

Publication number: CN117520215A
Application number: CN202210912615.6A
Authority: CN
Inventors: 龚磊
Original assignee: Huawei Cloud Computing Technologies Co Ltd
Current assignee: Huawei Cloud Computing Technologies Co Ltd
Priority date: 2022-07-30
Filing date: 2022-07-30
Publication date: 2024-02-06

Abstract

The embodiment of the application discloses a page fault processing method and related equipment, which are used for applying to HPA as required, so that the resource utilization rate of a host memory is improved. In the application, the OS receives page fault information about a physical address GPA of a virtual machine reported by a pass-through device, the GPA is a physical address of a guest, and the guest is a virtual machine running on the OS. And then, the OS performs page-missing processing on the GPA to obtain a host physical address HPA corresponding to the GPA, wherein the HPA is a physical address in a memory of a physical host, and sends a mapping relation indication to the pass-through device, and the mapping relation indication comprises a mapping relation between the GPA and the HPA. Because the OS can apply for the HPA as required, the complete mapping relation between GPA and HPA is not required to be established in the starting stage of the gust, the starting speed of the client is improved, and the utilization rate of the memory resources of the host is improved.

Description

Page missing processing method and related equipment

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a method and related apparatus for processing a page fault.

Background

A Virtual Machine (VM) refers to a complete computer system running in a completely isolated environment with complete hardware system functionality through software emulation. Virtual machines are typically run on hosts, each of which may run multiple virtual machines, also known as guests.

In order to pursue the extreme performance, pass-through devices may be configured to virtual machines. Pass-through devices are physical hardware, also known as external devices (peripherals), commonly used for input/output, also known as input/output (I/O) devices, such as network cards, chips or disks. The virtual machine can directly perform I/O interaction with the direct equipment, a virtual machine monitor (virtual machine monitor, VMM) is not needed to intervene on the data surface, redundant virtualization overhead is hardly generated, optimal performance targets such as high bandwidth and low time delay can be achieved, the virtual machine can obtain I/O performance close to that of a bare machine, and the availability of resources is improved.

However, since the pass-through device must have a corresponding real physical memory when performing a direct memory access (direct memory access, DMA) operation, otherwise an error may cause a system exception. For this purpose, it is often required to bind the physical memory of the virtual machine with the real physical memory, making a fixed mapping in the relevant page tables. In this way, the real physical memory cannot be reused, and the utilization rate of the real physical memory can be reduced.

Disclosure of Invention

The embodiment of the application provides a page fault processing method and related equipment, which are used for applying to HPA as required, so that the resource utilization rate of a host memory is improved.

The first aspect of the present application provides a page fault handling method, which is used for a physical host, in which an operating system OS runs, and in the present application, the OS receives page fault information about a physical address GPA of a virtual machine reported by a pass-through device, where GPA is a physical address of a client guest, and guest is a virtual machine running on the OS. And then, the OS performs page-missing processing on the GPA to obtain a host physical address HPA corresponding to the GPA, wherein the HPA is a physical address in a memory of a physical host, and sends a mapping relation indication to the pass-through device, and the mapping relation indication comprises a mapping relation between the GPA and the HPA. Because the OS can apply for the HPA as required, the complete mapping relation between GPA and HPA is not required to be established in the starting stage of the gust, the starting speed of the client is improved, and the utilization rate of the memory resources of the host is improved.

In some possible implementations, before the OS performs the page fault processing on the GPA, the method further includes:

the OS queries the HPA corresponding to the GPA in a built-in address translation table; if the HPA corresponding to the GPA cannot be found, executing the step of performing page fault processing on the GPA by the OS; and if the HPA corresponding to the GPA is found, executing the step that the OS sends a mapping relation instruction to the pass-through equipment. By searching the mapping relation between GPA and HPA in the built-in address translation table, compared with the processing of page missing, the response speed is faster, and the user experience is improved.

In some possible implementations, after the OS performs the page fault processing on the GPA, the method further includes:

and the OS updates an address translation table based on the mapping relation between the GPA and the HPA, wherein the updated address translation table comprises the mapping relation between the GPA and the HPA. By storing the mapping relation between GPA and HPA in the built-in address translation table, all binding of GPA and HPA is completed without starting at the gust, the starting speed of the client is improved, and the utilization rate of the memory resources of the host is improved.

In some possible implementations, the OS performs page fault processing on the GPA to obtain an HPA corresponding to the GPA, including:

the OS applies for the HPA corresponding to the GPA from the memory of the physical host, thereby acquiring the HPA corresponding to the GPA and realizing page fault processing.

In some possible implementations, the address translation table is multiplexed with the address translation and protection table ATPT, thereby fully utilizing storage resources and implementing super-allocation.

the OS updates the ATPT based on the mapping relationship between the GPA and the HPA, and the updated ATPT comprises the mapping relationship between the GPA and the HPA. Instead, the mapping relationship between GPA and HPA in the ATPT is updated, and the corresponding HPA may be determined from the ATPT based on GPA later.

In some possible implementations, the OS is a linux system.

In some possible implementations, the pass-through device is a peripheral component interconnect express (PCI express) standard PCIe device.

The second aspect of the present application provides a method for processing a page fault, including:

the method comprises the steps that through equipment receives an I/O request sent by a client, wherein the I/O request indicates GPA, the GPA is a physical address of a client guest, and the guest is a virtual machine running on an OS; the direct device reports page fault information about the GPA to the OS, and the OS belongs to a physical host; and the direct equipment receives a mapping relation instruction sent by the OS, wherein the mapping relation instruction comprises the mapping relation between the GPA and the HPA, and the HPA is a physical address in a memory of a physical host. Because the OS can apply for the HPA as required, the complete mapping relation between GPA and HPA is not required to be established in the starting stage of the gust, the starting speed of the client is improved, and the utilization rate of the memory resources of the host is improved.

In some possible implementations, before the pass-through device sends the page fault information about the GPA to the OS, the method further includes:

the direct-connection device queries the HPA corresponding to the GPA in a built-in cache; and if the HPA corresponding to the GPA cannot be found, executing the steps that the pass-through equipment sends page missing information about the GPA to the OS, and the pass-through equipment receives a mapping relation instruction sent by the OS. The direct device searches the mapping relation between GPA and HPA in the built-in cache, compared with the direct device which performs page-missing processing, the response speed is faster, and the user experience is improved.

In some possible implementations, after the pass-through device receives the mapping relationship indication sent by the OS, the method further includes:

and the direct connection equipment writes the mapping relation between the GPA and the HPA into the cache. The direct device searches the mapping relation between GPA and HPA in the built-in cache, compared with the direct device which performs page-missing processing, the response speed is faster, and the user experience is improved.

the pass-through device performs a Direct Memory Access (DMA) operation based on the HPA to read data from or write data in the HPA. Thereby implementing DMA operations based on HPAs.

In some possible implementations, the OS is a linux system.

A third aspect of the present application provides a communication system comprising: the device comprises a physical host and a through device, wherein an OS is operated in the physical host, and the physical host is used for executing any method executed by the page fault processing in the first aspect; the pass-through device is configured to perform any one of the methods of executing the page fault processing in the foregoing second aspect.

A fourth aspect of the present application provides a physical host running an OS, the physical host being configured to perform the method of any one of the preceding first aspects.

A fifth aspect of the present application provides a pass-through device for performing the method of any one of the preceding second aspects.

A sixth aspect of the present application provides a computer readable storage medium having instructions stored therein which, when run on a computer, cause the computer to perform the method of any of the first or second or third aspects above.

A seventh aspect of the present application provides a computer program product comprising computer-executable instructions stored in a computer-readable storage medium; the at least one processor of the apparatus may read the computer-executable instructions from a computer-readable storage medium, the at least one processor executing the computer-executable instructions causing the apparatus to implement the method provided by any one of the possible implementations of the first or second aspects described above.

An eighth aspect of the present application provides a communication device that may include at least one processor, a memory, and a communication interface. At least one processor is coupled with the memory and the communication interface. The memory is for storing instructions, the at least one processor is for executing the instructions, and the communication interface is for communicating with other communication devices under control of the at least one processor. The instructions, when executed by at least one processor, cause the at least one processor to perform the method of any possible implementation of the first or second aspect.

A ninth aspect of the present application provides a chip system comprising a processor for supporting the functions involved in implementing any one of the possible implementations of the first or second aspect.

In one possible design, the chip system may further include memory to hold the necessary program instructions and data. The chip system can be composed of chips, and can also comprise chips and other discrete devices.

The technical effects of the fourth to ninth aspects or any one of the possible implementation manners may be referred to technical effects of the different possible implementation manners of the first aspect or the second aspect, which are not described herein.

Drawings

Fig. 1 is a schematic hardware structure of a computer according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a virtualized computer architecture according to an embodiment of the present application;

FIG. 3-1 is a schematic diagram of a system architecture of a method for page fault handling according to an embodiment of the present disclosure;

fig. 3-2 is a schematic structural diagram of a synchronization device according to an embodiment of the present application;

fig. 3-3 are schematic structural diagrams of DTA provided in an embodiment of the present application;

fig. 4-1 is a schematic flow chart of an embodiment of a method for processing a page fault according to an embodiment of the present application;

Fig. 4-2 is another schematic flow chart of an embodiment of a page fault handling method according to an embodiment of the present application;

FIG. 5-1 is a schematic flow chart of another embodiment of a method for processing a page fault according to the embodiments of the present application;

FIG. 5-2 is a schematic flow chart of another embodiment of a method for processing a page fault according to the embodiments of the present application;

FIG. 6 is a schematic diagram of a physical host according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a through device according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a communication device according to an embodiment of the present application.

Detailed Description

Embodiments of the present application are described below with reference to the accompanying drawings.

The terms first, second and the like in the description and in the claims of the present application and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and are merely illustrative of the manner in which the embodiments of the application described herein have been described for objects of the same nature. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Virtual computers are a generic term for the running environment virtualized by software in all types of virtualized devices, and the concept includes virtual machines and containers. Virtualization is used as a core technology of cloud scene, and hardware resources are virtualized and shared for a plurality of users to use, so that the users can conveniently and flexibly use physical resources on the premise of safety isolation, and the utilization rate of the physical resources can be greatly improved.

For example, fig. 1 is a schematic diagram of a hardware structure of a computer according to an embodiment of the present application. As shown in fig. 1, a hardware structure 100 of a computer may include a processor 110, a memory 120, and components such as a network interface 130 (also referred to as a network card or a network adapter, etc.).

The processor 110 may be a single-core processor or a multi-core processor. When the processor 110 is a multi-core processor, the methods provided herein may run on one core or may be distributed to run on different cores. The number of the processors 110 may be one or plural, and the types of the plural processors may be the same or different. The type of processor is a central processing unit (central processing unit, CPU), a graphics processor (graphics processing unit, GPU), a microprocessor, a coprocessor, or the like. The network interface 130 may be used to connect other network devices, including wireless connections and wired connections.

Memory 120 includes volatile and nonvolatile memory, typically nonvolatile memory has stored thereon virtualized software program 122 and other program modules 123. Virtualization software program 122, after being read and executed by processor 110, virtualizes hardware structure 100, including creating a host layer, multiple virtual computers, and the like. The software programs of the page fault handling methods provided herein implement the various page fault handling methods provided by the various embodiments of the present application after being read and executed by the processor 110. The software programs provided herein may be incorporated into the virtualized software program 122.

The above components are connected by a bus 140. The bus 140 may be one or more. Bus 140 includes advanced microcontroller bus (advance microcontroller bus architecture, AMBA) industry standard architecture (industry standard architecture, ISA) bus, micro channel architecture (micro channel architecture, MCA) bus, extended-ISA (extended-ISA) bus, video electronics standards association (video electronics standard sassociation, VESA) local bus, and peripheral device interconnect (peripheral component interconnect, PCI) bus, among others.

Fig. 2 is a schematic diagram of a virtualized computer 200 according to an embodiment of the disclosure. The virtualized computer 200 may include a hardware layer, a host layer, and a virtualization layer that contains two virtual machines. The hardware layers in fig. 2 are illustrated as including two processors 210, a memory 220, a network interface 230, and so on. In other embodiments, the number of processors 210 and the number of virtual machines may be greater or fewer.

In other embodiments, a container (container) may be contained within the virtual machine, the container corresponding to the application. In other embodiments, the virtualization layer may be implemented by lightweight virtualization technology, such as libOS, which is a type of runtime that provides operating system-like functionality and runs linked with an application such that all resources necessary for the application to run are managed by the application itself rather than the operating system. Such as unikernel, OSv, dune, the libOS may be considered a lightweight virtual computer. An application is typically contained within a libOS, the entire libOS being one or more libraries, and the application being linked as a single address space mirror. In the embodiments of the present application, a virtual machine implemented by using a conventional virtualization technology is taken as an example, and other types of virtualization architectures may refer to the implementation of the virtual machine.

It should be noted that, in this embodiment, a computer is taken as an example for illustration, but the method provided in the application is not limited to this device, and all types of virtualization devices can be applied.

Processor 210 may include one or more physical cores (sometimes referred to herein simply as cores). The "physical core" represents the smallest processing unit in this application. As shown in fig. 2, each processor in this embodiment has two physical cores: core 0 and core 1, and a plurality of registers. In other embodiments, the number of cores that a processor contains may be greater or lesser, and the number of cores that each processor contains may be different.

Within the host machine are deployed a host machine operating system 270 and a virtual machine monitor 280 (virtual machine monitor, VMM), the VMM 280 being equivalent to a hypervisor or other type of virtual monitoring device in other virtualization architectures. The VMM 280 may be deployed within the host operating system 270 or separately from the host operating system 270. VMM 280 is responsible for managing the one or more virtual machines running thereon.

A Virtual Machine (VM) may include a virtual hardware layer, a guest operating system 290, and various applications. The virtual hardware layer contains virtual hardware such as virtual memory (not shown), virtual processor 210-v, and the like. As shown in FIG. 2, this embodiment includes two virtual machines, each including three virtual processors 210-v. The virtual processor 210-v is implemented in combination with hardware and software, and its operation is actually implemented by a physical core reading and running a software program, e.g., a physical core reading the software program and running the software program in a specific mode of hardware-assisted virtualization of the physical core (e.g., non-Root mode of x 86) to implement a virtual process 210-v.

In the following, some terms referred to in the present application will be briefly described.

1. And (5) a virtual machine.

Virtual machines refer to one or more virtual computers that are emulated by software on a physical computer. These virtual machines operate in a completely isolated environment, working as if they were a real computer. A guest operating system (guest operating system, guest OS) may be installed on the virtual machine, with one or more applications running on the guest operating system. The virtual machine may also access network resources. For applications running in virtual machines, it is as if they were working in a real computer. In the present embodiment, the virtual machine is also called a guest (guest).

2. A host (host) layer.

The host machine layer is used as a management layer for completing the management and distribution of hardware resources; presenting a virtual hardware platform for the virtual machine; scheduling and isolation of the virtual machine are realized. In some implementations, the host layer includes a host operating system and a virtual monitoring device, such as a VMM or hypervisor, where the virtual monitoring device may be deployed within the host operating system or outside the host operating system. In other implementations, the "host layer" may also include 1 privileged virtual machine (e.g., virtualization architecture Xen). The virtual hardware platform provides various hardware resources, such as a virtual processor, a virtual memory, a virtual disk, a virtual network card, and the like, for each virtual computer running on the virtual hardware platform. The virtual computer runs on a virtual hardware platform for which the host layer prepares itself. The host layer is sometimes referred to herein simply as a host.

3. Hardware layer.

The hardware layer refers to a hardware platform that the virtualized environment runs on. The hardware layer may include various hardware, for example, a hardware layer of a physical computer may include a processor and a memory, and may further include an interrupt controller, a network card (network interface card, NIC), an input/output (I/O) device, and the like.

4、libOS(library operating system)。

The lightweight virtualization technology provides an operating system, libOS, which is a runtime library that can provide the functions of a class operating system and run linked with an application, so that all the resources necessary for the application to run are managed by the application itself rather than the operating system. Such as unikernel, OSv, dune, etc. libOS may be considered a lightweight virtual computer.

5. A physical processor.

A physical processor may sometimes be referred to as a "processor" for short, and in this application refers to a physical processing unit, specifically, a minimum processing unit, i.e., a physical core in this application, and in some embodiments, a processing unit that includes multiple physical cores.

6. And a virtual processor.

Virtual processors are representations of physical processing units provided in a shared or sliced manner to virtual computers for use under virtualization technology, e.g., virtual CPUs (virtual central processing unit, vCPU). A virtual computer may have one or more virtual processors serving it, and when there are multiple virtual processors, typically one virtual processor is the master and the other is the slave.

It should be appreciated that a virtual computer corresponds to a stand-alone computer, so that a virtual computer performing an action may also be considered a virtual processor performing the action, while a virtual processor is software implemented, so that a virtual processor performing the action is in fact the physical processor or physical core on which the virtual processor is running. In various embodiments of the present application, the above expressions may be selectively used in order to follow the technical expression habit of the current scenario.

7. Single-root input/output virtualization (SR-IOV).

The SR-IOV technology may virtualize multiple virtual PCIe devices on one peripheral component interconnect express (peripheral component interconnect express, PCIe) device, where the virtual PCIe devices may only be configured and managed by the original physical PCIe device, and each virtual PCIe device may have an independent DMA, so that a virtual machine may directly access the physical PCIe device through the PCIe device without intervention of the VMM. Taking the network card supporting the SR-IOV as an example, each virtual PCIe device corresponds to one virtual network card, and messages are directly exchanged between the virtual PCIe device and the corresponding virtual network card without participation of a VMM (virtual machine monitor), so that the expenditure of the VMM can be reduced, and the performance of the virtual machine is improved.

The SR-IOV abstracts two types of functions for use by users, called physical functions (physical function, PF) and Virtual Functions (VF), respectively. Generally, a network card supporting the SR-IOV technology provides a PF, and the PF includes a function structure of the SR-IOV, so that a user manages the SR-IOV function of the network card by operating the PF. A VF is a type of function associated with a PF that is responsible for creating and maintaining VFs, each PF having multiple VFs associated with it and providing the VFs to a virtual machine for use, sharing the physical resources provided by the PF among the various VFs.

8. The virtual machine is directly connected with the equipment.

In order to pursue the best performance, each cloud manufacturer may choose to configure the pass-through device for the virtual machine, and directly access the pass-through device through the virtual machine, so that the virtual machine obtains performance close to that of the physical machine, achieves high throughput and low-latency virtualization performance, and can also reduce the overhead of a virtualization layer, and improve the availability of resources (for example, resources of a central processor of a host can be saved, and more virtual machines can be created). The public cloud may be a usable cloud provided by a third party provider for a user. The user may access the service through the internet. Public clouds are currently common, such as the bloom cloud, ali cloud, amazon web services (amazon web service, AWS), and the like. The private cloud can run on public resources, but can ensure that resources among all users are isolated, and the users can not be influenced by other users when in use. For example, the virtual pass-through device may be a PCIe device.

The virtual machine direct connection technology is to support the virtual machine to bypass the hypervisor layer and directly access the physical I/O device, so that the virtual machine obtains performance close to that of the physical machine. The SR-IOV direct connection technology is a hardware-based virtualization solution, virtual machines can be directly connected to a physical network card through the SR-IOV technology, and the physical network card can be shared among a plurality of virtual machines with high efficiency. The client can obtain I/O performance comparable to a physical host using SR-IOV pass-through technology.

In view of this, the embodiments of the present application provide a method and related apparatus for processing a page fault, which are used for a physical host, and an operating system OS is running in the physical host.

In the application, the OS receives page fault information about a physical address GPA of a virtual machine reported by a pass-through device, the GPA is a physical address of a guest, and the guest is a virtual machine running on the OS. And then, the OS performs page-missing processing on the GPA to obtain a host physical address HPA corresponding to the GPA, wherein the HPA is a physical address in a memory of a physical host, and sends a mapping relation indication to the pass-through device, and the mapping relation indication comprises a mapping relation between the GPA and the HPA. Because the OS can apply for the HPA as required, the complete mapping relation between GPA and HPA is not required to be established in the starting stage of the gust, the starting speed of the client is improved, and the utilization rate of the memory resources of the host is improved.

In order to facilitate understanding of the embodiments of the present application, a schematic diagram of a system architecture suitable for the page fault handling method provided in the embodiments of the present application is first described in detail below with reference to fig. 3-1.

Fig. 3-1 is a schematic diagram of a system architecture 300 suitable for use in the method of page fault handling provided in an embodiment of the present application.

As shown in fig. 3-1, a physical host 310 and pass-through devices 320 (2 pass-through devices are illustrated in fig. 3-1 as an example) may be included in the system architecture. For example, pass-through device 320 may be a PCIe device that is interconnected with physical host 310 via a PCIe protocol.

3-1, an Operating System (OS) 313, such as a linux operating system, may be running on the physical host 310. Through computational virtualization techniques, a VMM 314 and one or more guests (guests) 315 (e.g., 2 guests in FIG. 3-1) may be run on OS 313, where VMM 314 is configured to manage one or more guests 315, and VMM 314 may also process I/O requests issued by one or more guests 315 through to a software layer of a peripheral component interconnect express (peripheral component interconnect express, PCIe) device 320. Guest 315 has a virtual machine physical address (guest physical address, GPA).

In addition, the OS 313 includes an address translation and protection table (address translation and protection table, ATPT) 316, and the ATPT 316 is used to store the mapping relationship between GPA and HPA. RC die 312 includes root port 312-1 and translation agent (translation agent, TA) 312-2, root port 312-1 for communicating with PCIe device 320, TA 312-2 for querying ATPT 316, looking up HPA based on GPA, or looking up GPA based on HPA.

In the embodiment of the present application, OS 313 further includes synchronizer 313-1 and address translation table 313-2, and VMM 313 may pass the mapping between GPAs and HPAs into synchronizer 313-1. Address translation table 313-2 is a multiplexed hardware assisted virtualized acceleration page table (e.g., intel EPT/AMD NPT/ARM stage 1& stage 2 address translation table) or may be a completely newly built, independent mapping page table for holding GPAs to HPAs.

As shown in FIG. 3-2, the synchronization device 313-1 may include a hardware accelerated page table synchronization module, a control engine, a page fault handling engine, and an address translation engine.

The hardware accelerating page table synchronization module is used for synchronizing address conversion table contents and hardware auxiliary virtualization accelerating page tables, and comprises two parts of processing of establishing and invalidating the page tables; the control engine is used for processing the control information and command sent by the VMM, such as mapping relation from GPA to HPA; the page fault processing engine is used for processing page fault information reported by the direct equipment and reporting the page fault information to the memory management unit of the OS; the address translation engine is used for carrying out inquiry and synchronization processes of address translation (GPA to HPA) and works together with the hardware acceleration page table synchronization module.

Specifically, the hardware layer of the physical host 310 may include a memory (memory) 311 and a Root Complex (RC) chip 312. The RC chip 312 is a hardware interface defined in the PCIe specification, and the hardware interface is responsible for sending PCIe messages of the physical host 310 to the external pass-through device 320, and may also receive PCIe messages sent by the pass-through device 320.

Taking PCIe devices as an example, the hardware layer of the pass-through device 320 may include a CPU, a memory, and an End Point (EP) chip, where the EP chip is a hardware interface defined in the PCIe specification, and is used as a peripheral interface of the pass-through device 320, and responsible for sending PCIe messages to the physical host 310, or may also receive PCIe messages sent by the physical host 310. The embodiments of the present application do not limit the specific implementation of the RC chip 312 and the EP chip, as long as any RC chip 312 and EP chip implemented in compliance with PCIe specifications can be used. Pass-through device 320 may be an application specific integrated circuit (application specific integrated circuit, ASIC) chip, a virtual device (supporting Linux Endpoint Framework framework) of a field programmable gate array (field programmable gate array, FPGA), a smart card, disk, graphics card or graphics processor (graphics processing unit, GPU), or other device having computing and memory resources, without limitation.

In the embodiment of the present application, a cache (cache) and a device translation agent (device translation agent, DTA) may be included in the pass-through device 320.

Where the Cache is an on-chip Cache or on-chip Cache in pass-through device 320 for caching the address mapping of GPAs to HPAs. In the real scene of network receiving and transmitting packets, if the cache hits, the receiving and transmitting packet speed is the fastest, and the next table look-up and synchronization process is not needed.

As shown in fig. 3-3, the DTA includes a prefetch engine, a transaction layer packet (transaction layer packet, TLP) processing engine, a packet processing engine, and an address translation engine, where the prefetch engine is configured to accelerate processing of the packet, and put a hot mapping relationship into the cache in advance; the TLP processing engine is used for carrying out customizing processing on the TLP sent by the equipment, so that the TA can identify whether address translation is carried out or not, and repeated translation processing through the TA is not needed; the address translation engine is used for completing the process of inquiring, updating and invalidating the mapping relation from GPA to HPA and simultaneously completing the control command processing sent by the control engine in the synchronous device; the message processing engine is used for carrying out DMA processing on the message or reporting the page fault interrupt, emptying the hardware queue and the like according to the result of the address translation engine.

The following describes the method of the page fault handling according to the embodiment of the present application in detail with reference to fig. 4-1 and 4-2. It should be noted that, the method provided in the embodiments of the present application may be executed by a physical host, and specifically may be implemented by software deployed on the physical host by executing corresponding instructions. The software may be, for example, software deployed on a virtual machine created on the physical host.

Referring to fig. 4-2, a page fault handling method according to an embodiment of the present application is used in a packet sending process of a client (gust), and a network card is taken as an example for a pass-through device. The page fault processing method mainly comprises the following steps:

401. the client sends an I/O request to the pass-through device, the I/O request indicating the GPA.

In the embodiment of the application, when the client needs to send the message, the pass-through device is required to acquire data for the client, and for this purpose, the client sends an I/O request to the pass-through device, where the I/O request indicates a GPA with data, so as to instruct the pass-through device to determine the HPA based on the GPA, and acquire the data corresponding to the message based on the HPA.

402. The pass-through device queries the cache (HPA) corresponding to the GPA.

In some possible implementations, after receiving the I/O request, the pass-through device may first query the cache (cache) for the corresponding HPA based on the GPA indicated by the I/O request. It should be noted that, the cache (cache) may cache the mapping relationship between GPA and HPA. It should be noted that, the pass-through device receives the I/O request through the message processing engine, and then the message processing engine notifies the address translation engine, so that the address translation engine queries the corresponding HPA in the address translation table based on the GPA. In this embodiment of the present application, if the pass-through device queries the HPA corresponding to the GPA, step 409 is executed, otherwise step 403 is executed.

It should be noted that, step 402 is optional, that is, after the pass-through device receives the I/O request sent by the client, step 403 described below may be directly performed, which is not limited herein.

403. The pass-through device reports page fault information about the GPA to the OS.

In the embodiment of the application, the pass-through device may send page-missing information to the OS through the message processing engine, where the page-missing information indicates that the mapping relationship between the GPA and the corresponding HPA is absent, i.e., the page-missing information indicates the GPA. It should be noted that the OS may receive the page fault information through the page fault processing engine. It should be noted that the pass-through device temporarily closes the corresponding queue and triggers the queue draining logic, i.e. stops the flow of sending the message.

404. The OS queries the HPA corresponding to the GPA in the address translation table.

In this embodiment of the present application, after the OS may receive the page fault information about the GPA through the page fault processing engine, the page fault processing engine notifies the address translation engine, so that the address translation engine queries the HPA corresponding to the GPA from the address translation table. In the embodiment of the present application, if the address translation engine queries the HPA corresponding to the GPA, step 407 is executed, otherwise step 406 is executed.

It should be noted that, step 404 is optional, that is, after the OS receives the page fault information about the GPA reported by the pass-through device, the following step 405 may be directly performed, which is not limited herein.

405. And the OS performs page fault processing to obtain the HPA corresponding to the GPA.

In this embodiment of the present application, when the OS cannot query the HPA corresponding to the GPA in the address translation table, that is, the address translation table lacks the mapping relationship from the GPA to the HPA, the page-missing processing is required. For example, the OS first obtains the HPA corresponding to the GPA based on the application of the GPA, i.e. the application or swap-in of the memory page. In the embodiment of the application, because the HPA can be applied as required, the complete mapping relation between GPA and HPA is not required to be established in the starting stage of the client (guest), the starting speed of the client is improved, the utilization rate of the memory resources of the host is improved, and the super-allocation of the memory is realized.

406. The OS updates the address translation table based on the mapping relationship of GPAs and HPAs.

In this embodiment of the present application, after an page fault processing engine in an OS applies for an HPA corresponding to a GPA, the GPA and the HPA may be written into an address translation table by an address translation engine to update the address translation table, and the updated address translation table includes a mapping relationship between the GPA and the HPA. Then, when the OS receives the page fault information about the GPA reported by the pass-through device, the HPA corresponding to the GPA may be queried from the address translation table.

In some possible implementations, after the OS performs the page-missing processing to obtain the HPA corresponding to the GPA, the address translation engine may also notify the hardware acceleration page table synchronization module, so that the hardware acceleration page table synchronization module updates the ATPT, and the mapping relationship between the updated ATPAGPA and the HPA. In some possible implementations, the address translation table and the ATPT may be multiplexed, so that the address translation engine does not need to notify the hardware accelerated page table synchronization module, i.e., does not need to have the hardware accelerated page table synchronization module update the ATPT, which is not limited herein.

407. The OS sends a mapping relation indication to the pass-through device, wherein the mapping relation indication comprises the mapping relation between GPA and HPA.

In the embodiment of the application, after the OS performs page fault processing to obtain the HPA corresponding to the GPA, the mapping relationship indication may be sent to the pass-through device through the address translation engine, where the mapping relationship indication includes a mapping relationship between the GPA and the HPA. In some possible implementations, the pass-through device may receive the mapping indication through an address translation engine.

408. The pass-through device writes the mapping relationship of the GPAs and HPAs into a cache (cache).

In this embodiment of the present application, after receiving the mapping relation instruction sent by the OS, the pass-through device may write the mapping relation between the GPA and the HPA in the mapping relation instruction into a cache (cache). Then, when the pass-through device receives the I/O request sent by the client and the I/O request indicates the GPA, the pass-through device may query the cache (cache) for the corresponding HPA based on the GPA, and then no page fault information about the GPA needs to be sent to the OS.

409. The pass-through device performs DMA operations based on the HPA.

In the embodiment of the present application, after the pass-through device determines the HPA corresponding to the GPA, a direct memory access (direct memory access, DMA) operation may be performed based on the HPA, and the data corresponding to the HPA may be obtained from the memory. Illustratively, the pass-through device may program the data through a transaction layer packet (transaction layer packet, TLP) processing engine to obtain a TLP, thereby bypassing the TA translation actions, i.e., directly performing the DMA operation.

It should be noted that a DMA transfer copies data from one address space to another. When the CPU initiates this transfer action, the transfer action itself is carried out and completed by the DMA controller. A typical example is to move a block of external memory to a faster memory area inside the chip. Operations such as this do not hold the processor work off, but may be rearranged Cheng Quchu to handle other work. DMA transfer is important for high performance embedded system algorithms and networks.

410. And the direct connection equipment sends the message.

In the embodiment of the present application, after the pass-through device obtains the data corresponding to the HPA, the data packet may be sent to the target device.

Referring to fig. 5-1 and fig. 5-2, a page fault processing method provided in a second embodiment of the present application is used in a packet receiving process of a client (client), and a direct device is taken as an example for describing a network card. The page fault processing method mainly comprises the following steps:

501. the client sends an I/O request to the pass-through device, the I/O request indicating the GPA.

In the embodiment of the application, when the client receives the message, a GPA is allocated to the data in the message. It should be noted that, the client needs the pass-through device to write the data of the message to the pass-through device, and for this purpose, the client sends an I/O request to the pass-through device, where the I/O request indicates the data including the GPA and the message, so as to instruct the pass-through device to determine the HPA based on the GPA, and write the data of the message in the HPA of the memory.

502. The pass-through device queries the cache (HPA) corresponding to the GPA.

In some possible implementations, after receiving the I/O request, the pass-through device may first query the cache (cache) for the corresponding HPA based on the GPA indicated by the I/O request. It should be noted that, the cache (cache) may cache the mapping relationship between GPA and HPA. It should be noted that, the pass-through device receives the I/O request through the message processing engine, and then the message processing engine notifies the address translation engine, so that the address translation engine queries the corresponding HPA in the address translation table based on the GPA. In the embodiment of the present application, if the pass-through device queries the HPA corresponding to the GPA, step 509 is executed, otherwise step 503 is executed.

It should be noted that, step 502 is optional, that is, after the pass-through device receives the I/O request sent by the client, step 503 described below may be directly performed, which is not limited herein.

503. The pass-through device reports page fault information about the GPA to the OS.

504. The OS queries the HPA corresponding to the GPA in the address translation table.

In this embodiment of the present application, after the OS may receive the page fault information about the GPA through the page fault processing engine, the page fault processing engine notifies the address translation engine, so that the address translation engine queries the HPA corresponding to the GPA from the address translation table. In the embodiment of the present application, if the address translation engine queries the HPA corresponding to the GPA, step 507 is executed, otherwise step 506 is executed.

It should be noted that, step 504 is optional, that is, after the OS receives the page fault information about the GPA reported by the pass-through device, the following step 505 may be directly performed, which is not limited herein.

505. And the OS performs page fault processing to obtain the HPA corresponding to the GPA.

506. The OS updates the address translation table based on the mapping relationship of GPAs and HPAs.

507. The OS sends a mapping relation indication to the pass-through device, wherein the mapping relation indication comprises the mapping relation between GPA and HPA.

508. The pass-through device writes the mapping relationship of the GPAs and HPAs into a cache (cache).

509. The pass-through device performs DMA operations based on the HPA.

In the embodiment of the application, after the pass-through device determines the HPA corresponding to the GPA, a direct memory access (direct memory access, DMA) operation may be performed based on the HPA, and the data in the packet is written in the HPA of the memory. Illustratively, the pass-through device may program the data through a transaction layer packet (transaction layer packet, TLP) processing engine to obtain a TLP, thereby bypassing the TA translation actions, i.e., directly performing the DMA operation.

It should be noted that, for simplicity of description, the foregoing method embodiments are all expressed as a series of action combinations, but it should be understood by those skilled in the art that the present application is not limited by the order of actions described, as some steps may be performed in other order or simultaneously in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required in the present application.

In order to facilitate better implementation of the above-described aspects of the embodiments of the present application, the following further provides related devices for implementing the above-described aspects.

Referring to fig. 6, in an embodiment of the present application, a physical host 600 is provided, where an OS is running in the physical host 600, and the physical host 600 may include:

the transceiver module 601 is configured to receive page fault information about a physical address GPA of a virtual machine reported by a pass-through device, where GPA is a physical address of a client, and guest is a virtual machine running on the OS;

the processing module 602 is configured to perform page fault processing on the GPA to obtain a host physical address HPA corresponding to the GPA, where the HPA is a physical address in a memory of a physical host;

the transceiver module 601 is further configured to send a mapping relationship indication to the pass-through device, where the mapping relationship indication includes a mapping relationship between the GPA and the HPA.

In some possible implementations, the processing module 602 is further configured to: querying the HPA corresponding to the GPA in a built-in address translation table;

the processing module 602 is further configured to execute the step of performing the page fault processing on the GPA if the HPA corresponding to the GPA is not found; the transceiver module 601 is further configured to execute a step of sending a mapping relationship indication to the pass-through device if the HPA corresponding to the GPA is found.

In some possible implementations, the processing module 602 is further configured to: and updating an address translation table based on the mapping relation between the GPA and the HPA, wherein the updated address translation table comprises the mapping relation between the GPA and the HPA.

In some possible implementations, the processing module 602 is specifically configured to: and applying for the HPA corresponding to the GPA to a memory of the physical host.

In some possible implementations, the processing module 602 is specifically configured to: updating the ATPT based on the mapping relation between the GPA and the HPA, wherein the updated ATPT comprises the mapping relation between the GPA and the HPA.

Referring to fig. 7, a through device 700 provided in an embodiment of the present application may include:

a transceiver module 701, configured to receive an I/O request sent by a client, where the I/O request indicates a GPA, where the GPA is a physical address of a guest, and guest is a virtual machine running on an OS; the transceiver module 701 is further configured to send page fault information about the GPA to the OS, where the OS belongs to a physical host; the transceiver module 701 is further configured to receive a mapping relationship indication sent by the OS, where the mapping relationship indication includes a mapping relationship between the GPA and the HPA, and the HPA is a physical address in a memory of a physical host.

In some possible implementations, the processing module 702 is configured to query the built-in cache for the HPA corresponding to the GPA; the transceiver module 701 is further configured to perform the steps of sending page fault information about the GPA to the OS and receiving a mapping relationship instruction sent by the OS if the processing module cannot find the HPA corresponding to the GPA.

In some possible implementations, the processing module 702 is further configured to write the mapping relationship between the GPA and the HPA into the cache.

In some possible implementations, the processing module 702 is further configured to perform a direct memory access DMA operation based on the HPA to read data from or write data to the HPA.

It should be noted that, because the content of information interaction and execution process between the modules/units of the above-mentioned device is based on the same concept as the method embodiment of the present application, the technical effects brought by the content are the same as the method embodiment of the present application, and specific content can be referred to the description in the method embodiment shown in the foregoing application, which is not repeated here.

The embodiment of the application also provides a computer storage medium, wherein the computer storage medium stores a program, and the program executes part or all of the steps described in the embodiment of the method.

Referring to fig. 8, a communication device 800 according to another embodiment of the present application includes:

a receiver 801, a transmitter 802, a processor 803, and a memory 804. In some embodiments of the present application, the receiver 801, transmitter 802, processor 803, and memory 804 may be connected by a bus or other means, with the bus connection being exemplified in fig. 8.

Memory 804 may include read only memory and random access memory and provides instructions and data to the processor 803. A portion of the memory 804 may also include non-volatile random access memory (NVRAM). The memory 804 stores an operating system and operating instructions, executable modules or data structures, or a subset thereof, or an extended set thereof, where the operating instructions may include various operating instructions for performing various operations. The operating system may include various system programs for implementing various underlying services and handling hardware-based tasks.

The processor 803 controls the operation of the communication device 800, the processor 803 may also be referred to as a central processing unit (central processing unit, CPU). In a particular application, the various components of the communications device 800 are coupled together by a bus system that may include a power bus, a control bus, a status signal bus, and the like, in addition to a data bus. For clarity of illustration, however, the various buses are referred to in the figures as bus systems.

The methods disclosed in the embodiments of the present application may be applied to the processor 803 or implemented by the processor 803. The processor 803 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuitry of hardware or instructions in software form in the processor 803. The processor 803 may be a general purpose processor, a digital signal processor (digital signal processing, DSP), an application specific integrated circuit (application specific integrated circuit, ASIC), a field-programmable gate array (field-programmable gate array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in hardware, in a decoded processor, or in a combination of hardware and software modules in a decoded processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in the memory 804, and the processor 803 reads information in the memory 804, and in combination with the hardware, performs the steps of the above method.

The receiver 801 may be used to receive input digital or character information and to generate signal inputs related to related settings and function control, the transmitter 802 may include a display device such as a display screen, and the transmitter 802 may be used to output digital or character information through an external interface.

In this embodiment of the present application, the processor 803 is configured to execute the foregoing page fault processing method.

In another possible design, when the physical host 600, the pass-through device 700, or the communication device 800 is a chip, it includes: a processing unit, which may be, for example, a processor, and a communication unit, which may be, for example, an input/output interface, pins or circuitry, etc. The processing unit may execute the computer-executable instructions stored in the storage unit to cause the chip in the terminal to perform the method for transmitting wireless report information according to any one of the above first aspects. Alternatively, the storage unit is a storage unit in the chip, such as a register, a cache, or the like, and the storage unit may also be a storage unit in the terminal located outside the chip, such as a read-only memory (ROM) or other type of static storage device that may store static information and instructions, a random access memory (random access memory, RAM), or the like.

The processor mentioned in any of the above may be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more integrated circuits for controlling the execution of the programs of the above method.

It should be further noted that the above-described apparatus embodiments are merely illustrative, and that the units described as separate units may or may not be physically separate, and that units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in the drawings of the embodiment of the device provided by the application, the connection relation between the modules represents that the modules have communication connection therebetween, and can be specifically implemented as one or more communication buses or signal lines.

From the above description of the embodiments, it will be apparent to those skilled in the art that the present application may be implemented by means of software plus necessary general purpose hardware, or of course may be implemented by dedicated hardware including application specific integrated circuits, dedicated CPUs, dedicated memories, dedicated components and the like. Generally, functions performed by computer programs can be easily implemented by corresponding hardware, and specific hardware structures for implementing the same functions can be varied, such as analog circuits, digital circuits, or dedicated circuits. However, a software program implementation is a preferred embodiment in many cases for the present application. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a readable storage medium, such as a floppy disk, a usb disk, a removable hard disk, a ROM, a RAM, a magnetic disk or an optical disk of a computer, etc., including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform the method described in the embodiments of the present application.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product.

The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be stored by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy Disk, a hard Disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.

Claims

1. The page fault processing method is used for a physical host, wherein an Operating System (OS) is operated in the physical host, and the page fault processing method comprises the following steps:

the OS receives page fault information about a physical address GPA of a virtual machine, wherein the page fault information is reported by direct equipment, the GPA is a physical address of a client, and the Guest is a virtual machine running on the OS;

the OS performs page-missing processing on the GPA to obtain a host physical address HPA corresponding to the GPA, wherein the HPA is a physical address in a memory of a physical host;

and the OS sends a mapping relation instruction to the straight-through equipment, wherein the mapping relation instruction comprises the mapping relation between the GPA and the HPA.

2. The method of claim 1, wherein the OS further comprises, prior to the page fault handling of the GPA:

the OS queries the HPA corresponding to the GPA in a built-in address translation table;

if the HPA corresponding to the GPA cannot be found, executing the step of performing page fault processing on the GPA by the OS;

and if the HPA corresponding to the GPA is found, executing the step that the OS sends a mapping relation instruction to the pass-through equipment.

3. The method of claim 1 or 2, wherein after the OS performs the page fault processing on the GPA, further comprising:

And the OS updates an address translation table based on the mapping relation between the GPA and the HPA, wherein the updated address translation table comprises the mapping relation between the GPA and the HPA.

4. The method of any one of claims 1-3, wherein the OS performs page fault processing on the GPA to obtain an HPA corresponding to the GPA, including:

and the OS applies the HPA corresponding to the GPA to the memory of the physical host.

5. The method of any of claims 1-4, wherein the address translation table is multiplexed with an address translation and protection table, ATPT.

6. The method of any one of claims 1-4, wherein after the OS performs the page fault processing on the GPA, further comprising:

the OS updates the ATPT based on the mapping relationship between the GPA and the HPA, and the updated ATPT comprises the mapping relationship between the GPA and the HPA.

7. The method according to any one of claims 1-6, wherein the OS is a linux system.

8. The method of any of claims 1-7, wherein the pass-through device is a peripheral component interconnect express (PCIe) device.

9. A page fault handling method, comprising:

The method comprises the steps that through equipment receives an I/O request sent by a client, wherein the I/O request indicates GPA, the GPA is a physical address of a client guest, and the guest is a virtual machine running on an OS;

the direct device reports page fault information about the GPA to the OS, and the OS belongs to a physical host;

and the direct equipment receives a mapping relation instruction sent by the OS, wherein the mapping relation instruction comprises the mapping relation between the GPA and the HPA, and the HPA is a physical address in a memory of a physical host.

10. The method of claim 9, wherein before the pass-through device sends page fault information about the GPA to the OS, further comprising:

the direct-connection device queries the HPA corresponding to the GPA in a built-in cache;

and if the HPA corresponding to the GPA cannot be found, executing the steps that the pass-through equipment sends page missing information about the GPA to the OS, and the pass-through equipment receives a mapping relation instruction sent by the OS.

11. The method according to claim 9 or 10, wherein after the pass-through device receives the mapping relation indication sent by the OS, the method further comprises:

and the direct connection equipment writes the mapping relation between the GPA and the HPA into the cache.

12. The method according to any one of claims 9-11, wherein after the pass-through device receives the mapping relation indication sent by the OS, the method further comprises:

the pass-through device performs a Direct Memory Access (DMA) operation based on the HPA to read data from or write data in the HPA.

13. The method according to any one of claims 9-12, wherein the OS is a linux system.

14. The method of any of claims 9-13, wherein the pass-through device is a peripheral component interconnect express, PCIe, device.

15. A communication system, comprising: a physical host in which an OS is running, wherein the OS is for performing the method of any of the preceding claims 1-8, and a pass-through device for performing the method of any of the preceding claims 9-14.

16. A physical host, wherein an OS is running in the physical host, comprising:

the receiving and transmitting module is used for receiving page fault information about a virtual machine physical address GPA reported by the direct connection equipment, wherein the GPA is a physical address of a client guest, and the guest is a virtual machine running on the OS;

The processing module is used for carrying out page fault processing on the GPA to obtain a host physical address HPA corresponding to the GPA, wherein the HPA is a physical address in a memory of a physical host;

the transceiver module is further configured to send a mapping relationship indication to the pass-through device, where the mapping relationship indication includes a mapping relationship between the GPA and the HPA.

17. The physical host of claim 16, wherein the processing module is further configured to:

querying the HPA corresponding to the GPA in a built-in address translation table;

the processing module is further configured to execute the step of performing page fault processing on the GPA if the HPA corresponding to the GPA is not found;

and the transceiver module is further configured to execute the step of sending a mapping relationship instruction to the pass-through device if the HPA corresponding to the GPA is found.

18. The physical host of claim 16 or 17, wherein the processing module is further configured to:

and updating an address translation table based on the mapping relation between the GPA and the HPA, wherein the updated address translation table comprises the mapping relation between the GPA and the HPA.

19. The physical host according to any one of claims 16-18, wherein the processing module is specifically configured to:

And applying for the HPA corresponding to the GPA to a memory of the physical host.

20. The physical host according to any one of claims 16-19, wherein the processing module is specifically configured to:

updating the ATPT based on the mapping relation between the GPA and the HPA, wherein the updated ATPT comprises the mapping relation between the GPA and the HPA.

21. A pass-through device, comprising:

the receiving and transmitting module is used for receiving an I/O request reported by a client, wherein the I/O request indicates GPA, the GPA is a physical address of a client guest, and the guest is a virtual machine running on an OS;

the receiving and transmitting module is further configured to send page fault information about the GPA to the OS, where the OS belongs to a physical host;

the transceiver module is further configured to receive a mapping relationship indication sent by the OS, where the mapping relationship indication includes a mapping relationship between the GPA and the HPA, and the HPA is a physical address in a memory of a physical host.

22. The pass-through device of claim 21, further comprising:

the processing module is used for inquiring the HPA corresponding to the GPA in the built-in cache;

the transceiver module is further configured to, if the processing module cannot find the HPA corresponding to the GPA, perform the step of sending page fault information about the GPA to the OS, and perform the step of receiving the mapping relation instruction sent by the OS.

23. The pass-through device according to claim 21 or 22, characterized in that,

the processing module is further configured to write the mapping relationship between the GPA and the HPA into the cache.

24. The pass-through device according to any one of claims 21-23, characterized in that,

the processing module is further configured to perform a direct memory access DMA operation based on the HPA to read data from the HPA or write data in the HPA.

25. A computer readable storage medium, characterized in that the computer readable storage medium stores a program, which causes a computer device to perform the method of any one of claims 1-14.

26. A computer program product, the computer program product comprising computer-executable instructions stored on a computer-readable storage medium; at least one processor of a device reads the computer-executable instructions from the computer-readable storage medium, the at least one processor executing the computer-executable instructions causing the device to perform the method of any one of claims 1-14.

27. A communication device comprising at least one processor, a memory, and a communication interface;

The at least one processor is coupled with the memory and the communication interface;

the memory is used for storing instructions, the processor is used for executing the instructions, and the communication interface is used for communicating with other communication devices under the control of the at least one processor;

the instructions, when executed by the at least one processor, cause the at least one processor to perform the method of any of claims 1-14.

28. A chip system comprising a processor and a memory, the memory and the processor being interconnected by a line, the memory having instructions stored therein, the processor being configured to perform the method of any of claims 1-14.