CN117500356B - Gas sensor chip integrated with MEMS-CMOS and preparation method thereof - Google Patents

Gas sensor chip integrated with MEMS-CMOS and preparation method thereof Download PDF

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CN117500356B
CN117500356B CN202410005931.4A CN202410005931A CN117500356B CN 117500356 B CN117500356 B CN 117500356B CN 202410005931 A CN202410005931 A CN 202410005931A CN 117500356 B CN117500356 B CN 117500356B
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layer
mems
cmos
chip
gas sensor
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CN117500356A (en
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杨绍松
刘同庆
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WUXI SENCOCH SEMICONDUCTOR CO Ltd
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WUXI SENCOCH SEMICONDUCTOR CO Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N19/00—Integrated devices, or assemblies of multiple devices, comprising at least one thermoelectric or thermomagnetic element covered by groups H10N10/00 - H10N15/00
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/008—MEMS characterised by an electronic circuit specially adapted for controlling or driving the same
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/17—Systems in which incident light is modified in accordance with the properties of the material investigated
    • G01N21/25—Colour; Spectral properties, i.e. comparison of effect of material on the light at two or more different wavelengths or wavelength bands
    • G01N21/31—Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry
    • G01N21/35—Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using infrared light
    • G01N21/3504—Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using infrared light for analysing gases, e.g. multi-gas analysis
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/17—Systems in which incident light is modified in accordance with the properties of the material investigated
    • G01N21/25—Colour; Spectral properties, i.e. comparison of effect of material on the light at two or more different wavelengths or wavelength bands
    • G01N21/31—Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry
    • G01N21/35—Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using infrared light
    • G01N21/3504—Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using infrared light for analysing gases, e.g. multi-gas analysis
    • G01N21/3518—Devices using gas filter correlation techniques; Devices using gas pressure modulation techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/10—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects
    • H10N10/17—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects characterised by the structure or configuration of the cell or thermocouple forming the device
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors

Abstract

Embodiments of the present disclosure provide a gas sensor chip integrated with MEMS-CMOS and a method of manufacturing the same, including: the chip comprises a chip body; the chip body comprises a semiconductor structure layer, and a CMOS device structure and a MEMS device structure which are integrated in the semiconductor structure layer; the MEMS device structure comprises a plurality of thermocouple pairs formed on the semiconductor structure layer, wherein the thermocouple pairs comprise a cold end thermocouple pair and a hot end thermocouple pair; the hot end thermocouple pair is arranged at the central hot end of the chip body; the cold end thermocouple is connected with the drain electrode of the CMOS device structure as an anode, and the other cold end thermocouple is connected with the P+ contact GND end of the CMOS device structure as a cathode; the grid electrode of the CMOS device structure is connected with a multi-path check device of the peripheral circuit; wherein, the negative electrode is connected with the P+ contact GND end by a wire layer, and the grid electrode is connected with a multi-path check device of a peripheral circuit.

Description

Gas sensor chip integrated with MEMS-CMOS and preparation method thereof
Technical Field
The embodiment of the disclosure belongs to the technical field of gas sensors, and particularly relates to a gas sensor chip integrated with MEMS-CMOS and a preparation method thereof.
Background
A non-dispersive infrared (NDIR) gas sensor is a sensor that uses the principle of infrared absorption to detect the gas composition by detecting the absorption of infrared radiation of a specific wavelength by specific gas molecules in ambient air. The NDIR gas sensor mainly comprises a light source, a sample chamber, a spectral filter, a detector and the like. The sensor passes ambient air through the sample chamber, and gas molecules irradiated by the infrared light source in the sample chamber absorb infrared radiation with specific wavelength, and the amount of the absorbed infrared radiation is proportional to the concentration of the gas. The sensor then uses a spectral filter to select the wavelength of interest so that it can only reach the detector. The detector can measure the intensity of the absorbed infrared radiation and reflect the gas concentration value.
The NDIR infrared gas sensor is realized by utilizing the characteristic that different gases have own unique molecular structures and have specific absorption spectrums for infrared light, namely, different gases have absorption capacity for infrared light in a specific wave band. The infrared light of the specific wave band is called as infrared absorption peak of the gas, and the infrared absorption peaks of different gases are different, so that the infrared absorption of the gases in the mixed gas environment can not interfere with each other. The property is not changed by the change of external conditions, and the energy absorbed by a certain gas to be detected is related to the concentration of the gas in the infrared light region, and the larger the concentration is, the more energy is absorbed. When infrared light passes through the gas, energy attenuation is generated at the corresponding frequency, the energy attenuation degree is related to the gas concentration, and the gas concentration to be measured can be calculated by analyzing the infrared light attenuation degree. The absorption of infrared light by the gas to be measured obeys lambert-beer's law. NDIR gas sensors utilize this property to perform qualitative and quantitative analysis of a specific gas concentration.
Compared with other sensors, the NDIR gas sensor has the advantages of high detection precision, high response speed, good stability, strong anti-interference performance and the like, and can detect various gas components. Therefore, the NDIR gas sensor is widely applied to the fields of air quality detection, industrial emission monitoring, medical diagnosis and the like.
Chips in detectors of NDIR gas sensors in industry generally need to cooperate with outsourced filters with specific wave bands to detect characteristic gases, but the chips have the following problems: 1. the problem of low detection sensitivity; 2. the outsourced optical filters need TO be packaged with the gas chip, so that the sensor is large in size, inconvenient for customers TO install and use, and uncontrollable in consistency of the devices; 3. the concentration of different gases cannot be detected; 4. the interference immunity of gas concentration detection is poor.
Therefore, how to solve the above-mentioned problems is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
Embodiments of the present disclosure aim to solve at least one of the technical problems existing in the prior art, and provide a gas sensor chip integrated with MEMS-CMOS and a method for manufacturing the same.
In a first aspect of embodiments of the present disclosure, there is provided a MEMS-CMOS integrated gas sensor chip comprising:
the chip comprises a chip body; the chip body comprises a semiconductor structure layer, and a CMOS device structure and an MEMS device structure integrated in the semiconductor structure layer;
the MEMS device structure comprises a plurality of thermocouple pairs formed on the semiconductor structure layer, wherein the thermocouple pairs comprise a cold end thermocouple pair and a hot end thermocouple pair; the hot end thermocouple pair is arranged at the central hot end of the chip body;
the cold end thermocouple is connected with the drain electrode of the CMOS device structure by taking one cold end thermocouple as an anode, and the other cold end thermocouple is connected with the P+ contact GND end of the CMOS device structure by taking the other cold end thermocouple as a cathode; the grid electrode of the CMOS device structure is connected with a multi-path check device of a peripheral circuit; and the negative electrode is connected with the P+ contact GND end by utilizing the wire layer, and the grid electrode is connected with a multi-way check of a peripheral circuit.
Optionally, the semiconductor structure layer comprises a substrate, and a supporting layer, an oxide layer and a passivation layer which are laminated on the substrate;
the CMOS device structure comprises a P-well structure formed on the substrate, and a source electrode, a grid electrode, a drain electrode and a P+ contact GND terminal.
Optionally, the thickness of the oxide layer is 0.01-10 um, and the material of the oxide layer comprises silicon oxide.
Optionally, the passivation layer has a thickness ranging from 0.01 to 10um, and the material comprises silicon nitride.
Optionally, the material of the wire layer includes aluminum.
Further, the method further comprises the following steps:
a silicon lens array structure having a lens array; the silicon lens array structure is integrally connected with the upper surface of the chip body.
Further, the method further comprises the following steps:
the resonant cavity type array structure is arranged on the lower surface of the chip body; the resonant cavity type array structure is formed with a pit array;
a back cavity is formed on the substrate of the chip body; wherein, the surface of the pit is provided with a reflecting layer; the pits are arranged corresponding to the back cavity, and the pits and the back cavity jointly form a resonant cavity.
Optionally, the back cavity is convex; the back cavity and the pit jointly form a concave-convex resonant cavity.
Optionally, the supporting layer includes a first supporting layer, a second supporting layer and a third supporting layer sequentially laminated on the substrate; the first supporting layer is used as an oxide layer of the grid electrode; the third supporting layer is used as a field oxygen wet oxygen layer for electric isolation between the CMOS device structures.
In a second aspect of embodiments of the present disclosure, there is provided a method for manufacturing a MEMS-CMOS integrated gas sensor chip for manufacturing the above chip, including:
providing a substrate;
sequentially forming a supporting layer, an oxide layer and a passivation layer on the substrate to prepare a semiconductor structure layer;
and manufacturing a CMOS device structure and a MEMS device structure on the semiconductor structure layer.
The beneficial effects of the embodiments of the present disclosure include:
in the method, the CMOS-MEMS process integration is carried out on the thermopile gas chip, the designed CMOS device is integrated with the thermopile process, the CMOS device can be innovatively utilized to selectively regulate and control the MEMS thermopile gas chip, and further, the detection of different monomers in the array on different kinds of gas concentrations is realized.
Drawings
FIGS. 1-8 are flowcharts of a process for fabricating a silicon lens integrated gas sensor chip according to one embodiment of the present disclosure;
fig. 9-15 are flowcharts of a process for manufacturing a chip body according to an embodiment of the present disclosure;
FIG. 16 is a schematic diagram of a chip body array structure according to an embodiment of the disclosure;
FIGS. 17-23 are flowcharts of a process for fabricating an array chip for multiple gas detection according to an embodiment of the present disclosure;
FIG. 24 is a schematic diagram of a gas sensor chip integrated with a silicon lens according to an embodiment of the disclosure;
fig. 25 is a diagram showing the incidence effect of SOC integrated infrared light on a silicon micro concave lens, bottom reflective layer and NDIR infrared gas sensor chip of an integrated optical filter according to an embodiment of the present disclosure.
Detailed Description
In order that those skilled in the art will better understand the technical solutions of the present disclosure, the present disclosure will be described in further detail with reference to the accompanying drawings and detailed description.
Embodiments of the present application are described in further detail below with reference to the accompanying drawings and examples. The following detailed description of the embodiments and the accompanying drawings are provided to illustrate the principles of the present application and are not intended to limit the scope of the application, i.e., the application is not limited to the embodiments described. In the description of the present application, it is to be noted that, unless otherwise indicated, the meaning of "plurality" is two or more; the terms "upper," "lower," "left," "right," "inner," "outer," and the like are used merely for convenience in describing the present application and to simplify the description, and do not denote or imply that the devices or elements being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the present application. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The "vertical" is not strictly vertical but is within the allowable error range. "parallel" is not strictly parallel but is within the tolerance of the error.
In the description of the present application, it should also be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be directly connected or indirectly connected through an intermediate medium. The specific meaning of the terms in the present application can be understood as appropriate by one of ordinary skill in the art.
In the description of the present application, it should also be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be directly connected or indirectly connected through an intermediate medium. The specific meaning of the terms in the present application can be understood as appropriate by one of ordinary skill in the art.
As shown in fig. 7-8, a gas sensor chip integrated with a silicon lens, comprising:
the chip comprises a silicon lens array structure 10 and a chip body 11. The silicon lens array structure is provided with a lens array and is connected with the upper surface of the chip body in an integrated way.
Specifically, the silicon lens array structure 10 includes a silicon substrate 1 and a plurality of filters. The silicon substrate 1 has opposite first and second surfaces, the first surface being formed with a lens array. The second surface of the silicon substrate 1 is provided with a filter, and the lens is provided corresponding to the position of the filter.
The first surface of the silicon substrate 1 is integrally connected with the upper surface of the chip body 11, wherein the lens corresponds to the position of the central hot end of the chip body 11.
In the present disclosure, by integrating the optical filter on the chip body 11 and forming the lens array on the silicon substrate 1 of the optical filter carrier, the lens can converge the energy of the external infrared light source to the central hot end of the chip body 11, thereby improving the chip sensitivity.
In some embodiments, the filter is a narrow band spectral thin film filter.
In some embodiments, the lens array comprises a concave lens array.
In the present disclosure, by integrating the optical filter on the chip body 11 and forming the concave lens array on the silicon lens array structure 10 of the optical filter carrier, the concave lens can effectively converge the energy of the external infrared light source to the central hot end of the chip body 11, thereby significantly improving the chip sensitivity.
In some embodiments, referring to fig. 7, the filters include a methane filter 6, a reference alignment filter 7, and a carbon dioxide filter 8. The methane filter comprises AgF film or MgF 2 A thin film, a reference alignment filter comprising Al (NO 3 ) 3 The film, the carbon dioxide filter includes AlGaS film.
In the present disclosure, the reference alignment filter is used for reference alignment, so that external environmental interference can be eliminated. In addition, different filter film materials are selected TO realize the integration of the same chip, so that the detection of the concentration of various gases can be realized, and the TO packaging of external discrete devices is omitted. And the chip-level integrated package is used instead, so that the size can be reduced, and the installation and the use of customers are facilitated. Meanwhile, the integrated wafer preparation process is controllable, so that the consistency of the integrated device is controllable.
Referring to fig. 20-24, in some embodiments, the gas sensor chip further includes a resonant cavity array structure 20. The resonant cavity type array structure 20 is disposed on the lower surface of the chip body, and the resonant cavity type array structure is formed with a pit array. Specifically, the resonant cavity array structure 20 is formed with arrays of pits of different depths. The substrate of the chip body is provided with a back cavity, the back cavity corresponds to the central hot end position of the chip body, the surface of the pit is provided with a reflecting layer, the pit and the back cavity are correspondingly arranged, and the pit and the back cavity jointly form a resonant cavity.
In this disclosure, the required infrared wave band of detection of different gas concentrations is different, and the wavelength is different, and then the high difference of resonant cavity that chooses for use, this disclosure sets up the pit of different degree of depth, makes it constitute the resonant cavity of different height with the back of the body chamber, can realize multiple gaseous detection. Further, the reflection effect of the reflecting layer enables light to travel back and forth in the resonant cavity, so that the light energy of the transmitted narrow-band filter is continuously enhanced, self-excited oscillation is formed, the receiving and converging of weak light intensity emitted by the light source by the central part of the chip are further increased, and the sensitivity of the chip to specific gas detection is further enhanced.
Further, the optical filters correspond to the pit positions, and pits with different depths are provided with different optical filters. With this arrangement, a plurality of gases can be detected.
In some embodiments, the pits include a first pit 117, a second pit 118, and a third pit 119.
In one embodiment, the first pits 117 are provided corresponding to the methane filter, the second pits 118 are provided corresponding to the reference alignment filter, and the third pits 119 are provided corresponding to the carbon dioxide filter.
In some embodiments, referring to fig. 16 and 22, the back cavity 45 is convex, and the back cavity 45 and the pit together form the concave-convex resonant cavity 13.
In the disclosure, the concave-convex resonant cavity formed by the convex surface of the back cavity 45 and the concave surface of the substrate bottom of the chip body 11 can obviously make light travel back and forth in the resonant cavity, so that the energy of the transmitted narrow-band light is continuously enhanced, self-oscillation is formed, the receiving and converging of the weak light intensity emitted by the light source by the central part of the chip are further increased, and the sensitivity of the chip to specific gas detection is further enhanced.
In some embodiments, referring to fig. 20, the pit array includes pits of different depths.
In some embodiments, the pit depth value is 1/4λ to 3/4λ, where λ is the infrared band wavelength.
In the present disclosure, pits of different depths correspond to different infrared bands, different wavelengths, and further different heights of the resonant cavities, required for detection of a plurality of different gas concentrations. Furthermore, resonant cavities with different heights are selected to form self-oscillation, so that the receiving and converging of weak light intensity emitted by the infrared light source by the central part of the chip are increased.
In some embodiments, referring to fig. 12-16 and 22-24, the chip body 11 includes a semiconductor structural layer and CMOS device structures and MEMS device structures integrated within the semiconductor structural layer.
The MEMS device structure comprises a plurality of thermocouple pairs formed on the semiconductor structure layer, wherein each thermocouple pair comprises a cold-end thermocouple pair and a hot-end thermocouple pair, and each hot-end thermocouple pair is arranged at the central hot end of the chip body.
The cold end thermocouple is connected with the drain electrode of the CMOS device structure by taking one cold end thermocouple as an anode, the other cold end thermocouple is connected with the P+ contact GND end by taking the other cold end thermocouple as a cathode, and the grid electrode is connected with a multiplexer (also called a signal multiplexer) of the peripheral circuit. Wherein, the negative electrode is connected with the P+ contact GND end by a wire layer, and the grid electrode is connected with a multi-path check device of a peripheral circuit.
Wherein chip channel selection for the gas chip array is achieved using a multiple-way check (signal Multiplexer (MUX) 122). Specifically, the gas sensor is integrated with a CMOS device structure and an array of MEMS device structures. And each MEMS device structure is correspondingly provided with different wave band filters for detecting different types of gases. The CMOS device structure utilizes a signal Multiplexer (MUX) 122 to selectively regulate and control the MEMS thermopile gas chip by regulating and controlling the gate 30 voltages of different monolithic CMOS device structures in the array, thereby selectively detecting different gas concentrations.
Specifically, the chip body 11 includes a semiconductor structure layer including a substrate and a support layer, an oxide layer 41, and a passivation layer 44 laminated on the substrate, and a CMOS device structure and a MEMS device structure integrated in the semiconductor structure layer.
Referring to fig. 11-14, the cmos device structure includes a P-well structure 24 formed in the substrate, and a source 29, a gate 30, a drain 31, and a p+ contact GND terminal 36.
In some embodiments, the thickness of the oxide layer 41 ranges from 0.01 um to 10um, and the material includes silicon oxide.
In some embodiments, the passivation layer 44 has a thickness ranging from 0.01 um to 10um, and the passivation layer comprises silicon nitride.
In some embodiments, the material of the conductive line layer includes aluminum.
Specifically, the MEMS device structure includes a thermopile formed in a support layer, the thermopile including a plurality of thermocouple pairs.
The cold end thermocouple pair is connected with the drain electrode 31 as an anode, the other cold end thermocouple pair is connected with the P+ contact GND end 36 as a cathode, and the grid electrode 30 is connected with a multiplex check box of a peripheral circuit.
In the method, the CMOS-MEMS process integration is carried out on the thermopile gas chip, the designed CMOS device is integrated with the thermopile process, and the CMOS device can be innovatively utilized to selectively regulate and control the MEMS thermopile gas chip.
In some embodiments, referring to fig. 12, the support layer includes a first support layer 25, a second support layer 26, and a third support layer 27 laminated in sequence to the substrate. The first support layer 25 is used as an oxide layer of the gate electrode 30, and the third support layer 27 is used as a field oxide wet oxide layer for electrical isolation between the CMOS device structures.
In some embodiments, the stress of the first support layer 25 and the third support layer 27 is reversed from that of the second support layer 26.
Specifically, for the MEMS device structure portion, the above three support layers are prepared to improve the stress of the support film layer by reversing the stress of the first support layer 25 and the third support layer 27 with the stress of the second support layer 26. For the CMOS device structure portion, the first support layer 25 may serve as a gate 30 oxide layer, the third support layer 27 may serve as a field oxide wet oxide layer for electrical isolation between CMOS device structures, and the second support layer 26 may serve as a blocking mask layer for growth of the third support layer 27.
In some embodiments, the first support layer 25 is a silicon oxide support layer, the second support layer 26 is a silicon nitride support layer, and the third support layer 27 is a silicon oxide support layer.
Referring to fig. 1-8, in one embodiment of the present disclosure, a method for manufacturing a gas sensor chip integrated with a silicon lens is provided, including:
s101, preparing a silicon lens array structure 10;
s102, preparing a chip body 11;
s103, integrating the silicon lens array structure 10 and the chip body 11; the lens of the silicon lens array structure 10 corresponds to the position of the central hot end of the chip body 11.
In some embodiments, the preparing of the silicon lens array structure 10 of step S101 includes:
s1011, providing the silicon substrate 1, and performing cleaning and thinning processing.
In some embodiments, referring to fig. 1, the silicon substrate 1 is a P-type double polished silicon wafer. Further, the P-type double-polished silicon wafer is sequentially placed in acetone, absolute ethyl alcohol and deionized water according to the standard, respectively subjected to ultrasonic treatment for 5 minutes, and then the silicon wafer is placed on a hot plate and heated for half an hour at 100 ℃. By adopting the cleaning treatment, pollutants, dust and other particles on the surface of the silicon wafer can be removed.
Further, thinning the silicon wafer to the thickness of 400-600 um after cleaning, wherein the thinned silicon wafer is prepared for standby according to the requirement.
S1012, etching the surface of the silicon substrate by using a femtosecond laser processing technology to form a lens array on the silicon substrate.
In some embodiments, the cleaned and thinned silicon wafer (silicon substrate 1) is placed on a high-precision three-dimensional moving platform, the laser pulse width is 100-300 fs, the repetition frequency is 1-3 KHz, the pulse number is 100-200, the laser energy is in the range of 50-100 nJ/cm < 2 >, and the laser is focused on the surface of the silicon wafer through an objective lens (the magnification is 80 times) with the numerical aperture of 0.8.
Further, referring to fig. 2, an array of microporous structures in a certain arrangement is prepared on the surface of the silicon wafer by the movement of the three-dimensional moving platform. Specifically, after laser modification at a specific position, ultrasonic treatment is carried out on a sample in deionized water for 5 minutes to remove particles generated by surface laser ablation and scattered on the surface of the sample, and a preliminary solid pit array 2 is formed inside a silicon wafer after surface particles are removed.
Further, after laser modification, the silicon wafer with the solid pit array 2 is placed in an etching cavity of an inductively coupled plasma etching system (ICP), and dry etching is performed in a plasma environment of SF6 gas. ICP is chosen for its controllability of lateral and longitudinal etching.
In some embodiments, the adjustable ranges of the power of the upper RF source and the power of the lower RF source of the etching system are 400-500W and 200-300W respectively, and the airflow flux is 40-100 sccm.
In some embodiments, the etching process includes two stages, first a rapid etching of the laser modified region solid pit array 2 at an initial stage, and then a process in which the concave structures are expanded with an increase in etching time. Wherein, the rapid etching of the laser modified area solid pit array 2 in the initial stage lasts for 3-5 min.
Referring to fig. 3, during laser ablation to form the laser modified region solid pit array 2, oxygen in the air reacts with silicon atoms to form silicon oxide, and the crystal type of the silicon lattice of the ablated region also changes from a single crystal state to a polycrystalline or amorphous state. Therefore, the solid pit array 2 of the laser modified area is rapidly etched out 3-5 min after the etching starts, and the etching depth can rapidly reach a maximum value. In the initial stage of etching, the solid pit array 2 of the laser modified region is etched rapidly to form a hollow pit array 3, wherein the etching rate of the modified region is faster than that of the unmodified region by about 4-8 times.
Further, referring to fig. 4, in the expansion stage, the size of the microporous structure increases with the increase of etching time, and gradually expands to form the concave lens 4. Specifically, the silicon substrate has a first surface and a second surface opposite to each other, wherein the concave lens array is formed on the first surface.
In some embodiments, the etching time of the etching expansion stage is 5-50 min.
Under the condition that the etching time is 5-20 min, the transverse dimension of the concave lens is approximately linearly increased along with the increase of the etching time, so that the transverse etching rate is relatively stable along with the increase of the etching time. And the surface of the concave structure becomes smoother and smoother along with the increase of the etching time to 20-50 min.
In the etching process, as the etching time is increased, the etching depth is gradually reduced and gradually tends to be unchanged. This is caused by aspect ratio dependent etching (edge, or aperture effect), which causes insufficient local gas supply and untimely reflection of product discharge, resulting in a decrease in etching rate at the bottom of the concave lens 4 without any influence on the external etching rate. As the etching time increases, the aspect ratio of the concave lens 4 gradually decreases, so that the aperture effect also decreases accordingly, and the etching depth also gradually tends to be constant.
S1013, the optical filter is integrated on the surface of the silicon substrate 1 opposite to the lens array to prepare the silicon lens array structure 10. The optical filter corresponds to the lens in position and is used for converging energy of an external infrared light source to the central hot end of the chip body.
Specifically, referring to fig. 5, a layer of photoresist is coated on a bottom silicon plane of the silicon substrate 1 and a photolithography process is performed to form a photoresist 5 structure as a mask structure for subsequent filter integration. Specifically, the bottom surface is the second surface of the silicon substrate 1.
Referring to FIG. 6, an AgF film structure is deposited on the second surface of the silicon substrate 1, and the thickness is 400-700 nm or an MgF2 film structure is 800-1400 nm. The two functional materials have high transmittance to the infrared band of 3.43um, and the methane gas has strong absorption property to the infrared light of 3.43um, so the concentration of the methane gas can be detected through the feedback of the gas chip to the infrared light energy of 3.43 um.
Therefore, a layer of filter with high transmittance in a specific infrared band is integrated on the surface of the gas sensitive chip, so that the detection sensitivity can be greatly improved, and different gases absorb different infrared bands, so that the method has high selectivity in detecting the concentration of the gases. And the specific 3.43um infrared band high-transmittance filter film is integrated, so that the methane gas concentration can be detected.
Referring to FIG. 7, a silicon lens array structure 10 is fabricated by depositing Al (NO 3) 3 films with a thickness of 400-800 nm and AlGaS films with a thickness of 500-1000 nm on the surface of the silicon substrate 1, respectively, in the same manner. The two functional materials have high transmittance to infrared wave bands of 3.95um and 4.26um respectively. Most of the gas does not absorb infrared light in the 3.95um wave band, and only water vapor absorbs a large amount of infrared light in the 3.95um wave band, so that the Al (NO 3) 3 film functional material is used as a reference contrast to eliminate external environment interference. The carbon dioxide gas has the characteristic of strong absorption to infrared light in the 4.26um wave band, and the concentration of the carbon dioxide gas can be detected through the feedback of the gas chip on the infrared light energy in the 4.26um wave band. Therefore, the three functional materials on the surface of the silicon substrate 1 are respectively a monomer for detecting the concentration of methane gas, a reference monomer and a monomer for detecting the concentration of carbon dioxide gas in the functionality.
In some embodiments, further comprising: s1014, SOC integration is performed between the filter-integrated silicon lens array structure 10 and the chip body 11 by the optical adhesive 9. The chip body 11 is an NDIR infrared gas sensor chip array. With particular reference to fig. 8.
Specifically, the first step: and ultra-precisely polishing the bonding surface of the integrated device. The bonding surface of the silicon lens array structure 10 is the front surface of the lens surface on both sides, and the bonding surface of the NDIR infrared gas sensor chip array is the heat sensitive surface facing upwards. And a second step of: the silicon lens array structure 10 to be glued and the NDIR infrared gas sensor chip array are subjected to constant temperature treatment. The two optical cement pieces are placed in an environment of 50-100 ℃ and kept at the constant temperature for about 3 hours, so that the temperature of the device is uniform, and the optical cement is favorable for firmness. And thirdly, cleaning the photoresist piece. The soft material in the same environment is used for cleaning the photoresist surface, and the photoresist surface is covered by a dust-free glass cover after cleaning. And fourthly, applying a certain pressure on the two devices to realize the combination of the photoresist, and then coating a thin layer of photosensitive adhesive on the outer side of the contact edge of the photoresist surface to strengthen the photoresist effect.
Referring to fig. 9-16, in another embodiment of the present disclosure, a method for manufacturing an SOC monolithically integrated MEMS-CMOS gas sensor chip is provided, comprising:
s201, preparing a silicon lens array structure 10;
s202, preparing a chip body 11;
s203, preparing a resonant cavity type array structure 20;
s204, the integrated silicon lens array structure 10, the resonant cavity type array structure 20 and the chip body 11.
In some embodiments, the preparing the chip body 11 of step S202 includes:
s2021, providing a substrate 21.
In some embodiments, referring to fig. 9, substrate 21 is provided with a P-type double polished wafer and subjected to cleaning and thinning processes.
In some embodiments, the P-type double polished silicon wafer is sequentially placed in acetone, absolute ethyl alcohol and deionized water according to the standard, respectively subjected to ultrasonic treatment for 5 minutes, and the silicon wafer is placed on a hot plate and heated for half an hour at 100 ℃. By adopting the cleaning treatment, pollutants, dust and other particles on the surface of the silicon wafer can be removed.
Further, thinning the silicon wafer to the thickness of 400-600 um after cleaning, wherein the thinned silicon wafer is prepared for standby according to the requirement.
In some embodiments, referring to fig. 10, a thermal oxygen (dry oxygen) process is performed on the upper surface of the substrate 21 to implant the barrier layer 22, wherein the thermal oxygen current is 500-1000 a.
In some embodiments, the structural layers of substrate 21 and barrier layer 22 are subjected to photolithography.
Specifically, referring to fig. 11, a photoresist 23 is coated on the surface of the barrier layer 22, wherein the photoresist 23 exposes the CMOS region of the substrate 21. Further, boron ions are implanted into the CMOS region to form a lightly doped P-well structure 24, and the photoresist 23 is removed.
S2022, sequentially forming an upper support layer, an oxide layer 41, and a passivation layer 44 on the substrate 21 to prepare a semiconductor construction layer.
Further, referring to fig. 12, the support layers include a first support layer 25, a second support layer 26, and a third support layer 27.
In some embodiments, the first support layer 25 is a silicon oxide support layer, the second support layer 26 is a silicon nitride support layer, and the third support layer 27 is a silicon oxide support layer.
In some embodiments, forming the support layer on the substrate 21 includes: and depositing a first supporting layer 25 with the thickness of 0.1-5 um on the surface of the structural layer formed by the substrate 21 and the barrier layer by a thermal oxidation process, and depositing a second supporting layer 26 with the thickness of 0.01-0.5 um and a third supporting layer 27 with the thickness of 0.01-0.5 um on the surface of the first supporting layer 25 by utilizing a front low-pressure chemical vapor deposition.
In the present disclosure, for MEMS device structures, three support layers are fabricated to improve the stress of the support film layer by stress reversal of silicon nitride and silicon oxide. For CMOS device structures, the first support layer 25 may serve as a gate 30 oxide layer, the third support layer 27 may serve as a field oxide wet oxide layer for electrical isolation between CMOS devices, and the second support layer 26 may serve as a blocking mask layer for growth of the third support layer 27.
S2023, manufacturing a CMOS device structure and a MEMS device structure on the semiconductor structure layer.
Specifically, referring to fig. 13, a layer of polysilicon 28 with a thickness of 0.1-2 um is sputtered on the surface of the third support layer 27 by using a plasma enhanced chemical vapor deposition process, and phosphorus ions are doped by using an ion implantation and diffusion method to form an N-type polysilicon semiconductor.
Further, a source 29, a gate 30 and a drain 31 of the CMOS device structure are formed on the structural layer constituted by the substrate 21 and the support layer by a heavy doping process. A gas chip thermopile of the MEMS device structure portion is formed on the polysilicon 28 by a heavily doped process, wherein the gas chip thermopile of the MEMS device structure portion includes a first cold end thermocouple 32 and a second cold end thermocouple 35 of another thermocouple pair, and further includes a first hot end thermocouple 33 and a second hot end thermocouple 34 of another thermocouple pair.
Further, boron ions are doped into the polysilicon 28 by ion implantation and diffusion to form a P-type polysilicon semiconductor.
Further, referring to fig. 14, the p+ contact GND terminal 36 of the CMOS transistor is formed on the structural layer formed by the substrate 21 and the supporting layer through a heavy doping process, so as to provide a low-resistance connection point for the CMOS transistor and suppress the reverse breakdown of the source-drain junction and the generation of leakage current. Meanwhile, a gas chip thermopile third cold end thermocouple 37 and a fourth cold end thermocouple 40 of another thermocouple pair of MEMS device structures and a gas chip thermopile third hot end thermocouple 38 and a fourth hot end thermocouple 39 of another thermocouple pair of MEMS device structures are formed on the polysilicon 28 through a heavy doping process. Wherein the third hot-side thermocouple 38 (P-type polysilicon) and the first hot-side thermocouple 33 (N-type polysilicon) form a pair of hot-side thermocouple pairs. The fourth hot side thermocouple 39 (P-type polysilicon) and the second hot side thermocouple 34 (N-type polysilicon) form a pair of hot side thermocouple pairs. The third cold-end thermocouple 37 (P-type polysilicon) forms a pair of cold-end thermocouple pairs with the first cold-end thermocouple 32 (N-type polysilicon). The fourth cold end thermocouple 40 (P-type polysilicon) and the second cold end thermocouple 35 (N-type polysilicon) form a pair of hot end thermocouple pairs.
In some embodiments, the thermocouple pairs are connected in series through Al metal, and the potential accumulation forms a high-sensitivity thermopile, wherein an infrared gas chip formed by the thermopiles can feed back infrared light energy in real time.
In some embodiments, referring to fig. 15, a top oxide layer 41 is formed by depositing a layer of silicon oxide having a thickness of 0.01-10 um on polysilicon 28 by plasma enhanced chemical vapor deposition for electrical insulation.
In some embodiments, a layer of metal aluminum with a thickness of 100-500 nm is deposited by using a magnetron sputtering method, and a conducting wire layer 42 is formed by photolithography, where the conducting wire layer 42 is used to connect each MEMS part thermocouple pair, and simultaneously connect the third cold-end thermocouple 37 (positive electrode) of the MEMS gas chip with the drain electrode 31 of the CMOS part.
Further, a passivation layer 44 is formed by depositing a layer of silicon nitride with a thickness of 0.01-10 um on the surface of the oxide layer 41 by a plasma enhanced chemical vapor deposition method.
In some embodiments, with continued reference to fig. 15, a secondary magnetron sputtering process is performed to deposit a layer of tungsten gold having a thickness of 100-500 nm as the PAD layer 43 metal, and simultaneously to connect the PAD layer 43 metal leakage to the peripheral board level circuitry. Further, referring to fig. 16, the back cavity 45 is formed by performing bottom etching on the silicon substrate 21 by deep silicon etching, so as to release the central hot end position of the device, form a back release cavity, and complete the manufacture of the MEMS gas chip, where the back cavity 45 is used to reduce the heat loss of the central hot end, so that a temperature difference between cold and hot ends can be formed.
In some embodiments, a second cold-end thermocouple 35 (cathode) of the MEMS gas chip is connected to the p+ contact GND terminal 36 of the CMOS portion in an array using two layers of tungsten gold to form an MEMS gas sensor chip integrated with an electronic switching CMOS tube, wherein the thermopile cells are connected in a one-to-one correspondence with the CMOS devices.
Further, the array gate 30 is coupled in parallel to a peripheral circuit multiplexer MUX for selective detection of different gas concentrations by modulating the gate 30 voltages for different cells in the array. When the power supply voltage of the gate 30 is greater than the threshold voltage, the electrons form an N-type thin layer on the surface of the P substrate 21 near the gate 30, and are communicated with the two n+ regions, and form an N-type conduction channel between the drain and the source, so that the CMOS transistor is in an on state at this time, and is in an off state at this time.
In some embodiments, the preparing the resonant cavity array structure 20 of step S203 includes:
s2031, providing the P-type double polished silicon wafer 110, and cleaning and thinning. Referring specifically to fig. 17.
In some embodiments, the P-type double polished silicon wafer 110 is sequentially placed in acetone, absolute ethyl alcohol and deionized water according to the standard, respectively, and subjected to ultrasonic treatment for 5 minutes, and the silicon wafer is placed on a hot plate and heated at 100 ℃ for half an hour after ultrasonic treatment. By adopting the cleaning treatment, pollutants, dust and other particles on the surface of the silicon wafer can be removed.
Further, thinning the silicon wafer to the thickness of 400-600 um after cleaning, wherein the thinned silicon wafer is prepared for standby according to the requirement.
S2032, etching the surface of the silicon wafer by using a femtosecond laser processing technology to form a pit array on the silicon wafer.
Specifically, referring to fig. 18, the cleaned and thinned silicon wafer 110 is placed on a high-precision three-dimensional moving platform, and a first solid pit 111 is prepared by using linearly polarized femtosecond laser with a wavelength of 800nm, a laser pulse width of 100-300 fs, a repetition frequency of 1-3 khz, a pulse number of 20-50, and a laser energy range of 20-50 nJ/cm 2. The second solid pits 112 are prepared using a linearly polarized femtosecond laser with a pulse number of 100 to 200 and a laser energy ranging from 50 to 100nJ/cm 2. The third solid pits 113 are prepared using linearly polarized femtosecond laser with a pulse number of 300 to 500 and a laser energy ranging from 100 to 150nJ/cm 2.
In some embodiments, referring to fig. 19, laser modified silicon wafer 110 is placed in an etching chamber of an inductively coupled plasma etching system (ICP), and dry etched in a plasma environment of SF6 gas to form first hollow pits 114, second hollow pits 115, and third hollow pits 116. Further, referring to fig. 20, etching duration is 20-50 min to form first, second and third pits 117, 118 and 119 of different depths.
S2033, a reflective layer is formed on the pit surface.
Specifically, referring to fig. 21, a layer of aluminum chrome alloy with a thickness of 300-500 nm is deposited on the concave silicon surface of the pit by LPCVD to manufacture a metal reflective layer 125, so as to complete the preparation of the resonant cavity type array structure 20. The resonant cavity array structure 20 is a solid bottom silicon structure.
The aluminum chrome alloy can reflect more than 90% of infrared light, so that the heat of the hot end of the gas chip is improved, and the sensitivity of detecting the concentration of the gas is further improved. The pits with different depths are because infrared wave bands and wavelengths required for detecting different gas concentrations are different, and the bottoms are selected to be different in height as resonant cavities.
In some embodiments, the height of the resonant cavity is generally 1/4λ to 3/4λ, where λ is the infrared band wavelength. The wavelength of the selected resonant cavities is 3.43um,3.95um and 4.26um respectively, so that resonant cavities with different heights are selected to form self-oscillation, and the receiving and converging of the central part of the chip to weak light intensity emitted by the infrared light source are increased.
In some embodiments, referring to fig. 22, the resonant cavity array structure 20 is SOC integrated with the chip body 11 through the adhesive 120, wherein the chip body 11 is an NDIR gas sensor chip.
In some embodiments, referring to fig. 23, the gate electrode 30 of the electronic switch CMOS of the gas chip array integrated with the resonant cavity type array structure 20 is connected to a signal Multiplexer (MUX) 122 through a gold wire 121, and chip channel selection of the gas chip array is achieved by the signal Multiplexer (MUX) 122.
Further, the whole chip array is fixedly packaged on a bottom PCB board 124 by using a die attach adhesive 123, and the bottom is a substrate structure of the resonant cavity type array structure 20. In this disclosure, compare in back of body chamber structure, when in actual use, solid end silicon structure is more convenient for WLP encapsulation, has improved gaseous chip array's overall reliability and practicality. Further, referring to fig. 24, the silicon lens array structure 10, the chip body 11 and the resonant cavity type array structure 20 are packaged to prepare a gas sensor chip integrating a silicon lens.
In some embodiments, referring to fig. 25, fig. 25 is a graph of the SOC integrated infrared ray incidence effect of a silicon micro concave lens, bottom reflective layer, and NDIR infrared gas sensor chip of an integrated filter. In the figure, the design of this disclosure can make the infrared light energy that the infrared light source sent concentrate at the hot junction as far as possible, and concave lens and bottom unsmooth resonant cavity can assemble the energy of focusing infrared light source in the sensitive region of infrared chip, promotes the chip output, and then promotes gas concentration detection sensitivity.
It is to be understood that the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, however, the present disclosure is not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the disclosure, and are also considered to be within the scope of the disclosure.

Claims (10)

1. A MEMS-CMOS integrated gas sensor chip, the chip comprising a chip body; the chip body comprises a semiconductor structure layer, and a CMOS device structure and an MEMS device structure integrated in the semiconductor structure layer;
the MEMS device structure comprises a plurality of thermocouple pairs formed on the semiconductor structure layer, wherein the thermocouple pairs comprise a cold end thermocouple pair and a hot end thermocouple pair; the hot end thermocouple pair is arranged at the central hot end of the chip body;
the cold end thermocouple is connected with the drain electrode of the CMOS device structure by taking one cold end thermocouple as an anode, and the other cold end thermocouple is connected with the P+ contact GND end of the CMOS device structure by taking the other cold end thermocouple as a cathode; the grid electrode of the CMOS device structure is connected with a multi-path check device of a peripheral circuit; wherein the negative electrode is connected with the P+ contact GND end by a wire layer, and the grid is connected with a multi-way check of a peripheral circuit;
the gas sensor chip is integrated with a CMOS device structure and an MEMS device structure array; different wave band filters are correspondingly arranged on the MEMS device structures and are used for detecting different types of gases; the CMOS device structure utilizes the signal multiplexer to selectively regulate and control the MEMS thermopile gas chip by regulating and controlling the grid voltages of different single CMOS device structures in the array, thereby selectively detecting different gas concentrations.
2. The MEMS-CMOS integrated gas sensor chip of claim 1, wherein,
the semiconductor structure layer comprises a substrate, and a supporting layer, an oxide layer and a passivation layer which are laminated on the substrate;
the CMOS device structure comprises a P-well structure formed on the substrate, and a source electrode, a grid electrode, a drain electrode and a P+ contact GND terminal.
3. The MEMS-CMOS integrated gas sensor chip of claim 2, wherein,
the thickness of the oxide layer is 0.01-10 um, and the oxide layer is made of silicon oxide.
4. The MEMS-CMOS integrated gas sensor chip of claim 2, wherein,
the passivation layer thickness range is 0.01-10 um, and the material comprises silicon nitride.
5. The MEMS-CMOS integrated gas sensor chip of claim 1, wherein,
the material of the wire layer comprises aluminum.
6. The MEMS-CMOS integrated gas sensor chip of claim 1, further comprising:
a silicon lens array structure having a lens array; the silicon lens array structure is integrally connected with the upper surface of the chip body.
7. The MEMS-CMOS integrated gas sensor chip of claim 1, further comprising:
the resonant cavity type array structure is arranged on the lower surface of the chip body; the resonant cavity type array structure is formed with a pit array;
a back cavity is formed on the substrate of the chip body; wherein, the surface of the pit is provided with a reflecting layer; the pits are arranged corresponding to the back cavity, and the pits and the back cavity jointly form a resonant cavity.
8. The MEMS-CMOS integrated gas sensor chip of claim 7,
the back cavity is convex; the back cavity and the pit jointly form a concave-convex resonant cavity.
9. The MEMS-CMOS integrated gas sensor chip of claim 2, wherein,
the support layer comprises a first support layer, a second support layer and a third support layer which are sequentially laminated on the substrate; the first supporting layer is used as an oxide layer of the grid electrode; the third supporting layer is used as a field oxygen wet oxygen layer for electric isolation between the CMOS device structures.
10. A method for manufacturing an integrated MEMS-CMOS gas sensor chip according to any one of claims 1 to 9, comprising:
providing a substrate;
sequentially forming a supporting layer, an oxide layer and a passivation layer on the substrate to prepare a semiconductor structure layer;
and manufacturing a CMOS device structure and a MEMS device structure on the semiconductor structure layer.
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