CN117498869A

CN117498869A - Two-step single-slope analog-to-digital converter, readout circuit, image system and method

Info

Publication number: CN117498869A
Application number: CN202210864491.9A
Authority: CN
Inventors: 衡佳伟; 刘浩杰
Original assignee: SmartSens Technology Shanghai Co Ltd
Current assignee: SmartSens Technology Shanghai Co Ltd
Priority date: 2022-07-21
Filing date: 2022-07-21
Publication date: 2024-02-02

Abstract

The invention provides a two-step single slope analog-to-digital converter, comprising: a ramp generator for generating a ramp control signal and adjusting the ramp control signal based on a control feedback signal to generate a ramp voltage and output; the non-inverting input end of the comparator is connected with the slope voltage, the inverting input end of the comparator is connected with the pixel voltage and is used for comparing the slope voltage with the pixel voltage and outputting a comparison result; the memory is connected with the comparison output end of the comparator and is used for storing the value of the highest bit according to the comparison result in the coarse quantization stage; the digital control logic is connected with the output end of the memory and is used for generating a control feedback signal and adjusting the control feedback signal according to the value of the highest bit so as to reset the slope voltage; and the counter is connected with the comparison output end of the comparator and is used for carrying out quantization counting on the residual bits according to the comparison result in the fine quantization stage. The invention solves the problem that the area and the power consumption of the CIS are increased due to the fact that the number of ramp generators is large in the existing two-step SS ADC.

Description

Two-step single-slope analog-to-digital converter, readout circuit, image system and method

Technical Field

The invention relates to the field of integrated circuit design, in particular to a two-step single-slope analog-to-digital converter, a reading circuit, an image system and a method.

Background

The Single Slope analog-to-digital converter (SS ADC) has the advantages of simple circuit structure, low noise, small area, low power consumption and the likeSeries of advantages, but its A/D conversion speed is slow, 2 for every n bits of A/D conversion ⁿ This restricts the readout speed of the CMOS Image Sensor (CIS) by one clock period, limiting the improvement of CIS resolution and frame rate.

In order to increase the readout speed of the SS ADC, a concept of a two-step SS ADC is proposed, and a conventional two-step SS ADC quantization process is shown in fig. 1. The whole A/D conversion process is divided into two stages of coarse quantization and fine quantization, wherein the high C bit (the high C bit and the low F bit can be set, for example, an 11-bit ADC is generally selected to be 3 bits and 8 bits), and the corresponding quantization step length DeltaV _C Is VREF/2 ^C Coarse quantization divides the quantization range VREF into 2 ^C A voltage interval. According to the coarse quantization result, the voltage range of the input signal can be determined, then a proper fine quantization signal is selected to be connected to a comparator, the quantization of the low F bit is completed, and the quantization step length DeltaV corresponding to the fine quantization is performed _F Is (VREF/2) ^C )/2 ^F . Thus, for n-bit resolution, a two-step SS ADC only requires (2 ^C +2 ^F ) For a clock cycle, where n=c+f.

The two-step SS ADC can greatly improve the A/D conversion speed, but the quantization range VREF is divided into 2 due to coarse quantization ^C A voltage interval such that a conventional two-step SS ADC requires 2 ^C The fine quantization is performed by the ramp generators (coarse quantization can be used for multiplexing the fine quantized ramp generators), and in general, the coarse quantization is designed to be 3 bits, that is, 8 ramp generators are needed, and the 8 ramp generators can significantly increase the area and power consumption of the CIS, and in addition, the mismatch of slopes among the multiple ramps can cause the reduction of linearity.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a two-step single-slope analog-to-digital converter, a readout circuit, an image system and a method, which are used for solving the problem that the area and power consumption of the CIS increase due to the number of the ramp generators in the existing two-step SS ADC.

To achieve the above and other related objects, the present invention provides a two-step single-slope analog-to-digital converter comprising:

a ramp generator for generating a ramp control signal and adjusting the ramp control signal based on a control feedback signal to generate a ramp voltage and output;

the non-inverting input end of the comparator is connected with the slope voltage, the inverting input end of the comparator is connected with the pixel voltage and is used for comparing the slope voltage with the pixel voltage and outputting a comparison result;

the memory is connected with the comparison output end of the comparator and is used for storing the value of the most significant bit according to the comparison result in the coarse quantization stage;

the digital control logic is connected with the output end of the memory and is used for generating the control feedback signal and adjusting the control feedback signal according to the value of the highest bit so as to reset the ramp voltage;

and the counter is connected with the comparison output end of the comparator and is used for carrying out quantization counting on the residual bits according to the comparison result in the fine quantization stage.

Optionally, the two-step single slope analog-to-digital converter further comprises:

the first coupling capacitor is connected between the ramp voltage and the non-inverting input end of the comparator;

and the second coupling capacitor is connected between the pixel voltage and the inverting input end of the comparator.

the first zero clearing switch is connected between the in-phase input end and the in-phase output end of the comparator and is controlled by a zero clearing control signal;

the second zero clearing switch is connected between the inverting input end and the inverting output end of the comparator and is controlled by the zero clearing control signal.

Optionally, the ramp generator is implemented with a current steering digital-to-analog converter.

Optionally, the ramp generator includes: m groups of current control units, load resistor and dummy resistor, wherein, M groups of the circuit structures of the current control units all include: the first control switch is connected with the first control switch;

the power supply end of the current source is connected with a power supply voltage, the input end of the current source is connected with a bias voltage, the output end of the current source is connected with the first end of the first control switch and the first end of the second control switch, the second end of the first control switch is grounded through the load resistor and generates the slope voltage, the second end of the second control switch is grounded through the dummy resistor, the first control switch is controlled by the slope control signal, and the second control switch is controlled by an inverted signal of the slope control signal; wherein M is a positive number greater than 1.

Optionally, the memory is a 1-bit memory, and the counter is an (N-1) bit counter; wherein N is the resolution of the two-step single slope analog-to-digital converter.

The present invention also provides a readout circuit comprising: a two-step single slope analog to digital converter as claimed in any one of the preceding claims.

The present invention also provides an image system including: a readout circuit as described above.

The invention also provides a conversion method of the two-step single-slope analog-to-digital converter, which comprises the following steps:

in the initial stage, setting the value of the slope voltage as VREF;

a coarse quantization stage of reducing a value of the ramp voltage from VREF to 1/2VREF based on the ramp control signal, and comparing the pixel voltage VPIX and the ramp voltage; the most significant bit msb=1 if VPIX <1/2VREF, msb=0 if VPIX >1/2 VREF;

a transition phase in which the value of the ramp voltage is maintained at 1/2VREF based on the control feedback signal if msb=1, and reset from 1/2VREF to VREF based on the control feedback signal if msb=0;

and a fine quantization stage, wherein the value of the ramp voltage is controlled to gradually decrease based on the ramp control signal, the rest bits are quantized, and the quantization results of all bits are obtained according to the weight of the code value.

in the initial stage, setting the value of the slope voltage to 0;

a coarse quantization stage of raising a value of the ramp voltage from 0 to 1/2VREF based on the ramp control signal, and comparing the pixel voltage VPIX and the ramp voltage; the most significant bit msb=1 if VPIX <1/2VREF, msb=0 if VPIX >1/2 VREF;

a transition phase in which the value of the ramp voltage is reset from 1/2VREF to 0 based on the control feedback signal if msb=1, and maintained at 1/2VREF based on the control feedback signal if msb=0;

and a fine quantization stage, wherein the value of the ramp voltage is controlled to gradually rise based on the ramp control signal, the rest bits are quantized, and the quantization results of all bits are obtained according to the weight of the code value.

Optionally, the pixel voltage includes an image voltage and/or a reset voltage.

Optionally, correlated double sampling is performed based on the same ramp generator to obtain the reset voltage and the image voltage, respectively.

As described above, the two-step single-slope analog-to-digital converter, the readout circuit, the image system and the method of the present invention provide a new two-step single-slope analog-to-digital conversion scheme, where the N-bit resolution is divided into the Most Significant Bit (MSB) of 1 bit and the remaining bit of (N-1) bit, and the quantization of the MSB is completed by adopting the dichotomy in the first A/D conversion process, so that the quantization step can be effectively reduced, and the saved conversion clock period can be gradually increased with the improvement of the ADC resolution. The scheme does not need to add an extra slope generator, and can finish the quantization process of the two-step SS ADC only by utilizing one of the falling slope voltage or the rising slope voltage generated by the existing slope generator (namely, the traditional single-slope ADC is utilized and only one slope generator is needed). The ramp voltage is not different from the traditional SS ADC, so that all the advantages of the traditional SS ADC are reserved, the problems of the area, the power consumption and the linearity of the traditional two-step SS ADC are effectively solved, and the quantization speed of the SS ADC can be effectively improved on the premise that the area, the power consumption and the linearity of the CIS are not affected. In addition, the scheme is based on the traditional SS ADC architecture, so that reversible switching can be performed between the scheme and the traditional SS ADC algorithm without redesigning.

Drawings

Fig. 1 shows waveforms of the conversion process corresponding to the conventional two-step SS ADC.

Fig. 2 is a schematic circuit diagram of a two-step single-slope analog-to-digital converter according to the present invention.

Fig. 3 shows a schematic circuit diagram of the ramp generator according to the present invention.

Fig. 4 shows waveforms of the conversion process when msb=1 corresponding to the conversion method of the present invention, wherein the ramp voltage is a falling ramp signal.

Fig. 5 shows waveforms of the conversion process when msb=0 corresponding to the conversion method of the present invention, wherein the ramp voltage is a falling ramp signal.

Description of element reference numerals

1. Reading circuit

10. Two-step single slope analog-to-digital converter

100. Ramp generator

101. Current control unit

200. Comparator with a comparator circuit

300. Memory device

400. Digital control logic

500. Counter

2. Pixel circuit

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

Please refer to fig. 2 to fig. 5. It should be noted that, the illustrations provided in the present embodiment are merely schematic illustrations of the basic concepts of the present invention, and only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Example 1

As shown in fig. 2, the present embodiment provides a two-step single-slope analog-to-digital converter 10, the two-step single-slope analog-to-digital converter 10 including: ramp generator 100, comparator 200, memory 300, digital control logic 400, and counter 500.

The ramp generator 100 is used for generating a ramp control signal and adjusting the ramp control signal based on the control feedback signal ramp_az to generate and output a ramp voltage Vramp.

Specifically, as shown in fig. 3, the ramp generator 100 is implemented using a current steering digital-to-analog converter; comprising the following steps: the circuit structures of the M groups of current control units 101 include: a current source I0, a first control switch S1 and a second control switch S2; the power end of the current source I0 is connected with a power voltage VDD, the input end of the current source I0 is connected with a bias voltage, the output end of the current source I0 is connected with the first end of the first control switch S1 and the first end of the second control switch S2, the second end of the first control switch S1 is grounded through a load resistor Rload and generates a ramp voltage Vramp, the second end of the second control switch S2 is grounded through a dummy resistor Rdummy, the first control switch S1 is controlled by a ramp control signal, and the second control switch S2 is controlled by an inverted signal of the ramp control signal; wherein M is a positive number greater than 1.

Alternatively, the circuit configuration of the M-group current control unit 101 may be the same, i.e., the current sources I0 of the M-group current control unit 101 have the same current magnitude. Alternatively, the circuit structure of the M groups of current control units 101 may be different, i.e. the current source sizes of the current control units of each group of current control units 101 in the M groups of current control units 101 may be in a binary increasing proportion, for example, I:2I:4I:8I:16I:32I:64I:128I; the current source sizes of the current control units in the M groups of current control units 101 may also be mixed ratios, for example, I:2I:4I:8I:16I:16I:16I. Therefore, the current source sizes of the current control units in the M groups of current control units 101 may be designed based on actual requirements, which is not limited herein.

In this example, the M first control switches S1 are controlled by a ramp control signal, the M second control switches S2 are controlled by an inversion signal of the ramp control signal, and the magnitude of the current flowing to the load resistor Rload can be controlled by controlling the closing number of the first control switches S1, so as to control the magnitude of the ramp voltage Vramp; if m=5, the ramp control signal is 11111, and its inverted signal is 00000, at this time, all of the 5 first control switches S1 are closed, all of the 5 second control switches S2 are opened, the current flowing to the load resistor Rload is maximum, the ramp voltage Vramp is maximum, and VREF is set; for another example, m=5, where the ramp control signal is 00000, the inverted signal is 11111, at this time, all of the 5 first control switches S1 are opened, all of the 5 second control switches S2 are closed, the current flowing to the load resistor Rload is minimum, and the ramp voltage Vramp is minimum, which is 0.

The ramp voltage Vramp may be an ascending ramp signal or a descending ramp signal; the voltage value of the generated ramp voltage Vramp is changed up or down by controlling the number of the first control switches S1 to be turned on.

In practical application, two paths to ground are formed by using the load resistor Rload and the dummy resistor Rdummy, and the first control switch S1 and the second control switch S2 are controlled by the ramp control signal and the inversion signal thereof respectively, so that the current source I0 is guaranteed to have a conduction path all the time in the switching process of the switches, and burrs are avoided to be generated on the output node, thereby influencing the differential nonlinearity of the ramp voltage Vramp (if the current source I0 has no conduction path at a certain moment, the current source I0 charges the node above the corresponding switch, and when the switch is turned on again, the charges stored on the node above the switch are discharged to the output node and generate burrs to influence the differential nonlinearity of the ramp voltage Vramp).

The comparator 200 has a non-inverting input terminal connected to the ramp voltage Vramp and an inverting input terminal connected to the pixel voltage VPIX, and is configured to compare the ramp voltage Vramp with the pixel voltage VPIX and output a comparison result. For example, the comparator 200 outputs a high level when the ramp voltage Vramp is greater than the pixel voltage VPIX, and the comparator 200 outputs a low level when the ramp voltage Vramp is less than the pixel voltage VPIX.

The memory 300 is connected to a comparison output of the comparator 200 for storing a Most Significant Bit (MSB) value according to a comparison result in a coarse quantization stage. For example, when the comparator 200 outputs a high level, the memory 300 stores msb=1, and when the comparator 200 outputs a low level, the memory 300 stores msb=0. Since the memory 300 stores only 1-bit data (1 or 0), the memory 300 is generally a 1-bit memory.

The digital control logic 400 is coupled to the output of the memory 300 for generating a control feedback signal ramp_az, and adjusting the control feedback signal ramp_az according to the value of the Most Significant Bit (MSB) to reset the ramp voltage Vramp.

In this example, if the ramp voltage Vramp is a falling ramp signal, then: in an initial stage, the ramp generator 100 generates a ramp control signal to control all of the M first control switches S1 to be closed, so that the ramp voltage Vramp is VREF; in the coarse quantization phase, the ramp generator 100 generates a corresponding ramp control signal to control half of the M first control switches S1 to be closed so that the ramp voltage Vramp is 1/2VREF; in the transition stage, the digital control logic 400 generates the control feedback signal ramp_az and outputs the control feedback signal ramp_az to the ramp generator 100, if msb=1, the digital control logic 400 maintains the control feedback signal ramp_az in a low level state so as to maintain the ramp voltage Vramp at 1/2VREF, and if msb=0, the digital control logic 400 adjusts the control feedback signal ramp_az in a high level state so as to change the ramp control signal generated by the ramp generator 100, thereby controlling all of the M first control switches S1 to be closed and resetting the ramp voltage Vramp to VREF; in the fine quantization stage, the ramp control signal generated by the ramp generator 100 should control the M first control switches S1 to gradually decrease the number of closures on the basis of the prior art, so that the ramp voltage Vramp gradually decreases from 1/2VREF to 0 or from VREF to 1/2VREF.

If the ramp voltage Vramp is a rising ramp signal, then: in an initial stage, the ramp generator 100 generates a ramp control signal to control all of the M first control switches S1 to be turned off so that the ramp voltage Vramp is 0; in the coarse quantization phase, the ramp generator 100 generates a corresponding ramp control signal to control half of the M first control switches S1 to be closed so that the ramp voltage Vramp is 1/2VREF; in the transition stage, the digital control logic 400 generates the control feedback signal ramp_az and outputs the control feedback signal ramp_az to the ramp generator 100, if msb=1, the digital control logic 400 adjusts the control feedback signal ramp_az to be in a high level state so as to change the ramp control signal generated by the ramp generator 100, and further control all of the M first control switches S1 to be turned off, reset the ramp voltage Vramp to 0, and if msb=0, the digital control logic 400 maintains the control feedback signal ramp_az to be in a low level state so as to maintain the ramp voltage Vramp at 1/2VREF; in the fine quantization stage, the ramp control signal generated by the ramp generator 100 controls the M first control switches S1 to gradually increase the number of closures on the basis of the prior art, so that the ramp voltage Vramp gradually increases from 0 to 1/2VREF or from 1/2VREF to VREF.

In practical applications, the digital control logic 400 is implemented by a controller, and of course, other circuits that can generate the control feedback signal ramp_az according to the above logic are also applicable to the present example; the ramp control signal generated by the ramp generator 100 may be encoded in a binary code, a thermometer code, or a hybrid code.

The counter 500 is connected to the comparison output of the comparator 200, and is used for performing quantization counting of the remaining bits according to the comparison result in the fine quantization stage. Wherein, the counter is an (N-1) bit counter, and N is the resolution of the two-step single-slope analog-to-digital converter.

Further, the two-step single slope analog-to-digital converter 10 further includes: a first coupling capacitor C1 and a second coupling capacitor C2; the first coupling capacitor C1 is connected between the ramp voltage Vramp and the non-inverting input terminal Vinp of the comparator 200, and the second coupling capacitor C2 is connected between the pixel voltage VPIX and the inverting input terminal Vinn of the comparator 200, for buffering the corresponding voltage signal input to the comparator 200. In practical applications, the first coupling capacitor C1 is a variable capacitor, and the second coupling capacitor C2 is a fixed capacitor, wherein a specific capacitance value of the variable capacitor is set according to a value of the corresponding ramp voltage Vramp.

Further, the two-step single slope analog-to-digital converter 10 further includes: the first zero clearing switch K1 and the second zero clearing switch K2; the first zero clearing switch K1 is connected between the in-phase input terminal Vinp and the in-phase output terminal Vop1 of the comparator 200 and controlled by the zero clearing control signal cmp_az, and the second zero clearing switch K2 is connected between the inverting input terminal Vinn and the inverting output terminal Von1 of the comparator 200 and controlled by the zero clearing control signal cmp_az. When the zero clearing control signal cmp_az is valid, the first zero clearing switch K1 and the second zero clearing switch K2 are closed, the in-phase input end Vinp and the in-phase output end Vop1 of the comparator 200 are short-circuited, and the reverse phase input end Vinn and the reverse phase output end Von1 are short-circuited, so that zero clearing operation of the comparator 200 is realized.

Correspondingly, the present embodiment also provides a conversion method of the two-step single-slope analog-to-digital converter 10 described above, which includes: step 1), step 2), step 3) and step 4); in the conversion method, the ramp voltage Vramp is a falling ramp signal.

Step 1) in the initial stage, the value of the ramp voltage Vramp is set as VREF. For example, the M first control switches S1 are all controlled to be closed based on the first ramp control signal, thereby setting the value of the ramp voltage Vramp to VREF.

Step 2) a coarse quantization stage, which is to reduce the value of a ramp voltage Vramp from VREF to 1/2VREF based on a ramp control signal, and compare the pixel voltage VPIX with the current ramp voltage; the most significant bit msb=1 if VPIX <1/2VREF, and msb=0 if VPIX >1/2 VREF. For example, half of the M first control switches S1 are controlled to be closed based on the second ramp control signal, so that the value of the ramp voltage Vramp is quickly reduced to 1/2VREF from VREF; meanwhile, since the ramp voltage Vramp and the pixel voltage VPIX are respectively connected to the non-inverting input terminal and the inverting input terminal of the comparator 200, the current ramp voltage and the pixel voltage VPIX can be compared and the value of the MSB can be stored in the memory 300 according to the comparison result.

Step 3) a transition phase, if msb=1, the value of the ramp voltage Vramp is maintained at 1/2VREF based on the control feedback signal ramp_az generated by the digital control logic 400, and if msb=0, the value of the ramp voltage Vramp is reset from 1/2VREF to VREF based on the control feedback signal ramp_az. For example, if msb=1, the control feedback signal ramp_az generated by the digital control logic 400 is maintained at a low level, and the ramp control signal generated by the ramp generator 100 is unchanged to maintain the ramp voltage Vramp at 1/2VREF; if msb=0, the digital control logic 400 adjusts the control feedback signal ramp_az to be high, so that the ramp generator 100 changes the ramp control signal to control all of the M first control switches S1 to be closed, and resets the ramp voltage Vramp to VREF.

And 4) in the fine quantization stage, the value of the ramp voltage Vramp is controlled to gradually decrease based on the ramp control signal, the rest bits are quantized, and the quantization results of all bits are obtained according to the weight of the code value. For example, the M first control switches S1 are controlled to gradually decrease the number of closures based on the third ramp control signal, so that the ramp voltage Vramp gradually decreases from 1/2VREF to 0, or from VREF to 1/2VREF, and the remaining bits are quantized using the comparator 200 and the counter 500.

Specifically, the pixel voltage VPIX includes an image voltage Vsig and/or a reset voltage Vrst. In practice, the pixel voltage VPIX includes both the image voltage Vsig and the reset voltage Vrst; since the CMOS image sensor outputs the reset voltage Vrst first for a while and then outputs the image voltage Vsig, the two-step single-slope analog-to-digital converter 10 performs a/D conversion on the reset voltage Vrst first and then performs a/D conversion on the image voltage Vsig.

More specifically, when the pixel voltage VPIX includes the reset voltage Vrst and the image voltage Vsig, correlated double sampling is performed based on the same ramp generator to obtain the reset voltage Vrst and the image voltage Vsig, respectively. Since the ramp voltage Vramp of the quantized reset voltage Vrst and the image voltage Vsig of the present example are generated by the same ramp generator, true correlated double sampling can be performed, thereby eliminating noise such as KT/C and FPN; in contrast, in the conventional two-step SS ADC, since the ramp voltages for quantizing the reset voltage Vrst and the image voltage Vsig are not generated by the same ramp generator, correlated double sampling can be achieved only in a partial voltage range.

Correspondingly, the present embodiment also provides a conversion method of the two-step single-slope analog-to-digital converter 10 described above, which includes: step 1), step 2), step 3) and step 4); in the conversion method, the ramp voltage Vramp is a rising ramp signal.

Step 1) in the initial stage, the value of the ramp voltage Vramp is set to 0. For example, the M first control switches S1 are all turned off based on the first ramp control signal, thereby setting the value of the ramp voltage Vramp to 0.

Step 2) a coarse quantization stage, which is to raise the value of a ramp voltage Vramp from 0 to 1/2VREF based on a ramp control signal, and compare the pixel voltage VPIX with a current ramp voltage; the most significant bit msb=1 if VPIX <1/2VREF, and msb=0 if VPIX >1/2 VREF. For example, half of the M first control switches S1 are controlled to be closed based on the second ramp control signal, so that the value of the ramp voltage Vramp is quickly increased from 0 to 1/2VREF; meanwhile, since the ramp voltage Vramp and the pixel voltage VPIX are respectively connected to the non-inverting input terminal and the inverting input terminal of the comparator 200, the current ramp voltage and the pixel voltage VPIX can be compared and the value of the MSB can be stored in the memory 300 according to the comparison result.

Step 3) in the transition phase, if msb=1, the value of the ramp voltage Vramp is reset from 1/2VREF to 0 based on the control feedback signal ramp_az, and if msb=0, the value of the ramp voltage Vramp is maintained at 1/2VREF based on the control feedback signal ramp_az generated by the digital control logic 400. For example, if msb=1, the digital control logic 400 adjusts the control feedback signal ramp_az to be at a high level, so that the ramp generator 100 changes the ramp control signal to control all of the M first control switches S1 to be turned off, and resets the ramp voltage Vramp to 0; if msb=0, the control feedback signal ramp_az generated by the digital control logic 400 is maintained at a low level, and the ramp control signal generated by the ramp generator 100 is unchanged to maintain the ramp voltage Vramp at 1/2VREF.

And 4) in the fine quantization stage, the value of the ramp voltage Vramp is controlled to gradually rise based on the ramp control signal, the rest bits are quantized, and the quantization results of all bits are obtained according to the weight of the code value. For example, the M first control switches S1 are controlled to gradually increase the number of closures based on the third ramp control signal, so that the ramp voltage Vramp gradually increases from 0 to 1/2VREF, or from 1/2VREF to VREF, and the remaining bits are quantized using the comparator 200 and the counter 500.

Next, referring to fig. 2 and 3, referring to fig. 4 and 5, a conversion method of the two-step single-slope analog-to-digital converter according to the present embodiment will be described.

The pixel voltage VPIX includes an image voltage Vsig and a reset voltage Vrst, and since the time to quantize the image voltage Vsig is much longer than the time to quantize the reset voltage Vrst, attention is focused on the a/D conversion process of the image voltage Vsig; taking the ramp voltage Vramp as a falling ramp signal as an example.

In the initial stage, all of the M first control switches S1 are closed, and all of the M second control switches S2 are opened, and at this time, the initial value of the ramp voltage Vramp is VREF.

A coarse quantization stage, in which half of the M first control switches S1 are closed to reduce the value of the ramp voltage Vramp from VREF to VREF/2 in a very short time; meanwhile, the ramp voltage Vramp and the image voltage Vsig are correspondingly input to the non-inverting input terminal and the inverting input terminal of the comparator 200 and compared:

(1) If the output of the comparator 200 is not flipped, vsig < VREF/2 is illustrated, at which time msb=1 is stored into the memory 300;

then, entering a transition stage, maintaining the control feedback signal ramp_az at a low level, keeping half of the M first control switches S1 closed, and maintaining the value of the ramp voltage Vramp at VREF/2;

then, entering a fine quantization stage, gradually opening M first control switches S1 on the basis of closing half, gradually reducing the value of a ramp voltage Vramp from VREF/2 to 0, continuously quantizing the rest (N-1) bits according to the working mode of the traditional SS ADC, and finally obtaining an N-bit quantization result according to the weight of a code value.

(2) If the output of the comparator 200 toggles, vsig > VREF/2 is illustrated, at which time msb=0 is stored into the memory 300;

then, the transition stage is entered, the control feedback signal ramp_az is adjusted to be high level, all the M first control switches S1 are closed, and the value of the ramp voltage Vramp is quickly reset from VREF/2 to VREF;

and then, entering a fine quantization stage, gradually opening M first control switches S1 on the basis of complete closing, gradually reducing the value of the ramp voltage Vramp from VREF to VREF/2, continuously quantizing the rest (N-1) bits according to the working mode of the traditional SS ADC, and finally obtaining an N-bit quantization result according to the weight of the code value.

In both cases, the ramp voltage Vramp drops from VREF/2 to 0 and VREF/2, respectively, whereas the conventional SS ADC drops from VREF to 0, thus, the present inventionCompared with the traditional SS ADC, the proposal saves the clock period, and the clock period range is 2 ^N To 2 ^N-1 Between and infinitely approach 2 ^N-1 Moreover, compared with the traditional two-step SS ADC, the scheme does not need as many ramp generators, and effectively solves the problems of area, power consumption and linearity of the traditional two-step SS ADC.

The two-step SS ADC provided by the scheme improves the conversion speed of the SS ADC by applying a dichotomy in the first A/D conversion, and simultaneously retains the advantages of low noise, small area and low power consumption of the traditional SS ADC; in the coarse quantization process, although the signal linearity of the ramp voltage Vramp is poor, the acquisition of the 1-bit MSB and the subsequent fine quantization of the (N-1) bit code value are not affected. In the second a/D conversion process, the quantization range VREF is divided into upper and lower sub-sections, and according to the value of the MSB obtained in the first step, it is selected whether to reset the ramp voltage Vramp to VREF before fine quantization, and then the quantization of the remaining bits is completed. Therefore, compared with the traditional SS ADC, the time for obtaining the A/D conversion of the MSB is effectively reduced, and the effectiveness of the SS ADC is gradually improved along with the improvement of the resolution of the SS ADC; in addition, as only one slope generator is adopted, the problems of area, power consumption and linearity of the traditional two-step SS ADC are effectively solved.

Example two

As shown in fig. 2, the present embodiment provides a readout circuit 1, the readout circuit 1 including: the two-step single slope analog-to-digital converter 10 as described in embodiment one.

Accordingly, as shown in fig. 2, the present embodiment further provides an image system, which includes: the readout circuit 1 described above.

Further, the image system also comprises a pixel array, wherein the pixel array comprises a plurality of pixel units which are arranged in rows and columns to form an array; each pixel unit is correspondingly provided with a pixel circuit 2, wherein each pixel unit corresponds to the same or different column lines, so as to realize serial output or parallel output of the pixel voltage VPIX through the read-out circuit 1 respectively. It should be noted that, the pixel unit is any conventional pixel circuit, and its specific structure has no substantial effect on the present embodiment.

In summary, the two-step single-slope analog-to-digital converter, the readout circuit, the image system and the method of the present invention provide a new two-step single-slope analog-to-digital conversion scheme, where the N-bit resolution is divided into the highest bit (MSB) of 1 bit and the remaining bits of (N-1) bit, and the quantization of the MSB is completed by adopting the binary method in the first a/D conversion process, so that the quantization step can be effectively reduced, and the saved conversion clock period can be gradually increased with the improvement of the ADC resolution. The scheme does not need to add an extra slope generator, and can finish the quantization process of the two-step SS ADC only by utilizing one of the falling slope voltage or the rising slope voltage generated by the existing slope generator (namely, the traditional single-slope ADC is utilized and only one slope generator is needed). The ramp signal is not different from the traditional SS ADC, so that all advantages of the traditional SS ADC are reserved, the problems of area, power consumption and linearity of the traditional two-step SS ADC are effectively solved, and the quantization speed of the SS ADC can be effectively improved on the premise that the area, the power consumption and the linearity of the CIS are not affected. In addition, the scheme is based on the traditional SS ADC architecture, so that reversible switching can be performed between the scheme and the traditional SS ADC algorithm without redesigning. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. A two-step single-slope analog-to-digital converter, the two-step single-slope analog-to-digital converter comprising:

2. The two-step single-slope analog-to-digital converter of claim 1, further comprising:

3. The two-step single-slope analog-to-digital converter of claim 1, further comprising:

4. The two-step single slope analog-to-digital converter of claim 1, wherein the ramp generator is implemented with a current-steering digital-to-analog converter.

5. The two-step single-slope analog-to-digital converter of claim 4, wherein said ramp generator comprises: m groups of current control units, load resistor and dummy resistor, wherein, M groups of the circuit structures of the current control units all include: the first control switch is connected with the first control switch;

6. The two-step single slope analog-to-digital converter according to claim 1, wherein the memory is a 1-bit memory and the counter is an (N-1) bit counter; wherein N is the resolution of the two-step single slope analog-to-digital converter.

7. A readout circuit, the readout circuit comprising: a two-step single slope analog-to-digital converter as claimed in any one of claims 1-6.

8. An image system, the image system comprising: the sensing circuit of claim 7.

9. A conversion method of a two-step single slope analog-to-digital converter according to any of claims 1-6, characterized in that the conversion method comprises:

in the initial stage, setting the value of the slope voltage as VREF;

10. A conversion method of a two-step single slope analog-to-digital converter according to any of claims 1-6, characterized in that the conversion method comprises:

in the initial stage, setting the value of the slope voltage to 0;

11. A conversion method according to claim 9 or 10, wherein the pixel voltage comprises an image voltage and/or a reset voltage.

12. The conversion method according to claim 11, wherein correlated double sampling is performed based on the same ramp generator to obtain the reset voltage and the image voltage, respectively.