CN117494651A - Machine learning-based SRAM bit cell optimization design method, device, medium and terminal - Google Patents
Machine learning-based SRAM bit cell optimization design method, device, medium and terminal Download PDFInfo
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Abstract
The application provides an optimization design method, device, terminal and medium of an SRAM bit cell based on machine learning, wherein performance parameters are obtained by collecting real parameters of the SRAM bit cell, and arranging and combining various parameters in the SRAM bit cell and simulating the parameters. A size prediction model is constructed based on the real parameters and the performance parameters of the SRAM bit cell to realize the prediction of the size of the SRAM bit cell. The automatic parameter adjusting method reduces the possibility of errors in the artificial parameter adjusting process through an automatic process, improves the reliability and consistency of design, and provides a high-efficiency and accurate design tool for SRAM bit cell design, thereby greatly reducing the time cost, labor cost and economic cost of design, accelerating the development process of the SRAM bit cell, and improving the flexibility of the SRAM bit cell design.
Description
Technical Field
The present disclosure relates to the field of chip design, and in particular, to a method, an apparatus, a medium, and a terminal for optimizing an SRAM bit cell based on machine learning.
Background
SRAM (Static Random-Access Memory) is a type of Static Random Access Memory for storing and reading data. SRAM has faster access speed and lower power consumption than Dynamic Random Access Memory (DRAM). When the SRAM receives the write instruction, the data is written into the target memory cell. The write operation transfers data to the flip-flop circuit of the target memory cell through the control line, and the state of the flip-flop is updated to the written data value. When the data in the memory cell needs to be read, the data of the target memory cell is transmitted to an output line through a control line for reading by an external circuit. The read operation does not change the contents of the memory cell. The inputs to the SRAM include write data, write addresses, and write enable signals for writing data to the target memory cell. The output includes read data and a read enable signal for reading data from the target memory cell.
The design of the SRAM bit cell is automatically compiled according to parameters provided by the manufacturer, which include power consumption, speed, etc., but the parameters of the device itself in the SRAM are not of interest. Nor can the device parameters for SRAM be set in SPICE models, and thus the parameter values for SRAM devices cannot be provided. SRAM from different vendors is provided by different IP vendors, which results in a large difference between the bit cell sizes. In the design process, in order to save area, the bit cell uses the minimum size in the design rule in a large amount, however, the parameter of the minimum size is sensitive to the fluctuation of the process, so that each manufacturing plant uses special process conditions and process control to match the requirements of SRAM parameters, and particularly, when the product is transferred, clear parameter requirements are required for devices in the SRAM, otherwise, the process flow cannot be determined, thereby greatly improving the design complexity and reducing the design flexibility. And cannot meet the personalized needs of the user. Meanwhile, if the bit unit of the SRAM needs to be designed, large deviation can be generated by artificial experience tuning, so that tuning efficiency is reduced.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present application is to provide a method, an apparatus, a medium and a terminal for optimizing an SRAM bit cell based on machine learning, which are used for solving the problems of complexity, poor flexibility, inability to meet the personalized needs of users, large deviation of manual tuning, and low efficiency in the process of designing the SRAM bit cell in the prior art.
To achieve the above and other related objects, a first aspect of the present application provides a method for optimizing design of an SRAM bitcell based on machine learning, including collecting an SRAM bitcell parameter set of a process node; inputting the SRAM bit cell parameter set into simulation software for simulation to generate a performance index set; based on a machine learning algorithm, constructing a parameter prediction model through the performance index set and the SRAM bit cell parameter set; and inputting the expected performance set of the SRAM bit cell to be designed into the parameter prediction model to output and obtain the optimized parameter set of the SRAM bit cell to be designed.
In some embodiments of the first aspect of the present application, constructing a parameter prediction model from the set of performance metrics and the set of SRAM bitcell parameters based on a machine learning algorithm comprises: dividing the performance index set and the SRAM bit cell parameter set into a training set and a testing set; inputting the training set into the parameter prediction model to perform model training; the test set is input into the trained predictive model to evaluate performance of the predictive model.
In some embodiments of the first aspect of the present application, inputting the training set into the parametric prediction model for model training includes: inputting the performance index set in the training set into the parameter prediction model to generate a predicted SRAM bit cell parameter set; constructing a loss function based on a predicted SRAM bit cell parameter set and an SRAM bit cell parameter set corresponding to a performance index set in the training set; and training and optimizing the parameter prediction model based on the loss function.
In some embodiments of the first aspect of the present application, inputting the SRAM bitcell parameter set into simulation software for simulation to generate a performance index set includes: and arranging and combining the multiple types of parameters contained in the SRAM bit unit parameter set, and inputting each combination into simulation software for simulation so as to generate the performance index set formed by the performance indexes of the multiple combinations.
In some embodiments of the first aspect of the present application, the machine learning algorithm comprises: k-nearest neighbor algorithm, decision tree algorithm, regression algorithm, support vector machine algorithm, and neural network.
In some embodiments of the first aspect of the present application, the SRAM bitcell parameter set comprises at least one of the following parameter types: one or more of process corner parameters, threshold voltage parameters, transistor size parameters.
In some embodiments of the first aspect of the present application, the performance indicators in the performance indicator set include: one or more of read static noise capacity, read speed, read power consumption, write static noise capacity, write speed, write power consumption.
To achieve the above and other related objects, a second aspect of the present application provides an apparatus for optimally designing an SRAM bit cell based on machine learning, comprising: and a data acquisition module: an SRAM bit cell parameter set for collecting process nodes; inputting the SRAM bit cell parameter set into simulation software for simulation to generate a performance index set; model building module: the parameter prediction model is constructed through the performance index set and the SRAM bit cell parameter set based on a machine learning algorithm; and (3) an automatic design module: and the method is used for inputting the expected performance set of the SRAM bit cell to be designed into the parameter prediction model to generate an optimized parameter set for obtaining the SRAM bit cell to be designed.
To achieve the above and other related objects, a third aspect of the present application provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method of optimizing design of a machine learning based SRAM bitcell.
To achieve the above and other related objects, a fourth aspect of the present application provides an electronic terminal, including: a processor and a memory; the memory is used for storing a computer program, and the processor is used for executing the computer program stored in the memory, so that the terminal executes the optimized design method of the SRAM bit cell based on machine learning.
As described above, the present application relates to a method, an apparatus, a medium, and a terminal for optimizing design of an SRAM bit cell based on machine learning in the field of chip design, which has the following beneficial effects: the invention improves the reliability and consistency of the SRAM bit cell storage design, reduces the design time and labor cost, accelerates the development process of the SRAM bit cell, improves the design performance and the product competitiveness, and can carry out personalized customization on the bit cell of the SRAM according to the requirement of a user.
Drawings
FIG. 1 is a flow chart of an embodiment of a method for optimizing design of an SRAM bit cell based on machine learning.
FIG. 2 is a schematic flow chart of simulation performance data collection in an embodiment of the method for optimizing design of SRAM bit cells based on machine learning.
FIG. 3 is a flow chart of a model training process in one embodiment of the machine learning based SRAM bitcell optimization design method of the present application.
FIG. 4 is a schematic diagram of an embodiment of an apparatus for optimizing design of SRAM bit cells based on machine learning.
FIG. 5 is a schematic diagram of an embodiment of an electronic terminal for optimizing design of SRAM bitcells based on machine learning.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It is noted that in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present application. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present application is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Spatially relative terms, such as "upper," "lower," "left," "right," "lower," "upper," and the like, may be used herein to facilitate a description of one element or feature as illustrated in the figures as being related to another element or feature.
In this application, unless specifically stated and limited otherwise, the terms "mounted," "connected," "secured," "held," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" specify the presence of stated features, operations, elements, components, items, categories, and/or groups, but do not preclude the presence, presence or addition of one or more other features, operations, elements, components, items, categories, and/or groups. The terms "or" and/or "as used herein are to be construed as inclusive, or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; A. b and C). An exception to this definition will occur only when a combination of elements, functions or operations are in some way inherently mutually exclusive.
In order to solve the problems in the background art, the invention provides a method for solving the problems of complexity, low flexibility, incapability of meeting personalized requirements of users, large manual tuning deviation and low efficiency in the process of designing an SRAM bit cell in the prior art. Meanwhile, in order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be further described in detail by the following examples with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Before explaining the present invention in further detail, terms and terminology involved in the embodiments of the present invention will be explained, and the terms and terminology involved in the embodiments of the present invention are applicable to the following explanation:
<1> sram (static random access memory): a Static Random-Access Memory (SRAM) is one type of Random Access Memory. By "static", it is meant that such memory is constantly maintained for data stored therein as long as it remains powered on. When the power supply is stopped, the data stored in the SRAM is lost (referred to as a volatile memory).
<2> sram circuit composition: a Static Random-Access Memory (SRAM) is one type of Random Access Memory. By "static", it is meant that such memory is constantly maintained for data stored therein as long as it remains powered on. When the power supply is stopped, the data stored in the SRAM is lost (referred to as a volatile memory).
<3> sram memory cell: the memory cells of an SRAM are typically composed of 6 transistors, of which 4 are transfer gates for storing data and the other 2 are pass gates for controlling read and write operations. The transfer gate consists of two complementary MOSFETs (metal oxide semiconductor field effect transistors) connected to two nodes of the memory cell, respectively. The gate consists of two MOSFETs, one for the read operation and one for the write operation.
<4> bit cell: in a computer, a bit cell is the smallest unit of storage for storing the value of one binary bit (0 or 1).
<5> process corner: in semiconductor fabrication, process corner refers to the angle or edge between different regions or levels on a chip.
<6> tube threshold voltage: in a semiconductor device, the tub threshold voltage refers to a voltage threshold that controls the turning on or off of a tub.
<7> read/write static noise margin: in memory, read/write static noise margin refers to the degree of noise or interference that a memory cell can tolerate when reading or writing data.
<8>k value neighbor algorithm: the k-value neighbor algorithm is a machine learning algorithm for classification and regression that predicts or classifies by computing the distance between samples and selecting k nearest neighbors.
The embodiment of the invention provides an optimization design method of an SRAM bit cell based on machine learning, a system of the optimization design method of the SRAM bit cell based on machine learning and a storage medium for storing an executable program for realizing the optimization design method of the SRAM bit cell based on machine learning. With respect to implementation of the method for optimizing design of the SRAM bit cell based on machine learning, an exemplary implementation scenario of the optimizing design of the SRAM bit cell based on machine learning will be described.
Referring to FIG. 1, a flow chart of a method for optimizing design of an SRAM bit cell based on machine learning in an embodiment of the present invention is shown. The method for optimally designing the SRAM bit cell based on machine learning in the embodiment mainly comprises the following steps:
step S11: an SRAM bitcell parameter set of a process node is collected.
In an embodiment of the present invention, the parameter types included in the SRAM bit cell parameter set include: one or more of process corner parameters, threshold voltage parameters, transistor size parameters. Specifically, SRAM bitcells of a particular process node are collected and multiple sets of sizes are provided for MOSFET transistors in a ground drive transistor (PU), a load transistor (PG), a pass transistor (SP) therein. The invention does not limit the number of the acquired MOSFET sizes.
In one embodiment of the present invention, the threshold voltage parameters of the SRAM bitcells of the particular process node are collected from historical data. It should be noted that setting different threshold voltages in SRAM cells affects the reliability and power consumption of the memory. Higher threshold voltages may improve reliability of the memory and reduce bit flipping and bit error rate in the memory. However, higher threshold voltages also increase the power consumption of the memory. Lower threshold voltages may reduce power consumption of the memory, but may reduce reliability of the memory.
In one embodiment of the present invention, the SRAM bitcell parameter set includes a plurality of process corners, including but not limited to: SS process corner, TT process corner, FF process corner, SF process corner, and FS process corner.
Step S12: and inputting the SRAM bit cell parameter set into simulation software for simulation to generate a performance index set.
In one embodiment of the present invention, inputting the SRAM bitcell parameter set into simulation software for simulation to generate a performance index set includes: and arranging and combining the multiple types of parameters contained in the SRAM bit unit parameter set, and inputting each combination into simulation software for simulation so as to generate the performance index set formed by the performance indexes of the multiple combinations.
Further, the performance indexes in the performance index set include: one or more of read static noise capacity, read speed, read power consumption, write static noise capacity, write speed, write power consumption.
In an embodiment of the present invention, as shown in fig. 2, the collected process corner parameters, threshold voltage parameters, and transistor size parameters are arranged and combined to generate a plurality of parameter sets, and the parameter sets are input into simulation software for simulation to obtain a performance value index set.
Step S13: based on a machine learning algorithm, constructing a parameter prediction model through the performance index set and the SRAM bit cell parameter set
In one embodiment of the present invention, based on a machine learning algorithm, constructing a parameter prediction model from the set of performance indicators and the set of SRAM bitcell parameters includes: dividing the performance index set and the SRAM bit cell parameter set into a training set and a testing set; inputting the training set into the parameter prediction model to perform model training; the test set is input into the trained predictive model to evaluate performance of the predictive model.
Further, inputting the training set into the parameter prediction model for model training, including: inputting the performance index set in the training set into the parameter prediction model to generate a predicted SRAM bit cell parameter set; constructing a loss function based on a predicted SRAM bit cell parameter set and an SRAM bit cell parameter set corresponding to a performance index set in the training set; and training and optimizing the parameter prediction model based on the loss function. Wherein the machine learning algorithm includes, but is not limited to: k-nearest neighbor algorithms, decision tree algorithms, regression algorithms, support vector machine algorithms, neural networks, and the like.
As shown in fig. 3, an embodiment of the present invention is shown, after training data is collected, the data is divided into a training set and a test set, a model is constructed, a model with a good clustering effect and capable of freely adjusting weights is selected according to the training process, and after training for multiple iterations by using the training set, the numerical value of each coefficient in the model is determined. After the trained model is obtained, the test data is input into the prediction model, and the prediction size parameter is input. And comparing the predicted size parameter with the actual size parameter to obtain the accuracy of the prediction model.
When the K-means clustering algorithm is adopted, K pieces of sample data closest to the predicted sample distance are firstly obtained from the performance index set in the training set, statistics is carried out according to SRAM bit cell parameters corresponding to the obtained K pieces of sample data, and the SRAM bit cell parameter with the largest quantity of the corresponding SRAM bit cell parameter types is used as a prediction result of the current predicted performance index sample.
Step S14: and inputting the expected performance set of the SRAM bit cell to be designed into the parameter prediction model to output and obtain the optimized parameter set of the SRAM bit cell to be designed.
In one embodiment of the present invention, the expected performance parameters of the SRAM with design are obtained according to the user's requirements, wherein the expected performance parameters include, but are not limited to: one or more of read static noise capacity, read speed, read power consumption, write static noise capacity, write speed, write power consumption. And inputting the expected performance parameters into the parameter prediction model to output and obtain an optimized parameter set of the SRAM bit cell to be designed. And manually selecting the obtained optimized parameter set to reserve the optimized parameter set which can meet the layout design specification.
Referring to FIG. 4, a schematic diagram of an apparatus for optimizing design of SRAM bitcells based on machine learning is shown in an embodiment of the present invention. In this embodiment, the apparatus 400 for optimally designing an SRAM bit cell based on machine learning includes:
the data acquisition module 401: an SRAM bit cell parameter set for collecting process nodes; and inputting the SRAM bit cell parameter set into simulation software for simulation to generate a performance index set.
Model creation module 402: the parameter prediction model is constructed through the performance index set and the SRAM bit cell parameter set based on a machine learning algorithm.
Automatic design module 403: and the method is used for inputting the expected performance set of the SRAM bit cell to be designed into the parameter prediction model to generate an optimized parameter set for obtaining the SRAM bit cell to be designed.
In one embodiment of the present invention, based on a machine learning algorithm, constructing a parameter prediction model from the set of performance indicators and the set of SRAM bitcell parameters includes: dividing the performance index set and the SRAM bit cell parameter set into a training set and a testing set; inputting the training set into the parameter prediction model to perform model training; the test set is input into the trained predictive model to evaluate performance of the predictive model.
In one embodiment of the present invention, inputting the SRAM bitcell parameter set into simulation software for simulation to generate a performance index set includes: and arranging and combining the multiple types of parameters contained in the SRAM bit unit parameter set, and inputting each combination into simulation software for simulation so as to generate the performance index set formed by the performance indexes of the multiple combinations.
In an embodiment of the present invention, the parameter types included in the SRAM bit cell parameter set include: one or more of process corner parameters, threshold voltage parameters, transistor size parameters.
In an embodiment of the present invention, the performance indexes in the performance index set include: one or more of read static noise capacity, read speed, read power consumption, write static noise capacity, write speed, write power consumption.
It should be noted that: in the optimization design device for the SRAM bit cell based on machine learning provided in the above embodiment, only the division of each program module is used for illustration when the optimization design for the SRAM bit cell based on machine learning is performed, and in practical application, the process allocation may be performed by different program modules according to needs, that is, the internal structure of the device is divided into different program modules, so as to complete all or part of the processes described above. In addition, the device for optimizing the design of the SRAM bit cell based on machine learning provided in the above embodiment and the method embodiment for optimizing the design of the SRAM bit cell based on machine learning belong to the same concept, and detailed implementation processes of the device are shown in the method embodiment, and are not repeated here.
Referring to fig. 5, an optional hardware structure diagram of an SRAM bit cell optimization design terminal 500 based on machine learning according to an embodiment of the present invention may be shown, where the terminal 500 may be a mobile phone, a computer device, a tablet device, a personal digital processing device, a factory background processing device, etc. The machine learning based optimization design terminal 500 of the SRAM bit cell includes: at least one processor 501, memory 502, at least one network interface 504, and a user interface 506. The various components in the device are coupled together by a bus system 505. It is understood that bus system 505 is used to enable connected communications between these components. The bus system 505 includes a power bus, a control bus, and a status signal bus in addition to a data bus. But for clarity of illustration the various buses are labeled as bus systems in fig. 5.
The user interface 506 may include, among other things, a display, keyboard, mouse, trackball, click gun, keys, buttons, touch pad, or touch screen, etc.
It is to be appreciated that memory 502 can be either volatile memory or nonvolatile memory, and can include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read Only Memory (ROM), a programmable Read Only Memory (PROM, programmable Read-Only Memory), which serves as an external cache, among others. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM, static Random Access Memory), synchronous static random access memory (SSRAM, synchronous Static Random Access Memory). The memory described by embodiments of the present invention is intended to comprise, without being limited to, these and any other suitable types of memory.
The memory 502 in embodiments of the present invention is used to store various types of data to support the operation of the machine learning based optimization design terminal 500 for SRAM bitcells. Examples of such data include: any executable program for operating on the machine learning based SRAM bit cell optimization design terminal 500, such as an operating system 5021 and application 5022; the operating system 5021 contains various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 5022 may include various application programs such as a Media Player (Media Player), a Browser (Browser), and the like for implementing various application services. The method for optimizing the design of the SRAM bit cell based on the machine learning provided by the embodiment of the invention can be contained in the application 5022.
The method disclosed in the above embodiment of the present invention may be applied to the processor 501 or implemented by the processor 501. The processor 501 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuitry in hardware or instructions in software in the processor 501. The processor 501 may be a general purpose processor, a digital signal processor (DSP, digital Signal Processor), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The processor 501 may implement or perform the methods, steps and logic blocks disclosed in embodiments of the present invention. The general purpose processor 501 may be a microprocessor or any conventional processor or the like. The steps of the accessory optimization method provided by the embodiment of the invention can be directly embodied as the execution completion of the hardware decoding processor or the execution completion of the hardware and software module combination execution in the decoding processor. The software modules may be located in a storage medium having memory and a processor reading information from the memory and performing the steps of the method in combination with hardware.
In an exemplary embodiment, the machine-learning-based SRAM bitcell optimization design terminal 500 may be implemented by one or more application specific integrated circuits (ASICs, application Specific Integrated Circuit), DSPs, programmable logic devices (PLDs, programmable Logic Device), complex programmable logic devices (CPLDs, complex Programmable Logic Device) for performing the machine-learning-based SRAM bitcell optimization design methods described above.
Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the method embodiments described above may be performed by computer program related hardware. The aforementioned computer program may be stored in a computer readable storage medium. The program, when executed, performs steps including the method embodiments described above; and the aforementioned storage medium includes: various media that can store program code, such as ROM, RAM, magnetic or optical disks.
In the embodiments provided herein, the computer-readable storage medium may include read-only memory, random-access memory, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, U-disk, removable hard disk, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. In addition, any connection is properly termed a computer-readable medium. For example, if the instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. It should be understood, however, that computer-readable and data storage media do not include connections, carrier waves, signals, or other transitory media, but are intended to be directed to non-transitory, tangible storage media. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.
In summary, the present application provides an optimization design method, device, terminal and medium for SRAM bit cells based on machine learning. The invention provides a brand new dimension design method of the SRAM bit cell, reduces the possibility of errors in the artificial parameter adjustment process through an automatic process, improves the reliability and consistency of the design, and provides a high-efficiency and accurate design tool for the design of the SRAM bit cell, thereby greatly reducing the time cost, the labor cost and the economic cost of the design, accelerating the development process of the SRAM bit cell and improving the flexibility of the design of the SRAM bit cell. Therefore, the method effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles of the present application and their effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those of ordinary skill in the art without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications and variations which may be accomplished by persons skilled in the art without departing from the spirit and technical spirit of the disclosure be covered by the claims of this application.
Claims (10)
1. An optimization design method of an SRAM bit cell based on machine learning is characterized by comprising the following steps:
collecting an SRAM bit cell parameter set of a process node;
inputting the SRAM bit cell parameter set into simulation software for simulation to generate a performance index set;
based on a machine learning algorithm, constructing a parameter prediction model through the performance index set and the SRAM bit cell parameter set;
and inputting the expected performance set of the SRAM bit cell to be designed into the parameter prediction model to output and obtain the optimized parameter set of the SRAM bit cell to be designed.
2. The method for optimizing design of an SRAM bit cell based on machine learning according to claim 1, wherein constructing a parameter prediction model from the performance index set and the SRAM bit cell parameter set based on a machine learning algorithm comprises:
dividing the performance index set and the SRAM bit cell parameter set into a training set and a testing set;
inputting the training set into the parameter prediction model to perform model training;
the test set is input into the trained predictive model to evaluate performance of the predictive model.
3. The machine learning based method of optimizing design of SRAM bitcells of claim 2, wherein inputting the training set into the parametric prediction model for model training comprises:
inputting the performance index set in the training set into the parameter prediction model to generate a predicted SRAM bit cell parameter set;
constructing a loss function based on a predicted SRAM bit cell parameter set and an SRAM bit cell parameter set corresponding to a performance index set in the training set;
and training and optimizing the parameter prediction model based on the loss function.
4. The method for optimizing design of an SRAM bitcell based on machine learning of claim 1, wherein inputting the SRAM bitcell parameter set into simulation software for simulation to generate the performance index set comprises:
and arranging and combining the multiple types of parameters contained in the SRAM bit unit parameter set, and inputting each combination into simulation software for simulation so as to generate the performance index set formed by the performance indexes of the multiple combinations.
5. The method for optimizing design of a SRAM bitcell based on machine learning of claim 1, wherein the machine learning algorithm comprises: k-nearest neighbor algorithm, decision tree algorithm, regression algorithm, support vector machine algorithm, and neural network.
6. The method of optimizing design of a machine learning based SRAM bitcell of claim 1, wherein the SRAM bitcell parameter set comprises at least one of the following parameters: process corner parameters, threshold voltage parameters, transistor size parameters.
7. The method for optimizing design of a SRAM bitcell based on machine learning of claim 1, wherein the performance metrics in the performance metrics set comprise: one or more of read static noise capacity, read speed, read power consumption, write static noise capacity, write speed, write power consumption.
8. An apparatus for optimizing design of an SRAM bitcell based on machine learning, comprising:
and a data acquisition module: an SRAM bit cell parameter set for collecting process nodes; inputting the SRAM bit cell parameter set into simulation software for simulation to generate a performance index set;
and a model building module: the parameter prediction model is constructed through the performance index set and the SRAM bit cell parameter set based on a machine learning algorithm;
and (3) an automatic design module: and the method is used for inputting the expected performance set of the SRAM bit cell to be designed into the parameter prediction model to generate an optimized parameter set for obtaining the SRAM bit cell to be designed.
9. A computer readable storage medium having stored thereon a computer program, which when executed by a processor implements the method for optimizing design of a SRAM bitcell based on machine learning of any one of claims 1 to 7.
10. An electronic terminal, comprising: a processor and a memory;
the memory is used for storing a computer program;
the processor is configured to execute the computer program stored in the memory, so that the terminal executes the method for optimizing design of the SRAM bit cell based on machine learning according to any one of claims 1 to 7.
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