CN117479545A - Preparation process of low-contact-resistance capacitor - Google Patents

Abstract

The invention discloses a preparation process of low contact resistance and capacitance, which relates to the field of high-temperature state storages, and comprises the steps of arranging a liner layer on a falling pad; correspondingly arranging a base material on the lining layer of the falling pad; disposing a first stacked layer on an outer sidewall of a substrate; a spacer material is deposited in the gaps formed between the respective substrates and the substrates are removed. By applying the SADP dual self-alignment pattern technology and adjusting the laying sequence of the capacitor stacking materials, the problem of unstable etching of cell openings is avoided, and the problem of influence on the electrical property due to overlarge resistivity of a barrier layer at the bottom of the capacitor is also solved.

Description

Preparation process of low-contact-resistance capacitor

Technical Field

The invention relates to the field of high-temperature state storages, in particular to a low-contact resistance and capacitance preparation process.

Background

The High steady-state memory is a novel memory which uses High-K ferroelectric material as capacitance medium based on logic chip and realizes memory function by using the polarity of ferroelectric material, wherein the capacitance structure adopts an embedded mode, and a ferroelectric capacitor is embedded in a top winding layer. The embedded capacitor needs to etch deep holes on the dielectric layer at first, in order to avoid photoresist residues in the holes, a general hole opening mode is dry etching without mask, but the thin film in the Cell holes is thinned although the etching speed is slower during dry etching. Particularly, at the edge of the hole, the etching speed is far higher than that in the hole, so that the residual quantity in the hole is difficult to control, and after the hole is formed, a barrier layer metal is generally used for isolating a lower electrode and an M5 capacitor part in order to prevent the problem of parasitic capacitance between wires possibly caused by wire metal diffusion during metal interconnection, and the electrical property of the capacitor is influenced due to the fact that the resistivity of the barrier layer metal is too high;

therefore, the capacitor preparation process is designed to avoid the problem of residual quantity caused by different etching rates in the cell orifice and the cell, and avoid the too high resistivity of the barrier layer.

Disclosure of Invention

This section is intended to summarize some aspects of embodiments of the invention and to briefly introduce some preferred embodiments, which may be simplified or omitted from the present section and description abstract and title of the application to avoid obscuring the objects of this section, description abstract and title, and which is not intended to limit the scope of this invention.

In view of the foregoing and/or the dry etching existing in the prior art, the thin film in the Cell hole is thinned although the etching rate is slow. Particularly, at the edge of the hole, the etching speed is far greater than that in the hole, so that the residual quantity in the hole is difficult to control, and after the hole is formed, a barrier layer metal is generally used for isolating a lower electrode and an M5 capacitor part in order to prevent the problem of parasitic capacitance between wires possibly caused by wiring metal diffusion, and the problem that the electrical property of the capacitor is influenced due to the fact that the resistivity of the barrier layer metal is too high is generally solved.

Therefore, the technical problem to be solved by the invention is to design a capacitor preparation process capable of avoiding the residual quantity problem caused by different etching rates in a cell orifice and a cell and also capable of avoiding the too high resistivity of a barrier layer.

In order to solve the technical problems, the invention provides the following technical scheme: a low contact resistance capacitor preparation process comprises arranging a liner layer on a landing pad;

correspondingly arranging a base material on the lining layer of the falling pad;

disposing a first stacked layer on an outer sidewall of the substrate;

depositing a spacer material in the gap formed between the respective substrates and cleaning the substrates.

As a preferable scheme of the preparation process of the low contact resistance capacitor, the invention comprises the following steps: the surface area of the landing pad is divided into a punching area and a spacing area, and the punching area and the spacing area are arranged next to each other.

As a preferable scheme of the preparation process of the low contact resistance capacitor, the invention comprises the following steps: and depositing a lining material on the landing pad, paving photoresist in the punching area, and etching to form the lining layer.

As a preferable scheme of the preparation process of the low contact resistance capacitor, the invention comprises the following steps: depositing a dielectric material to cover the landing pad and the liner layer;

and paving the photoresist above the dielectric material of the punching area, and etching the dielectric material to be parallel to the liner layer to form the substrate.

As a preferable scheme of the preparation process of the low contact resistance capacitor, the invention comprises the following steps: sequentially depositing a lower electrode material and a barrier material on the substrate;

dry etching the bottom electrode material and the barrier material of the substrate top and the spacer, leaving the bottom electrode material and the barrier material of the substrate sidewall, generating the first stacked layer;

the first stacked layer includes a barrier layer and a lower electrode layer.

As a preferable scheme of the preparation process of the low contact resistance capacitor, the invention comprises the following steps: depositing the spacer material so that it covers the substrate and the first stacked layer, polishing the spacer material to the top of the substrate.

As a preferable scheme of the preparation process of the low contact resistance capacitor, the invention comprises the following steps: and paving the photoresist above the dielectric material of the spacer region, and etching the substrate to the top of the liner layer to form a cell hole.

As a preferable scheme of the preparation process of the low contact resistance capacitor, the invention comprises the following steps: sequentially depositing a High-K material, an upper electrode material and a plate line material to cover the cell holes and the spacer material;

and paving the photoresist on the top of the area where the cell hole is positioned, and sequentially performing plate line upper electrode etching and High-K material etching to generate a second stacked layer, wherein the second stacked layer comprises a High-K layer, an upper electrode layer and a plate line layer.

As a preferable scheme of the preparation process of the low contact resistance capacitor, the invention comprises the following steps: the ratio of the depth to the width of the cell hole is greater than 10:1.

As a preferable scheme of the preparation process of the low contact resistance capacitor, the invention comprises the following steps: the gasket material comprises titanium nitride with the thickness of 10-15 nm;

the dielectric material comprises silicon oxide and silicon nitride, wherein the thickness of the silicon oxide is 1000-1500 nm, and the thickness of the silicon nitride is 30-50 nm;

the lower electrode material is titanium nitride with the thickness of 10-15 nm;

the barrier material comprises tantalum nitride with the thickness of 10-15 nm;

the spacer material is silicon oxide with the thickness of 1500-2000 nm;

the High-K material comprises zirconium oxide or hafnium oxide with the thickness of 6-10 nm;

the upper electrode material is titanium nitride with the thickness of 10-15 nm;

the plate wire material is titanium and has a thickness of 300nm.

As a preferable scheme of the preparation process of the low contact resistance capacitor, the invention comprises the following steps:

the lining material is deposited by PVD physical vapor deposition;

the lower electrode material and the barrier material are deposited by ALD atomic layer deposition;

the dielectric material deposition mode is PVD physical vapor deposition or CVD chemical vapor deposition;

the deposition mode of the spacer material is CVD chemical vapor deposition;

the High-K material deposition mode is ALD atomic layer deposition;

the upper electrode deposition mode is ALD atomic layer deposition.

The invention has the beneficial effects that: by applying the SADP dual self-alignment pattern technology and adjusting the laying sequence of the capacitor stacking materials, the problem of unstable etching of cell openings is avoided, and the problem of influence on the electrical property due to overlarge resistivity of a barrier layer at the bottom of the capacitor is also solved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:

FIG. 1 is a schematic view of a low contact resistance and capacitance manufacturing process according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a pad preparation preliminary process of a low contact resistance capacitor preparation process according to an embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating a process for etching a liner material in a low contact resistance capacitor manufacturing process according to an embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating a deposition state of a dielectric material in a low contact resistance capacitor manufacturing process according to an embodiment of the present invention;

FIG. 5 is a schematic diagram illustrating an etching state of a dielectric material in a low contact resistance and capacitance manufacturing process according to an embodiment of the present invention;

FIG. 6 is a schematic diagram illustrating a deposition state of a bottom electrode material of a low contact resistance capacitor manufacturing process according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a lower electrode material etching state of a low contact resistance capacitor manufacturing process according to an embodiment of the present invention;

FIG. 8 is a schematic diagram illustrating a deposition state of a barrier layer in a low contact resistance capacitor manufacturing process according to an embodiment of the present invention;

FIG. 9 is a schematic diagram illustrating an etching state of a barrier layer in a low contact resistance and capacitance manufacturing process according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of another embodiment of a low contact resistance and capacitance process for preparing a bottom electrode material and a barrier material according to one embodiment of the present invention;

FIG. 11 is a schematic diagram illustrating a first stacked layer after etching according to an embodiment of the invention;

FIG. 12 is a schematic diagram illustrating a substrate removal state of a low contact resistance capacitor manufacturing process according to an embodiment of the present invention;

FIG. 13 is a schematic view showing a deposition state of a High-K material in a low contact resistance-capacitance manufacturing process according to an embodiment of the present invention;

FIG. 14 is a schematic diagram showing a deposition state of an upper electrode material in a low contact resistance capacitor manufacturing process according to an embodiment of the present invention;

FIG. 15 is a schematic view showing a deposition state of a plate wire material in a low contact resistance capacitor manufacturing process according to an embodiment of the present invention;

FIG. 16 is a schematic illustration of an on-board electrode etch for a low contact resistance capacitance process according to an embodiment of the present invention;

fig. 17 is a schematic diagram illustrating a capacitive state forming process of a low contact resistance capacitor according to an embodiment of the present invention.

Detailed Description

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present invention is not limited to the specific embodiments disclosed below.

In the following detailed description of the embodiments of the present invention, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration only, and in which is shown by way of illustration only, and in which the scope of the invention is not limited for ease of illustration. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

Further still, reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.

Example 1

Referring to fig. 1, the present embodiment provides a low-contact-resistance-capacitance manufacturing process, which includes disposing a liner layer 200 on a landing pad 100, wherein the landing pad 100 is a fifth layer of a capacitor metal, abbreviated as an M5 landing pad, and the liner layer 200 corresponds to a bottom capacitor contact portion of a barrier film layer in the prior art, and the thickness of the liner layer can be adjusted to achieve a barrier effect, and the electrical property of the capacitor is not affected by excessive resistivity due to excessive thickness, and it can be understood that the barrier portion which is originally deposited once is deposited twice;

further, the substrate 300 is correspondingly disposed on the liner layer 200 of the landing pad 100, so that the formation of the substrate 300 includes a large-area deposition dielectric layer covering the whole capacitor metal material, and subsequent etching work, the finally formed substrate 300 corresponds to the subsequent cell hole area, and the substrate 300 serves as a prefabricated part, and the technology is an SADP dual self-aligned pattern technology, which performs inverse etching on the cell holes, and does not etch the cell holes, but etches the interval areas between the cell holes, thereby ensuring that the formation of the cell holes is stable and precise;

further, a first stacked layer 400 is disposed on the outer sidewall of the substrate 300, the first stacked layer 400 is equivalent to a barrier layer and a lower electrode layer in a cell hole in the prior art, and the two film layers are also main parts for determining the resistivity of the capacitor, so that in order to solve the problem that the electrical property of the capacitor is affected by the resistance, the first stacked layer 400 completes the second deposition of the barrier film, the deposition of the lower electrode film and the subsequent etching work on the basis of the SADP dual self-aligned pattern technology, and finally forms a protective metal film layer stably attached to the surface of the sidewall of the substrate 300, and meanwhile, the protective metal film layer exists as a part of the capacitor, thereby ensuring the preparation of the subsequent cell hole and the precision of the resistivity of the bottom;

further, a spacer material is deposited in the gap formed between the substrates 300, the spacer material is a dielectric material, which is equivalent to a dielectric portion between the capacitors formed later, and is also a main component of the capacitor array except the capacitor body, and the determination of the spacer material also includes deposition and etching, so that after forming, the substrates 300 can be removed, and the substrates 300 prefabricated as cell holes are converted into cell holes which are not affected by different dry etching rates in the orifice holes under the protection of the first stacked layer 400.

Example 2

Referring to fig. 1 to 2, a second embodiment of the present invention is based on the previous embodiment, and is different from the previous embodiment in that: the surface area of the landing pad 100 is divided into a perforated area 101 and a spacer area 102, where the perforated area 101 is understood to be an area that will exist after the cell hole, and the spacer area 102 is an area outside the cell hole, where the perforated area 101 and the spacer area 102 are disposed next to each other, forming an entire capacitor array, i.e. a cross section of the wafer.

Example 3

Referring to fig. 1 to 3, a third embodiment of the present invention is based on the previous embodiment, and is different from the previous embodiment in that: the pad 100 is deposited with a spacer material, i.e., the spacer material 200 is deposited as a film prior to etching, and after deposition, the spacer material is removed from the spacer 102 by photolithography and etching, thereby forming the spacer 200.

Example 4

Referring to fig. 1 to 5, a fourth embodiment of the present invention is based on the previous embodiment, and is different from the previous embodiment in that: depositing a dielectric material, similar to the spacer material, which is present as a dielectric substance but which is one more layer of silicon nitride than the spacer material, as a protection for the cell aperture and the entire pre-wafer, so as to cover the landing pad 100 and the liner layer 200;

a yellow light etching process is performed on the dielectric material in the hole punching area 101, a photoresist L and a hard mask are laid in the hole punching area 101, and then plasma dry etching is used to dry-etch the dielectric material to be parallel to the liner layer 200, so as to form a substrate 300, namely the SADP dual self-aligned pattern technology, which is not directly dry-etched on the cells, but dry-etched on the cell hole spacing area, so as to ensure the stable etching of the cell hole opening.

Example 5

Referring to fig. 1 to 10, a fifth embodiment of the present invention is based on the previous embodiment, and is different from the previous embodiment in that: sequentially depositing a lower electrode material and a barrier material on the substrate 300, wherein the lower electrode material is a metal film layer for generating a lower electrode, and the barrier material is the same, so that after etching at a certain position, the lower electrode material and the barrier material form a barrier layer 401 and a lower electrode layer 402;

after the deposition of the bottom electrode material and the barrier material is completed, dry etching the bottom electrode material and the barrier material on the top of the substrate 300 and the spacer 102, and reserving the bottom electrode material and the barrier material on the side wall of the substrate 300, wherein the dry etching has anisotropy, etching in a specific direction can be performed by means of directional ion impact to form a vertical profile, and plasma etching is adopted to dry etch only from top to bottom but not from the side, so that after the material etching of a horizontal plane is completed, the material on the side wall is reserved, and the side wall material reserved on the substrate 300 and the liner layer 200 at the bottom are added to generate a first stacked layer 400;

the first stacked layer 400 includes a barrier layer 401, a liner layer 200, and a bottom electrode layer 402, wherein the liner layer 200 and the barrier layer 401 on both sidewalls of the substrate 300 form a complete capacitive barrier portion, and the bottom electrode layer 402 becomes a capacitive portion next to the substrate 300 and also serves as a cell hole second layer capacitive structure prior to removing the substrate 300.

In detail, there are two ways to prepare the lower electrode material and the barrier material in this order:

(1) sequentially depositing a lower electrode material and a barrier material, sequentially etching, and performing deposition and etching twice to finish the generation of the first stacked layer 400;

(2) depositing a lower electrode material, performing lower electrode etching, depositing a barrier material, performing barrier etching, and completing the generation of the first stacked layer 400

The two are not different in result, only the preparation sequence can be used for uniform deposition and uniform etching, and the etching can be performed once and twice in a circulating way.

Example 6

Referring to fig. 1 to 12, a sixth embodiment of the present invention is based on the previous embodiment, and is different from the previous embodiment in that: after depositing the spacer material so as to cover the substrate 300 and the first stack 400, and completely cover the entire pre-formed capacitor portion, the dielectric material is polished to the top of the substrate 300 using special techniques to complete the preparation of the wafer surface.

Example 7

Referring to fig. 1 to 12, a seventh embodiment of the present invention is based on the previous embodiment, and is different from the previous embodiment in that: the photoresist L is laid over the dielectric material of the spacer 102, and the substrate 300 is etched to the top of the liner layer 200, and since the entire capacitor holes are protected by the bottom electrode layer, the dry etching reaction gas used is a gas containing fluorine or is a gas containing fluorine when the dielectric material in the holes is removed, and only the dielectric material in the holes is reacted in this environment, but the bottom electrode metal film layer is not reacted, so that the dielectric material in the holes is not reacted after etching is completed, and if the dielectric material is to be reacted with the bottom electrode layer, the reaction gas must use a gas containing chlorine. In addition, when the dielectric material reacts, organic matters are attached to the side wall for protection, when the reaction is completed, the ashing process is performed to remove the organic matters, and finally the substrate 300 is completely removed under the wrapping of the lower electrode layer, and the formed holes are cell holes.

Example 8

Referring to fig. 1 to 17, an eighth embodiment of the present invention is based on the previous embodiment, and is different from the previous embodiment in that: sequentially depositing a High-K material, an upper electrode material and a plate wire material to cover the cell holes and the spacer material, wherein the step is that the conventional process is normally carried out, and the High-K material generally selects a material with High dielectric constant and ferroelectric polarity as a dielectric layer in the capacitor so as to maintain High conductivity and form an upper electrode layer and a plate wire connecting each capacitor after etching;

further, a photoresist L is paved on the top of the area where the cell hole is located, and electrode etching and High-K material etching on the plate line are sequentially carried out. The plate line upper electrode is etched uniformly, and the plate line and the upper electrode can be etched uniformly because the plate line and the upper electrode are metal film layers, the metal film layers are generally etched dry, the used precursors are chlorine or chlorine-containing gas, the properties of the High-K material are close to that of silicide, boron trifluoride or fluorine-containing gas is required to be adopted for dry etching, and the plate line and the upper electrode can be etched uniformly, but the High-K material is required to be independently etched by other gases.

In detail, after etching the three materials, a second stacked layer 500 is formed, in which a High-K material is etched separately to form a High-K layer 501, and is used as a capacitor core, and an upper electrode material and a plate line are etched simultaneously to form an upper electrode layer 502 and a plate line layer 503 respectively, so that the whole capacitor is approximately prepared, and the preparation of the memory chip part can be completed only by polishing and cleaning in a later period.

Example 9

Referring to fig. 1 to 12, a ninth embodiment of the present invention is based on the previous embodiment, and is different from the previous embodiment in that: the ratio of the depth to the width of the cell hole S is greater than 10:1, and the conventional mask photoetching and dry etching scheme is adopted because the depth-to-width ratio of the cell hole S is very high, photoresist residues in the hole cannot be removed cleanly, and therefore risks of poor film adhesion, product pollution and the like can be caused. Therefore, only a maskless scheme can be used for directly carrying out dry etching to remove the surface electrode material;

the maskless scheme is mainly based on the load effect (the number of reactive gas molecules in unit area is the same, and the deep hole is equal to the etching area, so the etching speed in the deep hole is far smaller than the etching speed of the wafer surface at the same position) in the plasma etching process;

the residual quantity at the edge of each cell hole is difficult to control, so that a certain difference exists in the area of each cell electrode plate, and the electrical property is unstable, according to a capacitance formula C=epsilon A/d, (epsilon is a dielectric capacitance constant and is determined by a material, A represents the area of parallel plates, d represents the distance between the parallel plates, namely the thickness of the dielectric, the upper electrode plate and the lower electrode plate are A in the formula), and the area of the electrode plate, namely A in the formula, is reduced because the surface of a wafer is excessively etched, and the film layer of the side wall near the opening is also removed.

Example 10

Referring to fig. 1 to 15, a tenth embodiment of the present invention is based on the previous embodiment, and is different from the previous embodiment in that: the gasket material is titanium nitride with the thickness of 10-15 nm;

the dielectric material comprises silicon oxide and silicon nitride, the thickness of the silicon oxide is 1000-1500 nm, and the thickness of the silicon nitride is 30-50 nm;

the lower electrode material is titanium nitride with the thickness of 10-15 nm, and the material and the lining material are consistent to form a complete lower electrode;

the barrier material is tantalum nitride with the thickness of 10-15 nm;

the spacing material is silicon oxide with the thickness of 1500-2000 nm, and the only difference is that the top of the dielectric material is additionally provided with a layer of silicon nitride film as a stop layer, but the barrier material is not provided;

the High-K material comprises zirconium oxide or hafnium oxide, and the thickness of silicide with High dielectric constant is 6-10 nm;

the upper electrode material is titanium nitride, the composition is the same as that of the lower electrode, and the thickness of the electrode part used as the capacitor is 10-15 nm;

the material component of the plate wire is titanium, the thickness is 300nm, and the plate wire and the upper electrode are both made of metallic titanium or titanium-containing metal, so that the plate wire and the upper electrode can be simultaneously removed by chlorine-containing gas dry etching.

Example 11

Referring to fig. 1 to 15, an eleventh embodiment of the present invention is based on the previous embodiment, and is different from the previous embodiment in that: the deposition mode of the lining material and the plate wire material is PVD physical vapor deposition, namely, after the surface of the source material is gasified or ionized under vacuum condition, the material is deposited on the surface of a base body below through low-pressure gas formation, and is generally used for depositing a metal film, so the titanium film of the lining material and the plate wire material adopts the technology;

the lower electrode material and the barrier material are deposited in an ALD atomic layer deposition mode, wherein the ALD atomic layer deposition is a method capable of plating substances on the surface of a substrate layer by layer in a single atomic film mode and is used for some metals which can have special molecular reactions;

the dielectric material deposition mode is CVD chemical vapor deposition, wherein the CVD chemical vapor deposition is a process of generating solid sediment by utilizing gaseous or vapor substances to react on a gas phase or gas-solid interface, and generally, the reaction is generated in a CVD generating device through heating and gas inlet and outlet, so that the dielectric material deposition method is only suitable for some nonmetal;

the deposition mode of the spacer material is CVD chemical vapor deposition, and silicide is nonmetal, so a CVD chemical vapor liner is used;

the High-K material and the upper electrode material are used as metal thin films with active molecular reaction, and the deposition mode is ALD atomic layer deposition.

It is important to note that the construction and arrangement of the present application as shown in a variety of different exemplary embodiments is illustrative only. Although only a few embodiments have been described in detail in this disclosure, those skilled in the art who review this disclosure will readily appreciate that many modifications are possible (e.g., variations in sizes, dimensions, structures, shapes and proportions of the various elements, values of parameters (e.g., temperature, pressure, etc.), mounting arrangements, use of materials, colors, orientations, etc.) without materially departing from the novel teachings and advantages of the subject matter described in this application. For example, elements shown as integrally formed may be constructed of multiple parts or elements, the position of elements may be reversed or otherwise varied, and the nature or number of discrete elements or positions may be altered or varied. Accordingly, all such modifications are intended to be included within the scope of present invention. The order or sequence of any process or method steps may be varied or re-sequenced according to alternative embodiments. In the claims, any means-plus-function clause is intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Other substitutions, modifications, changes and omissions may be made in the design, operating conditions and arrangement of the exemplary embodiments without departing from the scope of the present inventions. Therefore, the invention is not limited to the specific embodiments, but extends to various modifications that nevertheless fall within the scope of the appended claims.

Furthermore, in an effort to provide a concise description of the exemplary embodiments, all features of an actual implementation may not be described (i.e., those not associated with the best mode presently contemplated for carrying out the invention, or those not associated with practicing the invention).

It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions may be made. Such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

It should be noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present invention may be modified or substituted without departing from the spirit and scope of the technical solution of the present invention, which is intended to be covered in the scope of the claims of the present invention.

Claims (11)

1. A preparation process of a low contact resistance capacitor is characterized by comprising the following steps: comprising the steps of (a) a step of,

a cushion layer (200) is arranged on the falling pad (100);

a base material (300) is correspondingly arranged on the lining layer (200) of the falling pad (100);

providing a first stack (400) on an outer sidewall of the substrate (300);

depositing a spacer material in the gaps formed between the respective substrates (300) and cleaning the substrates (300).

2. The process for preparing the low contact resistance capacitor according to claim 1, wherein the process comprises the following steps: the surface area of the landing pad (100) is divided into a punching area (101) and a spacing area (102), and the punching area (101) and the spacing area (102) are arranged next to each other.

3. The process for preparing the low contact resistance capacitor according to claim 2, wherein: and depositing a lining material on the landing pad (100), paving photoresist (L) in the punching area (101), and etching to form the lining layer (200).

4. A process for preparing a low contact resistance capacitor according to claim 3, wherein: depositing a dielectric material to cover the landing pad (100) and the liner layer (200);

-laying the photoresist (L) over the dielectric material of the perforated area (101), -etching the dielectric material parallel to the liner layer (200), forming the substrate (300).

5. The process for preparing the low contact resistance capacitor according to claim 4, wherein: sequentially depositing a lower electrode material and a barrier material on the substrate (300);

-dry etching the bottom electrode material and the barrier material of the top of the substrate (300) and of the spacers (102), leaving the bottom electrode material and the barrier material of the sidewalls of the substrate (300), creating the first stacked layer (400);

the first stacked layer (400) includes a barrier layer (401) and a lower electrode layer (402).

6. The process for preparing the low contact resistance capacitor according to claim 5, wherein: depositing the spacer material so that it covers the substrate (300) and the first stack layer (400), polishing the spacer material to the top of the substrate (300).

7. A process for preparing a low contact resistance capacitor according to claim 5 or 6, wherein: and paving the photoresist (L) on the dielectric material of the interval region (102), and etching the substrate (300) to the top of the liner layer (200) to form a cell hole.

8. The process for preparing the low contact resistance capacitor according to claim 7, wherein: sequentially depositing a High-K material, an upper electrode material and a plate line material to cover the cell holes and the spacer material;

and paving the photoresist (L) on the top of the area where the cell hole is positioned, and sequentially performing plate line upper electrode etching and High-K material etching to generate a second stacked layer (500), wherein the second stacked layer (500) comprises a High-K layer (501), an upper electrode layer (502) and a plate line layer (503).

9. The process for preparing the low contact resistance capacitor according to claim 7, wherein: the ratio of the depth to the width of the cell hole is greater than 10:1.

10. The process for preparing the low contact resistance capacitor according to claim 8, wherein: the gasket material comprises titanium nitride with the thickness of 10-15 nm;

the dielectric material comprises silicon oxide and silicon nitride, wherein the thickness of the silicon oxide is 1000-1500 nm, and the thickness of the silicon nitride is 30-50 nm;

the lower electrode material is titanium nitride with the thickness of 10-15 nm;

the barrier material comprises tantalum nitride with the thickness of 10-15 nm;

the spacer material is silicon oxide with the thickness of 1500-2000 nm;

the High-K material comprises zirconium oxide or hafnium oxide with the thickness of 6-10 nm;

the upper electrode material is titanium nitride with the thickness of 10-15 nm;

the plate wire material is titanium and has a thickness of 300nm.

11. The process for preparing the low contact resistance capacitor according to claim 8, wherein:

the deposition mode of the lining material is PVD physical vapor deposition;

the deposition mode of the lower electrode material and the barrier material is ALD atomic layer deposition;

the dielectric material is deposited by CVD chemical vapor deposition;

the deposition mode of the spacer material is CVD chemical vapor deposition;

High-K material and upper electrode material, the deposition mode is ALD atomic layer deposition.