CN117476549B - Method for manufacturing semiconductor laminated structure and semiconductor structure - Google Patents
Method for manufacturing semiconductor laminated structure and semiconductor structure Download PDFInfo
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- CN117476549B CN117476549B CN202311789157.2A CN202311789157A CN117476549B CN 117476549 B CN117476549 B CN 117476549B CN 202311789157 A CN202311789157 A CN 202311789157A CN 117476549 B CN117476549 B CN 117476549B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 238000000034 method Methods 0.000 title claims abstract description 70
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 59
- 229910052751 metal Inorganic materials 0.000 claims abstract description 303
- 239000002184 metal Substances 0.000 claims abstract description 303
- 238000002955 isolation Methods 0.000 claims abstract description 101
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 238000005530 etching Methods 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 45
- 229920002120 photoresistant polymer Polymers 0.000 claims description 45
- 238000004140 cleaning Methods 0.000 claims description 17
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 238000005137 deposition process Methods 0.000 claims description 10
- 238000009413 insulation Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 239000007789 gas Substances 0.000 claims description 7
- 229910052742 iron Inorganic materials 0.000 claims description 7
- 229910052715 tantalum Inorganic materials 0.000 claims description 7
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 238000012546 transfer Methods 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 263
- 238000011161 development Methods 0.000 description 15
- 239000000126 substance Substances 0.000 description 10
- 230000003667 anti-reflective effect Effects 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- 238000011160 research Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000012827 research and development Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- KXLUWEYBZBGJRZ-POEOZHCLSA-N Canin Chemical compound O([C@H]12)[C@]1([C@](CC[C@H]1C(=C)C(=O)O[C@@H]11)(C)O)[C@@H]1[C@@]1(C)[C@@H]2O1 KXLUWEYBZBGJRZ-POEOZHCLSA-N 0.000 description 1
- GPFVKTQSZOQXLY-UHFFFAOYSA-N Chrysartemin A Natural products CC1(O)C2OC2C34OC3(C)CC5C(CC14)OC(=O)C5=C GPFVKTQSZOQXLY-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical compound [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Element Separation (AREA)
Abstract
The present disclosure relates to a method for manufacturing a semiconductor laminated structure and a semiconductor structure, the method includes providing a substrate, forming a first metal structure extending along a first direction and isolation structures located at two opposite sides of the first metal structure along a second direction on a top surface of the substrate, wherein a sacrificial oxide layer located at an outer side wall of the first metal structure is included between the first metal structure and the isolation structures; removing part of the isolation structure and the sacrificial oxide layer to form a target groove exposing part of the opposite side surfaces of the first metal structure along the second direction; forming an insulating layer on at least the exposed surface of the first metal structure; forming a second metal structure at least filling up the target groove and extending along a second direction; in other states than the first state, there is at least one interconnection state between the second metal structure and the first metal structure. The damage of the first metal structure can be avoided, and the problem of bad chip technology is reduced.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a method for manufacturing a semiconductor stacked structure and a semiconductor structure.
Background
With the development of the semiconductor manufacturing field, there is a higher demand for a chip manufacturing process. In the process of manufacturing, various chips with special structures are manufactured according to actual needs, and a special chip structure is currently formed by alternately stacking two metal layers.
In the manufacturing process of the special chip, two metal layers are deposited to form a laminated structure, except for a preset cross-stacked metal layer structure, other metal layers are arranged everywhere, and the two metal layers are positioned on the same plane, so that when the etching process is performed on the second metal structure, the first metal layer is easy to damage, the etching operation of the second metal layer needs to be accurately controlled to avoid the first metal layer damage, but the actual operation difficulty of the process is high, and challenges are presented to the manufacturing of the special chip.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method for manufacturing a semiconductor stacked structure and a semiconductor structure, which are capable of at least effectively avoiding damage to a first metal structure during etching a second metal structure, and avoiding problems occurring in an operating state due to a special chip based on the stacked structure.
To achieve the above and other related objects, an aspect of the present disclosure provides a method for manufacturing a semiconductor stacked structure, including:
Providing a substrate, forming a first metal structure extending along a first direction and isolation structures positioned on two opposite sides of the first metal structure along a second direction on the top surface of the substrate, wherein a sacrificial oxide layer positioned on the outer side wall of the first metal structure is arranged between the first metal structure and the isolation structures, and the first direction is intersected with the second direction;
removing part of the isolation structure and the sacrificial oxide layer to form a target groove exposing part of the opposite side surfaces of the first metal structure along the second direction;
forming an insulating layer on at least the exposed surface of the first metal structure;
forming a second metal structure at least filling up the target groove and extending along a second direction; wherein, the second metal structure is insulated from the first metal structure through the insulating layer in the first state; in other states than the first state, there is at least one interconnection state between the second metal structure and the first metal structure.
In the method for manufacturing a semiconductor stacked structure in the above embodiment, a first metal structure extending along a first direction and isolation structures located on two opposite sides of the first metal structure along a second direction are formed on a top surface of the substrate by providing the substrate, a sacrificial oxide layer located on an outer sidewall of the first metal structure is included between the first metal structure and the isolation structures, and the first direction intersects with the second direction to prepare for forming a second metal structure subsequently; forming a target groove exposing a part of opposite side surfaces of the first metal structure along the second direction by removing a part of the isolation structure and the sacrificial oxide layer; forming an insulating layer on at least the exposed surface of the first metal structure, and insulating the first metal structure from the second metal structure by using the insulating layer; preparing a semiconductor laminated structure by forming a second metal structure which at least fills the target groove and extends along a second direction; wherein, the second metal structure is insulated from the first metal structure through the insulating layer in the first state; in other states than the first state, there is at least one interconnection state between the second metal structure and the first metal structure. In the related manufacturing process of the laminated structure, besides the preset cross-stacked metal layer structure, other metal layers are arranged everywhere, and the two layers of metal are positioned on the same plane, so that when the etching process is performed on the second metal structure, the first metal structure is easy to damage, and further the chip based on the structure is problematic in the working state, and in order to avoid the damage of the first metal structure, the etching operation of the second metal structure needs to be accurately controlled, but the actual operation difficulty of the process is high. According to the manufacturing method of the semiconductor laminated structure, the first metal structure extending along the first direction is formed on the top surface of the substrate, the target groove exposing the opposite side surfaces of the part of the first metal structure along the second direction is formed, and then the second metal structure at least filled with the target groove and extending along the second direction is formed, so that the manufacturing of the semiconductor laminated structure is completed, wherein insulation is carried out between the second metal structure and the first metal structure through the insulation layer in the first state, at least one interconnection state is formed between the second metal structure and the first metal structure in other states different from the first state, the formation of a preset cross structure is ensured, the first metal structure is prevented from being damaged in the etching process of the second metal structure, the problem occurring in the working state of a special chip based on the laminated structure is reduced, meanwhile, the circuit module design of the special chip production process can be obtained, the foundation of basic processes and methods is provided for future development, production, research, cooperation and the like, and the reference standard of practical processes is provided for the subsequent more deep and complex special chip production processes.
In some embodiments, forming an insulating layer at least on the exposed surface of the first metal structure includes:
forming an insulating layer with a preset thickness on the exposed surface of the first metal structure under the conditions of a preset constant temperature and a preset gas atmosphere and within a preset time; wherein the preset constant temperature is 20-30 ℃; the content ratio of nitrogen to oxygen in the preset gas atmosphere is 10-20; the preset time is 8min-18 min; the predetermined thickness is 15 angstroms to 25 angstroms.
In some embodiments, the target recess includes a first recess and a second recess of equal size, the first recess and the second recess exposing a portion of opposite side surfaces of the first metal structure in the second direction, respectively; forming the target recess includes:
controlling etching depth by controlling etching rate and etching time of the dry etching isolation structure to form a first initial groove and a second initial groove which are respectively positioned on two opposite sides of the first metal structure along the second direction, wherein the first initial groove and the second initial groove respectively expose part of sacrificial oxide layers on the surfaces of the opposite sides of the first metal structure along the second direction;
and wet cleaning and removing the sacrificial oxide layers in the first initial groove and the second initial groove to obtain the first groove and the second groove.
In some embodiments, an isolation layer is included between the first metal structure and the substrate; forming a first metal structure and an isolation structure on the top surface of the substrate, including:
forming a first metal layer on the top surface of the isolation layer;
patterning the first metal layer to obtain first metal structures distributed at intervals along the second direction;
forming a sacrificial oxide layer on the exposed surface of the first metal structure;
forming an isolation material layer which fills the gap between the adjacent first metal structures and has a top surface higher than that of the sacrificial oxide layer;
and taking the top surface of the first metal structure as a stop layer, flattening the top surfaces of the isolation material layer and the sacrificial oxide layer, and forming the isolation structure by the residual isolation material layer.
In some embodiments, the isolation layer includes an alignment pattern thereon; forming a first initial groove and a second initial groove, comprising:
forming a first anti-reflection layer on the top surface of the first metal layer;
forming a first patterned photoresist layer on the top surface of the first anti-reflection layer based on the alignment pattern, wherein the first patterned photoresist layer comprises an opening pattern for defining a first initial groove and a second initial groove;
etching the first anti-reflection layer and the isolation structure by taking the first graphical photoresist layer as a mask plate to obtain a first initial groove and a second initial groove;
Forming the first recess and the second recess includes:
and wet cleaning and removing the residual first patterned photoresist layer, the residual first anti-reflection layer and the sacrificial oxide layers in the first initial groove and the second initial groove to obtain the target groove.
In some embodiments, forming a layer of isolation material over a first metal structure includes:
forming an isolation material layer by adopting a deposition process;
forming a sacrificial oxide layer on the exposed surface of the first metal structure, including:
during transfer of the substrate to a deposition chamber for depositing the layer of isolation material, a sacrificial oxide layer is formed at ambient temperature and pressure on the exposed surface of the first metal structure.
In some embodiments, forming the second metal structure further comprises:
forming a second metal layer which fills the target groove and has a top surface higher than the top surface of the insulating layer;
forming a second anti-reflection layer on the top surface of the second metal layer;
forming a second patterned photoresist layer on the top surface of the second anti-reflection layer based on the alignment pattern, wherein the second patterned photoresist layer comprises an opening pattern for defining a second metal structure;
etching the second anti-reflection layer, the second metal layer and the insulating layer by taking the isolation structure which is flush with the top surface of the first metal structure as a stop layer and taking the second graphical photoresist layer as a mask plate to obtain a second metal structure;
And removing the remaining second patterned photoresist layer and the remaining second anti-reflection layer.
In some embodiments, the isolation layer is different from the isolation structure; the target groove comprises a first groove and a second groove with equal sizes, and the first groove and the second groove respectively expose part of side surfaces of the first metal structure, which are opposite along the second direction; forming the target recess includes:
taking the isolation layer as a stop layer, and performing dry etching on the isolation structure according to a preset etching rate and a preset etching total amount to form a first initial groove and a second initial groove which are respectively positioned on two opposite sides of the first metal structure along the second direction, wherein the first initial groove and the second initial groove respectively expose part of sacrificial oxide layers on the surfaces of the opposite sides of the first metal structure along the second direction;
and wet cleaning and removing the sacrificial oxide layers in the first initial groove and the second initial groove to obtain the first groove and the second groove.
In some embodiments, the material of the first metal structure comprises titanium, tantalum, aluminum, iron, copper-based material, or a combination thereof; and/or the material of the second metal structure comprises titanium, tantalum, aluminum, iron, copper-based material, or a combination thereof.
In some embodiments, another aspect of the present disclosure provides a semiconductor structure prepared using the method of manufacturing a semiconductor stacked structure of any one of the above.
The unexpected technical effects that the present disclosure can produce are: by forming the first metal structure on the top surface of the substrate and carrying out planarization treatment on part of the isolation structure and the sacrificial oxide layer, the height difference between the first metal layer and the second metal layer is reduced, the first metal structure is prevented from being damaged when the second metal layer is etched, then the second metal structure is formed, the preparation of the semiconductor laminated structure is completed, the problems occurring under the working state of a special chip based on the semiconductor structure are reduced, meanwhile, the circuit module design of the special chip production process can be obtained, the foundation of basic processes and methods is provided for future development, production, research and development, cooperation and the like, and the referent standard of the actual process is provided for the subsequent deeper and complex special chip production process.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic top view of a semiconductor stacked structure according to an embodiment of the disclosure;
fig. 2 is a schematic cross-sectional view of a semiconductor stacked structure according to an embodiment of the disclosure;
fig. 3 is a flow chart illustrating a method for manufacturing a semiconductor stacked structure according to an embodiment of the disclosure;
fig. 4 is a schematic cross-sectional view of a semiconductor stacked structure provided in an embodiment of the present disclosure before forming a first metal layer;
fig. 5 is a schematic cross-sectional view of a structure obtained after forming a first metal layer in a method for manufacturing a semiconductor stacked structure according to an embodiment of the disclosure;
fig. 6 is a schematic cross-sectional view of a first metal structure formed in a method for manufacturing a semiconductor stacked structure according to an embodiment of the disclosure;
FIG. 7 is a schematic cross-sectional view of a semiconductor stacked structure according to an embodiment of the present disclosure after forming an isolation structure;
fig. 8 is a schematic cross-sectional view of a structure obtained after performing a planarization process on an isolation material layer in a method for manufacturing a semiconductor stacked structure according to an embodiment of the disclosure.
FIG. 9a is a schematic cross-sectional view of a semiconductor stacked structure according to an embodiment of the present disclosure after forming a first anti-reflective layer and a first patterned photoresist layer
FIG. 9b is a schematic top view of a semiconductor stacked structure according to an embodiment of the present disclosure after forming a first anti-reflective layer and a first patterned photoresist layer;
fig. 10 is a schematic cross-sectional view of a semiconductor stacked structure according to an embodiment of the present disclosure after forming a first initial recess and a second initial recess;
FIG. 11 is a schematic cross-sectional view of a semiconductor stacked structure according to an embodiment of the present disclosure after forming a target recess;
fig. 12 is a schematic cross-sectional view of a structure obtained after forming an insulating layer on at least an exposed surface of a first metal structure in a method for fabricating a semiconductor stacked structure according to an embodiment of the disclosure;
FIG. 13 is a schematic cross-sectional view of a semiconductor stacked structure according to an embodiment of the present disclosure after sequentially forming a second metal layer, a second anti-reflection layer and a second patterned photoresist layer;
fig. 14a is a schematic cross-sectional view of a semiconductor stacked structure according to an embodiment of the disclosure after forming a second metal structure;
fig. 14b is a schematic top view of a second metal structure formed in a method for manufacturing a semiconductor stacked structure according to an embodiment of the disclosure;
Fig. 15 is a schematic cross-sectional view illustrating a metal oxide layer formed on a semiconductor structure according to an embodiment of the disclosure.
Reference numerals illustrate:
10/10', substrate; 20. an isolation layer; 21. a layer of isolation material; 211. an isolation structure; 220. an anti-reflection layer; 221. a first anti-reflection layer; 222. a second anti-reflection layer; 231/231', a first patterned photoresist layer; 232. a second patterned photoresist layer; 24. a target groove; 24a, a first groove; 24b, a second groove; 241. a first initial groove; 242. a second initial groove; 30. A first metal layer; 31. a first metal structure; 32. a sacrificial oxide layer; 321. a metal oxide layer; 33. an insulating layer; 34. an isolation dielectric layer; 40. a second metal layer; 41. a second metal structure.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing, the regions illustrated in the figures being schematic in nature, and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.
In the manufacturing process of a special chip, two metal layers are required to be deposited to form a crisscross laminated structure, except for a preset cross laminated metal layer structure, other metal layers are arranged everywhere, and the two metal layers are positioned on the same plane, so that the first metal layer is easy to damage when the etching process is performed on the second metal layer, the etching operation of the second metal layer is required to be accurately controlled to avoid the damage of the first metal layer, but the actual operation difficulty of the process is high, and the manufacturing of the special chip is challenged.
As an example, referring to fig. 1-2, a related method for manufacturing a semiconductor stacked structure generally includes the following steps:
step S201: providing a substrate 10', forming an isolation layer 20 on the substrate 10', and forming first metal structures 31 extending along a first direction (for example, the OX direction) and distributed at intervals along a second direction (for example, the OY direction) on the isolation layer 20;
step S202: forming a groove (not shown) extending in a first direction, the groove exposing a portion of a side surface of the first metal structure 31 opposite in a second direction (e.g., OY direction), the first direction intersecting the second direction;
step S203: the second metal structure 41 is formed based on the grooves.
Specifically, referring to fig. 1-2, in step S203, the second metal structure 41 is formed, and the second metal structure 41 and the first metal structure 31 are insulated from each other by the isolation medium layer 34, except for the preset cross stacked structure, the metal layers of the rest of the structures are on the same plane, which results in easy damage to the first metal structure 31 when the etching process of the second metal structure 41 is performed, and in order to avoid the damage to the first metal structure 31, the etching operation of the second metal structure 41 needs to be precisely controlled, but the actual operation difficulty of the process is high.
The first direction may be an OX direction, and the second direction may be an OY direction.
Based on this, the embodiment of the disclosure provides a manufacturing method of a semiconductor laminated structure, which can at least effectively avoid damage to a first metal structure when etching a second metal structure, and avoid problems of a special chip based on the laminated structure in a working state.
In some embodiments, referring to fig. 3, in some embodiments of the present disclosure, a method for manufacturing a semiconductor stacked structure is provided, including the following steps:
step S42: providing a substrate, forming a first metal structure extending along a first direction and isolation structures positioned on two opposite sides of the first metal structure along a second direction on the top surface of the substrate, wherein a sacrificial oxide layer positioned on the outer side wall of the first metal structure is arranged between the first metal structure and the isolation structures, and the first direction is intersected with the second direction;
Step S44: removing part of the isolation structure and the sacrificial oxide layer to form a target groove exposing part of the opposite side surfaces of the first metal structure along the second direction;
step S46: forming an insulating layer on at least the exposed surface of the first metal structure;
step S48: forming a second metal structure at least filling up the target groove and extending along a second direction; wherein, the second metal structure is insulated from the first metal structure through the insulating layer in the first state; in other states than the first state, there is at least one interconnection state between the second metal structure and the first metal structure.
In some embodiments, please continue with reference to fig. 3, by providing a substrate, forming a first metal structure extending along a first direction and isolation structures located on opposite sides of the first metal structure along a second direction on a top surface of the substrate, wherein a sacrificial oxide layer located on an outer sidewall of the first metal structure is included between the first metal structure and the isolation structures, and the first direction intersects the second direction in preparation for forming a second metal structure subsequently; forming a target groove exposing a part of opposite side surfaces of the first metal structure along the second direction by removing a part of the isolation structure and the sacrificial oxide layer; forming an insulating layer on at least the exposed surface of the first metal structure, and insulating the first metal structure from the second metal structure by using the insulating layer; preparing a semiconductor laminated structure by forming a second metal structure which at least fills the target groove and extends along a second direction; wherein, the second metal structure is insulated from the first metal structure through the insulating layer in the first state; in other states than the first state, there is at least one interconnection state between the second metal structure and the first metal structure. In the related manufacturing process of the laminated structure, besides the preset cross-stacked metal layer structure, other metal layers are arranged everywhere, and the two layers of metal are positioned on the same plane, so that when the etching process is performed on the second metal structure, the first metal structure is easy to damage, and further the chip based on the structure is problematic in the working state, and in order to avoid the damage of the first metal structure, the etching operation of the second metal structure needs to be accurately controlled, but the actual operation difficulty of the process is high. According to the manufacturing method of the semiconductor laminated structure, the first metal structure extending along the first direction is formed on the top surface of the substrate, the target groove exposing the opposite side surfaces of the part of the first metal structure along the second direction is formed, and then the second metal structure at least filled with the target groove and extending along the second direction is formed, so that the manufacturing of the semiconductor laminated structure is completed, wherein insulation is carried out between the second metal structure and the first metal structure through the insulation layer in the first state, at least one interconnection state is formed between the second metal structure and the first metal structure in other states different from the first state, the formation of a preset cross structure is ensured, the first metal structure is prevented from being damaged in the etching process of the second metal structure, the problem occurring in the working state of a special chip based on the laminated structure is reduced, meanwhile, the circuit module design of the special chip production process can be obtained, the foundation of basic processes and methods is provided for future development, production, research, cooperation and the like, and the reference standard of practical processes is provided for the subsequent more deep and complex special chip production processes.
Specifically, the first state includes a normal temperature and pressure state, i.e., at 25 ℃ and 1.01325Pa, the first metal structure is insulated from the second metal structure via an insulating layer; in other states than the first state, at least one interconnection state is provided between the first metal structure and the second metal structure, for example, in a critical state, the interconnection state between the first metal structure and the second metal structure is in the middle of conduction and insulation; for another example, in the conductive state, the first metal structure and the second metal structure are conductive, and the conductive state may include a plurality of conductive states with different conductive resistances.
In some embodiments, referring to fig. 4, the substrate 10 provided in step S42 may be formed of a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate 10 may have a single-layer structure or a multilayer structure. For example, the substrate 10 may be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Alternatively, and also for example, the substrate 10 may be a layered substrate comprising a material such as Si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. The type of substrate 10 should not limit the scope of the present disclosure. The substrate 10 may include other electric elements and the like, and is omitted because it is not so much related to the present invention.
Referring to fig. 3-5, in some embodiments, after the substrate 10 is provided in step S42, an isolation layer 20 may be formed on the top surface of the substrate 10, the isolation layer 20 may include an oxide layer, and an alignment for a subsequent photolithography process may be formed in the isolation layer 20 to improve the alignment accuracy of the photolithography process.
With continued reference to fig. 3-5, in some embodiments, forming the first metal structure 31 and the isolation structure 211 on the top surface of the substrate 10 in step S42 includes:
step S421: forming a first metal layer 30 on the top surface of the isolation layer 20;
step S422: patterning the first metal layer 30 to obtain first metal structures 31 distributed at intervals along the second direction;
step S423: forming a sacrificial oxide layer 32 on the exposed surface of the first metal structure 31;
step S424: forming an isolation material layer 21 filling the gaps between the adjacent first metal structures 31 and having a top surface higher than that of the sacrificial oxide layer 32;
step S425: the top surface of the first metal structure 31 is used as a stop layer, the top surfaces of the isolation material layer 21 and the sacrificial oxide layer 32 are planarized, and the remaining isolation material layer 21 is used to form the isolation structure 211.
With continued reference to fig. 3-5, in some embodiments, in step S421, the first metal layer 30 is formed on the top surface of the isolation layer 20, and at least one of an electroplating process, an electroless plating process (chemical plating), a placement process (placement), a printing process, a physical vapor deposition process (physical vapor deposition, PVD), a chemical vapor deposition process (chemical vapor deposition, CVD), an atomic layer deposition process (Atomic Layer Deposition, ALD), a high-density plasma deposition process (High Density Plasma, HDP), a plasma enhanced deposition process (Plasma Enhance Chemical Vapor Desposition, PECVD), and the like may be used.
With continued reference to fig. 5-6, in some embodiments, patterning the first metal layer 30 in step S422 includes forming an anti-reflection layer 220 on a top surface of the first metal layer 30, forming a photoresist layer (not shown) on the anti-reflection layer 220, and performing a series of steps such as exposure, development, etc., to obtain a first patterned photoresist layer 231, where the first patterned photoresist layer 231 has an opening pattern for defining parameters such as a position and a shape of the first metal structure 31. The photoresist layer can be positive photoresist or negative photoresist, and the development mode can be positive development or negative development; the anti-reflection layer 220 and the first metal layer 30 are etched by using the first patterned photoresist layer 231 as a mask, so as to obtain first metal structures 31 distributed at intervals along the second direction.
Referring to fig. 7, in some embodiments, in step S423, a sacrificial oxide layer 32 is formed on the exposed surface of the first metal structure 31, including:
step S4231: during transfer of the substrate 10 to a deposition chamber for depositing the isolation material layer 21, a sacrificial oxide layer 32 is formed at normal temperature and pressure on the exposed surface of the first metal structure 31.
As an example, with continued reference to fig. 7, the normal temperature and pressure state is, for example, 25 ℃ and 1.01325Pa, the isolation layer 20 and the isolation material layer 21 include, but are not limited to, a silicon oxide layer (SiO 2 ) Silicon nitride layer (Si 3 N 4 ) Alumina (Al) 2 O 3 ) Or a silicon oxynitride layer (SiON). The isolation material layer 21 may be formed using a deposition process. To form the sacrificial oxide layer 32 of a desired thickness, one canIn transferring the substrate 10 to the deposition chamber for depositing the isolation material layer 21, the sacrificial oxide layer 32 is formed on the exposed surface of the first metal structure 31 at normal temperature and pressure for 1min to 3min, for example, 1min, 2min, or 3min, etc., and the sacrificial oxide layer 32 is required to be removed in a subsequent process because the sacrificial oxide layer 32 cannot be converted from an insulating state to an on state in a specific state and cannot be used for an insulating material in a specific junction structure.
With continued reference to fig. 7, in some embodiments, forming the isolation material layer 21 on the first metal structure 31 in step S424 includes:
step S4241: forming an isolation material layer 21 by a deposition process;
specifically, the deposition process may include, but is not limited to, one or more of a chemical vapor deposition process (Chemical Vapor Deposition, CVD), an atomic layer deposition process (Atomic Layer Deposition, ALD), a high density plasma deposition process (High Density Plasma, HDP), a plasma enhanced deposition process, and Spin-on Dielectric (SOD), among others.
Referring to fig. 8, in some embodiments, the planarization process in step S425 includes a chemical mechanical polishing process, wherein the top surfaces of the isolation material layer 21 and the sacrificial oxide layer 32 are planarized to expose the top surface of the first metal structure 31 by using an abrasive and a corrosive chemical polishing solution in combination with a polishing pad and a retaining ring. For example, the top surface of the first metal structure 31 is set as a stop layer for performing a chemical mechanical polishing process, and after the sacrificial oxide layer 32 on the upper surface of the first metal structure 31 is removed by setting the time of Over polishing (Over Polish), polishing is stopped, so as to avoid damage to the upper surface of the first metal structure 31 caused by the chemical mechanical polishing process, and the remaining sidewall sacrificial oxide layer 32 with a predetermined thickness can avoid damage to the first metal structure 31 caused by a subsequent etching process.
Referring to fig. 9 a-11, in some embodiments, the target recess 24 includes a first recess 24a and a second recess 24b with equal dimensions, and the first recess 24a and the second recess 24b respectively expose a portion of opposite side surfaces of the first metal structure 31 along the second direction; forming the target recess 24 includes:
step S441: controlling the etching depth by controlling the etching rate and the etching time of the dry etching isolation structure 211 to form a first initial groove 241 and a second initial groove 242 respectively positioned on two opposite sides of the first metal structure 31 along the second direction, wherein the first initial groove 241 and the second initial groove 242 respectively expose part of the sacrificial oxide layer 32 on the opposite side surfaces of the first metal structure 31 along the second direction;
Step S442: the sacrificial oxide layer 32 in the first initial recess 241 and the second initial recess 242 is wet cleaned and removed, resulting in the first recess 24a and the second recess 24b.
Referring to fig. 9a to fig. 10, in some embodiments, in step S441, the etching depth is controlled by controlling the etching rate and the etching time of the dry etching isolation structure 211, so as to form a first initial recess 241 and a second initial recess 242 respectively located on two opposite sides of the first metal structure 31 along the second direction, wherein a portion of the isolation structure 211 is included between the bottom surfaces of the first initial recess 241 and the second initial recess 242 and the top surface of the isolation layer 20, so that the thickness of the second metal structure can be reduced, the height difference between the first metal structure 31 and the second metal layer can be reduced, and damage to the first metal structure 31 during etching the second metal layer can be avoided.
As an example, please continue to refer to fig. 9 a-10, the isolation layer 20 includes an alignment pattern (not shown) thereon; in step S441, a first initial groove 241 and a second initial groove 242 are formed, including:
step S4411: forming a first anti-reflection layer 221 on the top surface of the first metal layer 30;
step S4412: forming a first patterned photoresist layer 231 'on the top surface of the first anti-reflection layer 221 based on the alignment pattern, the first patterned photoresist layer 231' including an opening pattern for defining a first initial recess 241 and a second initial recess 242;
Step S4413: the first patterned photoresist layer 231' is used as a mask to etch the first anti-reflection layer 221 and the isolation structure 211, so as to obtain a first initial groove 241 and a second initial groove 242.
It should be noted that the first groove 24a and the second groove 24b have equal dimensions, including equal length, width and depth, and the difference between the length, width and depth dimensions is within an allowable error range.
Referring to fig. 9a to fig. 10, in some embodiments, the isolation layer 20 and the isolation structure 211 are made of different materials, and the isolation structure 211 may be dry etched according to a predetermined etching rate and a predetermined total etching amount by using the isolation layer 20 as an etching stop layer, so as to form a first initial groove 241 and a second initial groove 242 respectively located on two opposite sides of the first metal structure 31 along the second direction, so as to improve the efficiency and the simplicity of forming the first initial groove 241 and the second initial groove 242.
Referring to fig. 10-11, in some embodiments, forming the first recess 24a and the second recess 24b in step S442 includes:
step S4421: wet cleaning and removing the remaining first patterned photoresist layer 231', the remaining first anti-reflective layer 221, and the sacrificial oxide layer 32 in the first initial recess 241 and the second initial recess 242, to obtain the target recess 24.
As an example, referring to fig. 11, in step S4421, specific chemical liquid and deionized water may be used to perform non-damage cleaning on the surface of the structure, and the wet cleaning mainly includes RCA cleaning, diluted chemical, IMEC cleaning or single wafer cleaning, for example, the single wafer cleaning has a better cleaning effect, and the chemical liquid and deionized water may be recycled during the cleaning process, so as to reduce the consumption of chemicals and improve the wafer cost efficiency.
Referring to fig. 12, in some embodiments, forming the insulating layer 33 on at least the exposed surface of the first metal structure 31 in step S46 includes:
step S461: forming an insulating layer 33 with a preset thickness on the exposed surface of the first metal structure 31 under the conditions of a preset constant temperature and a preset gas atmosphere and for a preset time; wherein the preset constant temperature is 20-30 ℃; the content ratio of nitrogen to oxygen in the preset gas atmosphere is 10-20; the preset time is 8min-18 min; the predetermined thickness is 15 angstroms to 25 angstroms.
As an example, please continue to refer to fig. 12, the nitrogen to oxygen content ratio is set to 10 under the conditions of 20 ℃ -30 ℃, for example, under the conditions of 20 ℃, 22 ℃, 25 ℃, 27 ℃, 28 ℃ or 30 ℃): 1, the oxidation time is set to 8min-12min synchronously, for example, the oxidation time can be 8min, 9min, 10min, 11min or 12min, etc., so as to form the insulating layer 33 with the thickness of 15 angstrom-20 angstrom, for example, the thickness of the insulating layer 33 can be 15 angstrom, 16 angstrom, 17 angstrom, 18 angstrom, 19 angstrom or 20 angstrom, etc.; for another example, the content ratio of nitrogen to oxygen is set to 20:1, the oxidation time is set to be 15min-18min synchronously, for example, the oxidation time may be 15min, 16min, 17min or 18min, etc., to form the insulating layer 33 with a thickness of 20 a-25 a, for example, the insulating layer 33 may be 15 a, 16 a, 17 a, 18 a, 19 a, 20 a, 22 a or 25 a, etc. Since the insulating layer 33 under the special environment can be formed in step S461, a semiconductor stacked structure capable of exhibiting an insulating state, a critical on state, and on states having different on resistances is prepared.
Referring to fig. 13-14 b, in some embodiments, forming the second metal structure 42 in step S48 further includes:
step S481: forming a second metal layer 40 filling up the target recess 24 and having a top surface higher than the top surface of the insulating layer 33;
step S482: forming a second anti-reflection layer 222 on the top surface of the second metal layer 40;
step S483: forming a second patterned photoresist layer 232 on the top surface of the second anti-reflection layer 222 based on the alignment pattern, the second patterned photoresist layer 232 including an opening pattern for defining the second metal structure 41;
step S484: etching the second anti-reflection layer 222, the second metal layer 40 and the insulating layer 33 by using the isolation structure 211 which is flush with the top surface of the first metal structure 31 as a stop layer and the second patterned photoresist layer 232 as a mask plate to obtain a second metal structure 41;
step S485: the remaining second patterned photoresist layer 232 and the remaining second anti-reflective layer 222 are removed.
As an example, in step S484, when the second patterned photoresist layer 232 is used as a mask to etch the second anti-reflective layer 222, the second metal layer 40 and the insulating layer 33, a portion of the isolation structure 211 located on the top surface of the first metal structure 31 may be reserved, so as to avoid the first metal structure 31 from being damaged by etching, and after the etching operation is completed, in the process of removing the remaining second patterned photoresist layer 232 and the remaining second anti-reflective layer 222, the reserved portion of the isolation structure 211 may be removed simultaneously; a wet cleaning solution may also be used alone to remove the remaining portion of isolation structure 211, exposing the top surface of first metal structure 31.
As an example, referring to fig. 13, in step S481, a deposition process may be used to form the second metal layer 40 that fills the target recess 24 and has a top surface higher than the top surface of the insulating layer 33, where the material of the second metal layer 40 includes titanium, tantalum, aluminum, iron, copper-based material, or a combination thereof.
As an example, referring to fig. 13, in step S482, a spin-on dielectric process may be used to form the second anti-reflection layer 222 on the top surface of the second metal layer 40.
As an example, referring to fig. 13, in step S483, a photoresist layer (not shown) may be formed on the second anti-reflection layer 222, and a series of steps such as exposure, development, etc. may be performed to obtain the second patterned photoresist layer 232, where the photoresist may be a positive photoresist or a negative photoresist, and the development may be a positive development or a negative development.
As an example, please continue to refer to fig. 13-14 b, in step S484, the second patterned photoresist layer 232, the second anti-reflection layer 222, the second metal layer 40 and the insulating layer 33 may be etched by dry method, for example, a plasma etching process may be used in dry method, wherein the plasma etching is to activate the reactive gas into active particles, such as source or free radicals, by using a high-frequency glow discharge reaction, and the active particles diffuse to the etched portion to react with the etched material to form volatile product to be removed, thereby achieving the etching purpose.
For example, referring to fig. 14 a-14 b, in step S485, wet etching and cleaning may be used to remove the remaining second patterned photoresist layer 232 and the remaining second anti-reflection layer 222.
In some embodiments, the material of the first metal structure comprises titanium, tantalum, aluminum, iron, copper-based material, or a combination thereof; and/or the material of the second metal structure comprises titanium, tantalum, aluminum, iron, copper-based material, or a combination thereof.
In some embodiments, referring to fig. 14 a-14 b, a semiconductor structure is provided, which is manufactured by the method for manufacturing a semiconductor stacked structure according to any one of the above.
In some embodiments, please continue to refer to fig. 14 a-14 b, the semiconductor structure includes a substrate 10, an isolation layer 20, a first metal structure 31, an isolation structure 211, an insulating layer 33, and a second metal structure 41, the first metal structure 31 extending along the first direction and the isolation structures 211 located on two opposite sides of the first metal structure 31 along the second direction are formed on the top surface of the substrate 10 by the manufacturing method of the semiconductor stacked structure, and the target recess 24 exposing a portion of the opposite side surfaces of the first metal structure 31 along the second direction is formed by removing a portion of the isolation structure 211 and the sacrificial oxide layer 32; forming an insulating layer 33 on at least the exposed surface of the first metal structure 31, and insulating or conducting the first metal structure 31 and the second metal structure 41 by using the insulating layer 33; the preparation of the semiconductor stacked structure is completed by forming a second metal structure 41 filling at least the target recess 24 and extending in the second direction; wherein insulation is provided between the second metal structure 41 and the first metal structure 31 via the insulation layer 33 in the first state; in other states than the first state, there is at least one interconnection state between the second metal structure 41 and the first metal structure 31. In the related semiconductor structure, except for a preset cross stacked metal layer structure, other metal layers are arranged at all positions, two layers of metal are arranged on the same plane, when the related semiconductor laminated structure is prepared, the second layer of conductive structure is subjected to an etching process, so that the first metal structure is easily damaged, further, the chip based on the structure is problematic in the working state, and in order to avoid the damage of the first metal structure, the etching operation of the second metal structure needs to be accurately controlled, but the actual operation difficulty of the process is large. In the semiconductor structure provided in the embodiment of the disclosure, the first metal structure 31 is formed on the top surface of the substrate 10, the planarization treatment is performed on the partial isolation structure 211 and the sacrificial oxide layer 32, and then the second metal structure 41 is formed, so as to complete the preparation of the semiconductor laminated structure, wherein the second metal structure 41 and the first metal structure 31 are insulated by the insulating layer 33 in the first state, and at least one interconnection state is provided between the second metal structure 41 and the first metal structure 31 in other states different from the first state, so that the problems occurring in the working state of a special chip based on the semiconductor structure are reduced, and meanwhile, the circuit module design of the special chip production process can be obtained, thereby providing the basis of basic processes and methods for future development, production, research, development, cooperation and the like, and providing the referent standard of the actual process for the subsequent deeper and complex special chip production process.
In some embodiments, referring to fig. 15, in the natural environment, a metal oxide layer 321 is formed on exposed surfaces of the first metal structure 31 and the second metal structure 41 in the semiconductor structure.
The unexpected technical effects that the present disclosure can produce are: by forming the first metal structure on the top surface of the substrate and carrying out planarization treatment on part of the isolation structure and the sacrificial oxide layer, the height difference between the first metal layer and the second metal layer is reduced, the first metal structure is prevented from being damaged when the second metal layer is etched, then the second metal structure is formed, the preparation of the semiconductor laminated structure is completed, the problems occurring under the working state of a special chip based on the semiconductor structure are reduced, meanwhile, the circuit module design of the special chip production process can be obtained, the foundation of basic processes and methods is provided for future development, production, research and development, cooperation and the like, and the referent standard of the actual process is provided for the subsequent deeper and complex special chip production process.
It should be understood that, although the steps in the flowchart of fig. 3 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, although at least a portion of the steps of FIG. 3 may include multiple steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order in which the steps or stages are performed is not necessarily sequential, and may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or other steps.
Note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
In the description of the present specification, reference to the term "some embodiments," "other embodiments," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present disclosure, which are described in more detail and are not to be construed as limiting the scope of the present disclosure. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the disclosure, which are within the scope of the present application.
Claims (10)
1. A method of manufacturing a semiconductor stacked structure, comprising:
providing a substrate, forming a first metal structure extending along a first direction and isolation structures positioned on two opposite sides of the first metal structure along a second direction on the top surface of the substrate, wherein a sacrificial oxide layer positioned on the outer side wall of the first metal structure is arranged between the first metal structure and the isolation structures, and the first direction is intersected with the second direction;
removing part of the isolation structure and the sacrificial oxide layer to form a target groove exposing part of the opposite side surfaces of the first metal structure along the second direction;
forming an insulating layer on at least the exposed surface of the first metal structure;
forming a second metal structure at least filling the target groove and extending along the second direction; wherein insulation is provided between the second metal structure and the first metal structure via the insulation layer in a first state; in other states different from the first state, at least one interconnection state between conduction and insulation is arranged between the second metal structure and the first metal structure.
2. The method of manufacturing a semiconductor stacked structure according to claim 1, wherein forming an insulating layer at least on an exposed surface of the first metal structure comprises:
Forming the insulating layer with a preset thickness on the exposed surface of the first metal structure under the conditions of a preset constant temperature and a preset gas atmosphere and within a preset time; wherein the preset constant temperature is 20-30 ℃; the content ratio of nitrogen to oxygen in the preset gas atmosphere is 10-20; the preset time is 8-18 min; the predetermined thickness is 15 angstroms to 25 angstroms.
3. The method of manufacturing a semiconductor stacked structure according to claim 2, wherein the target recess includes a first recess and a second recess of equal size, the first recess and the second recess exposing a portion of side surfaces of the first metal structure that are opposite in the second direction, respectively; forming the target recess includes:
controlling etching depth by controlling etching rate and etching time of the isolation structure by dry etching to form a first initial groove and a second initial groove which are respectively positioned on two opposite sides of the first metal structure along the second direction, wherein the first initial groove and the second initial groove respectively expose part of sacrificial oxide layers on the surfaces of the opposite sides of the first metal structure along the second direction;
And wet cleaning and removing the sacrificial oxide layers in the first initial groove and the second initial groove to obtain the first groove and the second groove.
4. The method of manufacturing a semiconductor stacked structure according to claim 3, wherein an isolation layer is included between the first metal structure and the substrate; forming the first metal structure and the isolation structure on the top surface of the substrate, including:
forming a first metal layer on the top surface of the isolation layer;
patterning the first metal layer to obtain the first metal structures which are distributed at intervals along the second direction;
forming a sacrificial oxide layer on the exposed surface of the first metal structure;
forming an isolation material layer which fills gaps between adjacent first metal structures and has a top surface higher than that of the sacrificial oxide layer;
and taking the top surface of the first metal structure as a stop layer, flattening the top surfaces of the isolation material layer and the sacrificial oxide layer, and forming the isolation structure by the rest isolation material layer.
5. The method of manufacturing a semiconductor stacked structure according to claim 4, wherein the spacer includes an alignment pattern thereon; forming the first initial groove and the second initial groove includes:
Forming a first anti-reflection layer on the top surface of the first metal layer;
forming a first patterned photoresist layer on the top surface of the first anti-reflection layer based on the alignment pattern, wherein the first patterned photoresist layer comprises an opening pattern for defining the first initial groove and the second initial groove;
etching the first anti-reflection layer and the isolation structure by taking the first graphical photoresist layer as a mask plate to obtain the first initial groove and the second initial groove;
forming the first recess and the second recess includes:
and wet cleaning and removing the residual first graphical photoresist layer, the residual first anti-reflection layer and the sacrificial oxide layers in the first initial groove and the second initial groove to obtain the target groove.
6. The method of manufacturing a semiconductor stacked structure according to claim 4, wherein forming an isolation material layer over the first metal structure comprises:
forming the isolation material layer by adopting a deposition process;
forming a sacrificial oxide layer on the exposed surface of the first metal structure, including:
during the transfer of the substrate to a deposition chamber for depositing the isolation material layer, the sacrificial oxide layer is formed on the exposed surface of the first metal structure at normal temperature and pressure.
7. The method of manufacturing a semiconductor stacked structure according to claim 5, wherein forming the second metal structure further comprises:
forming a second metal layer which fills the target groove and has a top surface higher than that of the insulating layer;
forming a second anti-reflection layer on the top surface of the second metal layer;
forming a second patterned photoresist layer on the top surface of the second anti-reflection layer based on the alignment pattern, wherein the second patterned photoresist layer comprises an opening pattern for defining the second metal structure;
etching the second anti-reflection layer, the second metal layer and the insulating layer by taking the isolation structure which is flush with the top surface of the first metal structure as a stop layer and the second graphical photoresist layer as a mask plate to obtain the second metal structure;
and removing the remaining second patterned photoresist layer and the remaining second anti-reflection layer.
8. The method for manufacturing a semiconductor stacked structure according to any one of claims 4 to 7, wherein a material of the isolation layer is different from that of the isolation structure; the target groove comprises a first groove and a second groove with equal sizes, and the first groove and the second groove respectively expose part of side surfaces of the first metal structure, which are opposite along the second direction; forming the target recess includes:
Taking the isolation layer as a stop layer, and performing dry etching on the isolation structure according to a preset etching rate and a preset etching total amount to form a first initial groove and a second initial groove which are respectively positioned on two opposite sides of the first metal structure along the second direction, wherein the first initial groove and the second initial groove respectively expose part of sacrificial oxide layers on the opposite side surfaces of the first metal structure along the second direction;
and wet cleaning and removing the sacrificial oxide layers in the first initial groove and the second initial groove to obtain the first groove and the second groove.
9. The method of manufacturing a semiconductor stacked structure according to any one of claims 1 to 7, wherein the material of the first metal structure comprises titanium, tantalum, aluminum, iron, copper-based material, or a combination thereof; and/or
The material of the second metal structure comprises titanium, tantalum, aluminum, iron, copper-based material, or a combination thereof.
10. A semiconductor structure prepared by the method of manufacturing a semiconductor stacked structure according to any one of claims 1 to 9.
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