CN117474059A - Computing circuit - Google Patents
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Abstract
The present application relates to a computing circuit. The system comprises a plurality of computing units of different types, wherein the computing units are arranged in an array, each computing unit comprises a multiplication computing circuit, a precharge circuit and a computing result output circuit, and the computing result output circuits of the computing units of different types are different; the computing result output circuit is used for respectively outputting the voltage of the computing output node through N output channels after receiving the signal input voltage so as to obtain a first computing result obtained by the multiplication computing circuit through N times of coupling of the voltage of the computing output node, wherein the first computing result is obtained by computing according to the signal input voltage and a first neural network weight value, the first neural network weight value is obtained according to an initial neural network weight value and the coupling times N, and the coupling times N corresponding to the computing result output circuit in different types of computing units are different. The calculation circuit reduces power consumption, improves integration level and simultaneously realizes the calculation of the multi-valued neural network.
Description
Technical Field
The present disclosure relates to the field of circuit technologies, and in particular, to a computing circuit.
Background
Compared with a binary weight neural network or a three-value weight neural network, the multi-value weight neural network can use more bit numbers to represent weights and activation values, so that the multi-value weight neural network has better precision.
In the prior art, a multi-value weight neural network is mostly implemented based on Static Random-Access Memory (SRAM).
However, such a multi-value weighted neural network implemented based on SRAM is high in power consumption and low in integration.
Disclosure of Invention
In view of the above, it is necessary to provide a calculation circuit with low power consumption and high integration.
The application provides a calculation circuit, which comprises a plurality of calculation units of different types, wherein the calculation units are arranged in an array, each calculation unit comprises a multiplication calculation circuit, a precharge circuit and a calculation result output circuit, and the calculation result output circuits of the calculation units of different types are different; the multiplication calculating circuit comprises a first ferroelectric transistor and a second ferroelectric transistor which are connected with each other, and the precharge circuit and the calculation result output circuit are electrically connected with a calculation output node between the first ferroelectric transistor and the second ferroelectric transistor; the first ferroelectric transistor and the second ferroelectric transistor are used for entering a target resistance state under the drive of write voltage so as to represent an initial neural network weight value; the precharge circuit is used for adjusting the calculated output node to a target voltage; the first ferroelectric transistor and the second ferroelectric transistor are used for receiving a signal input voltage after the calculation output node is adjusted to the target voltage; the calculation result output circuit is used for respectively outputting the voltage of the calculation output node through N output channels after receiving the signal input voltage so as to obtain a first calculation result calculated by the multiplication calculation circuit through N times of coupling of the voltage of the calculation output node, wherein the first calculation result is calculated according to the signal input voltage and the first neural network weight value, the first neural network weight value is obtained according to the initial neural network weight value and the coupling times N, N is a positive integer, and the coupling times N corresponding to the calculation result output circuit in the calculation units of different types are different.
In one embodiment, the calculation result output circuit includes N sub-output circuits, where each of the sub-output circuits is configured to output the voltage of the calculation output node through a different output path.
In one embodiment, the sub-output circuit comprises a first transistor and a second transistor, the gate of the first transistor and the gate of the second transistor are both connected to the calculation output node, the first pole of the first transistor is connected to a first voltage source, and the first pole of the second transistor is grounded.
In one embodiment, the computing circuit further includes a first bit line RBL, and the second pole of the first transistor and the second pole of the second transistor in each of the sub-output circuits are connected to the first bit line RBL to form an output path.
In one embodiment, the first bit line RBL includes a first sub bit line RBL and a second sub bit line RBL, a second pole of the first transistor is connected to the first sub bit line RBL, a second pole of the second transistor is connected to the second sub bit line RBL, and the first transistor and the second transistor are used for performing a charging operation or a discharging operation on the first sub bit line RBL and the second sub bit line RBL, respectively, under the control of the calculated output node voltage.
In one embodiment, the first sub bit line RBL and the second sub bit line RBL are connected by a computation result processing circuit, the computation result processing circuit includes a first switch, a second switch, a third switch, a fourth switch, a first capacitor and a second capacitor; the calculation result processing circuit is configured to perform an average process on the voltages of the first sub-bit line RBL and the second sub-bit line RBL to obtain calculation results of the plurality of calculation units.
In one embodiment, the output circuit includes a third capacitor, a first end of which is connected to the computing output node.
In one embodiment, the computing circuit further includes a second bit line RBL, and the second end of the third capacitor in each of the sub-output circuits is connected to the second bit line RBL; the third capacitor is used for coupling the voltage of the calculation output node to the second bit line RBL.
In one embodiment, the first ferroelectric transistor and the second ferroelectric transistor are further configured to receive the signal input voltage M times based on M pulses after the precharge circuit adjusts the calculated output node to the target voltage; the calculation result output circuit is used for respectively outputting the voltage of the calculation output node through N output channels after receiving the signal input pulse each time so as to obtain a second calculation result calculated by the multiplication calculation circuit through N times of coupling of the voltage of the calculation output node, wherein the second calculation result is calculated according to the signal input voltage and the second neural network weight value, the second neural network weight value is obtained according to the first neural network weight value and the pulse frequency M, and M is a positive integer.
In one embodiment, a first electrode of the first ferroelectric transistor is connected with a first electrode of the second ferroelectric transistor, a second electrode of the first ferroelectric transistor is a first signal input node, a second electrode of the second ferroelectric transistor is a second signal input node, a gate of the first ferroelectric transistor is a first write voltage driving node, and a gate of the second ferroelectric transistor is a second write voltage driving node; the first signal input node and the second signal input node are used for inputting the signal input voltage; the first write voltage driving node and the second write voltage driving node are used for inputting the write voltage.
In one embodiment, the compute output node is located between the first pole of the first ferroelectric transistor and the first pole of the second ferroelectric transistor.
In one embodiment, the precharge circuit includes a third transistor having a source connected to a second voltage source for outputting the target voltage, a drain connected to the calculation output node, and a gate for receiving a pulse signal to adjust the calculation output node to the target voltage based on the pulse signal.
In one embodiment, the computing circuit further includes a word line WL; the gate of the third transistor in the precharge circuit in each of the calculation units is connected to the WL; the WL is used for outputting the pulse signal to the gate of the third transistor in the precharge circuit in each of the calculation units.
The computing circuit comprises a plurality of computing units of different types, wherein the computing units are arranged in an array, each computing unit comprises a multiplication computing circuit, a precharge circuit and a computing result output circuit, and the computing result output circuits of the computing units of different types are different; the multiplication calculating circuit comprises a first ferroelectric transistor and a second ferroelectric transistor which are connected with each other, and the precharge circuit and the calculation result output circuit are electrically connected with a calculation output node between the first ferroelectric transistor and the second ferroelectric transistor; the first ferroelectric transistor and the second ferroelectric transistor are used for entering a target resistance state under the drive of write voltage so as to represent an initial neural network weight value; the precharge circuit is used for adjusting the calculated output node to a target voltage; the first ferroelectric transistor and the second ferroelectric transistor are used for receiving a signal input voltage after the calculation output node is adjusted to the target voltage; the calculation result output circuit is used for respectively outputting the voltage of the calculation output node through N output channels after receiving the signal input voltage so as to obtain a first calculation result calculated by the multiplication calculation circuit through N times of coupling of the voltage of the calculation output node, wherein the first calculation result is calculated according to the signal input voltage and the first neural network weight value, the first neural network weight value is obtained according to the initial neural network weight value and the coupling times N, N is a positive integer, and the coupling times N corresponding to the calculation result output circuit in the calculation units of different types are different. The calculation circuit provided by the application can be used for calculating the multi-valued neural network, and compared with the calculation circuit in the prior art, fewer components are used in the calculation circuit, so that the circuit power consumption can be effectively reduced and the integration level can be improved by adopting the calculation circuit provided by the application.
Drawings
FIG. 1 is a schematic diagram of a computing circuit in one embodiment;
FIG. 2 is a schematic diagram of I-V characteristics of the first ferroelectric transistor and the second ferroelectric transistor in one embodiment;
FIG. 3 is a timing diagram of a process for writing initial neural network weight values to a computing unit in one embodiment;
FIG. 4 is a timing diagram of the computing unit writing a weight value of 0 according to one embodiment;
FIG. 5 is a timing diagram of the computing unit writing a weight value of 1 according to one embodiment;
FIG. 6 is a timing diagram of the computing unit writing a weight value of-1 according to one embodiment;
FIG. 7 is a schematic diagram of another computing circuit in one embodiment;
FIG. 8 is a schematic diagram of another computing circuit in one embodiment;
FIG. 9 is a schematic diagram of another computing circuit in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
Furthermore, the terms "first," "second," and the like, if any, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the terms "plurality" and "a plurality" if any, mean at least two, such as two, three, etc., unless specifically defined otherwise.
In this application, unless explicitly stated and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly. For example, the two parts can be fixedly connected, detachably connected or integrated; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
In this application, unless expressly stated or limited otherwise, the meaning of a first feature being "on" or "off" a second feature, and the like, is that the first and second features are either in direct contact or in indirect contact through an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
It will be understood that if an element is referred to as being "fixed" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present. If an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like as used herein, if any, are for descriptive purposes only and do not represent a unique embodiment.
Compared with a binary weight neural network or a three-value weight neural network, the multi-value weight neural network can use more bit numbers to represent weights and activation values, so that the multi-value weight neural network has better precision.
In the prior art, a multi-value weight neural network is mostly implemented based on Static Random-Access Memory (SRAM).
However, the power consumption of the multi-value weighted neural network realized based on the SRAM is higher, and the integration level is lower.
In view of this, the present application provides a calculation circuit with low power consumption and high integration level, which can be used to implement calculation of a multivalued neural network.
In one embodiment, as shown in fig. 1, there is provided a calculation circuit including a plurality of calculation units 100 of different types arranged in an array, each of the calculation units 100 including a multiplication calculation circuit 101, a precharge circuit 102, and a calculation result output circuit 103, and the calculation result output circuits 103 of the different types of the calculation units 100 being different; the multiplication circuit 101 includes a first ferroelectric transistor 201 and a second ferroelectric transistor 202 connected to each other, and the precharge circuit 102 and the calculation result output circuit 103 are electrically connected to a calculation output node 203 located between the first ferroelectric transistor 201 and the second ferroelectric transistor 202.
The first ferroelectric transistor 201 and the second ferroelectric transistor 202 are used for entering a target resistive state under the drive of a write voltage to represent an initial neural network weight value.
In an alternative embodiment of the present application, as shown in fig. 1, the first pole of the first ferroelectric transistor 201 is connected to the first pole of the second ferroelectric transistor 202, the second pole of the first ferroelectric transistor 201 is the first signal input node (Vin 1 in fig. 1), the second pole of the second ferroelectric transistor 202 is the second signal input node (Vin 2 in fig. 1), the gate of the first ferroelectric transistor 201 is the first write voltage driving node (Vwrite 1 in fig. 1), and the gate of the second ferroelectric transistor 202 is the second write voltage driving node (Vwrite 2 in fig. 1).
Optionally, the first signal input node and the second signal input node are configured to input the signal input voltage, and the first write voltage driving node and the second write voltage driving node are configured to input the write voltage.
In one possible implementation, as shown in fig. 2, fig. 2 is an I-V characteristic diagram of the first ferroelectric transistor 201 and the second ferroelectric transistor 202, where-Vc and Vc in fig. 2 are threshold voltages in the positive and negative states of the first ferroelectric transistor 201 and the second ferroelectric transistor 202, respectively, that is, device parameter coercive voltages of the ferroelectric transistors, and for the first ferroelectric transistor 201 and the second ferroelectric transistor 202, when the positive gate-source voltage applied is greater than Vc, the first ferroelectric transistor 201 and the second ferroelectric transistor 202 will enter the positive state, that is, the low resistance state, and when the negative gate-source voltage applied is greater than Vc, the first ferroelectric transistor 201 and the second ferroelectric transistor 202 will enter the negative polarization state, that is, the high resistance state.
Alternatively, the write voltage is assumed to be Vwrite, and the value range of Vwrite is related to the value of Vc, specifically Vwrite > Vc > Vwrite/2.
In one possible implementation manner, assuming that the initial neural network weight value to be written into the computing unit 100 is 1, two stages are required, in the first stage, the Vwrite is input at the first write voltage driving node, and the second write voltage driving node is grounded, in the first stage, a positive gate source voltage greater than Vc is input to the first ferroelectric transistor, the first stage is equivalent to inputting a gate source voltage greater than Vc to the first ferroelectric transistor, the first ferroelectric transistor will enter or maintain a low resistance state, in the second stage, the first write voltage driving node is also input Vwrite, the second write voltage driving node is also grounded, in the first signal input node and the second signal input node, a negative gate source voltage greater than Vc is input to the second ferroelectric transistor, the second ferroelectric transistor will enter or maintain a high resistance state, the high resistance state and the low resistance state are equivalent to inputting a gate source voltage greater than Vc, the first resistance state is the first resistance state and the low resistance state is the initial neural network weight value to be 1, and the first resistance state is the initial neural network weight value to be the initial neural network, and the initial neural network weight value to be calculated to be the initial neural network 100 is the initial neural network weight value to be the Vc.
In another possible implementation manner, assuming that the initial neural network weight value to be written into the computing unit 100 is-1, two stages are required, in the first stage, the Vwrite is input at the second write voltage driving node, and the first write voltage driving node is grounded, in the first stage, a positive gate source voltage greater than Vc is input to the second ferroelectric transistor, the second ferroelectric transistor will enter or maintain a low resistance state, in the second stage, the second write voltage driving node is also input Vwrite, in the first stage, the Vwrite is also grounded, in the first signal input node, a negative gate source voltage greater than Vc is input to the first ferroelectric transistor, the first ferroelectric transistor will enter or maintain a high resistance state, the high resistance state and the low resistance state are both the gate source voltage greater than Vc, the first ferroelectric transistor is the initial neural network weight value to be written into the computing unit 100, and the initial neural network weight value to be 1 is the initial neural network weight value to be the computing unit 100.
In another possible implementation manner, assuming that the initial neural network weight value to be written into the computing unit 100 is 0, two stages are required, in the first stage, the first write voltage driving node and the second write voltage driving node are both grounded, in the first stage, 0 is input into the first signal input node and the second signal input node, in the first stage, the resistive states of the first ferroelectric transistor and the second ferroelectric transistor are not changed, in the second stage, the first write voltage driving node and the second write voltage driving node are both grounded, in the first signal input node and the second signal input node, a gate-source voltage which is negative and larger than Vc is input into the first ferroelectric transistor and the second ferroelectric transistor, in this time, the first ferroelectric transistor and the second ferroelectric transistor enter a high-resistance state, that is, the high-resistance state is the target state of the above, in which the initial neural network weight value to be written into the computing unit 100 is represented by the first neural network weight value to be the initial neural network, that is the initial neural network weight value to be 0, and the neural network weight value to be written into the computing unit 100 is calculated by the initial neural network.
As described above, the initial neural network weight value is written to the computing unit 100, and as shown in fig. 3, for a timing chart corresponding to the process, specific operations of the process may refer to table 1, where Vin1 (non-written row) and Vin2 (non-written row) in table 1 refer to Vin1 and Vin2 of other computing units in the computing circuit that do not perform the writing of the weight value.
TABLE 1
In one possible implementation, the inputs of Vin1 (non-write row) and Vin2 (non-write row) may also be kept at Vwrite/2, so that it may be ensured that the gate-source voltages of the first ferroelectric transistor and the second ferroelectric transistor in the computing unit 100 corresponding to Vin1 (non-write row) and Vin2 (non-write row) are not greater than Vwrite/2 during the process of writing the weight value, so as to ensure that the first ferroelectric transistor and the second ferroelectric transistor in the computing unit 100 corresponding to Vin1 (non-write row) and Vin2 (non-write row) do not undergo polarization inversion.
The precharge circuit 102 is configured to adjust the output node 203 to a target voltage.
In an alternative embodiment of the present application, as shown in fig. 1, the output node 203 is located between the first pole of the first ferroelectric transistor 201 and the first pole of the second ferroelectric transistor 202, and the point a in fig. 1 is the output node 203.
In an alternative embodiment of the present application, as shown in fig. 1, the precharge circuit includes a third transistor 1021, a source of the third transistor 1021 is connected to a second voltage source (Vprecharge in fig. 1) for outputting the target voltage, a drain of the third transistor 1021 is connected to the calculation output node 203, and a gate of the third transistor 1021 is for receiving a pulse signal to adjust the calculation output node 203 to the target voltage based on the pulse signal.
Alternatively, the third transistor 1021 may be an NMOS transistor, the voltage of the second voltage source being constant at V DD /2。
In an alternative embodiment of the present application, as shown in fig. 1, the computing circuit further includes a word line WL104;
wherein the gate of the third transistor 1021 in the precharge circuit 102 of each of the computing units 100 is connected to the WL104; the WL104 is configured to output the pulse signal to a gate of the third transistor 1021 in the precharge circuit 102 in each of the computing units 100.
Alternatively, as shown in fig. 4, 5 and 6, in the case that the initial neural network weight value is written into the computing unit 100, fig. 4 is a timing chart in which different input values are input after the precharge circuit performs the precharge process and performs the precharge process, in the case that the initial neural network weight value is written into the computing unit 100, fig. 6 is a timing chart in which different input values are input after the precharge process is performed, in the case that the precharge circuit performs the precharge process and performs the precharge process, in the case that different input values are input after the precharge process is performed, after the first ferroelectric transistor 201 and the second ferroelectric transistor 202 enter the target resistive state, that is, after the operation of writing the weight value into the computing unit 100 has been performed, the computing unit 100 based on the written initial neural network weight value needs to perform the multiplication operation, in the case that the precharge circuit writes the initial neural network weight value into the computing unit 100 is performed, and before the multiplication operation is performed, the precharge circuit needs to adjust the output voltage to the target node 203 based on the precharge circuit 102.
In one possible implementation, when the initial neural network weight value written by the computing unit 100 is 0, a positive pulse with a larger amplitude may be applied to the WL104, so that the computing output node 203 is charged to V by the first voltage source DD After the end of the applied pulse, the voltage on WL104 will revert to 0 and remain at 0, at which point the connection between the first voltage source and the calculation output node 203 is cut off.
In another possible implementation, when the initial neural network weight written by the computing unit 100 is 1, a positive pulse with a larger amplitude is applied to the WL104, and then the voltage of the computing output node is set to V under the combined action of the first signal input node and the first voltage source DD /2。
In another possible implementation, when the initial neural network weight written by the computing unit 100 is-1, a positive pulse with a larger amplitude is applied to the WL104, and then the voltage of the computing output node is set to V under the combined action of the second signal input node and the first voltage source DD /2。
The first ferroelectric transistor 301 and the second ferroelectric transistor 302 are configured to receive a signal input voltage after the calculation output node 203 is adjusted to the target voltage.
Optionally, the signal input voltage is used to characterize the value of the input.
In one possible implementation, if the voltage input by the first signal input node is V DD The voltage input to the second signal input node is 0, and the input value can be determined to be 1.
In another possible implementation, if the voltage input by the first signal input node is V DD 2, the voltage input by the second signal input node is V DD And/2, the value of the input can be determined to be 0.
In another possible implementation, if the first signal input node outputsThe voltage input by the second signal input node is V DD The value of the input can be determined to be-1.
The calculation result output circuit 103 is configured to output, after receiving the signal input voltage, the voltages of the calculation output nodes 203 through N output paths, respectively, so as to obtain, through N times of coupling on the voltages of the calculation output nodes 203, a first calculation result calculated by the multiplication calculation circuit 101, where the first calculation result is a calculation result calculated according to the signal input voltage and the first neural network weight value, the first neural network weight value is obtained according to the initial neural network weight value and the number of times of coupling N, N is a positive integer, and the number of times of coupling N corresponding to the calculation result output circuits in the calculation units 100 of different types are different.
In one embodiment, the calculation result output circuit 103 includes N sub-output circuits 1031 as shown in fig. 1, where each of the sub-output circuits 1031 is configured to output the voltage of the calculation output node 203 through a different output path.
In an alternative embodiment of the present application, as shown in fig. 1, the sub-output circuit 1031 includes a first transistor 301 and a second transistor 302, the gate of the first transistor 301 and the gate of the second transistor 302 are both connected to the computing output node 203, the first pole of the first transistor 301 is connected to a first voltage source (V in fig. 1 DD ) A first pole of the second transistor 302 is connected to ground.
In one possible implementation, as shown in fig. 1, the computing circuit in fig. 1 includes two computing units 100 of different types, namely, a first portion and a second portion, where the first portion includes one sub-output circuit 1031, the second portion includes two sub-output circuits 1031, that is, the first portion outputs the voltage of the computing output node 203 through only one output path, and the second portion outputs the voltage of the computing output node 203 through two output paths, it is understood that the initial neural network weights of the first portion and the second portion are (-1, 0, 1), the number of coupling times of the first portion is 1, the number of coupling times of the second portion is 2, the first neural network weight of the first portion is (-1, 0, 1), the first neural network weight of the second portion is (-2,0,2), if the first neural network weight of the first portion and the second portion are combined, then multiple computing weights can be implemented based on the computing circuits (-3, respectively, -35 of the computing circuits (-3).
In another possible implementation, as shown in fig. 7, the computing circuit in fig. 7 includes three different types of computing units 100, respectively, a first portion, a second portion and a third portion, where the first portion includes one sub-output circuit 1031, the second portion includes two sub-output circuits 1031, the third portion includes four sub-output circuits 1031, that is, the first portion outputs the voltage of the computing output node 203 through only one output path, the second portion outputs the voltage of the computing output node 203 through two output paths, the third portion outputs the voltage of the computing output node 203 through three output paths, which can be understood as the first portion, the initial neural network weight values of the second part and the third part are (-1, 0, 1), the coupling times of the first part are 1, the coupling times of the second part are 2, the coupling times of the third part are 4, the first neural network weight value of the first part is (-1, 0, 1), the first neural network weight value of the second part is (-2,0,2), the first neural network weight value of the third part is (-4,0,4), if the first neural network weight values of the first part, the second part and the third part are combined, the neural network calculation of multiple weight values can be realized based on the calculation circuit, and the weight values of the calculation circuit are (-7, -6, -5, -4, -3, -2, -1,0,1,2,3,4,5,6,7 respectively.
As described above, as the computing unit 100 increases in the computing circuit, the number of sub-output paths included in the computing unit 100 increases, specifically, if the added computing unit 100 is the M-th part, the added sub-output path is 2 M-1 The corresponding weight value is [ - (2) M -1)，-(2 M -2)，......，-2，-1，0，1，2，......，2 M -2，2 M -1]。
In one embodiment, as shown in fig. 1, the computing circuit further includes a first bit line RBL (not shown), and the second pole of the first transistor 301 and the second pole of the second transistor 302 in each of the sub-output circuits 103 are connected to the first bit line RBL to form an output path.
In one embodiment, as shown in fig. 1, the first bit line RBL includes a first sub bit line RBL501 and a second sub bit line RBL502, the second pole of the first transistor 301 is connected to the first sub bit line RBL501, and the second pole of the second transistor 302 is connected to the second sub bit line RBL 502.
The first transistor 301 and the second transistor 302 are used to perform a charging operation or a discharging operation on the first sub-bit line RBL501 and the second sub-bit line RBL502, respectively, under the control of the voltage of the calculation output node 203.
Alternatively, the first transistor 301 may be a PMOS transistor and the second transistor 302 may be an NMOS transistor.
In an alternative embodiment of the present application, before the multiplication circuit 101 performs calculation based on the signal input voltage and the first neural network weight value, the discharge processing and the floating processing are further performed on the first sub-bit line RBL501 and the second sub-bit line RBL502 based on transistors.
In an alternative embodiment of the present application, as shown in fig. 1, the first sub-bit line RBL501 and the second sub-bit line RBL502 are connected through a computation result processing circuit 106, and the computation result processing circuit 106 includes a first switch 601, a second switch 602, a third switch 603, a fourth switch connection 604, a first capacitor 605 and a second capacitor 606;
the calculation result processing circuit 106 is configured to perform an averaging process on the voltages of the first sub-bit line RBL501 and the second sub-bit line RBL502 to obtain the calculation results of the plurality of calculation units 100.
In one possible implementation, the first switch 601 and the second switch 602 remain closed and the third switch 603 and the fourth switch 604 remain open during the calculation of the multiplication circuit 101 based on the signal input voltage and the first neural network weight value.
As described above, the first transistor and the second transistor are used to perform a charging operation or a discharging operation on the first sub-bit line RBL501 and the second sub-bit line RBL502, respectively, under the control of the calculated output node voltage.
In one possible implementation, when the voltage at point A is V DD At the time of/2, the first transistor 301 and the second transistor 302 are not turned on, the voltage on the first sub-bit line RBL501 is 0, and the voltage on the second sub-bit line RBL502 is V DD 。
In another possible implementation, when the voltage at point A is V DD At this time, the first transistor 301 is not turned on, the second transistor 302 is turned on, the voltage on the first sub-bit line RBL501 is 0, and the voltage on the second sub-bit line RBL502 is V DD ΔV, which is the voltage change on the second sub-bit line RBL502 due to the stored charge change when the second transistor 302 performs a discharging operation.
In another possible implementation, when the voltage at the point a is 0, the second transistor 301 is turned on and the second transistor 302 is turned off, the voltage on the first sub-bit line RBL501 is Δv, and the voltage on the second sub-bit line RBL502 is V DD The Δv is a voltage change on the first sub-bit line RBL501 due to a stored charge change when the first transistor 301 performs a charging operation.
As described above, the calculation result processing circuit 106 is configured to perform an averaging process on the voltages of the first sub-bit line RBL501 and the second sub-bit line RBL502 to obtain the calculation results of the plurality of calculation units 100.
In one possible implementation manner, after the multiplication circuit 101 performs calculation based on the signal input voltage and the first neural network weight value, the first transistor 301 and the second transistor 302 perform charge operation or discharge operation on the first sub-bit line RBL501 and the second sub-bit line RBL502 respectively under the control of the voltage of the calculation output node 203, at this time, the first switch 601 and the second switch 602 are opened, the charges on the second capacitor 605 and the third capacitor 606 are still saved, and the third switch 603 and the fourth switch 604 are closed, at this time, the charges on the second capacitor 605 and the third capacitor 606 are charge-shared at the point B in fig. 1, and then the ADC is used to obtain the calculation result, specifically, refer to table 3.
TABLE 3 Table 3
In an alternative embodiment of the present application, as shown in fig. 8, the sub-output circuit 1031 includes a third capacitor 303, and a first end of the third capacitor 303 is connected to the node of the computing output node 203.
In one possible implementation, as shown in fig. 8, the computing circuit in fig. 8 includes three different types of computing units 100, that is, a first portion, a second portion and a third portion, where the first portion includes one sub-output circuit, the second portion includes two sub-output circuits, the third portion includes four sub-output circuits, that is, the first portion outputs the voltage of the computing output node 203 through only one output path, the second portion outputs the voltage of the computing output node 203 through two output paths, the third portion outputs the voltage of the computing output node 203 through three output paths, which can be understood as the first portion, the initial neural network weight values of the second part and the third part are (-1, 0, 1), the coupling times of the first part are 1, the coupling times of the second part are 2, the coupling times of the third part are 4, the first neural network weight value of the first part is (-1, 0, 1), the first neural network weight value of the second part is (-2,0,2), the first neural network weight value of the third part is (-4,0,4), if the first neural network weight values of the first part, the second part and the third part are combined, the neural network calculation of multiple weight values can be realized based on the calculation circuit, and the weight values of the calculation circuit are (-7, -6, -5, -4, -3, -2, -1,0,1,2,3,4,5,6,7 respectively.
In an alternative embodiment of the present application, as shown in fig. 8, the computing circuit further includes a second bit line RBL107, and the second end of the third capacitor 303 in each of the sub-output circuits 1031 is connected to the second bit line RBL 107; the third capacitor 303 is used to couple the voltage of the output node to the second bit line RBL.
In an alternative embodiment of the present application, before the multiplication circuit 101 performs calculation based on the signal input voltage and the first neural network weight value, a discharging process and a floating process are further performed on the second bit line RBL107 based on a transistor (001 in fig. 8).
In one possible implementation, after the multiplication circuit 101 performs calculation based on the signal input voltage and the first neural network weight value, the third capacitor couples the voltage of the calculation output node to the second bit line RBL107, and finally determines the calculation result of the calculation circuit based on the voltage on the second bit line RBL 107.
In one embodiment, in the case that the sub-output circuit includes a first transistor and a second transistor, the first ferroelectric transistor and the second ferroelectric transistor are further configured to receive the signal input voltage M times based on M pulses after the precharge circuit adjusts the calculated output node to the target voltage; the calculation result output circuit is used for respectively outputting the voltage of the calculation output node through N output channels after receiving the signal input pulse each time so as to obtain a second calculation result calculated by the multiplication calculation circuit through N times of coupling of the voltage of the calculation output node, wherein the second calculation result is calculated according to the signal input voltage and the second neural network weight value, the second neural network weight value is obtained according to the first neural network weight value and the pulse frequency M, and M is a positive integer.
In one possible implementation, assuming that the initial neural network weight of the computing unit is (-1, 0, 1), the computation result output circuit of the computing unit includes a sub-output circuit, and the pulse number M is 2, the second neural network weight is (-2,0,2).
In another possible implementation manner, assuming that the initial neural network weight value of the computing unit is (-1, 0, 1), the computing result output circuit of the computing unit includes two sub-output circuits, and the pulse number M is 2, the second neural network weight value is (-4,0,4).
As described above, as shown in fig. 9, the fig. 9 includes four different types of computing units 100, which are a zeroth portion, a first portion, a second portion and a third portion, respectively, where the zeroth portion includes one sub-output circuit, the first portion includes one sub-output circuit, the second portion includes two sub-output circuits, the third portion includes four sub-output circuits, that is, the first portion outputs the voltage of the computing output node 203 through only one output path, the second portion outputs the voltage of the computing output node 203 through two output paths, the third portion outputs the voltage of the computing output node 203 through three output paths, the number of pulses M of the zeroth portion is 1, the number of pulses M of the other three portions is 2, so that it can be understood that the zeroth portion, the first portion, the second portion and the third portion of the initial neural network are all (-1, 0, 1), the first neural network weight of the zeroth portion is (-1, 0, 62, the first neural network is (-1), the second weight of the second portion is (-0, 62), the second neural network is the second weight of the second portion is (-0, 42), the second weight of the third portion is the neural network is the second weight of the second portion is the second neural network, the second weight of the second portion is the second 52, the second weight of the second portion is the second 52, 0, 8), a neural network calculation of multiple weight values can be implemented based on the calculation circuit.
The computing circuit comprises a plurality of computing units of different types, wherein the computing units are arranged in an array, each computing unit comprises a multiplication computing circuit, a precharge circuit and a computing result output circuit, and the computing result output circuits of the computing units of different types are different; the multiplication calculating circuit comprises a first ferroelectric transistor and a second ferroelectric transistor which are connected with each other, and the precharge circuit and the calculation result output circuit are electrically connected with a calculation output node between the first ferroelectric transistor and the second ferroelectric transistor; the first ferroelectric transistor and the second ferroelectric transistor are used for entering a target resistance state under the drive of write voltage so as to represent an initial neural network weight value; the precharge circuit is used for adjusting the calculated output node to a target voltage; the first ferroelectric transistor and the second ferroelectric transistor are used for receiving a signal input voltage after the calculation output node is adjusted to the target voltage; the calculation result output circuit is used for respectively outputting the voltage of the calculation output node through N output channels after receiving the signal input voltage so as to obtain a first calculation result calculated by the multiplication calculation circuit through N times of coupling of the voltage of the calculation output node, wherein the first calculation result is calculated according to the signal input voltage and the first neural network weight value, the first neural network weight value is obtained according to the initial neural network weight value and the coupling times N, N is a positive integer, and the coupling times N corresponding to the calculation result output circuit in the calculation units of different types are different. The calculation circuit that this application provided can be used to the calculation of multivalue neural network, compares in the calculation circuit among the prior art, and the components and parts that the calculation circuit of this application used are fewer, consequently, adopts the calculation circuit that this application provided, can effectual reduction consumption and area, moreover, the calculation circuit that this application provided is including the weight value in the sign bit, and then can effectual promotion reasoning precision.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples represent only a few embodiments of the present application, which are described in more detail and are not thereby to be construed as limiting the scope of the present application. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application shall be subject to the appended claims.
Claims (13)
1. The computing circuit is characterized by comprising a plurality of computing units of different types, wherein the computing units are arranged in an array, each computing unit comprises a multiplication computing circuit, a precharge circuit and a computing result output circuit, and the computing result output circuits of the computing units of different types are different; the multiplication calculating circuit comprises a first ferroelectric transistor and a second ferroelectric transistor which are connected with each other, and the precharge circuit and the calculation result output circuit are electrically connected with a calculation output node between the first ferroelectric transistor and the second ferroelectric transistor;
The first ferroelectric transistor and the second ferroelectric transistor are used for entering a target resistance state under the drive of write voltage so as to represent an initial neural network weight value;
the precharge circuit is used for adjusting the calculation output node to a target voltage;
the first ferroelectric transistor and the second ferroelectric transistor are used for receiving a signal input voltage after the calculation output node is adjusted to the target voltage;
the calculation result output circuit is configured to output the voltages of the calculation output nodes through N output paths after receiving the signal input voltage, so as to obtain a first calculation result obtained by calculating the multiplication calculation circuit through N times of coupling of the voltages of the calculation output nodes, where the first calculation result is a calculation result obtained by calculating according to the signal input voltage and the first neural network weight value, the first neural network weight value is obtained according to the initial neural network weight value and the coupling times N, N is a positive integer, and the coupling times N corresponding to the calculation result output circuits in the calculation units of different types are different.
2. The computing circuit of claim 1, wherein the computation result output circuit comprises N sub-output circuits, wherein each of the sub-output circuits is configured to output the voltage of the computation output node through a different output path.
3. The computing circuit of claim 2, wherein the sub-output circuit comprises a first transistor and a second transistor, the gate of the first transistor and the gate of the second transistor are both connected to the computing output node, the first pole of the first transistor is connected to a first voltage source, and the first pole of the second transistor is grounded.
4. The computing circuit of claim 3, further comprising a first bit line RBL, a second pole of a first transistor in each of the sub-output circuits and a second pole of the second transistor being connected to the first bit line RBL to form an output path.
5. The computing circuit of claim 4, wherein the first bit line RBL includes a first sub bit line RBL and a second sub bit line RBL, a second pole of the first transistor is connected to the first sub bit line RBL, a second pole of the second transistor is connected to the second sub bit line RBL, and the first transistor and the second transistor are configured to perform a charging operation or a discharging operation on the first sub bit line RBL and the second sub bit line RBL, respectively, under control of the computation output node voltage.
6. The computing circuit of claim 5, wherein the first sub-bit line RBL and the second sub-bit line RBL are connected by a computation result processing circuit including a first switch, a second switch, a third switch, a fourth switch connection, a first capacitance, and a second capacitance;
the calculation result processing circuit is configured to perform an average process on voltages of the first sub-bit line RBL and the second sub-bit line RBL to obtain calculation results of the plurality of calculation units.
7. A computing circuit as claimed in claim 3, wherein the sub-output circuit comprises a third capacitor, a first end of the third capacitor being connected to the computing output node.
8. The computing circuit of claim 7, further comprising a second bit line RBL, a second end of a third capacitor in each of the sub-output circuits being connected to the second bit line RBL;
the third capacitor is configured to couple the voltage of the computing output node to the second bit line RBL.
9. The computing circuit of any of claims 1-6, wherein the first ferroelectric transistor and the second ferroelectric transistor are further configured to receive M times the signal input voltage based on M pulses after the precharge circuit adjusts the computing output node to the target voltage;
The calculation result output circuit is configured to output the voltages of the calculation output nodes through N output paths after receiving the signal input voltage each time, so as to obtain a second calculation result obtained by calculation of the multiplication calculation circuit through N times of coupling of the voltages of the calculation output nodes, where the second calculation result is a calculation result obtained by calculation according to the signal input voltage and the second neural network weight value, and the second neural network weight value is obtained according to the first neural network weight value and the pulse number M, where M is a positive integer.
10. The computing circuit of claim 1, wherein a first pole of the first ferroelectric transistor is connected to a first pole of the second ferroelectric transistor, a second pole of the first ferroelectric transistor is a first signal input node, a second pole of the second ferroelectric transistor is a second signal input node, a gate of the first ferroelectric transistor is a first write voltage drive node, and a gate of the second ferroelectric transistor is a second write voltage drive node;
the first signal input node and the second signal input node are used for inputting the signal input voltage;
The first write voltage driving node and the second write voltage driving node are used for inputting the write voltage.
11. The computing circuit of claim 10, wherein the compute output node is located between a first pole of the first ferroelectric transistor and a first pole of the second ferroelectric transistor.
12. The computing circuit of claim 1, wherein the precharge circuit comprises a third transistor having a source connected to a second voltage source for outputting the target voltage, a drain connected to the computing output node, and a gate for receiving a pulse signal to adjust the computing output node to the target voltage based on the pulse signal.
13. The computing circuit of claim 12, further comprising a word line WL;
a gate of a third transistor in the precharge circuit in each of the calculation units is connected to the WL;
the WL is configured to output the pulse signal to a gate of a third transistor in the precharge circuit in each of the computing units.
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