CN117457041A - Training device and training method suitable for gating clock signal - Google Patents

Training device and training method suitable for gating clock signal Download PDF

Info

Publication number
CN117457041A
CN117457041A CN202311459167.XA CN202311459167A CN117457041A CN 117457041 A CN117457041 A CN 117457041A CN 202311459167 A CN202311459167 A CN 202311459167A CN 117457041 A CN117457041 A CN 117457041A
Authority
CN
China
Prior art keywords
current
gating
delay
clock
training
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202311459167.XA
Other languages
Chinese (zh)
Other versions
CN117457041B (en
Inventor
古城
王晓阳
何亚军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Kuixin Integrated Circuit Design Co ltd
Original Assignee
Shanghai Kuixin Integrated Circuit Design Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Kuixin Integrated Circuit Design Co ltd filed Critical Shanghai Kuixin Integrated Circuit Design Co ltd
Priority to CN202311459167.XA priority Critical patent/CN117457041B/en
Publication of CN117457041A publication Critical patent/CN117457041A/en
Application granted granted Critical
Publication of CN117457041B publication Critical patent/CN117457041B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The invention provides a training device and a training method suitable for a gate control clock signal.A slow clock adjusting module generates a current slow clock based on a read instruction and a current slow clock delay mark; the gating enabling signal adjusting module synthesizes an initial gating enabling signal, generates a current gating enabling signal based on the current enabling signal delay mark and the initial gating enabling signal, and generates a current gating clock signal based on the current gating enabling signal and a slave device clock; the sampling module samples the current gating clock signal based on a plurality of sampling clocks to obtain current sampling results corresponding to the sampling clocks, the training module judges whether training is finished or not and sets a next slow clock delay mark and a next enabling signal delay mark based on the current sampling results, and the gating clock signal consistent with the data signal delay can be efficiently and accurately trained by combining a quick adjustment mode of the delay DFI clock and a fine adjustment mode of the delay initial gating enabling signal.

Description

Training device and training method suitable for gating clock signal
Technical Field
The invention relates to the technical field of memories, in particular to a training device and a training method suitable for gating clock signals.
Background
In high speed devices such as DRAM, FLASH, and HBM, the clock signal (e.g., the RDQS signal of DRAM) and the data signal (e.g., the DQ signal of DRAM) returned from these high speed devices may cause delays in the transmission of the clock signal and the data signal to be different, i.e., the clock signal is sometimes faster than the data or slower than the data, on passing through the board or with temperature and electromagnetic interference. Therefore, it is desirable to have a gated clock circuit that effectively controls the effective clock signal, avoiding introducing unwanted clock signals or glitches into the circuit, and thus avoiding affecting the normal function of other circuits.
In order to obtain a proper gating clock, a training circuit is required to find the proper gating clock, but the training time required by the current training scheme is longer, the efficiency is lower, or an effective gating frame can be found only for certain specific preamble clock (clock preamble) signals, so that the limit condition is more. Thus, there is a need for a gating clock training device and training method that is efficient and adaptable for use with respect to various preamble clocks.
Disclosure of Invention
The invention provides a training device and a training method suitable for a gating clock signal, which are used for solving the defects of lower efficiency or narrower application range in the prior art.
The invention provides a training device suitable for gating clock signals, which comprises:
the system comprises a training module, a slow clock adjusting module, a gate control enabling signal adjusting module and a sampling module;
after the training module sends a read instruction, the slow clock adjusting module generates a current slow clock based on the read instruction and a current slow clock delay mark;
the gating enabling signal adjusting module receives the current slow clock and the PHY clock, synthesizes the current slow clock and the PHY clock to obtain an initial gating enabling signal, generates a current gating enabling signal based on a current enabling signal delay mark and the initial gating enabling signal, and generates a current gating clock signal based on the current gating enabling signal and a slave device clock;
the sampling module samples the current gating clock signal based on a plurality of sampling clocks to obtain current sampling results corresponding to the sampling clocks, and the training module judges whether training is finished or not and sets a next slow clock delay flag and a next enabling signal delay flag based on the current sampling results.
According to the training device suitable for the gating clock signal, before the current sampling result meets the preset condition, the slow clock delay mark is maintained to be delayed, and the enabling signal delay mark is maintained to be not delayed; after the current sampling result meets the preset condition and before training is finished, the slow clock delay mark is maintained to be non-delayed, and the enabling signal delay mark is maintained to be delayed.
According to the training device suitable for the gating clock signal, the preset condition is that the current sampling results corresponding to the sampling clocks are not all 0.
According to the training device suitable for the gating clock signal, the training module is specifically used for:
judging whether the current sampling results corresponding to the sampling clocks contain periodic data of a preset mode or not;
if the current sampling results corresponding to the sampling clocks contain periodic data in a preset mode, determining that training is finished, and determining that the current gating clock signal is a trained gating clock signal;
if the current sampling results corresponding to the sampling clocks do not contain periodic data in a preset mode and are not all 0, determining that training is not finished, maintaining the delay of the next slow clock as no delay, maintaining the delay of the next enable signal as delay, and sending delay control information to the gating enable signal adjusting module so that the gating enable signal adjusting module delays the initial gating enable signal based on the delay control information to obtain the next gating enable signal.
According to the training device suitable for the gating clock signal, the delay control information is used for delaying the rising edge of the initial gating enabling signal to the position, corresponding to the plurality of sampling clocks, of the first part of the current sampling results, which accords with the preset mode.
The invention also provides a training method based on the training device suitable for gating clock signals, which comprises the following steps:
after a read instruction is sent based on the training module, a current slow clock is generated based on the slow clock adjusting module by utilizing the read instruction and a current slow clock delay mark;
receiving the current slow clock and the PHY clock based on the gating enable signal adjusting module, synthesizing to obtain an initial gating enable signal, generating a current gating enable signal based on a current enable signal delay mark and the initial gating enable signal, and generating a current gating clock signal based on the current gating enable signal and a slave device clock;
based on the sampling module, sampling the current gating clock signal by utilizing a plurality of sampling clocks to obtain current sampling results corresponding to the sampling clocks;
based on the training module, judging whether training is finished or not by using the current sampling result, and setting a next slow clock delay mark and a next enabling signal delay mark.
According to the training method provided by the invention, before the current sampling result meets the preset condition, the slow clock delay mark is maintained to be delayed, and the enabling signal delay mark is maintained to be not delayed; after the current sampling result meets the preset condition and before training is finished, the slow clock delay mark is maintained to be non-delayed, and the enabling signal delay mark is maintained to be delayed.
According to the training method provided by the invention, the preset condition is that the current sampling results corresponding to the sampling clocks are not all 0.
According to the training method provided by the invention, based on the training module, whether training is finished or not is judged by utilizing the current sampling result, and a next slow clock delay mark and a next enabling signal delay mark are set, and the training method specifically comprises the following steps:
judging whether the current sampling results corresponding to the sampling clocks contain periodic data of a preset mode or not;
if the current sampling results corresponding to the sampling clocks contain periodic data in a preset mode, determining that training is finished, and determining that the current gating clock signal is a trained gating clock signal;
if the current sampling results corresponding to the sampling clocks do not contain periodic data in a preset mode and are not all 0, determining that training is not finished, maintaining the delay of the next slow clock as no delay, maintaining the delay of the next enable signal as delay, and sending delay control information to the gating enable signal adjusting module so that the gating enable signal adjusting module delays the initial gating enable signal based on the delay control information to obtain the next gating enable signal.
According to the training method provided by the invention, the delay control information is used for delaying the rising edge of the initial gating enabling signal to the position where the first part of the current sampling results corresponding to the sampling clocks accords with the preset mode.
The invention provides a training device and a training method suitable for a gating clock signal.A slow clock adjusting module generates a current slow clock based on a read instruction and a current slow clock delay mark after a training module sends the read instruction; the gating enabling signal adjusting module receives the current slow clock and the PHY clock, synthesizes the current slow clock and the PHY clock to obtain an initial gating enabling signal, generates a current gating enabling signal based on the current enabling signal delay mark and the initial gating enabling signal, and generates a current gating clock signal based on the current gating enabling signal and the slave device clock; the sampling module samples the current gating clock signal based on a plurality of sampling clocks to obtain current sampling results corresponding to the sampling clocks, the training module judges whether training is finished or not and sets a next slow clock delay mark and a next enabling signal delay mark based on the current sampling results, and the gating clock signal consistent with the data signal delay can be efficiently and accurately trained by combining a quick adjustment mode of the delay DFI clock and a fine adjustment mode of the delay initial gating enabling signal.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a training apparatus for gating clock signals according to the present invention;
FIG. 2 is a schematic diagram of the operation of the training device for gating clock signals according to the present invention;
FIG. 3 is a schematic diagram of a current gating enable signal, a slave clock, and a current gating clock signal provided by the present invention;
fig. 4 is a flowchart of a training method suitable for gating clock signals according to the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 1 is a schematic structural diagram of a training device suitable for gating clock signals according to the present invention, as shown in fig. 1, the circuit includes:
training module 110, slow clock adjustment module 120, gating enable signal adjustment module 130, and sampling module 140.
Wherein, as shown in fig. 2, when the front wheel training begins, the training module 140 sends a read instruction to the slow clock adjustment module 120 and the slave device (e.g., memory granule). Based on the dfi_rd_en [3:0] field, the DDR controller may be instructed to request a read operation from the DDR PHY. After the slow clock adjustment module 120 receives the read command, the length of the read command can be controlled, specifically, the length information of the read signal can be determined according to preset leading information and trailing information, and the approximate range of the length of the read signal can be determined according to the current sampling result output by the sampling module in the previous training process, so that the training device is not limited to a specific leading clock. The length information is used to control the width of the subsequent gating clock enable signal and the width of the active signal in the gating clock signal. For example, the length of the read instruction may be set based on a configuration item in the DDR controller, dfi_rd_en_len [3:0 ]. Subsequently, the slow clock adjustment module 120 generates the current slow clock in combination with the read instruction based on the current slow clock delay flag set by the training module 110 after the last round of training is completed.
Here, if the current slow clock delay flag is a delay, the current slow clock is output according to the DFI (DDR PHY Interface) clock delay based on the read instruction, so that the current slow clock is delayed by a preset period with respect to the last slow clock (the initial slow clock is the DFI clock) generated during the previous round of training. The preset period may be preset, for example, 1 DFI clock period. In some cases, the received read instruction may be output one or more beats based on the DFI clock and bitwise ored and output the current slow clock after a delay value. Wherein the delay may be achieved by moving dfi_rd_en_len [3:0] to dfi_rd_en_len_dly [3:0 ]. If the current slow clock delay mark is not delayed, the current slow clock is the same as the last slow clock generated in the last round of training.
After the gating enable signal conditioning module 130 receives the current slow clock output by the slow clock conditioning module, the current slow clock and the PHY (Physical Layer) clock may be synthesized in parallel-serial manner to obtain an initial gating enable signal (dfi_gate_en). Subsequently, the GATE enable signal adjustment module 130 generates a current GATE enable signal (dfi_gate_en_dly) based on the current enable signal delay flag and the initial GATE enable signal set by the training module 110 after the previous training is completed, and generates a current GATE clock signal based on the current GATE enable signal and a slave clock returned by the slave according to the read command, wherein a schematic diagram of the current GATE enable signal, the slave clock, and the current GATE clock signal is shown in fig. 3. If the delay flag of the current enable signal is delayed, the initial gate enable signal is delayed to obtain the current gate enable signal. For example, the delay operation of the initial gate enable signal may be implemented using the rg_fine_dly register. If the delay flag of the current enable signal is not delayed, the current gate enable signal is the initial gate enable signal.
In some embodiments, when the delay flag of the current enable signal set after the previous training is finished is a delay, the training module 110 sends delay control information to the gating enable signal adjustment module 130 at the same time, so that the gating enable signal adjustment module 130 delays the initial gating enable signal based on the delay control information to obtain the current gating enable signal. The delay control information is used to delay the rising edge of the initial gate enable signal to a preset position, and in particular, how to delay the rising edge of the initial gate enable signal will be described in detail later.
The sampling module 140 samples the current gating clock signal based on a plurality of sampling clocks, so as to obtain current sampling results corresponding to the plurality of sampling clocks. The sampling module 140 includes a plurality of sampling units, which are respectively used for sampling the current gating clock signal based on the corresponding sampling clocks. In some embodiments, as shown in fig. 2, the conversion of different phases may be based on a PHY clock, resulting in a plurality of sampling clocks of different phases, which may include the original PHY clock. The current sampling result comprises a plurality of sampling sequences, and any sampling sequence comprises sampling values obtained by sampling the sampling clocks. Based on the current sampling result, the training module 110 may determine whether training is completed, and set a next slow clock delay flag and a next enable signal delay flag for a next round of training process when it is determined that training is not completed.
In some embodiments, the training module 110 controls the slow clock delay flag to be maintained as a delay and the enable signal delay flag to be maintained as a non-delay before the current sampling result meets the preset condition; after the current sampling result meets the preset condition and before the training is completed, the training module 110 controls the slow clock delay flag to be kept unchanged, and controls the enable signal delay flag to be kept unchanged. The preset condition is that the current sampling result contains effective data. In some embodiments, the preset condition may be that the current sampling result corresponding to the plurality of sampling clocks is not all 0. That is, in the early training period, the training module 110 controls the slow clock delay flag to be maintained as a delay, controls the enable signal delay flag to be maintained as a non-delay, and rapidly adjusts the gating frame (i.e., the area with the signal value of high level) of the current gating clock signal by using the mode of delaying the DFI clock, so that valid data can be collected based on the adjusted current gating clock signal; in the later stage of training, the training module 110 maintains the delay flag of the enable signal to be delayed by controlling the delay flag of the slow clock to be not delayed, and fine-tunes the gating frame of the current gating clock signal in a manner of delaying the initial gating enable signal, so that the delay of the adjusted current gating clock signal is consistent with that of the data signal, thereby ensuring the high efficiency and accuracy of the training of the gating clock signal.
In other embodiments, the training module 110 may specifically determine whether the current sampling results corresponding to the plurality of sampling clocks include periodic data in a preset mode. The preset pattern may be a sequence including 0 and 1 at the same time, and 0 is located at the beginning and end of the sequence, for example, the preset pattern may be 00 …, 01, 11, …, 00, …, 11, …, 00, or 01, …, 11, 10, …, 00, etc., but the embodiment of the present invention does not limit the specific setting of the preset pattern. If the sampling sequences in the current sampling results corresponding to the sampling clocks accord with the preset mode and are periodic, the delay of the current gating clock signal and the delay of the data signal are consistent, so that the training can be determined to be finished, and the current gating clock signal is determined to be the trained gating clock signal.
If the current sampling result corresponding to the plurality of sampling clocks does not include periodic data in the preset mode and is not all 0, determining that the training is not finished, maintaining the next slow clock delay mark as non-delay by the training module 110, and transmitting delay control information to the gating enable signal adjustment module, so that in the next round of training, the gating enable signal adjustment module delays the initial gating enable signal in a fine adjustment manner based on the delay control information to obtain the next gating enable signal. For example, the fine-tuning operation described above may be implemented using the rg_fine_dly register. By the fine tuning mode, accurate gating clock signals can be found until the current sampling results corresponding to the sampling clocks contain periodic data in a preset mode. In some embodiments, the initial gating enable signal may be fine-tuned based on a preset delay. In other embodiments, the delay control information may be used to delay the rising edge of the initial gating enable signal to a position where the first part of the current sampling result corresponding to the plurality of sampling clocks meets the preset mode, so as to implement rapid adjustment of the gating frame of the gating clock signal. The rising edge of the initial gating enable signal may be delayed backward until the rising edge of the sampling sequence partially matching the preset pattern in the current sampling result is aligned with the corresponding rising edge of the sampling sequence in the corresponding sampling clock. For example, taking the preset pattern as 1110 0111 as an example, if the current sampling result is 00001110, that is, includes two sampling sequences "0000" and "1110", it may be determined that each sampling value in the sampling sequence 1110 has a corresponding rising edge in the corresponding sampling clock, and then the earliest rising edge is selected, and the rising edge of the initial gate enable signal is delayed until the rising edge is aligned with the earliest rising edge.
In summary, in the training device provided by the embodiment of the present invention, after the training module sends the read command, the slow clock adjustment module generates the current slow clock based on the read command and the current slow clock delay flag; the gating enabling signal adjusting module receives the current slow clock and the PHY clock, synthesizes the current slow clock and the PHY clock to obtain an initial gating enabling signal, generates a current gating enabling signal based on the current enabling signal delay mark and the initial gating enabling signal, and generates a current gating clock signal based on the current gating enabling signal and the slave device clock; the sampling module samples the current gating clock signal based on a plurality of sampling clocks to obtain current sampling results corresponding to the sampling clocks, the training module judges whether training is finished or not and sets a next slow clock delay mark and a next enabling signal delay mark based on the current sampling results, and the gating clock signal consistent with the data signal delay can be efficiently and accurately trained by combining a quick adjustment mode of the delay DFI clock and a fine adjustment mode of the delay initial gating enabling signal.
The training method based on the training device suitable for the gating clock signal provided by the invention is described below, and the training method described below and the training device described above can be correspondingly referred to each other.
Based on any of the above embodiments, fig. 4 is a flow chart of a training method suitable for gating clock signals according to the present invention, where the method is based on the training device provided in the above embodiment, and as shown in fig. 4, the method includes:
step 410, after a read instruction is sent based on the training module, generating a current slow clock based on the slow clock adjustment module by using the read instruction and a current slow clock delay flag;
step 420, receiving the current slow clock and PHY clock based on the gating enable signal adjustment module and synthesizing to obtain an initial gating enable signal, generating a current gating enable signal based on a current enable signal delay flag and the initial gating enable signal, and generating a current gating clock signal based on the current gating enable signal and a slave clock;
step 430, based on the sampling module, sampling the current gating clock signal by using a plurality of sampling clocks to obtain current sampling results corresponding to the plurality of sampling clocks;
step 440, based on the training module, determining whether the training is completed according to the current sampling result, and setting a next slow clock delay flag and a next enable signal delay flag.
According to the method provided by the embodiment of the invention, after the training module sends the read instruction, the slow clock adjusting module generates the current slow clock based on the read instruction and the current slow clock delay mark; the gating enabling signal adjusting module receives the current slow clock and the PHY clock, synthesizes the current slow clock and the PHY clock to obtain an initial gating enabling signal, generates a current gating enabling signal based on the current enabling signal delay mark and the initial gating enabling signal, and generates a current gating clock signal based on the current gating enabling signal and the slave device clock; the sampling module samples the current gating clock signal based on a plurality of sampling clocks to obtain current sampling results corresponding to the sampling clocks, the training module judges whether training is finished or not and sets a next slow clock delay mark and a next enabling signal delay mark based on the current sampling results, and the gating clock signal consistent with the data signal delay can be efficiently and accurately trained by combining a quick adjustment mode of the delay DFI clock and a fine adjustment mode of the delay initial gating enabling signal.
Based on any of the above embodiments, the slow clock delay flag is maintained as a delay and the enable signal delay flag is maintained as a non-delay until the current sampling result meets a preset condition; after the current sampling result meets the preset condition and before training is finished, the slow clock delay mark is maintained to be non-delayed, and the enabling signal delay mark is maintained to be delayed.
Based on any one of the above embodiments, the preset condition is that the current sampling results corresponding to the plurality of sampling clocks are not all 0.
Based on any one of the foregoing embodiments, the determining, based on the training module, whether training is completed or not by using the current sampling result, and setting a next slow clock delay flag and a next enable signal delay flag specifically includes:
judging whether the current sampling results corresponding to the sampling clocks contain periodic data of a preset mode or not;
if the current sampling results corresponding to the sampling clocks contain periodic data in a preset mode, determining that training is finished, and determining that the current gating clock signal is a trained gating clock signal;
if the current sampling results corresponding to the sampling clocks do not contain periodic data in a preset mode and are not all 0, determining that training is not finished, maintaining the delay of the next slow clock as no delay, maintaining the delay of the next enable signal as delay, and sending delay control information to the gating enable signal adjusting module so that the gating enable signal adjusting module delays the initial gating enable signal based on the delay control information to obtain the next gating enable signal.
Based on any of the foregoing embodiments, the delay control information is configured to delay a rising edge of the initial gating enable signal to a position where a first portion of current sampling results corresponding to the plurality of sampling clocks corresponds to the preset pattern.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A training device adapted to gate a clock signal, comprising:
the system comprises a training module, a slow clock adjusting module, a gate control enabling signal adjusting module and a sampling module;
after the training module sends a read instruction, the slow clock adjusting module generates a current slow clock based on the read instruction and a current slow clock delay mark;
the gating enabling signal adjusting module receives the current slow clock and the PHY clock, synthesizes the current slow clock and the PHY clock to obtain an initial gating enabling signal, generates a current gating enabling signal based on a current enabling signal delay mark and the initial gating enabling signal, and generates a current gating clock signal based on the current gating enabling signal and a slave device clock;
the sampling module samples the current gating clock signal based on a plurality of sampling clocks to obtain current sampling results corresponding to the sampling clocks, and the training module judges whether training is finished or not and sets a next slow clock delay flag and a next enabling signal delay flag based on the current sampling results.
2. The training device for gating clock signal of claim 1, wherein the slow clock delay flag is maintained as delayed and the enable signal delay flag is maintained as not delayed until the current sampling result meets a preset condition; after the current sampling result meets the preset condition and before training is finished, the slow clock delay mark is maintained to be non-delayed, and the enabling signal delay mark is maintained to be delayed.
3. The training device for gating clock signal according to claim 2, wherein the preset condition is that the current sampling result corresponding to the plurality of sampling clocks is not all 0.
4. A training device adapted for gating clock signals as claimed in claim 3, wherein the training module is specifically adapted to:
judging whether the current sampling results corresponding to the sampling clocks contain periodic data of a preset mode or not;
if the current sampling results corresponding to the sampling clocks contain periodic data in a preset mode, determining that training is finished, and determining that the current gating clock signal is a trained gating clock signal;
if the current sampling results corresponding to the sampling clocks do not contain periodic data in a preset mode and are not all 0, determining that training is not finished, maintaining the delay of the next slow clock as no delay, maintaining the delay of the next enable signal as delay, and sending delay control information to the gating enable signal adjusting module so that the gating enable signal adjusting module delays the initial gating enable signal based on the delay control information to obtain the next gating enable signal.
5. The training device for gating clock signal of claim 4, wherein the delay control information is configured to delay a rising edge of the initial gating enable signal to a position where a first portion of current sampling results corresponding to the plurality of sampling clocks matches the preset pattern.
6. Training method based on a training device suitable for gating clock signals according to any one of claims 1 to 5, comprising:
after a read instruction is sent based on the training module, a current slow clock is generated based on the slow clock adjusting module by utilizing the read instruction and a current slow clock delay mark;
receiving the current slow clock and the PHY clock based on the gating enable signal adjusting module, synthesizing to obtain an initial gating enable signal, generating a current gating enable signal based on a current enable signal delay mark and the initial gating enable signal, and generating a current gating clock signal based on the current gating enable signal and a slave device clock;
based on the sampling module, sampling the current gating clock signal by utilizing a plurality of sampling clocks to obtain current sampling results corresponding to the sampling clocks;
based on the training module, judging whether training is finished or not by using the current sampling result, and setting a next slow clock delay mark and a next enabling signal delay mark.
7. The training method of claim 6, wherein the slow clock delay flag is maintained as delayed and the enable signal delay flag is maintained as not delayed until the current sampling result meets a preset condition; after the current sampling result meets the preset condition and before training is finished, the slow clock delay mark is maintained to be non-delayed, and the enabling signal delay mark is maintained to be delayed.
8. The training method of claim 7, wherein the preset condition is that current sampling results corresponding to the plurality of sampling clocks are not all 0.
9. The training method of claim 8, wherein the determining whether training is completed based on the training module by using the current sampling result, and setting a next slow clock delay flag and a next enable signal delay flag specifically comprises:
judging whether the current sampling results corresponding to the sampling clocks contain periodic data of a preset mode or not;
if the current sampling results corresponding to the sampling clocks contain periodic data in a preset mode, determining that training is finished, and determining that the current gating clock signal is a trained gating clock signal;
if the current sampling results corresponding to the sampling clocks do not contain periodic data in a preset mode and are not all 0, determining that training is not finished, maintaining the delay of the next slow clock as no delay, maintaining the delay of the next enable signal as delay, and sending delay control information to the gating enable signal adjusting module so that the gating enable signal adjusting module delays the initial gating enable signal based on the delay control information to obtain the next gating enable signal.
10. The training method of claim 9, wherein the delay control information is configured to delay a rising edge of the initial gating enable signal to a position where a first portion of current sampling results corresponding to the plurality of sampling clocks corresponds to the preset pattern.
CN202311459167.XA 2023-11-03 2023-11-03 Training device and training method suitable for gating clock signal Active CN117457041B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311459167.XA CN117457041B (en) 2023-11-03 2023-11-03 Training device and training method suitable for gating clock signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311459167.XA CN117457041B (en) 2023-11-03 2023-11-03 Training device and training method suitable for gating clock signal

Publications (2)

Publication Number Publication Date
CN117457041A true CN117457041A (en) 2024-01-26
CN117457041B CN117457041B (en) 2024-06-14

Family

ID=89596306

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311459167.XA Active CN117457041B (en) 2023-11-03 2023-11-03 Training device and training method suitable for gating clock signal

Country Status (1)

Country Link
CN (1) CN117457041B (en)

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100246290A1 (en) * 2009-03-30 2010-09-30 Denali Software, Inc. Method and apparatus for gate training in memory interfaces
US9672305B1 (en) * 2015-01-28 2017-06-06 Apple Inc. Method for gating clock signals using late arriving enable signals
CN109314506A (en) * 2016-06-02 2019-02-05 高通股份有限公司 Low clock power data gated FF
CN110853689A (en) * 2018-08-20 2020-02-28 爱思开海力士有限公司 Semiconductor device including data input circuit
CN111949582A (en) * 2020-08-25 2020-11-17 海光信息技术有限公司 Pointer synchronization device and method, asynchronous FIFO circuit and processor system
CN113553277A (en) * 2021-06-24 2021-10-26 西安电子科技大学 High-throughput and low-delay PHY (physical layer) interface circuit device of DDR5SDRAM (synchronous dynamic random access memory)
CN115547381A (en) * 2022-11-30 2022-12-30 合肥奎芯集成电路设计有限公司 Gate signal generating circuit of data gate signal and signal generating method thereof
CN116013394A (en) * 2023-01-10 2023-04-25 上海奎芯集成电路设计有限公司 Memory training circuit and memory training method
CN116312672A (en) * 2023-05-24 2023-06-23 长鑫存储技术有限公司 Command/address signal training mode circuit and memory
CN116595386A (en) * 2023-07-18 2023-08-15 芯耀辉科技有限公司 Training control method and system for memory
CN116720460A (en) * 2023-06-19 2023-09-08 海光信息技术股份有限公司 Training and determining method, system, equipment and medium for inserting gating clock

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100246290A1 (en) * 2009-03-30 2010-09-30 Denali Software, Inc. Method and apparatus for gate training in memory interfaces
US9672305B1 (en) * 2015-01-28 2017-06-06 Apple Inc. Method for gating clock signals using late arriving enable signals
CN109314506A (en) * 2016-06-02 2019-02-05 高通股份有限公司 Low clock power data gated FF
CN110853689A (en) * 2018-08-20 2020-02-28 爱思开海力士有限公司 Semiconductor device including data input circuit
CN111949582A (en) * 2020-08-25 2020-11-17 海光信息技术有限公司 Pointer synchronization device and method, asynchronous FIFO circuit and processor system
CN113553277A (en) * 2021-06-24 2021-10-26 西安电子科技大学 High-throughput and low-delay PHY (physical layer) interface circuit device of DDR5SDRAM (synchronous dynamic random access memory)
CN115547381A (en) * 2022-11-30 2022-12-30 合肥奎芯集成电路设计有限公司 Gate signal generating circuit of data gate signal and signal generating method thereof
CN116013394A (en) * 2023-01-10 2023-04-25 上海奎芯集成电路设计有限公司 Memory training circuit and memory training method
CN116312672A (en) * 2023-05-24 2023-06-23 长鑫存储技术有限公司 Command/address signal training mode circuit and memory
CN116720460A (en) * 2023-06-19 2023-09-08 海光信息技术股份有限公司 Training and determining method, system, equipment and medium for inserting gating clock
CN116595386A (en) * 2023-07-18 2023-08-15 芯耀辉科技有限公司 Training control method and system for memory

Also Published As

Publication number Publication date
CN117457041B (en) 2024-06-14

Similar Documents

Publication Publication Date Title
JP3987038B2 (en) Memory and adaptive timing system for controlling access to memory
US11430494B2 (en) DQS position adjustment method, controller and network device
CN1726560B (en) Two dimensional data eye centering for source synchronous data transfers
KR100902795B1 (en) Interface circuit
EP2189986B1 (en) Delay adjustment device, semiconductor device and delay adjustment method
US9105327B2 (en) Memory controller using a data strobe signal and method of calibrating data strobe signal in a memory controller
CN115547381B (en) Gate signal generating circuit of data gate signal and signal generating method thereof
US6760263B2 (en) Method and device for controlling data latch time
US10545866B1 (en) Method and system for efficient re-determination of a data valid window
CN112309452B (en) Method and related device for automatically calibrating data receiving window in prospect
CN115312092B (en) Gate-controlled data strobe signal generation circuit and signal generation method and device thereof
CN117457041B (en) Training device and training method suitable for gating clock signal
CA2538345A1 (en) Channel bonding of a plurality of multi-gigabit transceivers
CN116863980A (en) Dynamic adjusting circuit and method for gating signals
JP2013109637A (en) Memory interface circuit and operation method thereof
JP2003050739A (en) Memory controller
TWI521508B (en) Memory control circuit and method of controlling data reading process of memory module
CN116580743B (en) Memory read sampling circuit, delay adjusting method thereof and read sampling device
US10725681B2 (en) Method for calibrating the read latency of a DDR DRAM module
US11960895B2 (en) Method and control device for returning of command response information, and electronic device
US7836327B2 (en) Signal processing circuit for accessing a memory based on adjustable memory control clock
CN109144818B (en) Method and system for obtaining stability allowance of data bus interface
CN108345554B (en) Method for determining sampling phase of sampling clock signal and related electronic device
US6529570B1 (en) Data synchronizer for a multiple rate clock source and method thereof
CN115333667B (en) Method for adjusting time sequence and communication system

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant