CN117434357B - Angular load balance detection circuit - Google Patents
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- CN117434357B CN117434357B CN202311754012.9A CN202311754012A CN117434357B CN 117434357 B CN117434357 B CN 117434357B CN 202311754012 A CN202311754012 A CN 202311754012A CN 117434357 B CN117434357 B CN 117434357B
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- 238000001514 detection method Methods 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims abstract description 4
- 238000006243 chemical reaction Methods 0.000 claims description 13
- 230000002411 adverse Effects 0.000 description 1
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- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005485 electric heating Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/16—Measuring asymmetry of polyphase networks
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/02—Measuring effective values, i.e. root-mean-square values
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
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Abstract
The invention relates to the field of aviation deicing, in particular to an angular load balance detection circuit. The circuit comprises: 1) Load deviation acquisition circuit: according to the three-phase voltage and current effective values, load resistance deviation is obtained through an addition and subtraction operation circuit; 2) Self-detection circuit: the method is carried out under ideal conditions of input voltage balance and heating load balance, and is used for evaluating the accuracy of the self-acquisition of the controller, the result obtained by the load deviation acquisition circuit is directly compared with a set threshold value, and if the requirement is met, the deviation value in the mode is recorded; 3) System detection circuitry: the load deviation acquisition circuit is used for evaluating the actual load deviation under the actual use environment of the external field, comparing the result of the load deviation acquisition circuit with the set threshold value after the comprehensive operation of the deviation value record under the self-detection mode, and recording the deviation value under the mode.
Description
Technical Field
The invention relates to the field of aviation deicing, in particular to an angular load balance detection circuit.
Background
The angular load is widely used in the electric heating anti-icing field due to the characteristic of relatively small phase current. If the load is unbalanced, the aircraft power grid is adversely affected, and even the deicing unbalance of each phase of protection component can be caused to affect the aerodynamic characteristics. In addition, since the balance of the load tends to decrease gradually due to wear, aging, and the like during long-term use, it is necessary to periodically detect the angular load balance.
The accurate calculation of each phase current and each load resistor of the angular load relates to the acquisition of the phase voltage and the amplitude and the phase of the phase current, so that the implementation difficulty is high, and the approximate result meeting the engineering use requirement can be obtained through the calculation of the effective values of each phase voltage and each phase current. In the above operation process, arithmetic operations such as addition, subtraction, multiplication and division are involved, some parameters need to keep decimal parts in order to improve the accuracy of the result, and for a 51-series singlechip, the cost for completing the operations by using software is large, and certain errors are introduced due to calculation rounding and the like.
Disclosure of Invention
The invention aims to solve the technical problem of providing the angular load balance detection circuit, which can complete a main operation process by adopting a hardware circuit through effective values of phase voltage and phase current in an in-situ state and can solve the problems in the background art.
The technical scheme is as follows:
the invention provides an angular load balance detection circuit, comprising:
1) Load deviation acquisition circuit: according to the three-phase voltage and current effective values, load resistance deviation is obtained through an addition and subtraction operation circuit;
2) Self-detection circuit: the method is carried out under ideal conditions of input voltage balance and heating load balance, and is used for evaluating the accuracy of the self-acquisition of the controller, the result obtained by the load deviation acquisition circuit is directly compared with a set threshold value, and if the requirement is met, the deviation value in the mode is recorded;
3) System detection circuitry: the load deviation acquisition circuit is used for evaluating the actual load deviation under the actual use environment of the external field, comparing the result of the load deviation acquisition circuit with the set threshold value after the comprehensive operation of the deviation value record under the self-detection mode, and recording the deviation value under the mode.
Further, the effective value IB of the B-phase current is connected with one end of a resistor R1, and the other end of the resistor R1 is connected with the inverting input end of an operational amplifier U1B; the A-phase voltage effective value VA is connected with one end of a resistor R3, and the other end of the resistor R3 is connected with the inverting input end of an operational amplifier U1B; the phase A current effective value IA is connected with one end of a resistor R8, and the other end of the resistor R8 is connected with the non-inverting input end of an operational amplifier U1B; the B-phase voltage effective value VB is connected with one end of a resistor R6, and the other end of the resistor R6 is connected with the non-inverting input end of an operational amplifier U1B; a resistor R4 is arranged between the inverting input end of the operational amplifier U1B and GND; a resistor R5 is arranged between the non-inverting input end of the operational amplifier U1B and the reference voltage Vref, and a resistor R7 is arranged between the non-inverting input end of the operational amplifier U1B and GND; the inverting input end to the output end of the operational amplifier U1B are provided with a resistor R2; the output X1 of the operational amplifier U1B represents the difference between the AC phase load and the BC phase load;
the C-phase current effective value IC is connected with one end of a resistor R9, and the other end of the resistor R9 is connected with the inverting input end of an operational amplifier U2B; the B-phase voltage effective value VB is connected with one end of a resistor R11, and the other end of the resistor R11 is connected with the inverting input end of an operational amplifier U2B; the B-phase current effective value IB is connected with one end of a resistor R16, and the other end of the resistor R16 is connected with the non-inverting input end of an operational amplifier U2B; the C-phase voltage effective value VC is connected with one end of a resistor R14, and the other end of the resistor R14 is connected with the non-inverting input end of an operational amplifier U2B; a resistor R12 is arranged between the inverting input end of the operational amplifier U2B and GND; a resistor R13 is arranged between the non-inverting input end of the operational amplifier U2B and the reference voltage Vref, and a resistor R15 is arranged between the non-inverting input end of the operational amplifier U1B and GND; the inverting input end to the output end of the operational amplifier U2B are provided with a resistor R10; the output Y1 of the operational amplifier U2B represents the difference between the AB phase load and the AC phase load;
the phase A current effective value IA is connected with one end of a resistor R17, and the other end of the resistor R17 is connected with the inverting input end of an operational amplifier U3B; the C-phase voltage effective value VC is connected with one end of a resistor R19, and the other end of the resistor R19 is connected with the inverting input end of an operational amplifier U3B; the C-phase current effective value IC is connected with one end of a resistor R24, and the other end of the resistor R24 is connected with the non-inverting input end of an operational amplifier U3B; the A-phase voltage effective value VA is connected with one end of a resistor R22, and the other end of the resistor R22 is connected with the non-inverting input end of an operational amplifier U3B; a resistor R20 is arranged between the inverting input end of the operational amplifier U3B and GND; a resistor R21 is arranged between the non-inverting input end of the operational amplifier U3B and the reference voltage Vref, and a resistor R25 is arranged between the non-inverting input end of the operational amplifier U3B and GND; the inverting input end to the output end of the operational amplifier U3B are provided with a resistor R18; the output Z1 of the operational amplifier U3B represents the difference between the AB phase load and the BC phase load.
Further, the load deviation acquisition circuit is an addition and subtraction circuit formed based on an operational amplifier, and the input and output correspondence relationship is as follows:
；
wherein UA, UB, UC are effective values of three-phase input voltage after processing and conversion, IA, IB, IC are effective values of three-phase input current after processing and conversion.
Further, when r3=r6=r11=r14=r19=r22, r1=r8=r9=r16=r17=r24, r5=r13=r21, r2=r10=r18, the input-output correspondence is equivalent to:
X1=α(UB-UA)+β(IA-IB)+K；
Y1=α(UC-UB)+β(IB-IC)+K；
Z1=α(UA-UC)+β(IC-IA)+K；
wherein α=r2/R3, β=r2/R1, k= (R2/R5) Vref; and setting an offset through K pairs of deviation calculation results so as to facilitate unipolar input AD acquisition.
Further, the parameter beta in the load deviation acquisition circuit is the ratio of load deviation caused by load deviation to input current deviation under the condition that the input phase voltage is the same; the parameter alpha is the product of the input current deviation caused by the input voltage deviation and the input voltage deviation ratio under the condition of the same load and the parameter beta.
Further, the offset K is set to be the center point of the AD analog input range, so as to improve the acquisition accuracy.
Further, in the self-detection mode, setting three-phase input voltage effective values to be consistent and three-phase loads to be consistent; after AD conversion, X1, Y1 and Z1 are judged, and if the following conditions are satisfied, the self-detection is considered to pass:
|k-x1|≤γ；
|k-y1|≤γ；
|k-z1|≤γ；
wherein X1, Y1, Z1, K are respectively digital values after AD conversion of X1, Y1, Z1, K; gamma is a load deviation threshold caused by the acquisition precision of the product set by software;
when X1, Y1, and Z1 are determined and the following conditions are satisfied, the self-detection is considered to be passed, and three calculation values of xx1=k-X1, yy1=k-Y1, and zzz1=k-Z1 are stored.
Further, in the system detection mode, the X1, Y1, Z1 values acquired in real time are calculated with xx1, yy1, zz1 stored in the self-detection mode, and if the following conditions are satisfied, the detection is considered to pass:
|x1-k+xx1|≤δ；
|y1-k+yy1|≤δ；
|z1-k+zz1|≤δ；
where δ is the system allowable load bias for the software setting.
The invention has the beneficial effects that:
the invention can realize the approximate calculation of the load deviation through the phase voltage and the phase current collection, and the engineering realization difficulty is relatively low. The main operation is completed through a hardware circuit, so that the accuracy is higher, the instantaneity is better, and the cost of a processor is saved. The circuit and the method adopt a hardware circuit to collect the resistance deviation between any two phases of the angular load in real time, and then compare the resistance deviation with a threshold value to judge whether the load balance requirement is met. In order to eliminate interference caused by self acquisition errors, two working modes of self-detection and system detection are set, standard power supply voltage and standard load are used in the self-detection mode, and the difference of resistance values is recorded; and calculating and eliminating the resistance difference in the self-detection mode in the system detection mode to obtain an accurate result.
Drawings
Other features and advantages of the present invention will be better understood from the following detailed description of the preferred embodiment taken in conjunction with the accompanying drawings in which like reference characters identify the same or similar parts throughout, and in which:
fig. 1 is a circuit diagram of angular load bias acquisition.
Detailed Description
The making and using of the specific embodiments of the present invention are discussed in detail below with reference to the accompanying drawings. It should be understood, however, that the description herein of specific embodiments is merely illustrative of specific ways to make and use the invention, and does not limit the scope of the invention.
It should be noted that the directional representations of structures and actions, such as up, down, left, right, inner, outer, etc., used to explain various portions of the disclosed embodiments are not absolute, but rather relative. These representations are appropriate when the various portions of the disclosed embodiments are located in the positions shown in the figures. These representations are also changed according to the change in the position or frame of reference of the disclosed embodiments if the position or frame of reference of the disclosed embodiments is changed.
VA/VB/vc=actual voltage effective value, IA/IB/ic=actual current effective value, standard supply voltage effective value=115V, standard phase-to-phase load resistance value=10Ω.
The AD acquisition input voltage ranges from 0V to 10V, and corresponds to AD conversion to 0-1024, and the offset K=5.
α=0.15，β=0.58；
AD conversion error = +1%
Referring to fig. 1, a circuit and a method for detecting angular load balance, the circuit and the method include:
1) Load deviation acquisition circuit: according to the three-phase voltage and current effective values, load resistance deviation is obtained through an addition and subtraction operation circuit;
2) Self-detection: the method is carried out under ideal conditions (in-plant test environment) of input voltage balance and heating load balance, and is mainly used for evaluating the accuracy of the acquisition of the controller, the result obtained by the load deviation acquisition circuit is directly compared with a set threshold value, and if the requirement is met, the deviation value under the mode is recorded;
3) And (3) system detection: the load deviation acquisition circuit is used for evaluating the actual load deviation under the actual use environment of the external field, comparing the result of the load deviation acquisition circuit with the set threshold value after the comprehensive operation of the deviation value record under the self-detection mode, and recording the deviation value under the mode.
The three-phase current deviation is related to the load deviation and the input voltage deviation, and when the load deviation and the input voltage deviation change in a small range (the deviation value/basic value is less than or equal to 10 percent), the current deviation and the load deviation, and the current deviation and the input voltage deviation can be approximate to a proportional relation; when calculating the load deviation from the current deviation, it is necessary to eliminate the current deviation amount caused by the input voltage deviation.
The load deviation amount after the influence of the input voltage deviation is eliminated can be reflected by the load deviation amount obtained by the load deviation acquisition circuit:
X1=α(UB-UA)+β(IA-IB)+K；
Y1=α(UC-UB)+β(IB-IC)+K；
Z1=α(UA-UC)+β(IC-IA)+K；
the parameter beta is the ratio of load deviation to current deviation caused by the load deviation under the condition that the input phase voltage is the same; the parameter alpha is the product of the input current deviation caused by the input voltage deviation and the input voltage deviation ratio under the condition of the same load and the parameter beta.
Wherein the standard value of the power supply voltage is 115V/400Hz, and when the standard value of the load is 10Ω, the value of alpha is 0.15, and the value of beta is 0.58; the input voltage range of the AD converter is 0V-10V, the corresponding conversion AD value is 0-1023, and the K value is 5. The obtained X1/Y1/Z1 values represent the AC phase load deviation from the BC phase load deviation, the BC phase load deviation from the AB phase load deviation, the AB phase load deviation from the AC phase load deviation, respectively.
In order to eliminate errors caused by the acquisition circuit, setting three-phase input voltage effective values to be consistent and three-phase loads to be consistent in a self-detection mode; after AD conversion, X1, Y1 and Z1 are judged, and if the following conditions are satisfied, the self-detection is considered to pass:
|k-x1|≤γ；
|k-y1|≤γ；
|k-z1|≤γ；
wherein X1, Y1, Z1, K are respectively digital values after AD conversion of X1, Y1, Z1, K. And gamma is a load deviation threshold caused by the self-acquisition precision of a product set by software, and the value is 10, namely the allowable load deviation in a self-detection mode is 0.1 omega.
When X1, Y1, and Z1 are determined and the following conditions are satisfied, the self-detection is considered to be passed, and three calculation values of xx1=k-X1, yy1=k-Y1, and zzz1=k-Z1 are stored.
In the system detection mode, the X1, Y1 and Z1 values acquired in real time are calculated with xx1, yy1 and zz1 stored in the self-detection mode, and if the following conditions are met, the detection is considered to pass:
|x1-k+xx1|≤δ；
|y1-k+yy1|≤δ；
|z1-k+zz1|≤δ；
wherein delta is the allowable load deviation of the system set by software, and the value is 100, namely the allowable load deviation in the system detection mode is 1 omega.
Claims (7)
1. An angular load balance detection circuit, comprising:
1) Load deviation acquisition circuit: according to the three-phase voltage and current effective values, load resistance deviation is obtained through an addition and subtraction operation circuit;
2) Self-detection circuit: the method is carried out under ideal conditions of input voltage balance and heating load balance, and is used for evaluating the accuracy of the self-acquisition of the controller, the result obtained by the load deviation acquisition circuit is directly compared with a set threshold value, and if the requirement is met, the deviation value in the mode is recorded;
3) System detection circuitry: the method is carried out in an external field actual use environment, and is used for evaluating actual load deviation, comprehensively calculating the result of a load deviation acquisition circuit and the deviation value record in a self-detection mode, comparing the result with a set threshold value, and recording the deviation value in the mode;
the load deviation acquisition circuit comprises the following three sub-circuits;
for the B-phase subcircuit, a B-phase current effective value IB is connected with one end of a resistor R1, and the other end of the resistor R1 is connected with an inverting input end of an operational amplifier U1B; the A-phase voltage effective value VA is connected with one end of a resistor R3, and the other end of the resistor R3 is connected with the inverting input end of an operational amplifier U1B; the phase A current effective value IA is connected with one end of a resistor R8, and the other end of the resistor R8 is connected with the non-inverting input end of an operational amplifier U1B; the B-phase voltage effective value VB is connected with one end of a resistor R6, and the other end of the resistor R6 is connected with the non-inverting input end of an operational amplifier U1B; a resistor R4 is arranged between the inverting input end of the operational amplifier U1B and GND; a resistor R5 is arranged between the non-inverting input end of the operational amplifier U1B and the reference voltage Vref, and a resistor R7 is arranged between the non-inverting input end of the operational amplifier U1B and GND; the inverting input end to the output end of the operational amplifier U1B are provided with a resistor R2; the output X1 of the operational amplifier U1B represents the difference between the AC phase load and the BC phase load;
for the C-phase subcircuit, a C-phase current effective value IC is connected with one end of a resistor R9, and the other end of the resistor R9 is connected with an inverting input end of an operational amplifier U2B; the B-phase voltage effective value VB is connected with one end of a resistor R11, and the other end of the resistor R11 is connected with the inverting input end of an operational amplifier U2B; the B-phase current effective value IB is connected with one end of a resistor R16, and the other end of the resistor R16 is connected with the non-inverting input end of an operational amplifier U2B; the C-phase voltage effective value VC is connected with one end of a resistor R14, and the other end of the resistor R14 is connected with the non-inverting input end of an operational amplifier U2B; a resistor R12 is arranged between the inverting input end of the operational amplifier U2B and GND; a resistor R13 is arranged between the non-inverting input end of the operational amplifier U2B and the reference voltage Vref, and a resistor R15 is arranged between the non-inverting input end of the operational amplifier U1B and GND; the inverting input end to the output end of the operational amplifier U2B are provided with a resistor R10; the output Y1 of the operational amplifier U2B represents the difference between the AB phase load and the AC phase load;
for the phase A sub-circuit, the phase A current effective value IA is connected with one end of a resistor R17, and the other end of the resistor R17 is connected with the inverting input end of an operational amplifier U3B; the C-phase voltage effective value VC is connected with one end of a resistor R19, and the other end of the resistor R19 is connected with the inverting input end of an operational amplifier U3B; the C-phase current effective value IC is connected with one end of a resistor R24, and the other end of the resistor R24 is connected with the non-inverting input end of an operational amplifier U3B; the A-phase voltage effective value VA is connected with one end of a resistor R22, and the other end of the resistor R22 is connected with the non-inverting input end of an operational amplifier U3B; a resistor R20 is arranged between the inverting input end of the operational amplifier U3B and GND; a resistor R21 is arranged between the non-inverting input end of the operational amplifier U3B and the reference voltage Vref, and a resistor R25 is arranged between the non-inverting input end of the operational amplifier U3B and GND; the inverting input end to the output end of the operational amplifier U3B are provided with a resistor R18; the output Z1 of the operational amplifier U3B represents the difference between the AB phase load and the BC phase load.
2. The circuit of claim 1, wherein the load deviation acquisition circuit is an addition and subtraction circuit based on an operational amplifier, and the input-output correspondence relationship is:
；
wherein UA, UB, UC are effective values of three-phase input voltage after processing and conversion, IA, IB, IC are effective values of three-phase input current after processing and conversion.
3. The circuit of claim 2, wherein when r3=r6=r11=r14=r19=r22, r1=r8=r9=r16=r17=r24, r5=r13=r21, r2=r10=r18, the input-output correspondence is equivalent to:
X1=α(UB-UA)+β(IA-IB)+K；
Y1=α(UC-UB)+β(IB-IC)+K；
Z1=α(UA-UC)+β(IC-IA)+K；
wherein α=r2/R3, β=r2/R1, k= (R2/R5) Vref; and setting an offset through K pairs of deviation calculation results so as to facilitate unipolar input AD acquisition.
4. A circuit according to claim 3, wherein the parameter β in the load deviation acquisition circuit is the ratio of the load deviation caused by the load deviation to the input current deviation for the same input phase voltage; the parameter alpha is the product of the input current deviation caused by the input voltage deviation and the input voltage deviation ratio under the condition of the same load and the parameter beta.
5. The circuit of claim 4, wherein the offset K is set to the center point of the AD analog input range to improve acquisition accuracy.
6. The circuit of claim 5, wherein in the self-test mode, the three-phase input voltages are set to be identical in effective value and the three-phase loads are set to be identical in effective value; after AD conversion, X1, Y1 and Z1 are judged, and if the following conditions are satisfied, the self-detection is considered to pass:
|k-x1|≤γ；
|k-y1|≤γ；
|k-z1|≤γ；
wherein X1, Y1, Z1, K are respectively digital values after AD conversion of X1, Y1, Z1, K; gamma is a load deviation threshold caused by the acquisition precision of the product set by software;
when X1, Y1, and Z1 are determined and the following conditions are satisfied, the self-detection is considered to be passed, and three calculation values of xx1=k-X1, yy1=k-Y1, and zzz1=k-Z1 are stored.
7. The circuit of claim 6, wherein in the system detection mode, the X1, Y1, Z1 values acquired in real time are calculated with the xx1, yy1, zz1 values stored in the self-detection, and the detection is considered to pass if:
|x1-k+xx1|≤δ；
|y1-k+yy1|≤δ；
|z1-k+zz1|≤δ；
where δ is the system allowable load bias for the software setting.
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