CN117425335A - Storage system, manufacturing method thereof and electronic equipment - Google Patents
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- 238000003860 storage Methods 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 230000015654 memory Effects 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 239000000463 material Substances 0.000 claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims description 63
- 239000002131 composite material Substances 0.000 claims description 44
- 238000000034 method Methods 0.000 claims description 42
- 230000008569 process Effects 0.000 claims description 36
- 238000002360 preparation method Methods 0.000 claims description 33
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 10
- 238000004891 communication Methods 0.000 claims description 9
- 229910021332 silicide Inorganic materials 0.000 claims description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 9
- 238000013473 artificial intelligence Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 490
- 238000005516 engineering process Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 9
- 230000002411 adverse Effects 0.000 description 8
- 239000000470 constituent Substances 0.000 description 7
- 239000010408 film Substances 0.000 description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 230000002829 reductive effect Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 241000724291 Tobacco streak virus Species 0.000 description 1
- DZLPZFLXRVRDAE-UHFFFAOYSA-N [O--].[O--].[O--].[O--].[Al+3].[Zn++].[In+3] Chemical compound [O--].[O--].[O--].[O--].[Al+3].[Zn++].[In+3] DZLPZFLXRVRDAE-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Abstract
The memory system comprises a substrate, and a first structural layer, a second structural layer and a third structural layer which are sequentially stacked on the substrate, wherein the first structural layer comprises a processor circuit, the second structural layer comprises a control circuit, and the control circuit comprises at least one second transistor; the second transistor comprises a second active layer, the second active layer comprises a first contact area, a second contact area and a second channel area positioned between the first contact area and the second contact area, materials of the first contact area, the second contact area and the second channel area are the same, the third structure layer comprises a storage circuit, the processor circuit is electrically connected with the control circuit, and the control circuit is electrically connected with the storage circuit.
Description
Technical Field
Embodiments of the present disclosure relate to, but not limited to, the field of semiconductors, and in particular, to a memory system, a method for manufacturing the same, and an electronic device.
Background
The dynamic random access memory (DynamicRandomAccessMemory, DRAM) is a semiconductor memory, and compared with the static memory, the DRAM memory has the advantages of simpler structure, lower manufacturing cost and higher capacity density, and along with the development of the technology, the DRAM memory is increasingly widely applied.
With the development of internet technology, the amount of stored data is greatly increased, and the demands of high-bandwidth storage by HPC and AI chips are increased or decreased. Conventional high-bandwidth memories are based on conventional 2.5D packages, and are connected with a chip (DIE) through micro-scale silicon micro-nano holes (TSVs), so that it is difficult to further miniaturize the bandwidth and energy efficiency.
Disclosure of Invention
The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.
In a first aspect, an embodiment of the present disclosure provides a memory system, including a substrate, and a first structural layer, a second structural layer, and a third structural layer sequentially stacked on the substrate:
the first structural layer includes a processor circuit including a plurality of first transistors disposed on the substrate at intervals; the first transistor includes a first active layer including a first doped region, a second doped region, and a first channel region between the first doped region and the second doped region;
the second structural layer includes a control circuit including at least one second transistor; the second transistor comprises a second active layer, wherein the second active layer comprises a first contact region, a second contact region and a second channel region positioned between the first contact region and the second contact region, and the first contact region, the second contact region and the second channel region are made of the same semiconductor material;
The third structural layer includes a memory circuit including at least one memory cell including at least one third transistor; the third transistor comprises a third active layer, and the third active layer is an oxide semiconductor layer;
the processor circuit is electrically connected with the control circuit, and the control circuit is electrically connected with the storage circuit.
In an exemplary embodiment, the first transistor further includes:
a first gate electrode disposed on the first active layer, the first gate electrode being insulated from the first channel region;
a first gate insulating layer disposed between the first gate electrode and the first active layer;
the first electrode is arranged on the first doped region of the first active layer and is electrically connected with the first doped region; the second electrode is arranged on the second doped region of the first active layer and is electrically connected with the second doped region.
In an exemplary embodiment, the second transistor further includes:
a second gate electrode disposed on a second channel region of the second active layer, the second gate electrode being insulated from the second channel region;
A second gate insulating layer disposed between the second gate electrode and the second active layer;
a first contact layer disposed on the first contact region of the second active layer, the first contact layer being electrically connected to the first contact region;
a second contact layer disposed on a second contact region of the second active layer, the second contact layer being electrically connected to the second contact region;
a third electrode and a fourth electrode, wherein the third electrode is arranged on the first contact layer and is electrically connected with the first contact layer; the fourth electrode is arranged on the second contact layer and is electrically connected with the second contact layer.
In an exemplary embodiment, at least one of the first contact layer and the second contact layer includes a metal silicide layer.
In an exemplary embodiment, the second transistor further includes a sidewall disposed on a sidewall of the second gate electrode, the sidewall being located between the first contact layer and the sidewall of the second gate electrode, and between the second contact layer and the sidewall of the second gate electrode.
In an exemplary embodiment, the third transistor further includes:
a third gate electrode disposed between the second structural layer and the third active layer, the third gate electrode being insulated from the third active layer;
A third gate insulating layer disposed between the third gate electrode and the third active layer;
a third contact layer disposed on the third gate insulating layer and electrically connected to the first end of the third active layer;
the fourth contact layer is arranged on the third gate insulating layer and is electrically connected with the second end of the third active layer; the third contact layer and the fourth contact layer are disconnected from each other;
a fifth electrode and a sixth electrode, wherein the fifth electrode is arranged on the third contact layer and is electrically connected with the third contact layer; the sixth electrode is disposed on the fourth contact layer and electrically connected to the fourth contact layer.
In an exemplary embodiment, the first structural layer further includes a first composite insulating layer disposed on the substrate, the first composite insulating layer covering the processor circuit, the first composite insulating layer having a first nanopore disposed therein in communication with the processor circuit; the second structure layer further comprises a second composite insulating layer arranged on the first structure layer, the second composite insulating layer covers the control circuit, and a second nano hole communicated with the control circuit is arranged in the second composite insulating layer; the third structure layer further comprises a third composite insulating layer arranged on the second structure layer, the third composite insulating layer covers the storage circuit, a third nano hole communicated with the storage circuit is arranged in the third composite insulating layer, the first nano hole, the second nano hole and the third nano hole are sequentially communicated, and the control circuit is electrically connected with the processor circuit through the first nano hole and the second nano hole; the control circuit is electrically connected with the memory circuit through the second nano hole and the third nano hole.
In an exemplary embodiment, there is overlap in orthographic projections of the first, second, and third nanopores on the substrate.
In a second aspect, an embodiment of the disclosure further provides an electronic device, including the foregoing storage system.
In an exemplary embodiment, the electronic device comprises a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device, or a smart mobile terminal.
In a third aspect, embodiments of the present disclosure further provide a method for manufacturing a storage system, including:
forming a first structural layer on a substrate, the first structural layer comprising a processor circuit including a plurality of first transistors disposed on the substrate at intervals; the first transistor includes a first active layer including a first doped region, a second doped region, and a first channel region between the first doped region and the second doped region;
forming a second structural layer on the first structural layer, the second structural layer including a control circuit including at least one second transistor; the second transistor comprises a second active layer, wherein the second active layer comprises a first contact region, a second contact region and a second channel region positioned between the first contact region and the second contact region, and the first contact region, the second contact region and the second channel region are made of the same semiconductor material;
Forming a third structural layer on the second structural layer, the third structural layer including a memory circuit including at least one memory cell including at least one third transistor; the third transistor comprises a third active layer, and the third active layer is an oxide semiconductor layer;
the temperature required by the second structural layer preparation process is less than the temperature required by the first structural layer preparation process; the temperature required for the third structural layer preparation process is less than the temperature required for the second structural layer preparation process.
In an exemplary embodiment, forming a second structural layer on the first structural layer includes:
forming a semiconductor structure layer, and doping the semiconductor structure layer to form a doped pattern;
bonding the semiconductor structure layer with the first structure layer, removing undoped parts in the semiconductor structure layer through a patterning process, and reserving doped patterns to enable the doped patterns to form a second active layer;
forming a second gate insulating layer on the second active layer;
forming a dummy gate layer on the second gate insulating layer;
forming a first contact layer and a second contact layer on the second active layer, the first contact layer being electrically connected to a first contact region of the second active layer, the second contact layer being electrically connected to a second contact region of the second active layer;
Removing the dummy gate layer and forming a second gate electrode on the second gate insulating layer;
and forming a third electrode on the first contact layer, forming a fourth electrode on the second contact layer, wherein the third electrode is electrically connected with the first contact layer, and the fourth electrode is electrically connected with the second contact layer.
According to the storage system, the PN junction is formed by forming the doped region in the first active layer, then the second transistor of the second structural layer is formed through the junction-free CMOS technology, so that the PN junction is not formed in the second active layer of the second transistor, namely, the first contact region and the second contact region are both made of the same material as the second channel region, the temperature required by the preparation technology of the second structural layer is smaller than that required by the preparation technology of the first structural layer, and adverse effects on the first structural layer due to high temperature generated in the process of forming the second structural layer on the first structural layer are avoided.
According to the memory system, the third active layer of the third transistor is made of the oxide semiconductor, so that the temperature required by the preparation process of the third structural layer is smaller than that required by the preparation process of the second structural layer, and adverse effects on the second structural layer caused by high temperature generated in the process of forming the third structural layer on the second structural layer are avoided.
According to the storage system, the second structural layer is formed on the first structural layer, and the third structural layer is formed on the second structural layer, so that the processor circuit is electrically connected with the control circuit, and the control circuit is electrically connected with the storage circuit, the preparation process is simplified, and the production cost is reduced.
Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.
Drawings
The accompanying drawings are included to provide an understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.
FIG. 1 is a cross-sectional view of a storage system according to an embodiment of the present application;
FIG. 2 is a cross-sectional view of a first structural layer of a memory system according to an embodiment of the present application;
FIG. 3 is a cross-sectional view of a second structural layer of a memory system according to an embodiment of the present application;
FIG. 4 is a cross-sectional view of a third structural layer of a memory system according to an embodiment of the present application;
FIG. 5a is a schematic diagram of a semiconductor structure layer after forming a doped pattern during the manufacturing process of the memory system according to the embodiment of the present application;
FIG. 5b is a schematic diagram of a memory system according to an embodiment of the present disclosure after forming a second active layer during the fabrication process;
FIG. 5c is a schematic diagram of a memory system according to an embodiment of the present application after forming a dummy gate layer during the fabrication process;
FIG. 5d is a schematic diagram of a memory system according to an embodiment of the present disclosure after forming a first contact layer and a second contact layer during the fabrication process;
fig. 5e is a schematic diagram of the memory system according to the embodiment after forming the second gate electrode in the process of manufacturing the memory system.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail hereinafter with reference to the accompanying drawings. Note that embodiments may be implemented in a number of different forms. One of ordinary skill in the art will readily recognize the fact that the manner and content may be changed into a variety of forms without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure should not be construed as being limited to the following description of the embodiments. Embodiments of the present disclosure and features of embodiments may be combined with each other arbitrarily without conflict.
In the drawings, the size of each constituent element, the thickness of a layer, or a region may be exaggerated for clarity. Accordingly, one aspect of the present disclosure is not necessarily limited to this dimension, and the shapes and sizes of the various components in the drawings do not reflect actual proportions. Further, the drawings schematically show ideal examples, and one mode of the present disclosure is not limited to the shapes or numerical values shown in the drawings, and the like.
The ordinal numbers of "first", "second", "third", etc. in the present specification are provided to avoid mixing of constituent elements, and are not intended to be limited in number.
In the present specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, which indicate an azimuth or a positional relationship, are used to describe positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or elements referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus are not to be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the respective constituent elements are described. Therefore, the present invention is not limited to the words described in the specification, and may be appropriately replaced according to circumstances.
In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly, unless explicitly stated or limited otherwise. For example, it may be a fixed connection, a removable connection, or an integral connection; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art in the specific context.
In this specification, a transistor means an element including at least three terminals of a second gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (also referred to as a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (also referred to as a source electrode terminal, a source region, or a source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region through which current mainly flows.
In this specification, the first electrode mentioned below may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In practical applications, which of the first electrode and the second electrode is the source electrode and which is the drain electrode is related to the current flow, and in general, the current flows from the source to the drain. In the case of using a transistor having opposite polarity, or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other.
In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having a certain electric action, such as a physical connection relationship, or a signal connection relationship. The "element having a certain electric action" is not particularly limited as long as it can be an electric signal between constituent elements that can be connected. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.
In the present specification, the following parallel or perpendicular is about parallel and about perpendicular within an error range. "parallel" refers to a state in which two straight lines form an angle of-10 ° or more and 10 ° or less, and therefore, a state in which the angle is-5 ° or more and 5 ° or less is also included. The term "vertical" refers to a state in which an angle formed by two straight lines is 80 ° or more and 100 ° or less, and thus includes a state in which an angle is 85 ° or more and 95 ° or less.
In this specification, "film" and "layer" may be exchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". In the same manner, the "insulating film" may be replaced with the "insulating layer" in some cases.
The term "about" in this disclosure refers to values that are not strictly limited to the limits, but are allowed to fall within the limits of the process and measurement errors.
The embodiment of the application provides a storage system, which comprises a substrate and a first structural layer, a second structural layer and a third structural layer which are sequentially stacked on the substrate:
the first structural layer includes a processor circuit including a plurality of first transistors disposed on the substrate at intervals; the first transistor includes a first active layer including a first doped region, a second doped region, and a first channel region between the first doped region and the second doped region;
The second structural layer includes a control circuit including at least one second transistor; the second transistor comprises a second active layer, wherein the second active layer comprises a first contact region, a second contact region and a second channel region positioned between the first contact region and the second contact region, and the first contact region, the second contact region and the second channel region are made of the same semiconductor material;
the third structural layer includes a memory circuit including at least one memory cell including at least one; the third transistor comprises a third active layer, and the third active layer is an oxide semiconductor layer;
the processor circuit is electrically connected with the control circuit, and the control circuit is electrically connected with the storage circuit.
According to the storage system, the PN junction is formed by forming the doped region in the first active layer, then the second transistor of the second structural layer is formed through the junction-free CMOS technology, so that the PN junction is not formed in the second active layer of the second transistor, namely, the first contact region and the second contact region are both made of the same material as the second channel region, the temperature required by the preparation technology of the second structural layer is smaller than that required by the preparation technology of the first structural layer, and adverse effects on the first structural layer due to high temperature generated in the process of forming the second structural layer on the first structural layer are avoided.
According to the memory system, the third active layer of the third transistor is made of the oxide semiconductor, so that the temperature required by the preparation process of the third structural layer is smaller than that required by the preparation process of the second structural layer, and adverse effects on the second structural layer caused by high temperature generated in the process of forming the third structural layer on the second structural layer are avoided.
According to the storage system, the second structural layer is formed on the first structural layer, and the third structural layer is formed on the second structural layer, so that the processor circuit is electrically connected with the control circuit, and the control circuit is electrically connected with the storage circuit, the preparation process is simplified, and the production cost is reduced.
FIG. 1 is a cross-sectional view of a storage system according to an embodiment of the present application. In an exemplary embodiment, as shown in fig. 1, the memory system of the embodiment of the present application includes a substrate 40, and a first structural layer 30, a second structural layer 10, and a third structural layer 20 sequentially stacked on the substrate 40. The first structural layer 30 comprises processor circuitry, the second structural layer 10 comprises control circuitry, and the third structural layer 20 comprises memory circuitry. The processor circuit of the first structural layer can be used for receiving and operating the stored data, the control circuit of the second structural layer is used for providing control signals for the storage circuit of the third structural layer so as to control the storage circuit to store the data, and the storage circuit of the third structural layer can store the data.
In an exemplary embodiment, as shown in fig. 1, the first structural layer 30 is stacked on the substrate 40, and the processor circuit of the first structural layer 30 includes a plurality of first transistors 31 disposed on the substrate 40, the plurality of first transistors 31 being arranged at intervals along a first direction (direction X) parallel to the substrate 40, the plurality of first transistors 31 being electrically connected in sequence to form a Central Processing Unit (CPU).
In an exemplary embodiment, as shown in fig. 1, the second structural layer 10 is stacked on the first structural layer 30, and the control circuit of the second structural layer 10 includes at least one second transistor 100 disposed on the first structural layer 30. The second structural layer 10 includes, for example, a plurality of second transistors 100, the plurality of second transistors 100 being arranged at intervals along a first direction (direction X) parallel to the substrate 40, the plurality of second transistors 100 being electrically connected in turn.
In an exemplary embodiment, as shown in fig. 1, the third structural layer 20 is stacked on the second structural layer 10, and the memory circuit of the third structural layer 20 includes at least one memory cell, and illustratively, the third structural layer 20 includes a plurality of memory cells arranged at intervals along the first direction (direction X), and the plurality of memory cells are sequentially connected in series. Each memory cell comprises at least one third transistor 21. For example, the memory cell may have a 2T0C structure, and the memory cell includes two third transistors 21, one third transistor 21 as a read transistor and one third transistor 21 as a write transistor. The third transistor 21 of the third structural layer 20 may be connected to the second transistor 100 of the second structural layer 10, enabling the second transistor 100 to control the third transistor 21 for storage.
In an exemplary embodiment, as shown in fig. 1, a first nanopore 41 is provided in the first structural layer 30 in communication with the processor circuit, e.g., the first nanopore 41 may be in communication with the first transistor 31 of the processor circuit. The second structure layer 10 is provided therein with a second nanopore 42 in communication with a control circuit, for example, the second nanopore 42 may be in communication with a second transistor 100 of the control circuit. The third structure layer 20 is provided therein with a third nanopore 43 in communication with a memory circuit, for example, the third nanopore 43 may be in communication with a third transistor 21 of the memory circuit. The first nano hole 41, the second nano hole 42 and the third nano hole 43 are sequentially communicated, and the control circuit is connected with the processor circuit through the first nano hole 41 and the second nano hole 42; the control circuit is connected to the memory circuit through the second nanopore 42 and the third nanopore 43.
According to the storage system, the second structural layer is formed on the first structural layer, and the third structural layer is formed on the second structural layer, so that the processor circuit is electrically connected with the control circuit, and the control circuit is electrically connected with the storage circuit, the preparation process is simplified, and the production cost is reduced.
FIG. 2 is a cross-sectional view of a first structural layer of a memory system according to an embodiment of the present application. In an exemplary embodiment, as shown in fig. 2, the processor circuit of the first structural layer 30 includes first and second first transistors 31a and 31b disposed on the substrate 40 at intervals, the first and second first transistors 31a and 31b are arranged at intervals along a first direction (direction X) parallel to the substrate 40, and electrodes of the first transistors 31a are connected to electrodes of the second first transistors 31b through first connection holes 61, so that the first and second first transistors 31a and 31b are electrically connected to each other. Wherein the first connection hole 61 extends along a first direction (direction X) parallel to the substrate 40.
In the exemplary embodiment, the structure of the first transistor is described with the first transistor 31a as an example. As shown in fig. 2, the first transistor 31a includes a first active layer 301 disposed on the substrate 40, a first gate electrode 302, a first electrode 303, and a second electrode 304 disposed on the first active layer 301.
In an exemplary embodiment, as shown in fig. 2, the first active layer 301 includes a first channel region 3013, and first and second doped regions 3011 and 3012 located at opposite sides of the first channel region 3013. The first active layer 301 has a PN junction therein, for example, the material of the first channel region 3013 may be an N-type semiconductor, and the materials of the first and second doped regions 3011 and 3012 may be P-type semiconductors; alternatively, the material of the first channel region 3013 may be a P-type semiconductor, and the material of the first and second doped regions 3011 and 3012 may be an N-type semiconductor.
In an exemplary embodiment, as shown in fig. 2, the first gate electrode 302 is located on a side of the first active layer 301 away from the substrate 40, overlapping with a front projection of the first channel region 3013 of the first active layer 301 on the substrate 40, a first gate insulating layer 305 is disposed between the first gate electrode 302 and the first channel region 3013 of the first active layer 301, and the first gate electrode 302 is insulated from the first channel region 3013 by the first gate insulating layer 305.
In an exemplary embodiment, as shown in fig. 2, the first electrode 303 is located on a side of the first active layer 301 remote from the substrate 40, and the first electrode 303 is disposed on the first doping region 3011 and electrically connected to the first doping region 3011. The second electrode 304 is located on a side of the first active layer 301 away from the substrate 40, and the second electrode 304 is disposed on the second doped region 3012 and electrically connected to the second doped region 3012.
In an exemplary embodiment, as shown in fig. 2, the first structural layer 30 of the memory system of the embodiment further includes a first composite insulating layer 51 disposed on the substrate 40, the first composite insulating layer 51 covering the first and second first transistors 31a and 31b. The second structural layer 10 is disposed on the first composite insulating layer 51.
In an exemplary embodiment, as shown in fig. 2, a first nano-hole 41 is disposed in a first composite insulating layer 51 of the memory system of the embodiment of the present application, the first nano-hole 41 extends along a second direction (direction Z) perpendicular to a substrate 40, the first nano-hole 41 overlaps with a front projection of a first connection hole 61 on the substrate, and the first nano-hole 41 extends from a surface of the first composite insulating layer 51 away from the side of the substrate 40 to the first connection hole 61 and communicates with the first connection hole 61.
FIG. 3 is a cross-sectional view of a second structural layer of a memory system according to an embodiment of the present application. In an exemplary embodiment, as shown in fig. 3, the second structural layer 10 is disposed on the first composite insulating layer 51 of the first structural layer 30 in a stacked manner. The control circuit of the second structural layer 10 includes first and second transistors 11 and 12 disposed on the first composite insulating layer 51 at intervals, the first and second transistors 11 and 12 being arranged at intervals along a first direction (direction X) parallel to the substrate 40.
In the exemplary embodiment, the structure of the second transistor is described with the first and second transistors 11 as an example. As shown in fig. 3, the first and second transistors 11 include a second active layer 101 disposed on the first composite insulating layer 51, a second gate electrode 102, a first contact layer 103, and a second contact layer 104 disposed on the second active layer 101, and a third electrode 13 and a fourth electrode 14 disposed on the first contact layer 103 and the second contact layer 104.
In an exemplary embodiment, as shown in fig. 3, the second active layer 101 includes a first channel region 1013, and a first contact region 1011 and a second contact region 1012 located at opposite sides of the first channel region 1013. The first contact region 1011, the second contact region 1012 and the first channel region 1013 in the second active layer 101 are made of the same semiconductor material, i.e. the second active layer 101 has no PN junction therein. For example, the first contact region 1011, the second contact region 1012, and the first channel region 1013 each employ an N-type semiconductor or a P-type semiconductor.
In an exemplary embodiment, as shown in fig. 3, the second gate electrode 102 is located at a side of the second active layer 101 away from the substrate 40, overlapping with a front projection of the first channel region 1013 of the second active layer 101 in the substrate 40, and the second gate insulating layer 105 is disposed between the second gate electrode 102 and the first channel region 1013 of the second active layer 101, and the second gate electrode 102 is insulated from the first channel region 1013 by the second gate insulating layer 105.
In an exemplary embodiment, as shown in fig. 3, the first and second transistors 11 of the memory system of the embodiment of the present application may be formed using a HKMG (High-kmetal) manufacturing process, thereby improving circuit performance. The second gate electrode 102 is made of a metal material, and the second gate insulating layer 105 is made of a high dielectric constant material.
In an exemplary embodiment, as shown in fig. 3, the first contact layer 103 is disposed on the first contact region 1011 of the second active layer 101, and is electrically connected to the first contact region 1011. The second contact layer 104 is disposed on the second contact region 1012 of the second active layer 101 and is electrically connected to the second contact region 1012.
In an exemplary embodiment, as shown in fig. 3, the third electrode 13 is located at a side of the first contact layer 103 away from the substrate 40, and is electrically connected to the first contact layer 103. The fourth electrode 14 is located on a side of the second contact layer 104 away from the substrate 40 and is electrically connected to the second contact layer 104.
In an exemplary embodiment, as shown in fig. 3, at least one of the first contact layer 103 and the second contact layer 104 includes a metal silicide layer 108. The first contact layer 103 and the second contact layer 104 each include a semiconductor material layer 107 and a metal silicide layer 108 which are stacked, the semiconductor material layer 107 being connected to the second active layer 101, the metal silicide layer 108 being disposed on a side of the semiconductor material layer 107 remote from the second active layer 101.
The memory system of the embodiment of the present application can reduce parasitic resistances between the third electrode 13 and the first contact layer 103 and between the fourth electrode 14 and the second contact layer 104 through the metal silicide layer 108.
In an exemplary embodiment, as shown in fig. 3, the first second transistor 11 further includes a sidewall 106, where the sidewall 106 is disposed on a sidewall of the second gate electrode 102, and the sidewall 106 is located between a sidewall of the second gate electrode 102 and the first contact layer 103, and between a sidewall of the second gate electrode 102 and the second contact layer 104, for isolating the second gate electrode 102 from the first contact layer 103 and the second contact layer 104, and isolating the second gate electrode 102 from the first contact layer 103 and the second contact layer 104.
In an exemplary embodiment, as shown in fig. 3, the structure of the second transistor 12 may be the same as that of the first second transistor 11, and this embodiment will not be described herein.
In an exemplary embodiment, the first and second transistors 11 and 12 may be Metal-Oxide-semiconductor field-EffectTransistor, MOSFET and Effect Transistor (MOSFET), respectively.
According to the storage system, the PN junction is formed by forming the doped region in the first active layer, and then the second transistor of the second structural layer is formed through the junction-free CMOS technology, so that the PN junction is not formed in the second active layer of the second transistor, the temperature required by the preparation technology of the second structural layer is smaller than that required by the preparation technology of the first structural layer, and the adverse effect on the first structural layer caused by high temperature generated in the process of forming the second structural layer on the first structural layer is avoided.
In an exemplary embodiment, as shown in fig. 3, the second structural layer 10 of the memory system of the embodiment of the present application further includes a second composite insulating layer 52 disposed on the first composite insulating layer 51, the second composite insulating layer 52 covering the first and second transistors 11 and 12. The third structural layer 20 is disposed on the second composite insulating layer 52.
In an exemplary embodiment, as shown in fig. 3, a second nanopore 42 is disposed in a second composite insulating layer 52 of the memory system of the embodiment of the present application, the second nanopore 42 extends along a second direction (direction Z) perpendicular to the substrate 40, the second nanopore 42 does not overlap with an orthographic projection of the first second transistor 11 and the second transistor 12 on the substrate, and the second nanopore 42 overlaps with and communicates with an orthographic projection of the first nanopore 41 on the substrate. The second nanopore 42 penetrates the second composite insulating layer 52 from the surface of the second composite insulating layer 52 on the side far away from the substrate 40, and extends to the surface of the second composite insulating layer 52 on the side close to the substrate 40, and is communicated with the first nanopore 41.
In an exemplary embodiment, as shown in fig. 3, the third electrode 13 of the first and second transistors 11 communicates with the second nanohole 42 through the second connection hole 62. Wherein the second connection hole 62 extends along a first direction (direction X) parallel to the substrate 40.
In an exemplary embodiment, the first and second transistors 11 and 12 in the second structural layer can be formed by a CMOS process having a low process temperature (process temperature +.500℃ C.) without affecting the first structural layer.
FIG. 4 is a cross-sectional view of a third structural layer of a memory system of an embodiment of the present application. In an exemplary embodiment, as shown in fig. 4, a third structural layer 20 is disposed on the second structural layer 10 in a stacked manner. The memory circuit of the third structural layer 20 includes at least one memory cell including first and second third transistors 21a and 21b disposed on the second structural layer 10 at intervals, the first and second third transistors 21a and 21b being arranged at intervals along a first direction (direction X) parallel to the substrate 40.
In the exemplary embodiment, the structure of the third transistor is described with the first third transistor 21a as an example. As shown in fig. 4, the first third transistor 21a includes a third gate electrode 202 disposed on the second structural layer 10, a third gate insulating layer 205 disposed on the third gate electrode 202, and third active layer 201, third contact layer 203, and fourth contact layer 204 disposed on the third gate insulating layer 205. The third gate electrode 202 is insulated from the third active layer 201, the third contact layer 203, and the fourth contact layer 204, respectively, by a third gate insulating layer 205. The third gate electrode 202 overlaps with the orthographic projection of the third active layer 201 on the substrate 40. The third contact layer 203 and the fourth contact layer 204 are located at opposite sides of the third active layer 201 in the first direction (direction X), and a portion of the third contact layer 203 is disposed on the first end of the third active layer 201 and electrically connected to the first end of the third active layer 201. The fourth contact layer 204 is disposed on the second end of the third active layer 201 and connected to the second end of the third active layer 201. The third contact layer 203 and the fourth contact layer 204 are disconnected from each other and are respectively located at two sides of the third active layer 201.
In an exemplary embodiment, the third active layer 201 is an oxide semiconductor layer. The oxide semiconductor may be Indium Gallium Zinc Oxide (IGZO), indium Aluminum Zinc Oxide (IAZO), indium oxide, zinc oxide, or the like.
In the memory system of the embodiment of the present application, the third active layer 201 is an oxide semiconductor, so that the third transistor has a low leakage current, thereby greatly improving the data retention time and the readout speed of the memory cell.
According to the memory system, the third active layer of the third transistor is made of the oxide semiconductor, so that the temperature required by the preparation process of the third structural layer is smaller than that required by the preparation process of the second structural layer, and adverse effects on the second structural layer caused by high temperature generated in the process of forming the third structural layer on the second structural layer are avoided.
In an exemplary embodiment, as shown in fig. 4, the first third transistor 21a further includes a fifth electrode 15 and a sixth electrode 16, and the fifth electrode 15 is located on a side of the third contact layer 203 away from the substrate 40 and is electrically connected to the third contact layer 203. The sixth electrode 16 is located on a side of the fourth contact layer 204 away from the substrate 40 and is electrically connected to the fourth contact layer 204.
In an exemplary embodiment, as shown in fig. 4, the third structural layer 20 of the memory system of the embodiment further includes a third composite insulating layer 53 disposed on the second composite insulating layer 52, the third composite insulating layer 53 covering the first and second third transistors 21a and 21b.
In an exemplary embodiment, as shown in fig. 4, a third nanopore 43 is disposed in a third composite insulating layer 53 of the memory system of the embodiment of the present application, the third nanopore 43 extends along a second direction (direction Z) perpendicular to the substrate 40, the third nanopore 43 does not overlap with an orthographic projection of the first third transistor 21a and the second third transistor 21b on the substrate, and the third nanopore 43 overlaps with and communicates with an orthographic projection of the second nanopore 42 on the substrate. The third nanopore 43 extends from the surface of the third composite insulating layer 53 on the side away from the substrate 40, penetrates through the third composite insulating layer 53, and extends to the surface of the third composite insulating layer 53 on the side close to the substrate 40, and is communicated with the second nanopore 42.
In an exemplary embodiment, as shown in fig. 3, the fifth electrode 15 of the first third transistor 21a communicates with the third nanopore 43 through the third connection hole 63. Wherein the third connection hole 63 extends along a first direction (direction X) parallel to the substrate 40.
In an exemplary embodiment, the memory unit of the memory system of the embodiment of the present application may adopt a 2T0C structure. The preparation process of the memory unit is compatible with BEOL, and the memory unit has no capacitance, so that the influence of a capacitance high-temperature process on the second structural layer can be avoided.
The first nano hole, the second nano hole and the third nano hole in the storage system are all nano through holes, so that the integration level of the storage system can be improved, and higher bandwidth storage is realized.
The embodiment of the application also provides a manufacturing method of the storage system, which comprises the following steps:
forming a first structural layer on a substrate, the first structural layer comprising a processor circuit including a plurality of first transistors disposed on the substrate at intervals; the first transistor includes a first active layer including a first doped region, a second doped region, and a first channel region between the first doped region and the second doped region;
forming a second structural layer on the first structural layer, the second structural layer including a control circuit including at least one second transistor; the second transistor comprises a second active layer, wherein the second active layer comprises a first contact region, a second contact region and a second channel region positioned between the first contact region and the second contact region, and the first contact region, the second contact region and the second channel region are made of the same semiconductor material;
Forming a third structural layer on the second structural layer, the third structural layer including a memory circuit including at least one memory cell including at least one third transistor; the third transistor comprises a third active layer, and the third active layer is an oxide semiconductor layer;
the temperature required by the second structural layer preparation process is less than the temperature required by the first structural layer preparation process; the temperature required for the third structural layer preparation process is less than the temperature required for the second structural layer preparation process.
In an exemplary embodiment, forming a second structural layer on the first structural layer includes:
forming a semiconductor structure layer, doping in the semiconductor structure layer, and forming at least one doping pattern;
bonding the semiconductor structure layer with the first structure layer, and forming a second active layer by a doping pattern of the semiconductor structure layer through a patterning process;
forming a second gate insulating layer on the second active layer;
forming a second gate electrode on the second gate insulating layer, wherein the second gate electrode overlaps with a second channel region of the second active layer in orthographic projection of the substrate;
Forming a first contact layer and a second contact layer on the second active layer, the first contact layer being electrically connected to a first contact region of the second active layer, the second contact layer being electrically connected to a second contact region of the second active layer;
and forming a third electrode on the first contact layer, forming a fourth electrode on the second contact layer, wherein the third electrode is electrically connected with the first contact layer, and the fourth electrode is electrically connected with the second contact layer.
The manufacturing method of the memory system of the present application is achieved by making the temperature required for the second structural layer manufacturing process less than the temperature required for the first structural layer manufacturing process; the temperature required by the third structural layer preparation process is less than the temperature required by the second structural layer preparation process, so that the adverse effect on the first structural layer caused by the high temperature generated in the process of forming the second structural layer on the first structural layer and the adverse effect on the second structural layer caused by the high temperature generated in the process of forming the third structural layer on the second structural layer are avoided.
The following is an exemplary description of the fabrication process of the memory system of the present application.
The "patterning process" in the embodiments of the present disclosure includes processes of coating photoresist, mask exposure, development, etching, stripping photoresist, etc. for metallic materials, inorganic materials, or transparent conductive materials, and processes of coating organic materials, mask exposure, development, etc. for organic materials. The deposition may be any one or more of sputtering, evaporation, chemical vapor deposition, coating may be any one or more of spraying, spin coating, and ink jet printing, and etching may be any one or more of dry etching and wet etching, without limitation of the disclosure. "film" refers to a layer of film made by depositing, coating, or other process of a material on a substrate. The "film" may also be referred to as a "layer" if the "film" does not require a patterning process throughout the fabrication process. If the "thin film" requires a patterning process throughout the fabrication process, it is referred to as a "thin film" prior to the patterning process, and as a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern".
In an exemplary embodiment, a method of preparing a storage system may include:
(1) A first structural layer is formed. The first structural layer includes a processor circuit including a plurality of first transistors disposed on the substrate at intervals; the first transistor includes a first active layer 301 disposed on the substrate 40, a first gate electrode 302, a first electrode 303, and a second electrode 304 disposed on the first active layer 301, the first active layer 301 including a first channel region 3013, and first and second doped regions 3011 and 3012 located on opposite sides of the first channel region 3013. The first active layer 301 has a PN junction therein as shown in fig. 2.
(2) A second structural layer is formed over the first structural layer.
In an exemplary embodiment, forming the second structural layer on the first structural layer includes: firstly, doping is carried out in the semiconductor structure layer 1, the doped part in the semiconductor structure layer 1 forms a doped pattern 2, for example, N-type doping and P-type doping are respectively carried out in the semiconductor structure layer 1, so that the doped pattern 2 is formed on the N-type doped part and the P-type doped part of the semiconductor structure layer 1, wherein the doped concentration of the N-type doping and the doped concentration of the P-type doping can be 1 multiplied by 10 18 cm -3 Up to 1X 10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the An inorganic dielectric layer 3 covering the doping pattern 2 is formed on the semiconductor construction layer 1, and the material of the inorganic dielectric layer may be silicon dioxide as shown in fig. 5 a.
Subsequently, the semiconductor structure layer with the doped pattern is bonded with the first structure layer 30 at low temperature by using an interlayer insulating medium, the undoped portion of the semiconductor structure layer and the inorganic medium layer are removed by using a patterning process (such as grinding, thinning, etc.), and the doped pattern is remained, so that the doped pattern forms a second active layer 101 disposed on the first structure layer 30, as shown in fig. 5 b; the second active layer 101 includes a first channel region 1013, and a first contact region 1011 and a second contact region 1012 located at opposite sides of the first channel region 1013. The first contact region 1011, the second contact region 1012 and the first channel region 1013 in the second active layer 101 are made of the same semiconductor material, i.e. the second active layer 101 has no PN junction therein. For example, the first contact region 1011, the second contact region 1012, and the first channel region 1013 each employ an N-type semiconductor or a P-type semiconductor.
Subsequently, a second gate insulating layer 105 is formed on the second active layer 101, the second gate insulating layer 105 overlapping with the orthographic projection of the first channel region 1013 on the substrate 40; forming a dummy gate layer 4 on the second gate insulating layer 105, the dummy gate layer 4 being insulated from the first channel region 1013 by the second gate insulating layer 105; forming a side wall 106 on the side wall of the dummy gate layer 4; as shown in fig. 5 c. The second gate insulating layer 105 is prepared by adopting a plasma enhanced chemical vapor deposition method (PlasmaEnhancedChemicalVapor Deposition, abbreviated as PECVD), and the preparation temperature of the second gate insulating layer 105 is less than or equal to 400 ℃; the dummy gate layer 4 is prepared by adopting a low-pressure chemical vapor deposition method (LowPressureChemical VaporDeposition, LPCVD for short), and the preparation temperature of the dummy gate layer 4 is less than or equal to 400 ℃; the side wall 106 is prepared by adopting a plasma enhanced chemical vapor deposition (PlasmaEnhanced ChemicalVaporDeposition, PECVD for short), and the preparation temperature of the side wall 106 is less than or equal to 400 ℃.
Subsequently, a semiconductor material layer 107 is formed on the first contact region 1011 and the second contact region 1012 of the second active layer 101, respectively, a metal silicide layer 108 is formed on the semiconductor material layer 107, for example, metal nickel is deposited on the semiconductor material layer 107, and an annealing process (300 degrees celsius to 400 degrees celsius) is performed to form a nickel silicide layer to reduce parasitic resistance; as shown in fig. 5 d. Wherein the semiconductor material layer 107 and the metal silicide layer 108 on the first contact region 1011 form the first contact layer 103; the semiconductor material layer 107 and the metal silicide layer 108 on the second contact region 1012 form the second contact layer 104; the semiconductor material layer 107 may be a P-type semiconductor layer or an N-type semiconductor layer with a doping concentration of 1×10 20 cm -3 Up to 1X 10 21 cm -3 。
Subsequently, the dummy gate layer 4 is removed, and a second gate electrode 102 is formed on the second gate insulating layer 105, as shown in fig. 5 e. The second gate electrode 102 is made of a metal material, and the second gate insulating layer 105 is made of a high dielectric constant material.
Subsequently, a third electrode 13 is formed on the first contact layer 103, the third electrode 13 being electrically connected to the first contact layer 103; forming a fourth electrode 14 on the second contact layer 104, the fourth electrode 14 being electrically connected to the second contact layer 104; the second active layer 101, the second gate electrode 102, the first contact layer 103, the second contact layer 104, the third electrode 13, and the fourth electrode 14 form a second transistor; subsequently, a second composite insulating layer 52 is formed on the first structural layer, the second composite insulating layer 52 covering the second transistor, and a second nanopore 42 is formed in the second composite insulating layer 52 such that the second nanopore 42 communicates with the first nanopore 41, as shown in fig. 3.
A third structural layer is formed over the second structural layer. The third structural layer 20 includes a memory circuit including at least one memory cell including at least one third transistor including a third gate electrode 202 disposed on the second structural layer 10, a third gate insulating layer 205 disposed on the third gate electrode 202, and third active layer 201, third contact layer 203, and fourth contact layer 204 disposed on the third gate insulating layer 205. The third gate electrode 202 is insulated from the third active layer 201, the third contact layer 203, and the fourth contact layer 204, respectively, by a third gate insulating layer 205. The third gate electrode 202 overlaps with the orthographic projection of the third active layer 201 on the substrate 40. The third contact layer 203 and the fourth contact layer 204 are located at opposite sides of the third active layer 201 in the first direction (direction X), and a portion of the third contact layer 203 is disposed on the first end of the third active layer 201 and electrically connected to the first end of the third active layer 201. The fourth contact layer 204 is disposed on the second end of the third active layer 201 and connected to the second end of the third active layer 201. The third contact layer 203 and the fourth contact layer 204 are disconnected from each other and are respectively located at two sides of the third active layer 201, as shown in fig. 4. Wherein the third active layer 201 is an oxide semiconductor layer.
The manufacturing method of the storage system has good process compatibility, simple process implementation, easy implementation, high production efficiency, low production cost and high yield.
The embodiment of the application also provides electronic equipment, which comprises the storage system. The embodiment of the application does not particularly limit the specific form of the electronic device. The electronic equipment comprises a smart phone, a computer, a tablet personal computer, an artificial intelligent device, a wearable device or an intelligent mobile terminal.
The drawings in the present disclosure relate only to the structures to which the present disclosure relates, and other structures may be referred to in general. Features of embodiments of the present disclosure, i.e., embodiments, may be combined with one another to arrive at a new embodiment without conflict.
It will be understood by those skilled in the art that various modifications and equivalent substitutions may be made to the disclosed embodiments without departing from the spirit and scope of the disclosed embodiments, which are intended to be encompassed within the scope of the appended claims.
Claims (12)
1. A memory system comprising a substrate and a first structural layer, a second structural layer, and a third structural layer sequentially stacked on the substrate:
The first structural layer includes a processor circuit including a plurality of first transistors disposed on the substrate at intervals; the first transistor includes a first active layer including a first doped region, a second doped region, and a first channel region between the first doped region and the second doped region;
the second structural layer includes a control circuit including at least one second transistor; the second transistor comprises a second active layer, wherein the second active layer comprises a first contact region, a second contact region and a second channel region positioned between the first contact region and the second contact region, and the first contact region, the second contact region and the second channel region are made of the same semiconductor material;
the third structural layer includes a memory circuit including at least one memory cell including at least one third transistor; the third transistor comprises a third active layer, and the third active layer is an oxide semiconductor layer;
the processor circuit is electrically connected with the control circuit, and the control circuit is electrically connected with the storage circuit.
2. The memory system of claim 1, wherein the first transistor further comprises:
a first gate electrode disposed on the first active layer, the first gate electrode being insulated from the first channel region;
a first gate insulating layer disposed between the first gate electrode and the first active layer;
the first electrode is arranged on the first doped region of the first active layer and is electrically connected with the first doped region; the second electrode is arranged on the second doped region of the first active layer and is electrically connected with the second doped region.
3. The memory system of claim 1, wherein the second transistor further comprises:
a second gate electrode disposed on a second channel region of the second active layer, the second gate electrode being insulated from the second channel region;
a second gate insulating layer disposed between the second gate electrode and the second active layer;
a first contact layer disposed on the first contact region of the second active layer, the first contact layer being electrically connected to the first contact region;
a second contact layer disposed on a second contact region of the second active layer, the second contact layer being electrically connected to the second contact region;
A third electrode and a fourth electrode, wherein the third electrode is arranged on the first contact layer and is electrically connected with the first contact layer; the fourth electrode is arranged on the second contact layer and is electrically connected with the second contact layer.
4. The memory system of claim 3, wherein at least one of the first contact layer and the second contact layer comprises a metal silicide layer.
5. The memory system of claim 3, wherein the second transistor further comprises a sidewall disposed on a sidewall of the second gate electrode, the sidewall being between the first contact layer and the sidewall of the second gate electrode, and between the second contact layer and the sidewall of the second gate electrode.
6. The memory system of claim 1, wherein the third transistor further comprises:
a third gate electrode disposed between the second structural layer and the third active layer, the third gate electrode being insulated from the third active layer;
a third gate insulating layer disposed between the third gate electrode and the third active layer;
a third contact layer disposed on the third gate insulating layer and electrically connected to the first end of the third active layer;
The fourth contact layer is arranged on the third gate insulating layer and is electrically connected with the second end of the third active layer; the third contact layer and the fourth contact layer are disconnected from each other;
a fifth electrode and a sixth electrode, wherein the fifth electrode is arranged on the third contact layer and is electrically connected with the third contact layer; the sixth electrode is disposed on the fourth contact layer and electrically connected to the fourth contact layer.
7. The memory system of any one of claims 1 to 6, wherein the first structural layer further comprises a first composite insulating layer disposed on the substrate, the first composite insulating layer covering the processor circuit, the first composite insulating layer having a first nanopore disposed therein in communication with the processor circuit; the second structure layer further comprises a second composite insulating layer arranged on the first structure layer, the second composite insulating layer covers the control circuit, and a second nano hole communicated with the control circuit is arranged in the second composite insulating layer; the third structure layer further comprises a third composite insulating layer arranged on the second structure layer, the third composite insulating layer covers the storage circuit, a third nano hole communicated with the storage circuit is arranged in the third composite insulating layer, the first nano hole, the second nano hole and the third nano hole are sequentially communicated, and the control circuit is electrically connected with the processor circuit through the first nano hole and the second nano hole; the control circuit is electrically connected with the memory circuit through the second nano hole and the third nano hole.
8. The memory system of claim 7, wherein there is overlap in orthographic projections of the first nanopore, the second nanopore, and the third nanopore on the substrate.
9. An electronic device comprising a storage system as claimed in any one of claims 1 to 8.
10. The electronic device of claim 9, wherein the electronic device comprises a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a smart mobile terminal.
11. A method of manufacturing a memory system, comprising:
forming a first structural layer on a substrate, the first structural layer comprising a processor circuit including a plurality of first transistors disposed on the substrate at intervals; the first transistor includes a first active layer including a first doped region, a second doped region, and a first channel region between the first doped region and the second doped region;
forming a second structural layer on the first structural layer, the second structural layer including a control circuit including at least one second transistor; the second transistor comprises a second active layer, wherein the second active layer comprises a first contact region, a second contact region and a second channel region positioned between the first contact region and the second contact region, and the first contact region, the second contact region and the second channel region are made of the same semiconductor material;
Forming a third structural layer on the second structural layer, the third structural layer including a memory circuit including at least one memory cell including at least one third transistor; the third transistor comprises a third active layer, and the third active layer is an oxide semiconductor layer;
the temperature required by the second structural layer preparation process is less than the temperature required by the first structural layer preparation process; the temperature required for the third structural layer preparation process is less than the temperature required for the second structural layer preparation process.
12. The method of manufacturing a memory system according to claim 11, wherein forming a second structural layer on the first structural layer comprises:
forming a semiconductor structure layer, and doping the semiconductor structure layer to form a doped pattern;
bonding the semiconductor structure layer with the first structure layer, removing undoped parts in the semiconductor structure layer through a patterning process, and reserving doped patterns to enable the doped patterns to form a second active layer;
forming a second gate insulating layer on the second active layer;
forming a dummy gate layer on the second gate insulating layer;
Forming a first contact layer and a second contact layer on the second active layer, the first contact layer being electrically connected to a first contact region of the second active layer, the second contact layer being electrically connected to a second contact region of the second active layer;
removing the dummy gate layer and forming a second gate electrode on the second gate insulating layer;
and forming a third electrode on the first contact layer, forming a fourth electrode on the second contact layer, wherein the third electrode is electrically connected with the first contact layer, and the fourth electrode is electrically connected with the second contact layer.
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