CN117424655A - Phased array antenna channel reverse-beating testing method and device based on vector network - Google Patents
Phased array antenna channel reverse-beating testing method and device based on vector network Download PDFInfo
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- H04B17/10—Monitoring; Testing of transmitters
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- H04B17/12—Monitoring; Testing of transmitters for calibration of transmit antennas, e.g. of the amplitude or phase
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04B17/00—Monitoring; Testing
- H04B17/20—Monitoring; Testing of receivers
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Abstract
The application relates to a phased array antenna channel reverse-driving test method and device based on a vector network, wherein the method comprises the following steps: acquiring input parameters; setting the number of scanning points of a vector network according to a vector synthesis mode, setting a scanning mode of the vector network as a single-frequency point scanning mode, and configuring a triggering mode of the vector network as triggering acquisition after receiving an acquisition instruction of an upper computer; determining a current test channel and a current test frequency point; setting the current test frequency point as an execution frequency point of a vector network single frequency point scanning mode; determining a current phase code, and controlling a phase shifter and an attenuator of a TR module under a current test channel according to the current phase code; traversing all phase codes, and after finishing the control of the phase shifter and the attenuator according to the phase codes each time, sending an acquisition instruction to a vector network to enable the vector network to store vector data radiated by a current channel; traversing all the test frequency points and all the test channels to obtain standard vector data of all the test channels under all the frequency points.
Description
Technical Field
The application relates to the technical field of phased array antenna calibration, in particular to a phased array antenna channel reverse-driving test method and device based on a vector network.
Background
Phased array antennas have evolved from array antennas, relying primarily on phase changes to effect movement or scanning of the antenna beam pointing in space. Phased array antennas are made up of a plurality of antenna elements, also known as radiators. The antenna elements may be individual waveguide horns, dipoles, patch antennas, etc. A phase shifter is provided at the rear end of each antenna element for changing the phase relationship of the signals between the elements, the amplitude variation of the signals being achieved by a power splitting, summing network or attenuator.
In the whole phased array antenna wave control system, a distributed operation method is commonly used. The basic idea of the distributed operation method is that the wave control motherboard receives a control instruction from the radar subsystem, and the subarray operation processing module calculates wave control codes (namely amplitude phase codes) in real time according to the control instruction, and theoretical phase calibration codes (namely amplitude phase compensation data) are needed for calculating the wave control codes. In practical engineering implementation, due to the limitations of conditions such as assembly, processing technology and the like, certain amplitude gain and phase offset inconsistency exists among array element channels, and the phased array antenna is sensitive to the inconsistency of the channels, and when a system is designed, the inconsistency data is processed into amplitude-phase compensation data so as to reduce the influence of the inconsistency data on the performance of the phased array antenna, and the data is required to be obtained in a standard darkroom environment through practical acquisition and algorithm processing. In the calibration process, each channel unit needs to be normalized, under the condition that the units are unchanged, the amplitude of other units is further adjusted and analyzed (the finally obtained code is the amplitude compensation code), and meanwhile, the theoretical phase value of each unit is guaranteed to be 0 (the finally obtained code is the phase compensation code), so that when the adjustment is carried out, the phase of each unit is guaranteed to be in the same period, and the adjusted data can be guaranteed to be as accurate as possible. However, due to device variability between units and modules, the actual calibration results may not fully meet the theoretical or target values, and therefore, continuous calibration verification or iterative calibration may be required, which is a relatively long time.
Specifically, after the control of the phase shifter and the attenuator is completed in the existing channel reverse-beating test flow, mark points on the vector network are required to be set, then views corresponding to amplitude and phase values on the vector network are repeatedly switched, and the frequency of the mark points on the views is set. Therefore, the process is complex, a certain buffer time is needed for the vector network, and the corresponding vector data on the vector network can be collected and synthesized after time delay. Although the delay time may be only 100ms, when the number of channels to be tested, the number of frequency points, and the number of test phase states required for vector synthesis are increased, the time consumed by the final engineering test is greatly increased.
Disclosure of Invention
In order to at least overcome the problem that the time consumption of a channel reverse-beating test flow for calibrating the phased-array antenna in the related technology is long to a certain extent, the application provides a phased-array antenna channel reverse-beating test method and device based on a vector network.
The scheme of the application is as follows:
according to a first aspect of an embodiment of the present application, there is provided a phased array antenna channel reverse-driving test method based on a vector network, including:
acquiring input parameters;
setting the number of scanning points of a vector network according to a vector synthesis mode, setting a scanning mode of the vector network as a single-frequency point scanning mode, and configuring a triggering mode of the vector network as triggering acquisition after receiving an acquisition instruction of an upper computer;
determining a current test channel and a current test frequency point;
setting the current test frequency point as an execution frequency point of a vector network single frequency point scanning mode;
determining a current phase code, and controlling a phase shifter and an attenuator of a TR module under a current test channel according to the current phase code;
traversing all phase codes, and after finishing the control of the phase shifter and the attenuator according to the phase codes each time, sending an acquisition instruction to a vector network to enable the vector network to store vector data radiated by a current channel;
traversing all the test frequency points, and acquiring all vector data under each test frequency point of the current test channel from a vector network;
synthesizing all vector data of the current test channel based on a preset algorithm to obtain standard vector data of the current test channel at each frequency point;
traversing all the test channels to obtain standard vector data of all the test channels under each frequency point.
Preferably, the input parameters include: and analyzing the amplitude phase compensation data after the compensation, the number of test frequency points needing the back-beating and corresponding coordinate points of each channel on the scanning frame.
Preferably, the vector data comprises an amplitude value and a phase value.
Preferably, the preset algorithm is a PhaseToggle algorithm.
Preferably, all vector data under each test frequency point of the current test channel are obtained from a vector network, and the method further comprises:
the vector data is grouped according to a vector synthesis scheme.
Preferably, after determining the current test channel, the method further comprises:
the current channel is powered up.
Preferably, after powering up the current channel, the method further comprises:
and based on the coordinate points corresponding to the channels on the scanning frame, the probes on the scanning frame are corresponding to the position right above the current channel.
Preferably, all vector data under each test frequency point of the current test channel are obtained from a vector network, and the method further comprises:
the current channel is powered down.
According to a second aspect of embodiments of the present application, there is provided a phased array antenna channel reverse run test apparatus based on a vector network, including:
a processor and a memory;
the processor is connected with the memory through a communication bus:
the processor is used for calling and executing the program stored in the memory;
the memory is used for storing a program, and the program is at least used for executing a phased array antenna channel reverse-driving test method based on a vector network.
The technical scheme that this application provided can include following beneficial effect: the phased array antenna channel reverse-driving testing method based on the vector network comprises the following steps: acquiring input parameters; setting the number of scanning points of a vector network according to a vector synthesis mode, setting a scanning mode of the vector network as a single-frequency point scanning mode, and configuring a triggering mode of the vector network as triggering acquisition after receiving an acquisition instruction of an upper computer; determining a current test channel and a current test frequency point; setting the current test frequency point as an execution frequency point of a vector network single frequency point scanning mode; determining a current phase code, and controlling a phase shifter and an attenuator of a TR module under a current test channel according to the current phase code; traversing all phase codes, and after finishing the control of the phase shifter and the attenuator according to the phase codes each time, sending an acquisition instruction to a vector network to enable the vector network to store vector data radiated by a current channel; traversing all the test frequency points, and acquiring all vector data under each test frequency point of the current test channel from a vector network; synthesizing all vector data of the current test channel based on a preset algorithm to obtain standard vector data of the current test channel at each frequency point; traversing all the test channels to obtain standard vector data of all the test channels under each frequency point. According to the technical scheme, the existing phased array antenna channel reverse-beating test flow is improved, the problem that the time consumption is long because the calibration verification quantity is large and the verification speed is low is solved for a large phased array antenna, mark points on a vector network are not set after the phase shifter and the attenuator are controlled according to the phase code every time, and subsequent complex flow is not required to be executed, so that the buffer time of the vector network is skipped. According to the technical scheme, the purpose of saving test flow time is achieved through joint control of the upper computer and the vector network, and the time consumed in the test process is reduced by utilizing the characteristic that the vector network analyzer can store data.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic flow chart of a phased array antenna channel reverse-driving test method based on a vector network according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a conventional channel reverse run test flow provided in one embodiment of the present application;
fig. 3 is a schematic flow chart of another phased array antenna channel reverse-driving test method based on a vector network according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a phased array antenna channel reverse-driving test device based on a vector network according to an embodiment of the present application.
Reference numerals: a processor-21; and a memory 22.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
Example 1
Fig. 1 is a flow chart of a phased array antenna channel reverse-driving test method based on a vector network according to an embodiment of the present invention, and referring to fig. 1, a phased array antenna channel reverse-driving test method based on a vector network includes:
s11: acquiring input parameters;
s12: setting the number of scanning points of a vector network according to a vector synthesis mode, setting a scanning mode of the vector network as a single-frequency point scanning mode, and configuring a triggering mode of the vector network as triggering acquisition after receiving an acquisition instruction of an upper computer;
s13: determining a current test channel and a current test frequency point;
s14: setting the current test frequency point as an execution frequency point of a vector network single frequency point scanning mode;
s15: determining a current phase code, and controlling a phase shifter and an attenuator of a TR module under a current test channel according to the current phase code;
s16: traversing all phase codes, and after finishing the control of the phase shifter and the attenuator according to the phase codes each time, sending an acquisition instruction to a vector network to enable the vector network to store vector data radiated by a current channel;
s17: traversing all the test frequency points, and acquiring all vector data under each test frequency point of the current test channel from a vector network;
s18: synthesizing all vector data of the current test channel based on a preset algorithm to obtain standard vector data of the current test channel at each frequency point;
s19: traversing all the test channels to obtain standard vector data of all the test channels under each frequency point.
It should be noted that, the technical solution in this embodiment relates to the technical field of phased array antenna calibration, and is specifically applied to the near field calibration process of the active phased array antenna.
The input parameters include: and analyzing the amplitude phase compensation data after the compensation, the number of test frequency points needing the back-beating and corresponding coordinate points of each channel on the scanning frame.
It should be noted that, the number of vector network scan points is set according to the vector synthesis method, specifically, the number of vector network scan points is set to 2 according to the vector synthesis method n-1 N is the number of vectors required in the vector synthesis scheme. For example, the one-way quantity synthesis only needs to set 1 point, the two-way quantity synthesis needs 2 points, and so on, the four-vector synthesis needs 4 points.
In this embodiment, the scanning mode of the vector network is set to be the single-frequency point scanning mode, so that the time for setting mark points to repeatedly switch the view of the vector network can be reduced when collecting data required for vector synthesis.
It should be noted that, in this embodiment, the trigger mode of configuring the vector network is to trigger the collection after receiving the collection instruction of the upper computer, or may be said to be a "manual trigger" mode, in which the collection instruction may be sent to the vector network through the outside (upper computer), and then the vector network spontaneously records the vector data at the current time point.
And subsequently, entering a main test flow, performing traversal test according to the channel serial number, and sending an instruction to the wave control motherboard by the upper computer in the test, thereby controlling the circuit switch of the corresponding channel.
It should be noted that, after determining the current test channel, the method further includes:
the current channel is powered up.
After powering up the current channel, the method further comprises:
and based on the coordinate points corresponding to the channels on the scanning frame, the probes on the scanning frame are corresponding to the position right above the current channel.
The vector data includes an amplitude value and a phase value.
In specific practice, the preset algorithm is a PhaseToggle algorithm.
It can be understood that the PhaseToggle algorithm is a genetic algorithm, and can reduce the coupling effect between channels as much as possible, so as to obtain the standard amplitude value and the standard phase value under each frequency point of each channel.
It should be noted that, after all vector data under each test frequency point of the current test channel are obtained from the vector network, the method further includes:
the vector data is grouped according to a vector synthesis scheme.
In this embodiment, the four-vector combining method is taken as an example, and the number of vector network scan points set according to the four-vector combining method is 4, so that the vector network stores 4 sets of vector data for the 4 scan points.
It should be noted that, after all vector data under each test frequency point of the current test channel are obtained from the vector network, the method further includes:
the current channel is powered down.
It will be appreciated that after the vector data acquisition of the current test channel is completed, the current test channel needs to be powered down to start the vector data acquisition of the next test channel.
It should be noted that, fig. 2 is a schematic diagram of a conventional channel reverse-beating test flow, referring to fig. 2, after the control of the phase shifter and the attenuator is completed in the conventional channel reverse-beating test flow, mark points on the vector network need to be set, then views corresponding to the amplitude and the phase values are displayed on the vector network are repeatedly switched, and the frequency of the mark points on the views is set. Therefore, the process is complex, a certain buffer time is needed for the vector network, and the corresponding vector data on the vector network can be collected and synthesized after time delay. Although the delay time may be only 100ms, when the number of channels to be tested, the number of frequency points, and the number of test phase states required for vector synthesis are increased, the time consumed by the final engineering test is greatly increased.
In this embodiment, after the phase shifter and the attenuator are controlled according to the phase code each time, mark points on the vector network are not set, and a subsequent complex process is not required to be executed, so that the buffer time of the vector network is skipped. According to the technical scheme, the purpose of saving test flow time is achieved through joint control of the upper computer and the vector network, and the time consumed in the test process is reduced by utilizing the characteristic that the vector network analyzer can store data.
Example two
A phased array antenna path reverse run test apparatus based on a vector network, with reference to fig. 4, comprising:
a processor 21 and a memory 22;
the processor 21 is connected to the memory 22 via a communication bus:
wherein the processor 21 is used for calling and executing the program stored in the memory 22;
the memory 22 is configured to store a program, where the program is at least configured to execute one of the phased array antenna channel reverse run test methods based on the vector network in the above embodiments.
It is to be understood that the same or similar parts in the above embodiments may be referred to each other, and that in some embodiments, the same or similar parts in other embodiments may be referred to.
It should be noted that in the description of the present application, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present application, unless otherwise indicated, the meaning of "plurality" means at least two.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and further implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present application.
It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, and where the program, when executed, includes one or a combination of the steps of the method embodiments.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product.
The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, or the like.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives, and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.
Claims (9)
1. A phased array antenna channel reverse-driving test method based on a vector network is characterized by comprising the following steps:
acquiring input parameters;
setting the number of scanning points of a vector network according to a vector synthesis mode, setting a scanning mode of the vector network as a single-frequency point scanning mode, and configuring a triggering mode of the vector network as triggering acquisition after receiving an acquisition instruction of an upper computer;
determining a current test channel and a current test frequency point;
setting the current test frequency point as an execution frequency point of a vector network single frequency point scanning mode;
determining a current phase code, and controlling a phase shifter and an attenuator of a TR module under a current test channel according to the current phase code;
traversing all phase codes, and after finishing the control of the phase shifter and the attenuator according to the phase codes each time, sending an acquisition instruction to a vector network to enable the vector network to store vector data radiated by a current channel;
traversing all the test frequency points, and acquiring all vector data under each test frequency point of the current test channel from a vector network;
synthesizing all vector data of the current test channel based on a preset algorithm to obtain standard vector data of the current test channel at each frequency point;
traversing all the test channels to obtain standard vector data of all the test channels under each frequency point.
2. The method of claim 1, wherein the input parameters comprise: and analyzing the amplitude phase compensation data after the compensation, the number of test frequency points needing the back-beating and corresponding coordinate points of each channel on the scanning frame.
3. The method of claim 1, wherein the vector data comprises an amplitude value and a phase value.
4. The method of claim 1, wherein the predetermined algorithm is a PhaseToggle algorithm.
5. The method of claim 1, wherein all vector data for each test frequency point of the current test channel is obtained from a vector network, the method further comprising:
the vector data is grouped according to a vector synthesis scheme.
6. The method of claim 2, wherein after determining the current test channel, the method further comprises:
the current channel is powered up.
7. The method of claim 6, wherein after powering up the current channel, the method further comprises:
and based on the coordinate points corresponding to the channels on the scanning frame, the probes on the scanning frame are corresponding to the position right above the current channel.
8. The method of claim 1, wherein all vector data for each test frequency point of the current test channel is obtained from a vector network, the method further comprising:
the current channel is powered down.
9. A phased array antenna path reverse run test apparatus based on a vector network, comprising:
a processor and a memory;
the processor is connected with the memory through a communication bus:
the processor is used for calling and executing the program stored in the memory;
the memory is configured to store a program, where the program is configured to at least perform a phased array antenna channel reverse run test method based on a vector network as claimed in any one of claims 1 to 8.
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109541558A (en) * | 2018-09-30 | 2019-03-29 | 航天恒星科技有限公司 | A kind of calibration method of whole process total system Active Phase-Array Radar target seeker |
| CN110794222A (en) * | 2019-10-23 | 2020-02-14 | 上海霍莱沃电子***技术股份有限公司 | Antenna test system and control method thereof |
| CN112202509A (en) * | 2020-09-17 | 2021-01-08 | 湖北航天技术研究院总体设计所 | Phased array seeker front end frequency conversion calibration compensation system |
| CN114895269A (en) * | 2022-05-12 | 2022-08-12 | 四川九洲电器集团有限责任公司 | Multichannel phased array TR assembly amplitude-phase consistency test system and test method |
| CN115561531A (en) * | 2022-11-10 | 2023-01-03 | 成都华芯天微科技有限公司 | Phased array antenna multi-beam channel calibration system |
| WO2023010707A1 (en) * | 2021-08-06 | 2023-02-09 | 北京航天长征飞行器研究所 | Fast calibration test system and method for phased-array antenna |
| CN115712097A (en) * | 2022-11-15 | 2023-02-24 | 中国电子科技集团公司第三十八研究所 | Radar active module test system and test method |
| CN116165618A (en) * | 2023-03-03 | 2023-05-26 | 零八一电子集团有限公司 | Testing method and system for automatic acquisition of active phased array radar array surface amplitude and phase data |
| CN116208265A (en) * | 2023-05-06 | 2023-06-02 | 北京中科睿信科技有限公司 | Calibration method, device and medium for active phased array antenna |
| CN116633457A (en) * | 2023-05-09 | 2023-08-22 | 中国舰船研究设计中心 | Dual-polarized phased array field intensity calibration system and method |
| CN116643095A (en) * | 2023-03-13 | 2023-08-25 | 中国电子科技集团公司第十研究所 | Phased array antenna pattern testing system and method |
-
2023
- 2023-12-19 CN CN202311746075.XA patent/CN117424655B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109541558A (en) * | 2018-09-30 | 2019-03-29 | 航天恒星科技有限公司 | A kind of calibration method of whole process total system Active Phase-Array Radar target seeker |
| CN110794222A (en) * | 2019-10-23 | 2020-02-14 | 上海霍莱沃电子***技术股份有限公司 | Antenna test system and control method thereof |
| CN112202509A (en) * | 2020-09-17 | 2021-01-08 | 湖北航天技术研究院总体设计所 | Phased array seeker front end frequency conversion calibration compensation system |
| WO2023010707A1 (en) * | 2021-08-06 | 2023-02-09 | 北京航天长征飞行器研究所 | Fast calibration test system and method for phased-array antenna |
| CN114895269A (en) * | 2022-05-12 | 2022-08-12 | 四川九洲电器集团有限责任公司 | Multichannel phased array TR assembly amplitude-phase consistency test system and test method |
| CN115561531A (en) * | 2022-11-10 | 2023-01-03 | 成都华芯天微科技有限公司 | Phased array antenna multi-beam channel calibration system |
| CN116106642A (en) * | 2022-11-10 | 2023-05-12 | 成都华芯天微科技有限公司 | Trigger type phased array antenna multi-beam channel calibration system |
| CN115712097A (en) * | 2022-11-15 | 2023-02-24 | 中国电子科技集团公司第三十八研究所 | Radar active module test system and test method |
| CN116165618A (en) * | 2023-03-03 | 2023-05-26 | 零八一电子集团有限公司 | Testing method and system for automatic acquisition of active phased array radar array surface amplitude and phase data |
| CN116643095A (en) * | 2023-03-13 | 2023-08-25 | 中国电子科技集团公司第十研究所 | Phased array antenna pattern testing system and method |
| CN116208265A (en) * | 2023-05-06 | 2023-06-02 | 北京中科睿信科技有限公司 | Calibration method, device and medium for active phased array antenna |
| CN116633457A (en) * | 2023-05-09 | 2023-08-22 | 中国舰船研究设计中心 | Dual-polarized phased array field intensity calibration system and method |
Non-Patent Citations (1)
| Title |
|---|
| 杨顺平: "平面近场诊断在相控阵天线通道幅相性能测试中的应用", 《 电讯技术》, 28 December 2019 (2019-12-28) * |
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