CN117422037A - Training method for automatic layout model of simulation chip and automatic layout method - Google Patents
Training method for automatic layout model of simulation chip and automatic layout method Download PDFInfo
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Abstract
The invention relates to the technical field of design of simulation chips, and provides a training method and an automatic layout method for an automatic layout model of a simulation chip. According to the training method, an automatic layout model of the simulation chip configured in each target layout intelligent body can be obtained, a decentralization layout decision is realized, the layout efficiency and the layout effect of the subsequent simulation chip can be improved, and a layout result with the performance equivalent to that of the manual layout can be obtained in second-level time on the premise of not needing a large amount of layout data, so that the automatic layout is realized, the wiring of the subsequent simulation chip is facilitated, and convenience is provided for the rapid production and the batch application of the simulation chip.
Description
Technical Field
The invention relates to the technical field of simulation chip design, in particular to a simulation chip automatic layout model training method and an automatic layout method.
Background
In the process of designing an analog chip, the layout of the analog chip is a crucial link. Layout refers to the process of placing individual devices (e.g., transistors, capacitors, resistors, etc.) in the corresponding metal layers of an analog chip to achieve the functional and performance requirements of the circuit. The quality of the analog chip layout directly affects the performance, power consumption, noise characteristics, and overall reliability of the circuit.
Analog chip layout faces many challenges. First, analog circuits are generally sensitive to interactions and locations between electronic components, so analog chip layout must meet specific requirements of circuit designers, such as maintaining low noise, minimizing power supply jitter, and maximizing circuit bandwidth. Secondly, there are a large number of interconnect lines in the analog circuit, and the lengths, shapes and positions of these interconnect lines all lead to parasitic parameters of different degrees, which affect the circuit performance, so that accurate layout and position planning are required. Furthermore, analog circuits often need to take into account symmetry placement between devices, and therefore, devices that appear in pairs need to be laid out reasonably during the analog chip layout process to reduce unwanted coupling and interference.
However, the existing simulation chip layout process has the problems of long running time of automatic layout, poor usability of layout results and the like, and the simulation chip layout has low efficiency and poor layout effect.
Disclosure of Invention
The invention provides an automatic layout model training method and an automatic layout method for a simulation chip, which are used for solving the defects in the prior art.
The invention provides a training method for an automatic layout model of a simulation chip, which comprises the following steps:
acquiring sample information of a simulation chip sample, and determining each sample layout intelligent agent corresponding to the simulation chip sample, a sample layout environment of the simulation chip sample and an initial state of each sample layout intelligent agent based on the sample information; each sample layout agent is used for characterizing one or more devices in the analog chip sample;
inputting the initial state of each sample layout intelligent agent into a corresponding strategy network to obtain an initial prediction action of each sample layout intelligent agent, and inputting the initial state and the initial prediction action of each sample layout intelligent agent into a value network to obtain a value result corresponding to each sample layout intelligent agent;
based on each sample layout agent, interacting the corresponding initial prediction action with the sample layout environment, calculating the total return value corresponding to each sample layout agent, and calculating a loss function based on the value result and the total return value corresponding to each sample layout agent;
Based on the loss function, carrying out iterative updating on the structural parameters of each strategy network and each value network, and taking each trained strategy network as an automatic layout model of the simulation chip configured in one target layout intelligent body.
According to the training method for the automatic layout model of the simulation chip, the sample information comprises sample constraint information, sample netlist information, symmetry information of each device in a sample of the simulation chip and size information of each sample layout intelligent body; based on the sample information, determining each sample layout agent corresponding to the analog chip sample, a sample layout environment of the analog chip sample, and an initial state of each sample layout agent, including:
based on symmetry information of devices in the simulation chip sample, at least two devices with symmetry relation in the simulation chip sample are used as a sample layout intelligent body, and an independent device without symmetry relation in the simulation chip sample is used as a sample layout intelligent body;
and determining the sample layout environment based on the sample constraint information, the sample netlist information and the size information of each sample layout agent, and determining the initial state of each sample layout agent based on the sample constraint information.
According to the training method of the automatic layout model of the simulation chip provided by the invention, the corresponding initial prediction action is interacted with the sample layout environment based on each sample layout agent, and the total return value corresponding to each sample layout agent is calculated, which comprises the following steps:
based on each sample layout intelligent agent, interacting the corresponding initial prediction action with the sample layout environment to obtain the update state of each sample layout intelligent agent;
for any sample layout agent, respectively calculating distance information, overlapping area information and routability information between the any sample layout agent and other sample layout agents based on the updated state and size information of each sample layout agent;
and calculating the total return value based on the distance information, the overlapping area information and the routability information corresponding to each sample layout agent.
According to the simulated chip automatic layout model training method provided by the invention, the overlapping area information is determined based on the following steps:
determining a sequence of intersections in an overlap region between the any one sample layout agent and any other sample layout agent;
And taking the adjacent three intersection points in the intersection point sequence as a group to determine triangles, and taking the total area of all the triangles in the overlapping area as the overlapping area information between any sample layout agent and any other sample layout agent.
According to the training method of the automatic layout model of the simulation chip, the value network comprises a first layer of perceptron and a second layer of perceptron; inputting the initial state and the initial prediction action of each sample layout intelligent agent to a value network to obtain a value result corresponding to each sample layout intelligent agent, wherein the method comprises the following steps:
inputting the initial state and initial prediction action of each sample layout intelligent agent to the first layer perceptron to obtain the perception result of each sample layout intelligent agent;
for any sample layout agent, calculating attention characteristics between the any sample layout agent and other sample layout agents by adopting an attention mechanism based on a perception result of each sample layout agent;
and inputting the sensing result and the corresponding attention characteristic of any sample layout intelligent agent to a second layer sensing machine to obtain the value result corresponding to any sample layout intelligent agent.
The invention also provides an automatic layout method of the simulation chip, which comprises the following steps:
acquiring target information of a simulation chip to be laid out, and determining each target layout intelligent agent corresponding to the simulation chip to be laid out, a target layout environment of the simulation chip to be laid out and an initial state of each target layout intelligent agent based on the target information; each target layout intelligent agent is used for representing one or more devices in the simulation chip to be laid out;
inputting the initial state of each target layout intelligent agent into an automatic layout model of a simulation chip configured in the initial state to obtain the predicted action information of each target layout intelligent agent;
and based on each target layout intelligent agent, interacting corresponding prediction action information with the target layout environment to complete automatic layout of the simulation chip to be laid out.
According to the automatic layout method of the simulation chip, the target information comprises target constraint information, target netlist information, symmetry information of all devices in the simulation chip to be laid out and size information of all target layout agents;
the determining, based on the target information, the target layout agents corresponding to the to-be-laid-out simulation chip, the target layout environment of the to-be-laid-out simulation chip, and the initial state of each target layout agent includes:
Based on symmetry information of devices in the simulation chip to be laid out, at least two devices with symmetry relation in the simulation chip to be laid out are used as a target layout intelligent body, and an independent device without symmetry relation in the simulation chip to be laid out is used as a target layout intelligent body;
and determining the target layout environment based on the target constraint information, the target netlist information and the size information of each target layout agent, and determining the initial state of each target layout agent based on the target constraint information.
According to the automatic layout method of the simulation chip, the target constraint information comprises target layout boundary information, and the initial state of each target layout intelligent body comprises initial position information; the determining the initial state of each target layout intelligent agent based on the target constraint information comprises the following steps:
and determining that the initial position information of each target layout intelligent agent is the same position information meeting the target layout boundary information.
The invention also provides an electronic device, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor realizes the simulation chip automatic layout model training method or the simulation chip automatic layout method when executing the computer program.
The present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a simulated chip automated layout model training method or a simulated chip automated layout method as described in any of the above.
The invention also provides a computer program product comprising a computer program which when executed by a processor implements a simulated chip automated layout model training method or a simulated chip automated layout method as described in any of the above.
According to the training method and the automatic layout method for the automatic layout model of the simulation chip, which are provided by the invention, the strategy network corresponding to each sample layout intelligent agent is trained synchronously, so that the centralized training of the automatic layout model of the simulation chip can be realized, and the reinforcement learning convergence efficiency and stability are improved. According to the training method, an automatic layout model of the simulation chip configured in each target layout intelligent body can be obtained, a decentralization layout decision is realized, the layout efficiency and the layout effect of the subsequent simulation chip can be improved, and a layout result with the performance equivalent to that of the manual layout can be obtained in millisecond-level time on the premise of not needing a large amount of layout data, so that the automatic layout is realized, the wiring of the subsequent simulation chip is facilitated, and convenience is provided for the rapid production and the batch application of the simulation chip.
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In order to more clearly illustrate the invention or the technical solutions of the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious to those skilled in the art that other drawings can be obtained according to these drawings without inventive effort.
FIG. 1 is a schematic flow chart of an automatic layout model training method for a simulation chip provided by the invention;
FIG. 2 is a schematic diagram of the structure of a value network in the training method of the automatic layout model of the simulation chip;
FIG. 3 is a second flow chart of the training method of the automatic layout model of the simulation chip according to the present invention;
FIG. 4 is a schematic diagram of the connection relationship between each strategy network and the value network in the training method of the automatic layout model of the simulation chip;
FIG. 5 is a schematic flow chart of an automated layout method for an analog chip provided by the invention;
FIG. 6 is a schematic diagram showing interactions between each target layout agent and the target layout environment in the automated layout method of the analog chip provided by the present invention;
FIG. 7 is a schematic diagram of a training device for an automated layout model of a simulation chip according to the present invention;
FIG. 8 is a schematic diagram of an automated layout apparatus for an analog chip according to the present invention;
fig. 9 is a schematic structural diagram of an electronic device provided by the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The features of the invention "first", "second" and the like in the description and in the claims may be used for the explicit or implicit inclusion of one or more such features. In the description of the invention, unless otherwise indicated, the meaning of "a plurality" is two or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
Because the problems of long running time of automatic layout, poor usability of layout results and the like exist in the existing simulation chip layout process, the simulation chip layout has low efficiency and poor layout effect. Therefore, the embodiment of the invention provides a simulated chip automatic layout model training method which is used for training a simulated chip automatic layout model with short running time, high layout efficiency, strong usability of layout results and better layout effect, thereby being beneficial to the rapid production and batch application of the simulated chip.
Fig. 1 is a schematic flow chart of an automatic layout model training method for an analog chip according to an embodiment of the present invention. As shown in fig. 1, the training method includes:
s11, acquiring sample information of a simulation chip sample, and determining each sample layout intelligent agent corresponding to the simulation chip sample, a sample layout environment of the simulation chip sample and an initial state of each sample layout intelligent agent based on the sample information; each sample layout agent is used for characterizing one or more devices in the analog chip sample;
s12, inputting the initial state of each sample layout intelligent agent into a corresponding strategy network to obtain an initial prediction action of each sample layout intelligent agent, and inputting the initial state and the initial prediction action of each sample layout intelligent agent into a value network to obtain a value result corresponding to each sample layout intelligent agent;
s13, based on each sample layout agent, interacting the corresponding initial prediction action with the sample layout environment, calculating the total return value corresponding to each sample layout agent, and calculating a loss function based on the value result and the total return value corresponding to each sample layout agent;
And S14, based on the loss function, carrying out iterative updating on the structural parameters of each strategy network and each value network, and taking each trained strategy network as an automatic layout model of a simulation chip configured in one target layout intelligent body.
Specifically, in the method for training an automatic layout model of a simulated chip provided in the embodiment of the present invention, the execution subject is a device for training an automatic layout model of a simulated chip, and the device may be configured in a computer, where the computer may be a local computer or a cloud computer, and the local computer may be a computer, a tablet, etc., and is not limited herein specifically.
First, step S11 is performed to obtain sample information of a sample of the analog chip. The simulation chip sample refers to an unobstructive simulation chip for training an automated layout model of the simulation chip.
The sample information may include sample constraint information, sample netlist information, symmetry information of devices in a sample of the simulation chip, and size information of sample layout agents.
The sample constraint information may include sample layout boundary information of the analog chip sample, which is generally determined by the size of the analog chip sample, characterized by a layout bounding box, DRC rule information, and so on. Sample layout boundary information may be used for out-of-range resilience. DRC rule information may include design rule checking, electrical rule checking, short circuit checking, and the like.
The sample netlist information may include the connection relationships required for each device in a sample of a simulation chip.
The symmetry information of each device in the simulation chip sample refers to symmetry relation and symmetry axis among devices in the simulation chip sample, and the size information of each device in the simulation chip sample refers to width, height and the like of each device in the simulation chip sample.
Furthermore, by using the sample information, the sample layout environment of the analog chip sample, the sample layout intelligent objects corresponding to the analog chip sample and the initial states thereof can be determined.
The sample layout environment can be determined by sample information, and can comprise sample constraint information, sample netlist information, symmetry information of each device in a simulation chip sample, size information of each sample layout intelligent agent and the like.
It will be appreciated that each sample layout agent is used to characterize one or more devices in a sample of the analog chip, and that when a sample layout agent characterizes one device in a sample of the analog chip, it is indicative of no other devices in the sample of the analog chip that are symmetrical to that device, and that when a sample layout agent characterizes multiple devices in a sample of the analog chip, it is indicative of those devices being symmetrical. That is, at least two devices having a symmetry relationship in the analog chip sample may be used as one sample layout agent and an individual device having no symmetry relationship in the analog chip sample may be used as one sample layout agent according to symmetry information of each device in the analog chip sample. The reason is that the symmetry constraint is a hard constraint, and unsatisfied results in an increase in parasitic parameters, so all devices having symmetry relationships are laid out as a whole here.
In addition, the initial state of each sample layout agent can be determined according to the sample constraint information. The initial state of each sample layout agent may include initial position information of each sample layout agent, initial overlapping area information between each sample layout agent and other sample layout agents, initial spreadability information, and the like, so that the initial position information of each sample layout agent may be directly determined to satisfy the same position information of sample layout boundary information in sample constraint information, that is, a layout area in a sample of a simulation chip may be determined according to the sample constraint information, and the initial position information of each sample layout agent may be determined to be the same position information in the layout area.
The initial overlapping area information corresponding to each sample layout agent can be determined according to the initial position information and the size information of each sample layout agent. The initial routability information corresponding to each sample layout agent can be determined by the half perimeter of the signal line acquired by the router.
The size information of each sample layout agent may be determined according to the size information of the device corresponding to the sample layout agent, for example, if the sample layout agent has only one device corresponding to the sample layout agent, the size of the sample layout agent is equal to the size information of the corresponding device, and if the sample layout agent has a plurality of devices corresponding to the sample layout agent, the size of the sample layout agent may be determined based on the symmetry axis of the corresponding device and the size information of the corresponding device.
For example, the number of devices corresponding to the sample layout agent is 2, and the symmetry axis is parallel to the width direction, and then the agent height of the sample layout agent is equal to: the corresponding individual device height and distance from the symmetry axis are doubled, and the sample layout agent width is equal to: the width of the corresponding individual device.
Then, step S12 is executed, and a Deep Q Network (DQN) is introduced, where the Deep Q network refers to a Q learning algorithm based on Deep learning, combines a value function approximation and a neural network technology, and performs training of the network by adopting a target network and a playback experience method. Here, the deep Q network employed may be a Double DQN. The deep Q network is the value network.
Before training each strategy network and value network, defining a sample state space and a sample action space of a sample simulation chip layout corresponding to deep reinforcement learning; and defining a return value calculation function, a value network, a strategy network, related parameters and the like applicable to the sample simulation chip layout.
The sample action space may include, but is not limited to: up, down, left, right, 45 ° rotation, 90 ° rotation, 135 ° x-axis mirror, y-axis mirror, and stationary.
The sample state space may be a three-dimensional space, and the three dimensions are two-dimensional position information (x, y) of the sample layout agent and overlapping area information between the sample layout agent and other sample layout agents, respectively.
In the embodiment of the invention, the number of the strategy networks is equal to the number of the sample layout intelligent agents, and the initial state of each sample layout intelligent agent is input into the corresponding strategy network to obtain the initial prediction action of each sample layout intelligent agent.
For each sample layout agent, the structural parameters of the value network are shared, and the policy network corresponding to each sample layout agent can be deployed within the corresponding sample layout agent. For example, the number of sample layout agents is N, and the initial state of the ith sample layout agent is input to the corresponding policy network to obtain the initial prediction action of the ith sample layout agent.
And then inputting the initial state and the initial prediction action of each sample layout intelligent agent into a value network to obtain the value result corresponding to each sample layout intelligent agent. For example, the initial state and the initial prediction action of the ith sample layout agent are input into the value network, so that a value result corresponding to the ith sample layout agent can be obtained.
Thereafter, step S13 is executed to interact the corresponding initial prediction action with the sample layout environment by using each sample layout agent, thereby obtaining the updated state of each sample layout agent
Further, a total return value corresponding to each sample layout agent can be calculated. And then calculating a loss function by using the value result and the total return value corresponding to each sample layout agent.
Finally, step S14 is executed, and the structural parameters of each policy network and each value network are iteratively updated by using the loss function, where the structural parameters may be iteratively updated by using a gradient descent method until the iteration termination condition is satisfied, and the iteration update process is ended, so as to obtain each trained policy network and value network. Here, the iteration termination condition may be that the loss function converges, or that the iteration number reaches a preset iteration number.
In the process of iteratively updating the structural parameters of the value network, the following process may be performed:
initializing a value network playback buffer (replay buffer);
the updating the value network and the structure parameters of each policy network may include the following processes:
samples are extracted from the playback buffer to obtain (o t ,a t ,r t ,o t+1 ,done)，o t A is the state at time t t For action at time t, r t For the total return value at time t, o t+1 The state at time t+1 is shown, and done indicates that it has been taken out.
The structural parameters of the value network may be expressed as w now The structural parameters of the target network can be expressed as
Calculating a value result for each sample layout agent, e.g., the value result of the ith sample layout agent at time t may be expressed as
The value results corresponding to all sample layout agents are collected as follows:
calculating the value result of the ith sample layout agent at the time t+1 by using the target network:
the value results corresponding to all sample layout agents are collected as follows:
computing time series differential (Temporal Difference, TD) targetsAnd TD error (i.e., loss function) delta t ：
Updating the structural parameters of the value network:
updating the structural parameters of the target network:
updating the structural parameters of the policy network corresponding to the ith sample layout agent:
after each trained strategy network and value network are obtained, each trained strategy network can be respectively used as a simulated chip automatic layout model configured in a target layout intelligent body. The input of the automatic layout model of the simulation chip is the state of the target layout agent at each moment, the output is the prediction action of the target layout agent, and the automatic layout can be realized through the prediction action.
According to the simulation chip automatic layout model training method provided by the embodiment of the invention, firstly, sample information of a simulation chip sample is obtained, and based on the sample information, a sample layout environment of the simulation chip sample, sample layout intelligent objects corresponding to the simulation chip sample and initial states of the sample layout intelligent objects are determined; then inputting the initial state of each sample layout intelligent agent into a corresponding strategy network to obtain an initial prediction action of each sample layout intelligent agent, and inputting the initial state and the initial prediction action of each sample layout intelligent agent into a value network to obtain a value result corresponding to each sample layout intelligent agent; then, each sample layout intelligent agent is utilized to interact corresponding initial prediction actions with a sample layout environment, the total return value corresponding to each sample layout intelligent agent is calculated, and a loss function is calculated based on the value result and the total return value corresponding to each sample layout intelligent agent; and finally, iteratively updating the structural parameters of each strategy network and each value network by using a loss function, and taking each trained strategy network as an automatic layout model of the simulation chip configured in one target layout intelligent body. According to the training method, the strategy network corresponding to each sample layout intelligent agent is trained synchronously, so that the centralized training of the automatic layout model of the simulation chip can be realized, and the reinforcement learning convergence efficiency and stability are improved. According to the training method, an automatic layout model of the simulation chip configured in each target layout intelligent body can be obtained, a decentralization layout decision is realized, the layout efficiency and the layout effect of the subsequent simulation chip can be improved, and a layout result with the performance equivalent to that of the manual layout can be obtained in millisecond-level time on the premise of not needing a large amount of layout data, so that the automatic layout is realized, the wiring of the subsequent simulation chip is facilitated, and convenience is provided for the rapid production and the batch application of the simulation chip.
Based on the above embodiment, the interacting, based on each sample layout agent, the corresponding initial prediction action with the sample layout environment, and calculating a total return value corresponding to each sample layout agent includes:
based on each sample layout intelligent agent, interacting the corresponding initial prediction action with the sample layout environment to obtain the update state of each sample layout intelligent agent;
for any sample layout agent, respectively calculating distance information, overlapping area information and routability information between the any sample layout agent and other sample layout agents based on the updated state and size information of each sample layout agent;
and calculating the total return value based on the distance information, the overlapping area information and the routability information corresponding to each sample layout agent.
Specifically, in the embodiment of the present invention, the total return value corresponding to each sample layout agent may be calculated by using the following return value calculation function:
wherein r is t Representing the total return value at time t, agents representing the sample layout agent set, actions represents a set of actions that are taken,representing distance information between the ith sample layout agent and other sample layout agents when attempting the kth action,/for the sample layout agent >Information indicating the overlapping area between the ith sample layout agent and the other sample layout agents when attempting the kth action, ++>Representing routability information, w, between an ith sample layout agent and other sample layout agents when attempting a kth action d 、w o W r Respectively indicate-> And +.>Weight coefficient of (c) in the above-mentioned formula (c). Here, w d 、w o May be set to 1.0, 10000, respectively.
The method can be calculated by the following formula:
the method can be calculated by the following formula:
the half perimeter of the signal line, which can be obtained by the router algorithm, is characterized.
Wherein x is i 、y i Respectively representing two-dimensional position information of an ith sample layout agent at t time, x j 、y j Respectively representing two-dimensional position information of jth sample layout intelligent agent at t moment, S i Representing the area of the ith sample layout agent at time t, S j The j-th sample is shown laying out the area of the agent at time t.
In the embodiment of the invention, the total return value considers the distance information, the overlapping area information and the routability information among the sample layout agents, so that the layout effect of the simulated chip automatic layout model obtained by training can be further improved, and the subsequent wiring operation is facilitated.
On the basis of the above embodiment, the overlapping area information is determined based on the following steps:
Determining a sequence of intersections in an overlap region between the any one sample layout agent and any other sample layout agent;
and taking the adjacent three intersection points in the intersection point sequence as a group to determine triangles, and taking the total area of all the triangles in the overlapping area as the overlapping area information between any sample layout agent and any other sample layout agent.
Specifically, when the overlap area information between the ith sample layout agent and the jth sample layout agent is calculated, the polygon overlap area calculation method may be designed first to calculate the overlap area information between the ith sample layout agent and the jth sample layout agent.
Here, the intersection point sequence in the overlapping area between the ith sample layout agent and the jth sample layout agent may be determined first, and a triangle is determined by taking the adjacent three intersection points in the intersection point sequence as a group, and the sum of the areas of all the triangles is taken as the information of the overlapping area between the ith sample layout agent and the jth sample layout agent, where the following formula is shown:
wherein Area represents the overlapping Area, i, j, k represent the intersection points in the overlapping Area, respectively, and the total combined Area is calculated by summing up by a triangle formula every triplet.
If the number of intersection points in the overlapping region<3, indicating no overlapping area, the overlapping area information is null, s O ＝0。
On the basis of the embodiment, the value network comprises a first layer perceptron and a second layer perceptron; inputting the initial state and the initial prediction action of each sample layout intelligent agent to a value network to obtain a value result corresponding to each sample layout intelligent agent, wherein the method comprises the following steps:
inputting the initial state and initial prediction action of each sample layout intelligent agent to the first layer perceptron to obtain the perception result of each sample layout intelligent agent;
for any sample layout agent, calculating attention characteristics between the any sample layout agent and other sample layout agents by adopting an attention mechanism based on a perception result of each sample layout agent;
and inputting the sensing result and the corresponding attention characteristic of any sample layout intelligent agent to a second layer sensing machine to obtain the value result corresponding to any sample layout intelligent agent.
Specifically, as shown in fig. 2, the value network has a two-layer perceptron network, including a first-layer perceptron and a second-layer perceptron, where the network structure of the first-layer perceptron includes: full connectivity layer (input dimension: 2 x hidden_dim, output dimension: hidden_dim), leakyRelu layer, and full connectivity layer (input dimension: hidden_dim, output dimension: number of motion spaces). The network structure of the second layer perceptron comprises: normalization layer, full connection layer (input dimension is the dimension of the state space, output dimension is hidden_dim), and LeakyRelu layer. The specific value of hidden_dim is related to the number of the intelligent agents in each sample layout and the difficulty level of the task.
For the ith sample layout agent, the value network can be expressed by the following formula: q (Q) i (o,a)＝f(g(o i ,a i ),b i )，b i ＝∑ j≠i α j h(Vg(o j ,a j ))。
Wherein o is i ,a i Laying out the state and actions of the agent for the ith sample, o j ,a j Respectively laying out states and actions of the intelligent agents for the ith sample, g is a first layer perceptron, f is a second layer perceptron, b i For the attention characteristic between the ith sample layout agent and the other sample layout agents, represent the sum of weighted vectors of the ith sample layout agent and the other sample layout agents, α j The attention weight of the jth sample layout agent and the ith sample layout agent is represented by the similarity of states of the jth sample layout agent and the ith sample layout agent, h is a LeakyRelu activation function, and V is a value matrix determined based on an attention mechanism.
The LeakyRelu activation function can be expressed as:
fig. 3 is a schematic flow chart of a training method for an automatic layout model of an analog chip according to an embodiment of the present invention, where the method includes:
determining sample information of the simulation chip sample, and determining a sample layout environment of the simulation chip sample, corresponding sample layout intelligent agents and initial states of the sample layout intelligent agents by using the sample information;
Calculating a total return value corresponding to each sample layout agent, and inputting actions in an action space to a sample layout environment by using N sample layout agents;
and exploring a global optimal strategy through multi-agent cooperation, and iteratively updating the states of all sample layout agents to realize the iterative updating of the structural parameters of all strategy networks and value networks.
Fig. 4 is a schematic diagram of a value network in an automatic layout model training method for a simulation chip according to an embodiment of the present invention, where the value network may be connected to N policy networks, where the N policy networks are respectively a policy network 1, a policy network 2, a policy network …, and a policy network N, and the inputs are respectively states o of corresponding sample layout agents 1 ,o 2 ,…,o N Outputting actions a of the corresponding sample layout intelligent agents 1 ,a 2 ,…,a N 。
The input of the value network is the state theta of the N sample layout intelligent agents respectively 1 ,o 2 ,…,o N Action a of N sample layout agents 1 ,a 2 ,…,a N Outputting value results Q corresponding to N sample layout agents respectively 1 ,Q 2 ,…,Q N 。
As shown in fig. 5, on the basis of the above embodiment, the embodiment of the present invention further provides an automated layout method for an analog chip, where the method includes:
s21, acquiring target information of a simulation chip to be laid out, and determining each target layout intelligent agent corresponding to the simulation chip to be laid out, a target layout environment of the simulation chip to be laid out and an initial state of each target layout intelligent agent based on the target information; each target layout intelligent agent is used for representing one or more devices in the simulation chip to be laid out;
S22, respectively inputting the initial state of each target layout intelligent agent into an automatic layout model of a simulation chip configured in the initial state to obtain the predicted action information of each target layout intelligent agent;
s23, based on each target layout intelligent agent, corresponding prediction action information is interacted with the target layout environment, and automatic layout of the simulation chip to be laid out is completed.
Specifically, in the method for automatically laying out an analog chip provided in the embodiment of the present invention, the execution subject is an automatic layout device for an analog chip, and the device may be configured in a computer, where the computer may be a local computer or a cloud computer, and the local computer may be a computer, a tablet, or the like, and is not limited herein specifically.
Step S21 is first executed to obtain target information of the to-be-laid-out simulation chip, where the target information may include target constraint information, target netlist information, symmetry information of each device in the to-be-laid-out simulation chip, and size information of each target layout agent.
The target constraint information may include target layout boundary information of the to-be-laid-out simulation chip, DRC rule information, and the like, and the target layout boundary information may be determined according to the size of the to-be-laid-out simulation chip and may be characterized by a layout boundary box. The target layout boundary information may be used for out-of-range resilience. DRC rule information may include design rule checking, electrical rule checking, short circuit checking, and the like.
The target netlist information may include the connection relationships required for each device in the simulated chip to be placed. The symmetry information of each device in the simulation chip to be laid out refers to symmetry relation and symmetry axis among devices in the simulation chip to be laid out, and the size information of each device in the simulation chip to be laid out refers to width, height and the like of each device in the target symmetry information.
Furthermore, the target information is utilized to determine the target layout environment of the simulation chip to be laid out, each target layout intelligent agent corresponding to the simulation chip to be laid out and the initial state thereof.
The target layout environment can be determined by target information, and can comprise target constraint information, target netlist information, symmetry information of each device in the simulation chip to be laid out, size information of each target layout agent and the like.
It will be appreciated that each target layout agent is used to characterize one or more devices in the simulated chip to be laid out, and that when a certain target layout agent characterizes one device in the simulated chip to be laid out, it is said that there are no other devices in the simulated chip to be laid out that are symmetrical to that device, and that when a certain target layout agent characterizes a plurality of devices in the simulated chip to be laid out, it is said that those devices are symmetrical. That is, at least two devices having a symmetry relationship in the to-be-laid-out simulation chip may be used as one target layout agent, and an individual device having no symmetry relationship in the to-be-laid-out simulation chip may be used as one target layout agent, according to symmetry information of each device in the to-be-laid-out simulation chip.
In addition, the initial state of each target layout agent can be determined according to the target constraint information. The initial state of each target layout agent may include initial position information of each target layout agent, initial overlapping area information between each target layout agent and other target layout agents, initial distributable linear information, and the like, so that the initial position information of each target layout agent may be directly determined to be the same position information satisfying the target layout boundary information in the target constraint information, that is, a layout-capable area in the simulation chip to be laid out is determined according to the target constraint information, and the initial position information of each target layout agent is determined to be the same position information in the layout-capable area.
The initial overlapping area information corresponding to each target layout agent can be determined according to the initial position information and the size information of each target layout agent. The initial routability information corresponding to each target layout agent can be determined by the half perimeter of the signal line acquired by the router.
The size information of each target layout agent may be determined according to the size information of the device corresponding to the target layout agent, for example, if only one device corresponding to the target layout agent exists, the size of the agent of the target layout agent is equal to the size information of the corresponding device, and if the device corresponding to the target layout agent includes a plurality of devices, the size of the agent of the target layout agent may be determined based on the symmetry axis of the corresponding device and the size information of the corresponding device.
Then, step S22 is executed to input the initial state of each target layout agent to each target layout agentAnd (3) automatizing the layout model by the internally configured simulation chip to obtain the predicted action information of each target layout intelligent agent. The number of the target layout intelligent agents can be N, and the structural parameters are respectively theta 1 ,θ 2 ,…,θ N The states of the target layout agents can be represented as o respectively 1 ,o 2 ,…,o N The actions of each target layout agent are respectively a 1 ,a 2 ,…,a N The actions of each target layout agent may be determined by the corresponding target layout agent, i.e., a 1 ～π(·|o 1 ；θ 1 )、a 2 ～π(·|o 2 ；θ 2 )、…、a N ～π(·|o N ；θ N )，π(·|o 1 ；θ 1 ),π(·|o 2 ；θ 2 ),…,π(·|o N ；θ N ) The 1 st, 2 nd, … th and N th target layout agents are respectively represented.
Finally, step S23 is executed, as shown in fig. 6, each target layout agent interacts the corresponding prediction action information with the target layout environment, so as to obtain the final state of each target layout agent, and complete the automatic layout of the simulated chip to be laid out.
According to the automatic layout method of the simulation chip, target information of the simulation chip to be laid out is obtained, and a target layout environment of the simulation chip to be laid out, target layout intelligent agents corresponding to the simulation chip to be laid out and initial states of the target layout intelligent agents are determined based on the target information; then, the initial state of each target layout intelligent agent is respectively input into an automatic layout model of a simulation chip configured in the initial state to obtain the predicted action information of each target layout intelligent agent; and finally, based on each target layout intelligent agent, interacting corresponding prediction action information with a target layout environment to complete the automatic layout of the simulation chip to be laid out. According to the layout method, the automatic layout model of the simulation chip configured in each target layout intelligent body is utilized, each device in the simulation chip to be laid out can be laid out synchronously, the layout efficiency and the layout effect of the follow-up simulation chip can be improved, and the layout result with the performance equivalent to the manual layout performance can be obtained in millisecond-level time on the premise that a large amount of layout data is not needed, so that the automatic layout is realized, the wiring of the follow-up simulation chip is facilitated, and convenience is provided for the rapid production and batch application of the simulation chip.
As shown in fig. 7, on the basis of the above embodiment, an embodiment of the present invention provides an apparatus for training an automated layout model of a simulation chip, including:
a first information obtaining module 71, configured to obtain sample information of a sample of a simulation chip, and determine, based on the sample information, each sample layout agent corresponding to the sample of the simulation chip, a sample layout environment of the sample of the simulation chip, and an initial state of each sample layout agent; each sample layout agent is used for characterizing one or more devices in the analog chip sample;
the network module 72 is configured to input an initial state of each sample layout agent to a corresponding policy network to obtain an initial prediction action of each sample layout agent, and input the initial state and the initial prediction action of each sample layout agent to a value network to obtain a value result corresponding to each sample layout agent;
the loss function calculation module 73 is configured to interact the corresponding initial prediction action with the sample layout environment based on each sample layout agent, calculate a total return value corresponding to each sample layout agent, and calculate a loss function based on the value result and the total return value corresponding to each sample layout agent;
The iterative training module 74 is configured to iteratively update the structural parameters of each policy network and each value network based on the loss function, and use each trained policy network as an automated layout model of the simulation chip configured in one target layout agent.
On the basis of the embodiment, the sample information comprises sample constraint information, sample netlist information, symmetry information of each device in the sample of the simulation chip and size information of each sample layout agent;
the first information acquisition module is specifically configured to:
based on symmetry information of devices in the simulation chip sample, at least two devices with symmetry relation in the simulation chip sample are used as a sample layout intelligent body, and an independent device without symmetry relation in the simulation chip sample is used as a sample layout intelligent body;
and determining the sample layout environment based on the sample constraint information, the sample netlist information and the size information of each sample layout agent, and determining the initial state of each sample layout agent based on the sample constraint information.
On the basis of the above embodiment, the simulation chip automatic layout model training device provided in the embodiment of the present invention, the loss function calculation module is specifically configured to:
based on each sample layout intelligent agent, interacting the corresponding initial prediction action with the sample layout environment to obtain the update state of each sample layout intelligent agent;
for any sample layout agent, respectively calculating distance information, overlapping area information and routability information between the any sample layout agent and other sample layout agents based on the updated state and size information of each sample layout agent;
and calculating the total return value based on the distance information, the overlapping area information and the routability information corresponding to each sample layout agent.
On the basis of the above embodiment, the simulation chip automatic layout model training device provided in the embodiment of the present invention, the loss function calculation module is further specifically configured to:
determining a sequence of intersections in an overlap region between the any one sample layout agent and any other sample layout agent;
and taking the adjacent three intersection points in the intersection point sequence as a group to determine triangles, and taking the total area of all the triangles in the overlapping area as the overlapping area information between any sample layout agent and any other sample layout agent.
On the basis of the embodiment, the simulation chip automatic layout model training device provided by the embodiment of the invention comprises a first layer perceptron and a second layer perceptron; the network module is specifically configured to:
inputting the initial state and initial prediction action of each sample layout intelligent agent to the first layer perceptron to obtain the perception result of each sample layout intelligent agent;
for any sample layout agent, calculating attention characteristics between the any sample layout agent and other sample layout agents by adopting an attention mechanism based on a perception result of each sample layout agent;
and inputting the sensing result and the corresponding attention characteristic of any sample layout intelligent agent to a second layer sensing machine to obtain the value result corresponding to any sample layout intelligent agent.
Specifically, the functions of each module in the simulation chip automatic layout model training device provided in the embodiment of the present invention are in one-to-one correspondence with the operation flow of each step in the above method embodiment, and the achieved effects are consistent.
As shown in fig. 8, on the basis of the above embodiment, an automatic layout device for an analog chip is further provided in the embodiment of the present invention, including:
the second information obtaining module 81 is configured to obtain target information of a to-be-laid-out simulation chip, and determine each target layout agent corresponding to the to-be-laid-out simulation chip, a target layout environment of the to-be-laid-out simulation chip, and an initial state of each target layout agent based on the target information; each target layout intelligent agent is used for representing one or more devices in the simulation chip to be laid out;
the action prediction module 82 is configured to input the initial state of each target layout agent into the simulation chip automation layout model configured therein, so as to obtain predicted action information of each target layout agent;
and the automated layout module 83 is configured to interact corresponding predicted action information with the target layout environment based on each target layout agent, so as to complete automated layout of the to-be-laid-out simulation chip.
On the basis of the above embodiment, the automatic layout device for the simulation chip provided in the embodiment of the present invention, where the target information includes target constraint information, target netlist information, symmetry information of each device in the simulation chip to be laid out, and size information of each target layout agent; the second information acquisition module is specifically configured to:
Based on symmetry information of devices in the simulation chip to be laid out, at least two devices with symmetry relation in the simulation chip to be laid out are used as a target layout intelligent body, and an independent device without symmetry relation in the simulation chip to be laid out is used as a target layout intelligent body;
and determining the target layout environment based on the target constraint information, the target netlist information and the size information of each target layout agent, and determining the initial state of each target layout agent based on the target constraint information.
On the basis of the foregoing embodiment, the automatic layout device for an analog chip provided in the embodiment of the present invention, where the second information obtaining module is further specifically configured to:
and determining that the initial position information of each target layout intelligent agent is the same position information meeting the target layout boundary information.
Specifically, the functions of each module in the automatic layout device for an analog chip provided in the embodiment of the present invention are in one-to-one correspondence with the operation flows of each step in the above method embodiment, and the implemented effects are consistent.
Fig. 9 illustrates a physical schematic diagram of an electronic device, as shown in fig. 9, which may include: processor (Processor) 910, communication interface (Communications Interface) 920, memory (Memory) 930, and communication bus 940, wherein Processor 910, communication interface 920, and Memory 930 communicate with each other via communication bus 940. Processor 910 may invoke logic instructions in memory 930 to perform the simulated chip automated layout model training method or the simulated chip automated layout method provided in the embodiments described above.
Further, the logic instructions in the memory 930 described above may be implemented in the form of software functional units and may be stored in a computer-readable storage medium when sold or used as a stand-alone product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In another aspect, the present invention also provides a computer program product, where the computer program product includes a computer program, where the computer program can be stored on a non-transitory computer readable storage medium, and when the computer program is executed by a processor, the computer can execute the simulated chip automation layout model training method or the simulated chip automation layout method provided in the foregoing embodiments.
In yet another aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, is implemented to perform the simulated chip automated layout model training method or the simulated chip automated layout method provided in the above embodiments.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. The method for training the automatic layout model of the simulation chip is characterized by comprising the following steps of:
acquiring sample information of a simulation chip sample, and determining each sample layout intelligent agent corresponding to the simulation chip sample, a sample layout environment of the simulation chip sample and an initial state of each sample layout intelligent agent based on the sample information; each sample layout agent is used for characterizing one or more devices in the analog chip sample;
inputting the initial state of each sample layout intelligent agent into a corresponding strategy network to obtain an initial prediction action of each sample layout intelligent agent, and inputting the initial state and the initial prediction action of each sample layout intelligent agent into a value network to obtain a value result corresponding to each sample layout intelligent agent;
based on each sample layout agent, interacting the corresponding initial prediction action with the sample layout environment, calculating the total return value corresponding to each sample layout agent, and calculating a loss function based on the value result and the total return value corresponding to each sample layout agent;
based on the loss function, carrying out iterative updating on the structural parameters of each strategy network and each value network, and taking each trained strategy network as an automatic layout model of the simulation chip configured in one target layout intelligent body.
2. The method for training an automated layout model of a simulation chip according to claim 1, wherein the sample information includes sample constraint information, sample netlist information, symmetry information of each device in the sample of the simulation chip, and size information of each sample layout agent; based on the sample information, determining each sample layout agent corresponding to the analog chip sample, a sample layout environment of the analog chip sample, and an initial state of each sample layout agent, including:
based on symmetry information of devices in the simulation chip sample, at least two devices with symmetry relation in the simulation chip sample are used as a sample layout intelligent body, and an independent device without symmetry relation in the simulation chip sample is used as a sample layout intelligent body;
and determining the sample layout environment based on the sample constraint information, the sample netlist information and the size information of each sample layout agent, and determining the initial state of each sample layout agent based on the sample constraint information.
3. The method for training an automated layout model of a simulated chip according to claim 1, wherein said interacting the corresponding initial predicted actions with the sample layout environment based on each sample layout agent, calculating the total return value corresponding to each sample layout agent, comprises:
Based on each sample layout intelligent agent, interacting the corresponding initial prediction action with the sample layout environment to obtain the update state of each sample layout intelligent agent;
for any sample layout agent, respectively calculating distance information, overlapping area information and routability information between the any sample layout agent and other sample layout agents based on the updated state and size information of each sample layout agent;
and calculating the total return value based on the distance information, the overlapping area information and the routability information corresponding to each sample layout agent.
4. The simulated chip automated layout model training method of claim 3, wherein said overlap area information is determined based on the steps of:
determining a sequence of intersections in an overlap region between the any one sample layout agent and any other sample layout agent;
and taking the adjacent three intersection points in the intersection point sequence as a group to determine triangles, and taking the total area of all the triangles in the overlapping area as the overlapping area information between any sample layout agent and any other sample layout agent.
5. The simulated chip automated layout model training method of any of claims 1-4, wherein said value network comprises a first tier perceptron and a second tier perceptron; inputting the initial state and the initial prediction action of each sample layout intelligent agent to a value network to obtain a value result corresponding to each sample layout intelligent agent, wherein the method comprises the following steps:
inputting the initial state and initial prediction action of each sample layout intelligent agent to the first layer perceptron to obtain the perception result of each sample layout intelligent agent;
for any sample layout agent, calculating attention characteristics between the any sample layout agent and other sample layout agents by adopting an attention mechanism based on a perception result of each sample layout agent;
and inputting the sensing result and the corresponding attention characteristic of any sample layout intelligent agent to a second layer sensing machine to obtain the value result corresponding to any sample layout intelligent agent.
6. An automated layout method for an analog chip, comprising:
acquiring target information of a simulation chip to be laid out, and determining each target layout intelligent agent corresponding to the simulation chip to be laid out, a target layout environment of the simulation chip to be laid out and an initial state of each target layout intelligent agent based on the target information; each target layout intelligent agent is used for representing one or more devices in the simulation chip to be laid out;
Inputting the initial state of each target layout intelligent agent into an automatic layout model of a simulation chip configured in the initial state to obtain the predicted action information of each target layout intelligent agent;
and based on each target layout intelligent agent, interacting corresponding prediction action information with the target layout environment to complete automatic layout of the simulation chip to be laid out.
7. The automated layout method of a simulation chip according to claim 6, wherein the target information includes target constraint information, target netlist information, symmetry information of each device in the simulation chip to be laid out, and size information of each target layout agent;
the determining, based on the target information, the target layout agents corresponding to the to-be-laid-out simulation chip, the target layout environment of the to-be-laid-out simulation chip, and the initial state of each target layout agent includes:
based on symmetry information of devices in the simulation chip to be laid out, at least two devices with symmetry relation in the simulation chip to be laid out are used as a target layout intelligent body, and an independent device without symmetry relation in the simulation chip to be laid out is used as a target layout intelligent body;
And determining the target layout environment based on the target constraint information, the target netlist information and the size information of each target layout agent, and determining the initial state of each target layout agent based on the target constraint information.
8. The automated layout method of a simulation chip according to claim 7, wherein the target constraint information includes target layout boundary information, and the initial state of each target layout agent includes initial position information; the determining the initial state of each target layout intelligent agent based on the target constraint information comprises the following steps:
and determining that the initial position information of each target layout intelligent agent is the same position information meeting the target layout boundary information.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the simulated chip automated layout model training method of any of claims 1-5 or the simulated chip automated layout method of any of claims 6-8 when executing the computer program.
10. A non-transitory computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements the simulated chip automated layout model training method of any of claims 1-5 or the simulated chip automated layout method of any of claims 6-8.
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