CN117422032A - Local reset circuit of complex system comprising multiple subsystems - Google Patents
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Abstract
The invention provides a local reset circuit of a complex system comprising a plurality of subsystems, which is provided with a system global reset signal, a first subsystem local reset signal and a second subsystem local reset signal; the first subsystem comprises a first output trigger, a bypass trigger unit and a logic gate unit, and the second subsystem comprises a second output trigger; the first input end of the bypass trigger unit is connected with the first subsystem local reset signal, the bypass trigger unit internally comprises a first bypass trigger, the output end of the first bypass trigger is a first output end of the bypass trigger unit and is coupled with the first input end of the logic gate unit, the output end of the first output trigger is coupled with the second input end of the logic gate unit, and the output end of the logic gate unit is coupled with the input end of the second output trigger. The present invention provides a true path that can be analyzed and constrained by the STA.
Description
Technical Field
The invention relates to the technical field of circuit design, in particular to a local reset circuit of a complex system comprising a plurality of subsystems.
Background
In the design of complex system-on-a-chip (SoC), a strategy is typically employed to divide the overall system into a plurality of relatively independent subsystems, each of which is responsible for specific functional modules and tasks. The design method can improve maintainability and expandability of the chip. The reset design will also be more complex due to the multiple subsystems in the chip. Besides the common power-on reset and system reset, the system reset also has local reset for each subsystem. The local reset only resets the logic unit inside the subsystem, and the part outside the subsystem is not affected.
The current mainstream design method of the reset circuit is asynchronous reset and synchronous release. The design mode has the advantages of quick response, metastability avoidance and the like. But in a complex system chip, this results in a spurious Path (False Path) from the reset of one subsystem trigger to the input of the other subsystem trigger. For example, from a local reset of the first subsystem, it passes through the reset port of the first flip-flop, then through the intermediate other processing circuits, and finally to the input of the second flip-flop of the second subsystem. Static Timing Analysis (STA) is incapable of analyzing the timing from the trigger reset to the input output. Therefore, whether the signal change caused by the local reset in the first subsystem can meet the setup hold time requirement of the second trigger is not guaranteed by the STA. Only through gate level simulation is the timing of the path found and required to be optimized specifically by the backend personnel. Once the omission occurs, the method becomes a great hidden trouble in chip design.
Disclosure of Invention
The invention aims to provide a local reset circuit of a complex system comprising a plurality of subsystems, which provides a true path from a reset end to a trigger input end, wherein the true path can be analyzed and constrained by a STA, and design risks caused by the existence of a false path between the subsystems are avoided.
In order to achieve the above purpose, the present invention provides the following technical scheme:
a local reset circuit of a complex system comprising a plurality of subsystems, the complex system comprising at least a first subsystem and a second subsystem, having a system global reset signal, a first subsystem local reset signal, a second subsystem local reset signal; the first subsystem comprises a first output trigger, a bypass trigger unit and a logic gate unit, and the second subsystem comprises a second output trigger; the logic gate unit is provided with a first input end, a second input end and an output end, the bypass trigger unit is provided with a first input end, a first output end and a second output end, the first input end of the bypass trigger unit is connected with the local reset signal of the first subsystem, the bypass trigger unit internally comprises a first bypass trigger, the output end of the first bypass trigger is the first output end of the bypass trigger unit and is coupled with the first input end of the logic gate unit, the output end of the first output trigger is coupled with the second input end of the logic gate unit, the output end of the logic gate unit is coupled with the input end of the second output trigger, and the second output end of the bypass trigger unit is coupled with the reset end or the set end of the first output trigger.
In an embodiment, the bypass trigger unit further includes a second bypass trigger, the first subsystem further includes a first and gate, the first and gate has a first input end, a second input end and an output end, the input end of the first bypass trigger is used as the first input end of the bypass trigger unit and connected with the local reset signal of the first subsystem, the output end of the first bypass trigger is further connected with the input end of the second bypass trigger, the output end of the second bypass trigger is used as the second output end of the bypass trigger unit and is coupled with the first input end of the first and gate, the second input end of the first and gate is connected with the global reset signal of the system, the output end of the first and gate is connected with the reset end of the first output trigger, the reset end of the first bypass trigger and the reset end of the second bypass trigger are both connected with the global reset signal of the system, and the logic gate unit is an and the reset value of the first subsystem is 0.
In an embodiment, the bypass trigger unit further includes a second bypass trigger, the first subsystem further includes a first and gate and a first not gate, the first and gate has a first input end, a second input end and an output end, the input end of the first bypass trigger is used as the first input end of the bypass trigger unit and is connected with the local reset signal of the first subsystem, the output end of the first bypass trigger is used as the first output end of the bypass trigger unit, the output end of the first and gate is connected with the first input end of the logic gate unit through the first not gate, the output end of the first bypass trigger is further connected with the input end of the second bypass trigger, the output end of the second bypass trigger is used as the second output end of the bypass trigger unit and is coupled with the first input end of the first and gate, the second input end of the first and gate is connected with the global reset signal of the system, the output end of the first and the first gate trigger is connected with the first reset signal of the first or gate, and the reset signal of the first gate is set by the reset system.
In an embodiment, the bypass trigger unit further includes a second input terminal, and the input terminal of the first bypass trigger is used as the second input terminal of the bypass trigger unit and connected with an output control signal, where the output control signal is two clock cycles earlier than the first subsystem local reset signal; the first subsystem further comprises a first AND gate device, the first AND gate device is provided with a first input end, a second input end and an output end, the first subsystem local reset signal is connected with the first input end of the bypass trigger unit, and the first subsystem local reset signal is directly output from the second output end of the bypass trigger unit; the second output end of the bypass trigger unit is coupled with the first input end of the first AND gate, the second input end of the first AND gate is connected with the system global reset signal, the output end of the first AND gate is connected with the reset end of the first output trigger, the reset end of the first bypass trigger is connected with the system global reset signal, the logic gate unit is an AND gate, and the reset value of the first subsystem is 0.
In an embodiment, the bypass trigger unit further includes a second input terminal, and the input terminal of the first bypass trigger is used as the second input terminal of the bypass trigger unit and connected with an output control signal, where the output control signal is two clock cycles earlier than the first subsystem local reset signal; the first subsystem further comprises a first AND gate device, the first AND gate device is provided with a first input end, a second input end and an output end, the first subsystem local reset signal is connected with the first input end of the bypass trigger unit, and the first subsystem local reset signal is directly output from the second output end of the bypass trigger unit; the second output end of the bypass trigger unit is coupled with the first input end of the first AND gate, the second input end of the first AND gate is connected with the system global reset signal, the output end of the first AND gate is connected with the set end of the first output trigger, the reset end of the first bypass trigger is connected with the system global reset signal, the logic gate unit is an OR gate, and the reset value of the first subsystem is 1.
In an embodiment, the second bypass flip-flop is a multi-stage flip-flop, the stage number is m, and the active level of the first subsystem local reset signal is maintained for at least m+1 clock cycles.
In an embodiment, the first subsystem local reset signal is an asynchronous signal, the first subsystem further includes a two-stage synchronization unit, and the first input end of the bypass trigger unit is connected with the first subsystem local reset signal through the two-stage synchronization unit.
In one embodiment, all flip-flops are in the same clock domain.
In an embodiment, the second subsystem further comprises a combinational logic unit, and an output terminal of the logic gate unit is connected to an input terminal of the second output flip-flop via the combinational logic unit.
In an embodiment, the complex system further includes a test signal, the first subsystem further includes a first or gate, the second subsystem further includes a second or gate and a second or gate, the first or gate, the second or gate and the second or gate each have a first input terminal, a second input terminal, or an output terminal, the second output terminal of the bypass trigger unit is connected to the first input terminal of the first or gate, the second input terminal of the first or gate is connected to the test signal, the output terminal of the first or gate is connected to the first input terminal of the first or gate, the first input terminal of the second or gate is connected to the local reset signal of the second subsystem, the second input terminal of the second or gate is connected to the test signal, the output terminal of the second or gate is connected to the first input terminal of the second or gate, the second input terminal of the second or gate is connected to the global reset signal of the system, and the output terminal of the second or gate is connected to the second trigger.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects: according to the local reset circuit of the complex system comprising a plurality of subsystems, the local reset signal of the first subsystem finally reaches the input end of the second output trigger of the second subsystem through the output end of the first bypass trigger in the bypass trigger unit, and the local reset circuit is a true path (relative to a pseudo path) which can be analyzed and constrained by the STA, so that design risks caused by the existence of the pseudo path between the subsystems are avoided. And the manual optimization work of the back-end staff is reduced, and the quality and the reliability of chip design are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a local reset circuit of a complex system including multiple subsystems according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of a local reset circuit of a complex system including multiple subsystems according to a second embodiment of the present invention;
FIG. 3 is a schematic diagram of a local reset circuit of a complex system including multiple subsystems according to a third embodiment of the present invention;
FIG. 4 is a schematic diagram of a local reset circuit of a complex system including multiple subsystems according to a fourth embodiment of the present invention;
FIG. 5 is a waveform diagram of signals in a partial reset circuit of a complex system including a plurality of subsystems according to a first embodiment of the present invention shown in FIG. 1;
fig. 6 is a waveform diagram of signals in a local reset circuit of a complex system including a plurality of subsystems according to a third embodiment of the present invention shown in fig. 3.
Detailed Description
The following description of the technical solutions in the embodiments of the present invention will be clear and complete, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention based on the embodiments of the present invention. It should be noted that the following description order of the embodiments is not intended to limit the preferred order of the embodiments of the present invention. In the following embodiments, the descriptions of the embodiments are focused on, and for the part that is not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.
Referring to fig. 1, a first embodiment of the present invention provides a local reset circuit of a complex system including a plurality of subsystems, wherein the complex system at least includes a first subsystem S1 and a second subsystem S2, and has a system global reset signal SR, a first subsystem local reset signal PRN1, and a second subsystem local reset signal PRN2; the first subsystem S1 includes a first output trigger RO1, a bypass trigger unit RSU, and a logic gate unit LU, and the second subsystem S2 includes a second output trigger RO2; the bypass trigger unit LU has a first input end, a second input end and an output end, the bypass trigger unit RSU has a first input end, a first output end and a second output end, the first input end of the bypass trigger unit RSU is connected with the first subsystem local reset signal PRN1, the bypass trigger unit RSU includes a first bypass trigger RS1 therein, the output end QS1 of the first bypass trigger RS1 is the first output end of the bypass trigger unit RSU, and is coupled with the first input end of the logic gate unit LU, the output end QO1 of the first output trigger RO1 is coupled with the second input end of the logic gate unit LU, the output end of the logic gate unit LU is coupled with the input end DO2 of the second output trigger RO2, and the second output end of the bypass trigger unit RSU is coupled with the reset end RNO1 of the first output trigger RO 1.
According to the local reset circuit of the complex system comprising a plurality of subsystems, the first subsystem local reset signal PRN1 finally reaches the input end DO2 of the second output trigger RO2 of the second subsystem S2 through the output end QS1 of the first bypass trigger RS1 in the bypass trigger unit RSU, and the local reset circuit is a true path (relative to a pseudo path) which can be analyzed and constrained by the STA, so that design risks caused by the existence of the pseudo path among the subsystems are avoided.
In a first embodiment, the bypass trigger unit RSU further includes a second bypass trigger RS2, the first subsystem S1 further includes a first and gate AG1, the first and gate AG1 has a first input terminal, a second input terminal and an output terminal, the input terminal DS1 of the first bypass trigger RS1 is used as the first input terminal of the bypass trigger unit RSU and is connected to the first subsystem local reset signal PRN1, the output terminal QS1 of the first bypass trigger RS1 is further connected to the input terminal DS2 of the second bypass trigger RS2, the output terminal QS2 of the second bypass trigger RS2 is used as the second output terminal of the bypass trigger unit RSU and is coupled to the first input terminal of the first and gate AG1, the second input terminal DS1 of the first and gate AG1 is connected to the system global reset signal SR, the output terminal QS1 of the first and the first output trigger RS1 is connected to the reset signal RNO1, and the first and the reset signal RNO1 is connected to the first and the first gate RS2 of the first and the second gate RS 1.
Referring to fig. 2, in a second embodiment, the bypass trigger unit RSU further includes a second bypass trigger RS2, the first subsystem S1 further includes a first and gate AG1 and a first not gate NG1, the first and gate AG1 has a first input terminal, a second input terminal and an output terminal, the input terminal DS1 of the first bypass trigger RS1 is used as the first input terminal of the bypass trigger unit RSU and is connected to the first subsystem local reset signal PRN1, the output terminal QS1 of the first bypass trigger RS1 is used as the first output terminal of the bypass trigger unit RSU, the output terminal QS1 of the first bypass trigger RS1 is connected to the first input terminal of the logic gate unit LU via the first not gate NG1, the output terminal of the first bypass trigger RS1 is further connected to the input terminal DS2 of the second bypass trigger RS2, the output terminal DS2 of the second bypass trigger RS1 is used as the first input terminal of the bypass trigger unit RSU, the reset terminal QS1 is connected to the first and the first gate AG1, the reset terminal QS1 is connected to the first and the reset signal RS1 of the first and the first gate RS1 is the reset signal r 1.
Referring to fig. 3, in a third embodiment, the bypass trigger unit RSU further includes a second input terminal, and the input terminal DS1 of the first bypass trigger RS1 is used as the second input terminal of the bypass trigger unit RSU, and is connected to an output control signal OC, where the output control signal OC is two clock cycles earlier than the first subsystem local reset signal PRN 1; the first subsystem S1 further includes a first and gate AG1, where the first and gate AG1 has a first input end, a second input end, and an output end, and the first subsystem local reset signal PRN1 is connected to the first input end of the bypass trigger unit RSU and directly output from the second output end of the bypass trigger unit RSU; the second output end of the bypass trigger unit RSU is coupled to the first input end of the first and gate AG1, the second input end of the first and gate AG1 is connected to the system global reset signal SR, the output end of the first and gate AG1 is connected to the reset end RNO1 of the first output trigger RO1, the reset end RNS1 of the first bypass trigger RS1 is connected to the system global reset signal SR, the logic gate unit LU is an and gate, and the reset value of the first subsystem S1 is 0.
Referring to fig. 4, in the fourth embodiment, the bypass trigger unit RSU further includes a second input terminal, and the input terminal DS1 of the first bypass trigger RS1 is used as the second input terminal of the bypass trigger unit RSU, and is connected to an output control signal OC, where the output control signal OC is two clock cycles earlier than the first subsystem local reset signal PRN 1; the first subsystem S1 further includes a first and gate AG1, where the first and gate AG1 has a first input end, a second input end, and an output end, and the first subsystem local reset signal PRN1 is connected to the first input end of the bypass trigger unit RSU and directly output from the second output end of the bypass trigger unit RSU; the second output end of the bypass trigger unit RSU is coupled to the first input end of the first and gate AG1, the second input end of the first and gate AG1 is connected to the system global reset signal SR, the output end of the first and gate AG1 is connected to the set end SNO1 of the first output trigger RO1, the reset end RNS1 of the first bypass trigger RS1 is connected to the system global reset signal SR, the logic gate unit LU is an or gate, and the reset value of the first subsystem S1 is 1.
Referring to fig. 1 and 5 in combination, the first embodiment shown in fig. 1 includes the operation principle of a local reset circuit of a complex system including a plurality of subsystems:
a) At time t0, when the first subsystem local reset signal PRN1 is pulled low, it is sampled one beat via the first bypass flip-flop RS1 (at time t1, the output terminal QS1 of the first bypass flip-flop RS1 is pulled low) and transmitted to the logic gate unit LU (and gate) also connected to the output terminal QO1 of the first output flip-flop RO 1. Accordingly, at time t1, the first bypass flip-flop RS1 pulls the output Out1 of the first subsystem S1 to the reset state (low level 0) through the and gate (logic gate unit LU). A true path is thus formed here, which can be analyzed and constrained by the STA, i.e. a path from the output QS1 of the first bypass flip-flop RS1 to the input DO2 of the second output flip-flop RO 2.
b) It should be noted that when the first subsystem local reset signal PRN1 is pulled down, the first output flip-flop RO1 is affected by the driving of the previous stage flip-flop, and the input DO1 also jumps. This level change will be sampled by the first output flip-flop RO1 at time t 1. Essentially this is also a false path from the flip-flop reset to the flip-flop input, so that at time t1 the first output flip-flop RO1 is metastable. But now the output Out1 of the first subsystem S1 has been stabilized in the reset state by the first bypass flip-flop RS1, so this metastability has no influence on the subsequent circuits.
c) At time t1, although the output of the first output flip-flop RO1 has been pulled to a reset state by and gate, the value stored by the first output flip-flop RO1 itself is not reset and may even be in a metastable state. Here the output of the first bypass flip-flop RS1 is resampled by a beat by the second bypass flip-flop RS2 and is connected as a reset signal together with the system global reset signal SR to the reset terminal RNO1 of the first output flip-flop RO 1. That is, at time t2, the first output flip-flop RO1 will be reset by the output of the second bypass flip-flop RS 2.
d) Taking the first subsystem local reset signal PRN1 for two clock cycles as an example, the output terminal QS1 of the first bypass flip-flop RS1 will be pulled high at time t3, and the output Out1 of the first subsystem S1 will be driven by the output of the first output flip-flop RO1 only. But the output QS2 of the second bypass flip-flop RS2 is still at a low level, i.e. the first output flip-flop RO1 is still in a reset state, so the output Out1 of the first subsystem S1 does not have any level change.
e) At time t4, the output terminal QS2 of the second bypass flip-flop RS2 is pulled high, the first output flip-flop RO1 exits the reset state, and the local reset procedure of the first subsystem S1 is completed.
The second embodiment of fig. 2 shows a partial reset circuit of a complex system including a plurality of subsystems, which operates in substantially the same manner as the first embodiment of fig. 1 shows a partial reset circuit of a complex system including a plurality of subsystems. The difference is that in the first embodiment of the local reset circuit of the complex system comprising a plurality of subsystems shown in fig. 1, the reset value of the first subsystem S1 is 0, and in the second embodiment of the local reset circuit of the complex system comprising a plurality of subsystems shown in fig. 2, the reset value of the first subsystem S1 is 1, correspondingly, the first output flip-flop RO1 is connected to the set terminal SNO1 instead of the reset terminal RNO1, and the logic gate unit LU is also transformed into an or gate by an and gate, and a not gate is connected between the output terminal QS1 of the first bypass flip-flop RS 1.
Referring to fig. 3 and fig. 6 in combination, the third embodiment shown in fig. 3 includes the operation principle of the local reset circuit of the complex system of a plurality of subsystems:
a) At time t0, the output control signal OC is pulled down before the first subsystem local reset signal PRN1, sampled by the first bypass flip-flop RS1 for one beat, and then transmitted to the logic gate unit LU (and gate) also connected to the output terminal QO1 of the first output flip-flop RO1, and correspondingly, at time t1, the first bypass flip-flop RS1 pulls the output Out1 of the first subsystem S1 to the reset state through the and gate (logic gate unit LU). A true path is thus formed here, which can be analyzed and constrained by the STA, i.e. a path from the output QS1 of the first bypass flip-flop RS1 to the input DO2 of the second output flip-flop RO 2.
b) In order to ensure that the signal output by the first subsystem S1 is stable, the first subsystem local reset signal PRN1 is required to lag the output control signal OC by at least 2 clock cycles, i.e. the output control signal OC is two clock cycles earlier than the first subsystem local reset signal PRN 1.
d) At time t2, the first subsystem local reset signal PRN1 is pulled low, the first output flip-flop RO1 is reset, and its output QO1 is in a reset state. At the same time, the output control signal OC is pulled high.
d) At time t3, the first bypass flip-flop RS1 samples the high value of the output control signal OC, the output terminal QS1 thereof will also be pulled high, and the output of the first subsystem S1 will be driven by the output terminal QO1 of the first output flip-flop RO1 only. At this point the value stored by the first output flip-flop RO1 has been reset and therefore the output Out1 of the first subsystem S1 does not have any level change.
e) At time t4, when the first subsystem local reset signal PRN1 is pulled high, the local reset procedure of the first subsystem S1 is completed.
The third embodiment of the local reset circuit of the complex system comprising a plurality of subsystems shown in fig. 3 differs from the first embodiment of the local reset circuit of the complex system comprising a plurality of subsystems shown in fig. 1 mainly in that the third embodiment of the local reset circuit of the complex system comprising a plurality of subsystems shown in fig. 3 additionally introduces an output control signal OC, but reduces the use of flip-flops. The operation principle of the local reset circuit of the complex system including a plurality of subsystems according to the fourth embodiment shown in fig. 4 is substantially the same as that of the local reset circuit of the complex system including a plurality of subsystems according to the third embodiment shown in fig. 3. The difference is that the third embodiment of the local reset circuit of the complex system including a plurality of subsystems shown in fig. 3 has a reset value of 0 of the first subsystem S1, the fourth embodiment of the local reset circuit of the complex system including a plurality of subsystems shown in fig. 4 has a reset value of 1 of the first subsystem S1, correspondingly, the first output flip-flop RO1 is connected to a set terminal SNO1 instead of a reset terminal RNO1, and the logic gate unit LU is also converted into an or gate by an and gate, and the high level and the low level of the corresponding signal are adaptively converted.
In the first and second embodiments, the second bypass flip-flop RS2 is a multi-stage flip-flop with a stage number of m, and the active level of the first subsystem local reset signal PRN1 is maintained for at least m+1 clock cycles. If a certain reset delay is desired in the system design, the number of stages m of the second bypass flip-flop RS2 may be increased, whereas the number of stages m of the second bypass flip-flop RS2 may be decreased. Of course, said m is at least 1.
In all embodiments, all flip-flops are in the same clock domain CK. Accordingly, the first subsystem local reset signal PRN1 is in the clock domain. If the first subsystem local reset signal PRN1 is an asynchronous signal, the first subsystem S1 further comprises a two-stage synchronization unit, and the first input terminal of the bypass trigger unit LU is connected to the first subsystem local reset signal PRN1 via the two-stage synchronization unit, so as to perform signal synchronization.
In all embodiments, the second subsystem S2 further comprises a combinational logic unit CL via which the output of the logic gate unit LU is connected to the input DO2 of the second output flip-flop RO 2.
In all embodiments, the complex system further has a test signal SC, the first subsystem S1 further includes a first or gate OG1, the second subsystem S2 further includes a second or gate AG2 and a second or gate OG2, the first or gate OG1, the second or gate AG2, the second or gate OG2 each has a first input, a second input or an output, the second output of the bypass trigger unit RSU is connected to the first input of the first or gate OG1, the second input of the first or gate OG1 is connected to the test signal SC, the output of the first or gate OG1 is connected to the first input of the first or gate AG1, the first input of the second or gate OG2 is connected to the second subsystem local reset signal AG2, the second input of the second or gate OG2 is connected to the test signal SC, the second input of the second or gate OG2 is connected to the second input of the second or gate AG2, and the second output of the second or gate AG2 is connected to the second input of the second or gate AG 2. Specifically, in the first and third embodiments, the output end of the second and gate AG2 is connected to the reset end RNO2 of the second output flip-flop RO2; in the second and fourth embodiments, the output terminal of the second and gate AG2 is connected to the set terminal SNO2 of the second output flip-flop RO 2. Thus, the test can be conveniently performed.
Finally, it should be noted that, in the foregoing embodiments, the transmission of the local reset signal of the first subsystem to the second subsystem is taken as an example to be described; if the local reset signal of the second subsystem is to be transmitted to the first subsystem, the bypass trigger unit of any embodiment is correspondingly arranged in the second subsystem. The bypass trigger unit is only required to be connected with the last stage output trigger of each subsystem, namely the first output trigger is the last stage output trigger in the first subsystem, other output triggers in the first subsystem are not required to be connected with the bypass trigger unit, namely the second output trigger is the last stage output trigger in the second subsystem, and other output triggers in the second subsystem are not required to be connected with the bypass trigger unit.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the local reset circuit of the complex system comprising a plurality of subsystems, the local reset signal of the first subsystem finally reaches the input end of the second output trigger of the second subsystem through the output end of the first bypass trigger in the bypass trigger unit, and the local reset circuit is a true path (relative to a pseudo path) which can be analyzed and constrained by the STA, so that design risks caused by the existence of the pseudo path between the subsystems are avoided. And the manual optimization work of the back-end staff is reduced, and the quality and the reliability of chip design are improved.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims. Furthermore, the foregoing description of the principles and embodiments of the invention has been provided for the purpose of illustrating the principles and embodiments of the invention and for the purpose of providing a further understanding of the principles and embodiments of the invention, and is not to be construed as limiting the invention.
Claims (10)
1. A local reset circuit of a complex system comprising a plurality of subsystems, wherein the complex system comprises at least a first subsystem and a second subsystem, and has a system global reset signal, a first subsystem local reset signal, and a second subsystem local reset signal; the first subsystem comprises a first output trigger, a bypass trigger unit and a logic gate unit, and the second subsystem comprises a second output trigger; the logic gate unit is provided with a first input end, a second input end and an output end, the bypass trigger unit is provided with a first input end, a first output end and a second output end, the first input end of the bypass trigger unit is connected with the local reset signal of the first subsystem, the bypass trigger unit internally comprises a first bypass trigger, the output end of the first bypass trigger is the first output end of the bypass trigger unit and is coupled with the first input end of the logic gate unit, the output end of the first output trigger is coupled with the second input end of the logic gate unit, the output end of the logic gate unit is coupled with the input end of the second output trigger, and the second output end of the bypass trigger unit is coupled with the reset end or the set end of the first output trigger.
2. A local reset circuit for a complex system comprising a plurality of subsystems according to claim 1, wherein said bypass trigger unit further comprises a second bypass trigger, said first subsystem further comprises a first and gate having a first input, a second input and an output, said first bypass trigger input being connected as said bypass trigger unit first input to said first subsystem local reset signal, said first bypass trigger output being further connected to said second bypass trigger input, said second bypass trigger output being said bypass trigger unit second output being coupled to said first and gate first input, said first and gate second input being connected to said system global reset signal, said first and gate output being connected to said first output trigger reset signal, said first and gate reset unit reset logic value being said first and gate reset unit reset logic value.
3. The local reset circuit of a complex system comprising a plurality of subsystems according to claim 1, wherein the bypass trigger unit further comprises a second bypass trigger, the first subsystem further comprises a first and gate and a first not gate, the first and gate has a first input, a second input and an output, the input of the first bypass trigger is used as the first input of the bypass trigger unit and is connected with the first subsystem local reset signal, the output of the first bypass trigger is used as the first output of the bypass trigger unit, the output of the first bypass trigger is connected with the first input of the logic gate unit via the first not gate, the output of the first bypass trigger is further connected with the input of the second bypass trigger, the output of the second bypass trigger is used as the second output of the bypass trigger unit and is coupled with the first input of the first and gate, the second input of the first and gate trigger is connected with the global reset signal, the first reset trigger is connected with the first reset gate of the first system reset trigger, and the first reset trigger is connected with the first gate, and the reset signal of the first gate is set.
4. A complex system local reset circuit comprising a plurality of subsystems according to claim 1, wherein said bypass trigger unit further comprises a second input, said first bypass trigger input being a second input of said bypass trigger unit, connected to an output control signal, said output control signal being two clock cycles earlier than said first subsystem local reset signal; the first subsystem further comprises a first AND gate device, the first AND gate device is provided with a first input end, a second input end and an output end, the first subsystem local reset signal is connected with the first input end of the bypass trigger unit, and the first subsystem local reset signal is directly output from the second output end of the bypass trigger unit; the second output end of the bypass trigger unit is coupled with the first input end of the first AND gate, the second input end of the first AND gate is connected with the system global reset signal, the output end of the first AND gate is connected with the reset end of the first output trigger, the reset end of the first bypass trigger is connected with the system global reset signal, the logic gate unit is an AND gate, and the reset value of the first subsystem is 0.
5. A complex system local reset circuit comprising a plurality of subsystems according to claim 1, wherein said bypass trigger unit further comprises a second input, said first bypass trigger input being a second input of said bypass trigger unit, connected to an output control signal, said output control signal being two clock cycles earlier than said first subsystem local reset signal; the first subsystem further comprises a first AND gate device, the first AND gate device is provided with a first input end, a second input end and an output end, the first subsystem local reset signal is connected with the first input end of the bypass trigger unit, and the first subsystem local reset signal is directly output from the second output end of the bypass trigger unit; the second output end of the bypass trigger unit is coupled with the first input end of the first AND gate, the second input end of the first AND gate is connected with the system global reset signal, the output end of the first AND gate is connected with the set end of the first output trigger, the reset end of the first bypass trigger is connected with the system global reset signal, the logic gate unit is an OR gate, and the reset value of the first subsystem is 1.
6. A complex system local reset circuit comprising a plurality of subsystems according to claim 2 or 3, wherein said second bypass flip-flop is a multi-stage flip-flop having a number of stages m, and wherein the active level of said first subsystem local reset signal is maintained for at least m+1 clock cycles.
7. A local reset circuit for a complex system comprising a plurality of subsystems according to claim 2 or 3, wherein said first subsystem local reset signal is an asynchronous signal, said first subsystem further comprising a two-stage synchronization unit, said first input of said bypass trigger unit being connected to said first subsystem local reset signal via said two-stage synchronization unit.
8. A local reset circuit for a complex system comprising multiple subsystems according to any of claims 2-5, wherein all flip-flops are in the same clock domain.
9. The local reset circuit of a complex system including a plurality of subsystems according to claim 8, wherein said second subsystem further comprises a combinational logic unit, an output of said logic gate unit being connected to an input of said second output flip-flop via said combinational logic unit.
10. The local reset circuit of a complex system comprising a plurality of subsystems according to claim 9, wherein said complex system further comprises a test signal, said first subsystem further comprises a first or gate, said second subsystem further comprises a second or gate, said first or gate, said second or gate each having a first input, a second input or an output, respectively, said second output of said bypass trigger unit is connected to a first input of said first or gate, said second input of said first or gate is connected to said test signal, said output of said first or gate is connected to a first input of said first or gate, said first input of said second or gate is connected to said second subsystem local reset signal, said second input of said second or gate is connected to said test signal, said output of said second or gate is connected to a first input of said second or gate, said second input of said second or gate is connected to said global reset signal, and said second output of said second or gate is connected to said global reset signal.
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| CN202311751203.XA CN117422032B (en) | 2023-12-19 | 2023-12-19 | Local reset circuit of complex system comprising multiple subsystems |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101082939A (en) * | 2006-05-31 | 2007-12-05 | 中国科学院微电子研究所 | Reset circuit design method in system design on piece |
| WO2007142201A1 (en) * | 2006-06-05 | 2007-12-13 | Panasonic Corporation | Multi-cycle path information verification method and multi-cycle path information verification device |
| JP2008123056A (en) * | 2006-11-08 | 2008-05-29 | Sharp Corp | Timing constraint-generating system of logic circuit and timing constraint-generating method of logic circuit, control program, and readable recording medium |
| US9760672B1 (en) * | 2014-12-22 | 2017-09-12 | Qualcomm Incorporated | Circuitry and method for critical path timing speculation to enable process variation compensation via voltage scaling |
| CN113131904A (en) * | 2021-05-25 | 2021-07-16 | 天津科迪特科技有限责任公司 | Double-rising-edge trigger pulse generation circuit and system |
-
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101082939A (en) * | 2006-05-31 | 2007-12-05 | 中国科学院微电子研究所 | Reset circuit design method in system design on piece |
| WO2007142201A1 (en) * | 2006-06-05 | 2007-12-13 | Panasonic Corporation | Multi-cycle path information verification method and multi-cycle path information verification device |
| JP2008123056A (en) * | 2006-11-08 | 2008-05-29 | Sharp Corp | Timing constraint-generating system of logic circuit and timing constraint-generating method of logic circuit, control program, and readable recording medium |
| US9760672B1 (en) * | 2014-12-22 | 2017-09-12 | Qualcomm Incorporated | Circuitry and method for critical path timing speculation to enable process variation compensation via voltage scaling |
| CN113131904A (en) * | 2021-05-25 | 2021-07-16 | 天津科迪特科技有限责任公司 | Double-rising-edge trigger pulse generation circuit and system |
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