CN117409847B - Storage testing device and testing method thereof - Google Patents
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- 238000003860 storage Methods 0.000 title claims abstract description 64
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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Abstract
The invention provides a storage testing device and a testing method thereof, wherein the storage testing device is used for testing a memory, the storage testing device comprises a central processing unit, and the central processing unit is electrically connected with the memory, wherein the central processing unit comprises: the storage unit is used for storing a plurality of parameter sets, wherein the parameter sets at least comprise initial preset information and initial cyclic check codes of the initial preset information; the verification code modification unit is used for acquiring preset information to be detected according to the initial preset information after the memory receives the initial preset information and the partial data are overturned; the verification code acquisition unit acquires a to-be-detected cyclic verification code of the to-be-detected preset information from the memory after the to-be-detected preset information is written into the memory; and the check code comparison unit is used for acquiring comparison result data of the to-be-tested cyclic check code and the initial cyclic check code, and storing the test device to traverse and test a plurality of parameter sets or stop the test according to the comparison result data.
Description
Technical Field
The invention relates to the technical field of storage testing, in particular to a storage testing device and a testing method thereof.
Background
By means of cyclic redundancy check (Cyclic Redundancy Check, CRC) unexpected changes of the original computer data commonly used in storage devices such as digital telecommunication networks and hard disk drives can be detected. When a computer reads a corrupted or incomplete file, a cyclic redundancy error is triggered, which can determine if the transmitted data is erroneous.
In a storage device, a cyclic redundancy check may be triggered as long as data transmission is involved. For the storage device, the storage device is required to process normal read-write operation and simultaneously restore to a normal state when the system sends an instruction or data errors. Thus, the endurance strength of the cyclic redundancy check is directly related to the efficiency of the memory device.
Disclosure of Invention
The invention aims to provide a storage testing device and a testing method thereof, which are used for comprehensively and high-intensity testing the verification capability of storage equipment.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides a storage testing device, which is used for testing a memory, and comprises a central processing unit, wherein the central processing unit is electrically connected with the memory, and the central processing unit comprises:
the storage unit is used for storing a plurality of parameter sets, wherein the parameter sets at least comprise initial preset information and initial cyclic check codes of the initial preset information;
the check code modification unit is used for acquiring preset information to be detected according to the initial preset information after the memory receives the initial preset information and partial data are overturned;
the verification code acquisition unit acquires a to-be-detected cyclic verification code of the to-be-detected preset information from the memory after the to-be-detected preset information is written into the memory; and
and the check code comparison unit is used for acquiring comparison result data of the to-be-tested cyclic check code and the initial cyclic check code, and the storage test device traverses and tests a plurality of parameter sets or stops testing according to the comparison result data.
In an embodiment of the invention, the parameter set further includes a supply voltage of the memory, an interface transmission speed of the memory, a clock frequency of the memory, and a write mode of the memory.
In an embodiment of the present invention, the initial preset information is user data or a host command.
In an embodiment of the present invention, the initial preset information and the preset information to be detected include first data, last data and a plurality of intermediate data, respectively, where the first data and the last data of the initial preset information and the preset information to be detected are the same, and the initial preset information and part of the intermediate data of the preset information to be detected are opposite.
In an embodiment of the invention, the storage test device includes a socket, the socket is electrically connected with the memory, and the socket is connected with the memory in a pluggable manner.
In an embodiment of the present invention, when the initial cyclic check code is the same as the cyclic check code to be tested, the storage test device stops the test.
In an embodiment of the present invention, when the initial cyclic check code and the cyclic check code to be tested are different, the storage test device tests another parameter set until the parameter set in the storage unit is traversed.
The invention provides a testing method of a storage testing device, which is based on the storage testing device and comprises the following steps:
setting a plurality of parameter sets, wherein the parameter sets at least comprise initial preset information and initial cyclic check codes of the initial preset information;
the initial preset information is sent to a memory, and partial data of the initial preset information are overturned to obtain preset information to be detected;
writing the preset information to be tested into the memory, and checking the preset information to be tested to obtain a cyclic check code to be tested; and
and comparing the initial cyclic check code with the cyclic check code to be tested, obtaining comparison result data, and traversing a plurality of parameter sets to be tested or stopping testing according to the comparison result data.
In an embodiment of the present invention, when the initial cyclic check code and the cyclic check code to be tested are different, a next parameter set is acquired and tested until the parameter set in the storage unit is traversed.
In an embodiment of the present invention, when the initial cyclic check code is the same as the cyclic check code to be tested, the test is stopped, and the check firmware of the memory is adjusted.
As described above, the storage testing device and the testing method thereof provided by the invention can simulate various process environments of cyclic redundancy check, thereby comprehensively testing the bearable strength of the storage device for cyclic redundancy check and improving the delivery efficiency of the storage device. According to the storage testing device and the testing method thereof, the bias of the cyclic check test can be flexibly adjusted according to products in different application environments, so that the testing accuracy is considered, and the testing efficiency is improved. According to the storage testing device and the testing method thereof, the storage reliability of the storage equipment can be ensured, and the compatibility of the storage equipment is improved, so that the production of high-grade storage equipment is facilitated.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a memory test device according to an embodiment of the invention.
FIG. 2 is a schematic diagram of a memory according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram of a control module according to an embodiment of the invention.
FIG. 4 is a schematic diagram of a test firmware according to an embodiment of the invention.
Fig. 5 is a schematic diagram of steps S10 to S50 in an embodiment of the invention.
Fig. 6 is a schematic diagram illustrating modification of initial preset information according to an embodiment of the invention.
Fig. 7 is a flowchart of step S60 in an embodiment of the invention.
In the figure: 100. storing the testing device; 101. a central processing unit; 102. a memory; 103. a socket; 104. a power supply; 105. a memory card; 106. an interface; 200. a memory; 201. a microprocessor; 202. a cache chip; 203. a flash memory chip; 204. a verification module; 300. a control module; 301. testing the firmware; 302. a configuration unit; 303. a voltage regulating unit; 304. a transmission speed adjusting unit; 305. a bandwidth adjusting unit; 306. a clock unit; 307. a storage unit; 308. a writing method selecting unit; 309. an error collection unit is applied.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The cyclic redundancy check is suitable for check detection of the hard disk drive. In this embodiment, the storage device may be any storage device including a flash memory, and the storage device may be applied to various digital devices forming a computer, a video camera, and the like. Wherein the flash memory may be a NAND flash memory. In cyclic redundancy check, a fixed number of check bits are appended to a message to be transmitted for the information to be transmitted. Wherein the information to be transmitted includes host instructions and host data. After receiving the data, the data receiver acquires the check value of the cyclic redundancy check and confirms whether the check value has any error. The check bit may be checked for errors by various mathematical methods, for example, the information to be transmitted is processed by polynomial division, then the remainder of the polynomial division is obtained, and the obtained remainder is used as the check code. In the step of obtaining the check code, the divisor is self-defined, so that if the obtained check code is not consistent with the preset data, negative confirmation is sent, and the data is retransmitted.
Referring to fig. 1, the present invention provides a memory test device 100, where the memory test device 100 includes a central processing unit 101, a memory 102, a socket 103, a power source 104, a memory card 105, and an interface 106. The central processor 101 is an operation core of a computer. The memory 102 is a dynamic random access memory (Dynamic Random Access Memory, DRAM). The socket 103 is electrically connected to the memory 200 in a pluggable manner. The power supply 104 is electrically connected to the cpu 101, the memory 102 and the socket 103, so as to supply power to the memories 200 in the cpu 101, the memory 102 and the socket 103. The memory Card 105 may be a nonvolatile memory such as a multimedia Card (MMC), an SD Card, and a memory stick. The cpu 101 is electrically connected to the memory 102 and the memory card 105, respectively, and exchanges data. The memory 102 is a power-down volatile storage device, and can quickly exchange data with the cpu 101. The central processing unit 101 is electrically connected with the memory 200 through the socket 103, and exchanges data with the memory 200. The interface 106 is used for connecting with an external device to realize functions such as firmware burning and information transmission. And interface 106 may be a SATA hard disk, a high speed serial computer expansion bus interface (Peripheral Component Interconnect express, PCIe), a SAS interface, and so on.
Referring to fig. 1 and 2, in an embodiment of the invention, a memory 200 includes a microprocessor 201, a cache chip 202, a flash memory chip 203, and a verification module 204. Wherein the microprocessor 201 is a reduced instruction system computer (Reduced Instruction System Computer, RISC) and in particular an ARM processor. The cache chip 202 is a Static Random-Access Memory (SRAM). The flash memory chip 203 is a NAND flash memory. The check module 204 may be used to perform a cyclic redundancy check. Wherein the microprocessor 201 is electrically connected to the verification module 204 and exchanges data. The verification module 204 is electrically connected to the cache chip 202 and the flash memory chip 203. Wherein the flash memory chip 203 is electrically connected to the cache chip 202. When data transmission is performed, data or instructions sent by the microprocessor 201 first pass through the verification module 204 and then are written into the cache chip 202 or the flash memory chip 203. If the check code is found to be wrong, the check module 204 corrects the information and then writes the correct data into the cache chip 202 or the flash memory chip 203. Wherein the microprocessor 201 can write data directly to the flash memory chip 203. The microprocessor 201 may write data to the cache chip 202 before writing data to the flash memory chip 203. In the present embodiment, the memory 200 is an embedded multimedia memory card (Embedded Multi Media Card, eMMC).
Referring to fig. 1 to 3, in an embodiment of the invention, the cpu 101 includes a control module 300 for controlling a test process of the memory 200. The control module 300 includes a test firmware 301, a configuration unit 302, a voltage adjustment unit 303, a transmission speed adjustment unit 304, a bandwidth adjustment unit 305, a clock unit 306, a storage unit 307, and a write method selection unit 308, and an application error collection unit 309. The configuration unit 302 is electrically connected to the test firmware 301, and the voltage adjusting unit 303, the transmission speed adjusting unit 304, the bandwidth adjusting unit 305, and the clock unit 306, so as to adjust the working voltage, the interface transmission speed, the bus width, and the clock frequency when the corresponding operation of the test firmware 301 is performed. And the voltage adjusting unit 303 is used to adjust the operation voltage. The transmission speed adjusting unit 304 is used for adjusting the interface transmission speed between the memory 200 and the central processing unit 101. The bandwidth adjusting unit 305 is used for adjusting the bus width of data transmission. The clock unit 306 is electrically connected to the storage unit 307 and the write method selection unit 308, and the error collection unit 309 is used to control the transmission frequency of data and command transmission. And the clock unit 306 is electrically connected to the test firmware 301 and the configuration unit 302, so as to adjust the start nodes of the test firmware 301 and the configuration unit 302. The storage unit 307 stores therein user data to be written to the cache chip 202 and the flash memory chip 203, and a host instruction to be sent to the microprocessor 201. The writing method selecting unit 308 is used to adjust the writing mode of the data, which is not limited in the present invention. Wherein the application error collection unit 309 is configured to collect test data of the memory 200. In this embodiment, the test firmware 301 is electrically connected to an external host, so as to implement firmware burning. Wherein the external host may be a burner.
Referring to fig. 1 to 4, in an embodiment of the present invention, the test firmware 301 includes a parameter set setting unit 3011, a check code modifying unit 3012, a check code acquiring unit 3013, and a check code comparing unit 3014. The parameter set setting unit 3011 is configured to set a plurality of parameter sets, and store the parameter sets in the storage unit 307, where the parameter sets include at least initial preset information and an initial cyclic check code. After the initial preset information is sent to the microprocessor 201, the check code modification unit 3012 is configured to modify the initial preset information, and modify the initial preset information into preset information to be tested. After writing the preset information to be tested into the flash memory chip 203, the verification module 204 generates a cyclic verification code to be tested according to the written preset information to be tested. The check code acquisition unit 3013 acquires the cyclic check code to be tested, and sends the cyclic check code to be tested to the check code comparison unit 3014. The check code comparing unit 3014 acquires and compares the initial cyclic check code and the cyclic check code to be tested, and acquires comparison result data. When the initial cyclic check code is the same as the cyclic check code to be tested, the check module 204 checks that a problem occurs, stops the test, and tests the check firmware of the check module 204. And when the initial cyclic check code is different from the cyclic check code to be tested, continuing to test under the condition of the next parameter set. Specifically, the memory 200 is set according to parameters such as the voltage of the parameter set and the transmission speed of the interface, and initial preset information is sent to the memory 200, and the above test is continued until all the parameter sets are tested. In the step of obtaining the comparison result data, after the comparison result data is obtained, the verification information is sent to the memory 200, and whether the read-write of the verification information can be correctly completed is tested, so that the test error caused by the error of the read-write of the memory 200 is eliminated.
Referring to fig. 1 to 5, the present invention provides a testing method of a storage testing device 100 for performing a pressure test on a storage 200. The test method of the storage test device 100 includes steps S10 to S50.
Step S10, a plurality of parameter sets are set, wherein the parameter module at least comprises a power supply voltage, an interface transmission speed, a clock frequency, a writing mode, initial preset information and a corresponding initial cyclic check code.
Step S20, selecting a parameter set, sending the initial preset information to the microprocessor, and changing the initial preset information by keeping the initial cyclic check code unchanged to obtain the preset information to be detected.
Step S30, writing preset information to be tested into the flash memory chip, obtaining a cyclic check code to be tested of the preset information to be tested, and comparing the cyclic check code to be tested with the initial cyclic check code.
And S40, updating the verification firmware of the verification module when the initial cyclic verification code is the same as the cyclic verification code to be tested, and retesting the updated verification firmware.
And S50, when the initial cyclic check code is different from the cyclic check code to be tested, replacing the parameter set and retesting until the parameter set is traversed.
Referring to fig. 1 to 5, in an embodiment of the invention, before step S10, test firmware is entered 301 into the memory test device 100, and the memory test device 100 is initialized. The test firmware 301 may implement the test method of steps S20 to S50 according to the present invention. In the present embodiment, after the entry of the test firmware 301 is completed through the interface 106, the memory 200 is installed in the socket 103. The memory 200, the central processing unit 101, the memory 102 and the memory card 105 are then powered up by the power supply 104. Specifically, the external host is electrically connected to the cpu 101 through the interface 106. Wherein interface 106 is a USB interface. The control module 300 of the cpu 101 is then turned on by the external host, and the test firmware 301 is burned into the control module 300. The memory 200, the central processing unit 101, the memory 102 and the memory card 105 are then powered up by the power supply 104.
Referring to fig. 1 to 5, in an embodiment of the invention, in step S10, a plurality of parameter sets are set. The parameter set at least comprises a power supply voltage, an interface transmission speed, a clock frequency, a writing mode, initial preset information and a corresponding initial cyclic check code. The power supply voltage is the power supply voltage of the memory 200, and in this embodiment, the power supply voltage is, for example, 1.1v to 3.6v. The interface transmission speed is the data transmission speed between the memory 200 and the central processing unit 101. In this embodiment, the interface transmission speed may be a data transmission speed of a Synchronous Dynamic Random Access Memory (SDRAM). Specifically, the interface transmission speed is, for example, 66MT/s, for example, 100MT/s, or, for example, 133MT/s. In this embodiment, the interface transmission speed may be a data transmission speed of the DDR memory. Specifically, the interface transmission speed is 266MT/s to 400MT/s, for example. In this embodiment, the interface transmission speed may be a flash memory data transmission speed of the model HS 200. Specifically, the interface transmission speed is, for example, 200MB/s. In this embodiment, the interface transmission speed may be a flash memory data transmission speed of the model HS 400. Specifically, the interface transmission speed is, for example, 400MB/s. Wherein the clock frequency is, for example, 0 to 200MHz. And may be, in particular, for example, 100MHz, for example 133MHz, for example 166MHz, for example 200MHz, etc. Wherein the clock signal may be a single transmission rate or a double transmission rate. Wherein the data transmission or the transmission of control signals or signal addressing, etc. is only performed at the rising edge of the clock at a single transmission rate. The data transmission can be performed on the rising edge and the falling edge of the clock under the double rate transmission, and the transmission of the control signal or the signal addressing can be performed on the rising edge of the clock. In this embodiment, the write mode may be support of single memory block writing, support of multiple memory block writing, queue writing, predefined manner (Pre-defined) writing, and open-end writing. Wherein the memory block is a physical block (block) in the flash memory chip 203. In this embodiment, the write mode of writing to the single memory block corresponding to the command CMD24 may be used, the write mode of writing to the single memory block corresponding to the command CMD25 may be used, and the write mode of writing to the single memory block corresponding to the command CMDQ may be used.
Referring to fig. 1 to 5, and referring to the following table, in an embodiment of the present invention, the initial default information may be user data or a Command (CMD). In step S10, known user data and control commands are preset. In this embodiment, a plurality of initial preset information is set, and the initial preset information has a corresponding initial cyclic check code.
The plurality of initial preset information and initial cyclic check codes are shown in the following table:
。
referring to fig. 1 to 5, and as shown in the above table, in step S10, the predetermined information is, for example, 10 bits, and the predetermined information includes a first bit and a last bit. In this embodiment, the first bit of the preset information is, for example, 0, the last bit is, for example, 1, and the middle 8 bits may be set randomly. In this embodiment, the preset information set by the cpu 101 is defined as initial preset information, and the initial preset information modified by the microprocessor 201 is defined as preset information to be measured. In step S10, a plurality of initial preset information is set, and the arrangement of the middle bits of the preset information is traversed by the plurality of initial preset information. Wherein the plurality of initial preset information and the initial cyclic check code are arranged to form an original information table, as shown in the above table. The original information table comprises a data number, first bit data, last bit data, a plurality of middle bit data, an initial cyclic check code and check data. Wherein the data number is the ordering number of the initial preset information. As shown in the table above, the present invention shows, for example, 8 data, and is data0 to data7. In the original information table shown in the above table, the first data is 0, the last data is 1, and the preset information is arranged in a horizontal line. In this embodiment, the check data is the sum of the middle bit data of the initial preset information along the column. In this embodiment, the preset information is two-level system data, and the check data is hexadecimal data. For example, the sum of the first column of middle bit data is 69 in hexadecimal, and the binary data from top to bottom is 01101001. For another example, the sum of the last column of middle bit data is AF in hexadecimal, and binary data from top to bottom is 10101111. CRC16 (origin) in the original information table is the initial cyclic check code. In the invention, the initial cyclic check code is obtained by cyclic redundancy check. The invention does not limit the specific value of the initial cyclic check code, nor the cyclic redundancy check algorithm for acquiring the initial cyclic check code.
Referring to fig. 1 to 5, after setting the parameter set in an embodiment of the present invention, different types of parameter sets may be set according to the type of the memory 200, and different variables may be set in the parameter sets. For example, the supply voltage in the parameter set is set as a variable. The preset information in the parameter set, the data transmission speed, the bus width, the clock frequency, the writing mode, and the like are all set as the optimal parameters. Where the optimal parameters refer to the experimentally obtained operating parameters of the most adapted memory 200. For example, for eMMC chips, the supply voltage may be, for example, 1.8V or, for example, 3.3V. The clock frequency may be, for example, 200MB/s or 400MB/s. According to the parameter quantity in the parameter set, a plurality of configuration conditions can be set, and different parameters are respectively set as unique variables, so that the test efficiency is improved. The source manufacturer or model of the memory 200 and the distribution density of chips in the memory 200 can directly use different configuration conditions without traversing the parameter set.
Referring to fig. 1 to 6, in step S20, a parameter set is selected randomly or sequentially from among the parameter sets, and the operating parameters of the memory 200 are set according to the parameter set. The initial preset information is then sent from the central processor 101 to the microprocessor 201. In the microprocessor 201, the initial preset information is changed to obtain the preset information to be measured. And keeping the initial cyclic check code unchanged, so that the preset information to be detected and the initial cyclic check code are positioned in the same original information table. It should be noted that, the initial preset information and the initial cyclic check code are corresponding to each other, and after the initial preset information is changed, the preset information to be tested and the initial cyclic check code are not corresponding to each other, so that a data transmission error generated in the transmission process from the central processing unit 101 to the microprocessor 201 or from the microprocessor 201 to the flash memory chip 203 is simulated. Specifically, in the step of changing the initial cyclic check code, the value of the check data is changed, and the value of the check data is converted into the secondary system data. And changing middle bit data in the original information table according to the converted secondary system data to obtain a first information table.
For example, the first information table is shown in the following table:
。
referring to fig. 1 to 6, and referring to the table, in an embodiment of the invention, one or more middle bit data in the check data are randomly changed to form new check data and preset information to be tested. In this embodiment, the preset information to be measured is the horizontal line data in the first information table, and the preset information to be measured is the modified preset information. For example, 0×69 is modified to 0×29, 0×4c is modified to 0×5c, 0×af is modified to 0×be, and the like. The initial cyclic check codes in the first information table and the original information table are the same, and the first position and the last position of preset information to be detected are also the same as the preset information.
Referring to fig. 1 to 5, and referring to the table below, in step S30, the predetermined information to be tested is sent to the flash memory chip 203, and the address mapping information of the predetermined information to be tested is stored in the cache chip 202. And the predetermined information to be tested passes through the verification module 204 in the process of being transmitted to the flash memory chip 203. The verification module 204 verifies the preset information to be tested to obtain the cyclic verification code to be tested. If the verification module 204 is in a normal working state, the to-be-detected cyclic verification code and the to-be-detected preset information are in a corresponding relationship. After the verification module 204 verifies, the initial cyclic check code in the first information table is changed to obtain the cyclic check code to be tested, and a second information table is formed.
For example, the second information table is shown in the following table:
。
referring to fig. 1 to 5, in an embodiment of the invention, after comparing the to-be-tested cyclic check code with the initial cyclic check code in step S40 and step S50, if the to-be-tested cyclic check code and the initial cyclic check code are identical, the check module 204 does not detect an error of the first preset information, and step S40 is performed. In step S40, a plurality of pieces of preset information to be measured are set in the first information table and the second information table. Each piece of preset information to be tested corresponds to the cyclic check code to be tested. And comparing the initial preset information with the check codes of the preset information to be tested, wherein the initial preset information and the check codes of the preset information to be tested are the same in number, namely comparing the initial cyclic check codes with the cyclic check codes to be tested. Any of the sets of check codes is the same and then the current operating environment is deemed to have exceeded the endurance capacity of the check module 204. For example, if the value of the cyclic check code to be tested of data4 is CRC16 (origin), then the check of data4 is erroneous. Thus, step S40 is performed to adjust the verification algorithm. The method for adjusting the verification algorithm is not limited by the invention. If any set of the to-be-tested cyclic check codes is different from the initial cyclic check code, the check module 204 has not reached the upper bearing limit. Therefore, step S50 is performed to change the parameter set, and steps S20 to S50 are continued. It should be noted that, in this embodiment, the parameter set is continuously changed until the parameter set is traversed, so that an arbitrary working environment can be simulated, and thus the pressure-bearing capacity of the verification module 204 is comprehensively tested, and the pressure-bearing capacity of the verification module 204 is determined.
Referring to fig. 1 to 5, in an embodiment of the invention, the storage test device 100 may be placed in a normal temperature environment or a set temperature environment for testing, so as to simulate the working environment of the verification module 204 in a high temperature environment or a low temperature environment. It should be noted that, the multiple sets of preset information in the second information table are not synchronized to complete verification. While the current preset information is written into the cache chip 202 or the flash memory chip 203, the last written preset information is checked, and a to-be-tested cyclic check code of the last preset information is obtained. After a set of preset information is written, comparison of the to-be-tested cyclic check code and the initial cyclic check code can be performed. The comparison of the to-be-tested cyclic check code and the initial cyclic check code can also be carried out after each piece of preset information is written. In this embodiment, the data writing process, the checking process, and the data reading process of the memory 200 can be performed simultaneously to simulate the normal use environment of the memory 200.
Referring to fig. 1 to 5, and fig. 7, in an embodiment of the invention, before step S50, it is verified whether the memory 200 is operating normally. And the step of verifying whether the memory 200 is operating normally includes steps S61 to S63.
Step S61, verification information is set, and the verification information is written into the flash memory chip.
Step S62, the verification information is read out from the flash memory chip.
Step S63, when the read authentication information and the written authentication information are the same, step S50 is performed.
Referring to fig. 1 to 5 and fig. 7, in step S61, the verification information may be any data or initial preset information. Address mapping information of the verification information is stored in the cache chip 202 while the verification information is written in the flash memory chip 203. In step S62, the verification information is read out from the flash memory chip 203 according to the address mapping information in the cache chip 202. In step S63, the read-out authentication information and the written authentication information are compared. When the read authentication information and the written authentication information are inconsistent, the storage capacity of the memory 200 is doubtful, and bad blocks may occur. The test is stopped and the memory 200 is checked or the memory 200 is replaced. When the read verification information and the written verification information are consistent, the memory 200 is normal, and the test process of the test device 100 is continued to be stored until the verification firmware of the verification module 204 can traverse the parameter set and pass the stress test. After traversing the parameter sets, the test is ended. The microprocessor 201 generates test data and transmits the test data to the central processor 101.
Referring to fig. 1 to 5, and fig. 7, in an embodiment of the invention, if the verification module 204 is stuck during the execution of steps S10 to S60, the test is stopped and the cause of the stuck is analyzed. Wherein the verification module 204 blocks data embodied in that the microprocessor 201 did not receive the return of the verification module 204 within a threshold time. The cause of the jamming may be that another process occupies too much memory resource, a certain hardware fails, or the firmware is not designed reasonably. In the present embodiment, the cause of the seizing of the verification module 204 is analyzed according to various parameters of the memory 200, and the cause of seizing is sent to the application error collection unit 309. The verification firmware of the verification module 204 is then modified to optimize the verification algorithm. The invention does not limit how the verification algorithm is optimized. In the process of the testing method, not only the unsuitable use environment of the verification module 204 can be comprehensively checked, but also the potential risk of the memory 200 can be found in the testing process. The memory 200 according to the present invention has extremely high compatibility, and can be applied to various environments, or has particularly efficient verification capability in specific environments.
The invention provides a storage testing device and a testing method thereof, and the storage testing device is used for testing a memory. The storage testing device comprises a central processing unit, and the central processing unit is electrically connected with the memory. The central processing unit comprises a storage unit, a check code modification unit, a check code acquisition unit and a check code comparison unit. The storage unit stores a plurality of parameter sets, and the parameter sets at least comprise initial preset information and initial cyclic check codes of the initial preset information. After the memory receives the initial preset information, the check code acquires the preset information to be detected according to the initial preset information after the partial data are overturned. After the preset information to be tested is written into the memory, the check code acquisition unit acquires the cyclic check code to be tested of the preset information to be tested from the memory. The check code comparison unit is used for acquiring comparison result data of the to-be-tested cyclic check code and the initial cyclic check code, and storing the test device to traverse and test a plurality of parameter groups or stop the test according to the comparison result data. The invention provides a storage testing device and a testing method thereof, which can simulate various process environments of cyclic redundancy check so as to comprehensively test the bearable strength of the storage equipment for cyclic redundancy check and further improve the delivery efficiency of the storage equipment. According to the storage testing device and the testing method thereof, the bias of the cyclic check test can be flexibly adjusted according to products in different application environments, so that the testing accuracy is considered, and the testing efficiency is improved. According to the storage testing device and the testing method thereof, the storage reliability of the storage equipment can be ensured, and the compatibility of the storage equipment is improved, so that the production of high-grade storage equipment is facilitated.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (10)
1. The storage testing device is used for testing a memory, and comprises a central processing unit, and the central processing unit is electrically connected with the memory, wherein the central processing unit comprises:
the storage unit is used for storing a plurality of parameter sets, wherein the parameter sets at least comprise initial preset information and initial cyclic check codes of the initial preset information;
the check code modification unit takes the initial preset information after partial data are overturned as preset information to be detected after the memory receives the initial preset information;
the verification code acquisition unit acquires a to-be-detected cyclic verification code of the to-be-detected preset information from the memory after the to-be-detected preset information is written into the memory; and
and the check code comparison unit is used for acquiring comparison result data of the to-be-tested cyclic check code and the initial cyclic check code, and the storage test device traverses and tests a plurality of parameter sets or stops testing according to the comparison result data.
2. The memory test device of claim 1, wherein the set of parameters further comprises a supply voltage of the memory, an interface transfer speed of the memory, a clock frequency of the memory, and a write mode of the memory.
3. The memory test device of claim 1, wherein the initial predetermined information is user data or host instructions.
4. The memory test device according to claim 1, wherein the initial preset information and the preset information to be tested respectively include first data, last data and a plurality of intermediate data, wherein the first data and the last data of the initial preset information and the preset information to be tested are the same, and the initial preset information and part of the intermediate data of the preset information to be tested are opposite.
5. The memory test device of claim 1, wherein the memory test device comprises a socket, the socket is electrically connected to the memory, and the socket is connected to the memory in a pluggable manner.
6. The memory test device of claim 1, wherein the memory test device stops testing when the initial cyclic check code and the cyclic check code under test are the same.
7. A memory test device according to claim 1, wherein when the initial cyclic check code and the cyclic check code to be tested are different, the memory test device tests another parameter set until traversing the parameter set in the memory cell.
8. A method of testing a memory test device based on a memory test device according to claim 1, comprising the steps of:
setting a plurality of parameter sets, wherein the parameter sets at least comprise initial preset information and initial cyclic check codes of the initial preset information;
the initial preset information is sent to a memory, and partial data of the initial preset information are overturned to obtain preset information to be detected;
writing the preset information to be tested into the memory, and checking the preset information to be tested to obtain a cyclic check code to be tested; and
and comparing the initial cyclic check code with the cyclic check code to be tested, obtaining comparison result data, and traversing a plurality of parameter sets to be tested or stopping testing according to the comparison result data.
9. The method according to claim 8, wherein when the initial cyclic check code and the cyclic check code to be tested are different, the next parameter set is acquired and tested until the parameter set in the memory unit is traversed.
10. The method of claim 8, wherein when the initial cyclic check code and the cyclic check code to be tested are the same, stopping the test and adjusting the check firmware of the memory.
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