CN117394852A - Method and device for achieving output phase consistency of multi-path second pulse signals - Google Patents
Method and device for achieving output phase consistency of multi-path second pulse signals Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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Abstract
The invention discloses a method and a device for realizing the consistency of output phases of multipath second pulse signals, and belongs to the technical field of time frequency. The method comprises the following steps: configuring an initial delay value for the delay module; generating a plurality of paths of second pulse signals, and outputting the second pulse signals to a delay module, wherein the plurality of paths of second pulse signals comprise one path of first signals and at least one path of second signals; the delay module carries out delay processing on the second pulse signal according to the delay value and outputs the second pulse signal to the interface module; the interface module outputs the second pulse signal in two paths, wherein one path of the second pulse signal is output to the control module to form a loop-back signal; the control module outputs loop signals of the first signal and loop signals of one path of second signal to the phase detection module as a group of loop signals; the phase discrimination module performs phase difference measurement on the received two loops of loop signals; the control module generates a delay value according to the phase difference measurement result and configures the delay value to the delay module. The invention realizes the alignment of the phases of each path of signal and the reference signal.
Description
Technical Field
The invention belongs to the technical field of time frequency, and particularly relates to a method and a device for realizing output phase consistency of multipath pulse per second signals.
Background
Time frequency is the basis of modern information technology, belongs to basic support technology in modern construction, and time frequency products can be divided into two major categories, namely frequency series and time synchronization series. The frequency series product generates various frequency signals required for electronic devices and systems by generating and processing the frequency signals. The frequency series products comprise atomic clocks, crystal devices, frequency components and equipment. The time synchronization serial products provide unified time and frequency signals for each application system by receiving, generating, maintaining and transmitting standard time and frequency signals. The time synchronization series products comprise board cards, modules, equipment, systems and the like, and are mainly applied to the fields of weapon equipment, aerospace, satellite communication, military and civil communication, electric power, traffic, internet of things and the like.
A pulse per second (pps) signal is often used as a time standard for access to terminal devices requiring time synchronization. The standard second pulse signal is usually output by a high-precision time service type satellite navigation module (gps module/bd 2 module and the like), the precision is about +/-20 ns, the standard second pulse signal is connected to a transmission device, a reference frequency source of the transmission device is calibrated, and then the calibrated multi-path second pulse signal is output to different terminal devices through the transmission device.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a method and a device for realizing the consistency of output phases of multipath pulse per second signals.
The aim of the invention is realized by the following technical scheme:
the first aspect of the invention discloses a method for realizing the consistency of output phases of multi-path pulse per second signals, which comprises the following steps:
the control module configures an initial delay value for each delay module;
the control module generates a plurality of paths of second pulse signals and outputs each path of second pulse signals to the corresponding delay module, wherein the plurality of paths of second pulse signals comprise a path of first signals and at least a path of second signals;
the delay module carries out delay processing on the received second pulse signal according to the delay value configured by the control module, and outputs the second pulse signal after the delay processing to the corresponding interface module;
the interface module performs level conversion on the received second pulse signal, and outputs the second pulse signal after the level conversion in two paths, wherein one path of second pulse signal is output to an external interface, and the other path of second pulse signal is output to the control module to form a loop-back signal;
the control module outputs each group of loop signals to the corresponding phase discrimination module, and each group of signals to be detected comprises a loop signal of a first signal and a loop signal of a second signal;
the phase discrimination module performs phase difference measurement on the received two loops of loop signals;
the control module generates a time delay value for phase compensation according to the phase difference measurement result, and configures the time delay value to a corresponding time delay module;
the delay module delays the second pulse signal according to the initial delay value, and the phase of the first signal lags behind the phase of the second signal.
Further, the control module generates a plurality of paths of second pulse signals and outputs each path of second pulse signals to the corresponding delay module, wherein the plurality of paths of second pulse signals comprise a path of first signals and at least a path of second signals, and the method comprises the following steps:
the control module receives a clock signal from an external clock;
the control module divides the frequency of the clock signal to generate a plurality of paths of second pulse signals, one path of second pulse signals are determined to be first signals, and each path of other second pulse signals are determined to be second signals;
the control module outputs each path of pulse per second signal to the corresponding delay module.
Further, the phase discrimination module performs phase difference measurement on the received two loops of signals, and the phase discrimination module comprises:
the phase discrimination module performs digital coding on the received two loops of loop signals and extracts input waveform information;
the phase discrimination module performs phase difference extraction on the waveform information;
and the phase discrimination module performs phase difference calculation according to the data obtained by phase difference extraction.
Further, the phase discrimination module performs phase difference measurement on the received two loops of signals, and the phase discrimination module comprises:
the analog processing unit of the phase discrimination module carries out digital coding on two loops of signals from the control module, extracts input waveform information and outputs the waveform information to the first wave unit of the phase discrimination module;
the first wave unit judges whether the waveform information meets the quality requirement or not, and outputs the waveform information to a time-to-digital converter of the phase discrimination module when the waveform information meets the quality requirement;
the time-to-digital converter performs phase difference extraction on the received waveform information according to the phase difference measurement steps set in the control module configuration register of the phase detection module, and writes data obtained by the phase difference extraction into the original data register of the phase detection module;
the arithmetic logic unit of the phase discrimination module performs phase difference calculation according to the data written into the original data register by the time-to-digital converter, and writes the calculated phase difference into the read register.
The second aspect of the invention discloses a device for realizing the consistency of output phases of multi-path pulse per second signals, which comprises:
the control module is used for generating a plurality of paths of second pulse signals and outputting each path of second pulse signals to the corresponding delay module, wherein the plurality of paths of second pulse signals comprise a path of first signals and at least a path of second signals;
the control module is also used for configuring an initial delay value for the delay module;
the delay module is used for carrying out delay processing on the received second pulse signal according to the delay value configured by the control module and outputting the second pulse signal subjected to delay processing to the interface module;
the interface module is used for carrying out level conversion on the received second pulse signal, outputting the second pulse signal after the level conversion in two paths, wherein one path of second pulse signal is output to an external interface, and the other path of second pulse signal is output to the control module to form a loop signal;
the control module is further used for outputting each group of loop signals to the phase discrimination module, and each group of signals to be detected comprises a loop signal of the first signal and a loop signal of one path of second signal;
the phase discrimination module is used for carrying out phase difference measurement on the received loop-back signal;
the control module is also used for generating a time delay value for phase compensation according to the phase difference measurement result and configuring the time delay value to the corresponding time delay module;
the delay module delays the second pulse signal according to the initial delay value, and the phase of the first signal lags behind the phase of the second signal.
Further, the delay module includes:
a decoding register for storing the delay value from the control module;
a control register for storing an enable signal from the control module;
and the time delay control module is used for carrying out phase compensation on the second pulse signal according to the time delay value under the action of the enabling signal.
Further, the phase discrimination module includes:
the control module configuration register is used for storing configuration information from the control module;
reading a register;
an original data register;
the analog processing unit is used for digitally encoding the two loops of signals from the control module, extracting input waveform information and outputting the waveform information to the first wave unit;
the first wave unit is used for judging whether the waveform information meets the quality requirement or not, and outputting the waveform information to the time-to-digital converter when the waveform information meets the quality requirement;
the time-to-digital converter is used for extracting the phase difference of the received waveform information according to the phase difference measurement stepping setting set in the control module configuration register, and writing the data obtained by the phase difference extraction into the original data register;
the arithmetic logic unit is used for performing phase difference calculation according to the data written into the original data register by the time-to-digital converter and writing the calculated phase difference into the read register;
and the SPI interface is used for realizing communication between the phase discrimination module and the control module.
Further, the wires of each loop signal are equal in length.
Further, the apparatus further comprises:
and the clock source is used for outputting a clock signal to the control module.
The beneficial effects of the invention are as follows: the invention designs a loop feedback loop mechanism and a real-time dynamic phase difference measurement compensation mechanism of the second pulse signal, realizes the alignment of the phases of each path of signal and the reference signal, and realizes the consistency of multiple paths of second pulse signals.
Drawings
FIG. 1 is a flow chart of the method of the present invention;
FIG. 2 is a block diagram of one component of the apparatus of the present invention;
fig. 3 is a block diagram of yet another embodiment of the apparatus of the present invention.
Detailed Description
The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by a person skilled in the art without any inventive effort, are intended to be within the scope of the present invention, based on the embodiments of the present invention.
Referring to fig. 1 to 3, the present invention provides a method and apparatus for implementing output phase consistency of multiple second pulse signals:
a first aspect of the present embodiment discloses a method for implementing output phase consistency of multiple second pulse signals, as shown in fig. 1, where the method includes steps S100 to S700.
S100, the control module configures initial delay values for each delay module.
Specifically, after the delay module delays the second pulse signal according to the initial delay value, the phase of the first signal lags behind the phase of the second signal. For example, the initial delay value corresponding to the second signal is 0ms, and the initial delay value corresponding to the first signal is a certain value.
And S200, the control module generates a plurality of paths of second pulse signals and outputs each path of second pulse signals to the corresponding delay module, wherein the plurality of paths of second pulse signals comprise one path of first signals and at least one path of second signals.
In some embodiments, step S200 specifically includes steps S210 to S230.
Step S210, the control module receives a clock signal from an external clock.
For example, the control module receives a clock signal from an external clock source.
S220, the control module divides the frequency of the clock signal to generate multiple paths of second pulse signals, one path of second pulse signals are determined to be first signals, and each path of other second pulse signals are determined to be second signals.
For example, the control module divides the clock signal into multiple second pulse signals via a frequency divider.
Specifically, one second pulse signal is selected from all the generated second pulse signals as a reference signal, and is recorded as a first signal, and then each second pulse signal except the first signal is recorded as a second signal.
And S230, the control module outputs each path of second pulse signal to the corresponding delay module.
Specifically, each path of pulse per second signal is subjected to time delay processing through an independent time delay module, so that corresponding time delay values can be independently configured for each path of pulse per second signal, and further accurate phase compensation of each path of pulse per second signal is realized.
And S300, the delay module carries out delay processing on the received second pulse signal according to the delay value configured by the control module, and outputs the second pulse signal after the delay processing to the corresponding interface module.
Specifically, the initial delay value of the delay module can be set according to the requirement, and only the delay module needs to ensure that the phase of the first signal lags behind the phase of the second signal after delay processing is performed on the second pulse signal according to the initial delay value. If the control module does not configure a new delay value (delay value for phase compensation) for a certain delay module, the delay module carries out delay processing on the second pulse signal according to the current delay value all the time; if the control module configures a new delay value for a certain delay module, the delay module carries out delay processing on the second pulse signal according to the new delay value until the control module configures a new delay value for the delay module.
In general, the delay modules are in one-to-one correspondence with the interface modules, and each delay module outputs a second pulse to the corresponding interface module.
And S400, the interface module performs level conversion on the received second pulse signal, and outputs the second pulse signal after the level conversion in two paths, wherein one path of second pulse signal is output to an external interface, and the other path of second pulse signal is output to the control module to form a loop signal.
S500, the control module outputs each group of loop signals to the corresponding phase discrimination module, wherein each group of signals to be detected comprises a loop signal of a first signal and a loop signal of a second signal.
And S600, performing phase difference measurement on the received two loops of loop signals by the phase discrimination module.
In some embodiments, the phase detection module performs phase difference measurement on the received two loop signals, including steps S601 to S603.
S601, the phase discrimination module carries out digital coding on the received two loops of loop signals, and extracts input waveform information.
S602, phase difference extraction is carried out on the waveform information by the phase discrimination module.
And S603, performing phase difference calculation by the phase difference module according to the data obtained by phase difference extraction.
In some embodiments, the phase detection module performs phase difference measurement on the received two loop signals, including steps S611 to S614.
S611, the analog processing unit of the phase discrimination module carries out digital coding on the two loops of signals from the control module, extracts waveform information input by the two loops of signals, and outputs the waveform information to the first wave unit of the phase discrimination module.
And S612, the first wave unit judges whether the waveform information meets the quality requirement or not, and outputs the waveform information to the time-digital converter of the phase discrimination module when the waveform information meets the quality requirement. And S613, the time-to-digital converter extracts the phase difference of the received waveform information according to the phase difference measurement steps set in the configuration register of the control module of the phase detection module, and writes the data obtained by the phase difference extraction into the original data register of the phase detection module. The phase difference measurement step refers to a minimum sampling interval corresponding to a sampling frequency, for example, a minimum sampling interval corresponding to a sampling rate of 1GHz is 1ns, and different sampling rates are set according to the input clock frequency in this embodiment.
In some embodiments, when the waveform information does not meet the requirements, the time-to-digital converter does not sample and extract the waveform information and counts the abnormal waveform, and then stores the count in a register. The time-to-digital converter encodes the input waveform, sets the sampling rate to 1GHz, the sampling duration to 1ms, and when the second pulse waveform is converted from low level to high level, the high level duration to 1ms, the rise time (10%V) H ～90％V H ) Waveform information that does not satisfy a rise time of more than 20ns and a high level duration of less than 1ms is regarded as not satisfying 20nsAnd if not, the waveform information meets the quality requirement.
And S614, the arithmetic logic unit of the phase discrimination module performs phase difference calculation according to the data written into the original data register by the time-to-digital converter, and writes the calculated phase difference into the read register.
And S700, the control module generates a time delay value for phase compensation according to a phase difference measurement result, and configures the time delay value to a corresponding time delay module.
For example, the phase discrimination module calculates the phase difference between the loop-back signal of the first signal and the loop-back signal of the second signal A, and stores the phase difference in the read register, the control module reads the phase difference in the read register through the SPI interface, then generates a delay value for phase compensation according to the phase difference, and configures the delay value to the delay module corresponding to the second signal A, so as to realize the phase compensation of the second signal A.
In this embodiment, after receiving data every second, the control module performs phase discrimination operation, obtains a compensation value, and performs phase compensation to align phases of each path of second signal and the first signal, thereby realizing consistency of multiple paths of second pulse signals.
The second aspect of the embodiment discloses a device for realizing the phase consistency of the output of the multipath pulse per second signals, which comprises a control module, a delay module, an interface module and a phase discrimination module. As shown in fig. 2, the FPGA in fig. 2 is a control module, the PDC is a delay module, the interface chip is an interface module, and the TDC is a phase discrimination module.
The control module is used for generating a plurality of paths of second pulse signals and outputting each path of second pulse signals to the corresponding delay module, wherein the plurality of paths of second pulse signals comprise one path of first signals and at least one path of second signals.
The control module is also used for configuring an initial delay value for the delay module. The delay module delays the second pulse signal according to the initial delay value, and the phase of the first signal lags behind the phase of the second signal.
The control module is also used for outputting each group of loop signals to the phase detection module, and each group of signals to be detected comprises the loop signals of the first signals and the loop signals of one path of second signals.
The control module is also used for generating a time delay value for phase compensation according to the phase difference measurement result and configuring the time delay value to the corresponding time delay module.
In some embodiments, the delay module is coupled to the control module through a parallel interface. During compensation, the control module communicates with the delay module through the multi-bit parallel data interface and transmits the delay value, so that the phase compensation function is completed.
The delay module is used for carrying out delay processing on the received second pulse signal according to the delay value configured by the control module and outputting the second pulse signal subjected to delay processing to the interface module.
The interface module is used for carrying out level conversion on the received second pulse signal, and outputting the second pulse signal after the level conversion in two paths, wherein one path of second pulse signal is output to the external interface, and the other path of second pulse signal is output to the control module to form a loop signal.
In this embodiment, the interface module is used to implement signal conversion and signal loop function, the type of the interface module is determined by the type of the output signal, and the type of the output signal is usually LVDS, RS422, RS485, etc., and by converting the output LvTTL into the type of the output signal required by the system, the interface module in fig. 2 adopts an LVDS bus interface, and after the conversion output, the interface module can be directly input to the signal pin of the FPGA to complete the loop function of second pulse.
In some embodiments, the wires of each loop signal are equal in length, so that phase difference caused by different wire lengths of each loop signal is avoided, and the accuracy of phase compensation is improved.
The phase discrimination module is used for carrying out phase difference measurement on the received loop-back signal.
In some embodiments, as shown in fig. 3, the delay module includes a decode register, a control register, and a delay control unit. The FPGA in fig. 3 is a control module, the PDC is a delay module, the interface chip is an interface module, and the TDC is a phase discrimination module.
The decode register is used to store the delay value from the control module.
The control register is used for storing an enable signal from the control module.
The time delay control module is used for carrying out phase compensation on the second pulse signal according to the time delay value under the action of the enabling signal.
In some embodiments, as shown in fig. 3, the phase discrimination module includes a control module configuration register, a read register, a raw data register, an analog processing unit, a first wave unit, a time to digital converter, an arithmetic logic unit, and an SPI interface.
The control module configuration register is used for storing configuration information from the control module.
The analog processing unit is used for carrying out digital coding on the two loops of signals from the control module, extracting input waveform information and outputting the waveform information to the first wave unit.
The first wave unit is used for judging whether the waveform information meets the quality requirement or not, and outputting the waveform information to the time-digital converter of the phase discrimination module when the waveform information meets the quality requirement.
The time-to-digital converter is used for extracting the phase difference of the received waveform information according to the phase difference measurement stepping setting set in the control module configuration register, and writing the data obtained by the phase difference extraction into the original data register.
The arithmetic logic unit is used for performing phase difference calculation according to the data written into the original data register by the time-to-digital converter, and writing the calculated phase difference into the read register.
The SPI interface is used for realizing communication between the phase discrimination module and the control module. For example, the SPI interface is a 4-wire SPI interface, and is configured to receive configuration information from the control module, configure the control module configuration registers (for example, configure a sampling rate, and meet the requirements of waveform quality (waveform high level duration and waveform rise time register)), and simultaneously parse other read instruction information from the control module (for example, the waveform rise time register, waveform rise middle time register, waveform normal flag bit register, and two inter-waveform phase difference registers), and retransmit phase difference data to the control module to implement extraction of phase differences between input signals.
In some embodiments, the apparatus further comprises a clock source for outputting a clock signal to the control module.
The foregoing is merely a preferred embodiment of the invention, and it is to be understood that the invention is not limited to the form disclosed herein but is not to be construed as excluding other embodiments, but is capable of numerous other combinations, modifications and environments and is capable of modifications within the scope of the inventive concept, either as taught or as a matter of routine skill or knowledge in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.
Claims (9)
1. A method for achieving phase consistency of a multi-path pulse per second signal output, comprising:
the control module configures an initial delay value for each delay module;
the control module generates a plurality of paths of second pulse signals and outputs each path of second pulse signals to the corresponding delay module, wherein the plurality of paths of second pulse signals comprise a path of first signals and at least a path of second signals;
the delay module carries out delay processing on the received second pulse signal according to the delay value configured by the control module, and outputs the second pulse signal after the delay processing to the corresponding interface module;
the interface module performs level conversion on the received second pulse signal, and outputs the second pulse signal after the level conversion in two paths, wherein one path of second pulse signal is output to an external interface, and the other path of second pulse signal is output to the control module to form a loop-back signal;
the control module outputs each group of loop signals to the corresponding phase discrimination module, and each group of signals to be detected comprises a loop signal of a first signal and a loop signal of a second signal;
the phase discrimination module performs phase difference measurement on the received two loops of loop signals;
the control module generates a time delay value for phase compensation according to the phase difference measurement result, and configures the time delay value to a corresponding time delay module;
the delay module delays the second pulse signal according to the initial delay value, and the phase of the first signal lags behind the phase of the second signal.
2. The method of claim 1, wherein the control module generates a plurality of pulse-per-second signals and outputs each pulse-per-second signal to a corresponding delay module, the plurality of pulse-per-second signals including a first signal and at least a second signal, and the method comprises:
the control module receives a clock signal from an external clock;
the control module divides the frequency of the clock signal to generate a plurality of paths of second pulse signals, one path of second pulse signals are determined to be first signals, and each path of other second pulse signals are determined to be second signals;
the control module outputs each path of pulse per second signal to the corresponding delay module.
3. The method for achieving phase consistency of output phases of multiple second pulse signals according to claim 1, wherein the phase discrimination module performs phase difference measurement on the received two loop signals, and the method comprises the following steps:
the phase discrimination module performs digital coding on the received two loops of loop signals and extracts input waveform information;
the phase discrimination module performs phase difference extraction on the waveform information;
and the phase discrimination module performs phase difference calculation according to the data obtained by phase difference extraction.
4. The method for achieving phase consistency of output phases of multiple second pulse signals according to claim 1, wherein the phase discrimination module performs phase difference measurement on the received two loop signals, and the method comprises the following steps:
the analog processing unit of the phase discrimination module carries out digital coding on two loops of signals from the control module, extracts input waveform information and outputs the waveform information to the first wave unit of the phase discrimination module;
the first wave unit judges whether the waveform information meets the quality requirement or not, and outputs the waveform information to a time-to-digital converter of the phase discrimination module when the waveform information meets the quality requirement;
the time-to-digital converter performs phase difference extraction on the received waveform information according to the phase difference measurement steps set in the control module configuration register of the phase detection module, and writes data obtained by the phase difference extraction into the original data register of the phase detection module;
the arithmetic logic unit of the phase discrimination module performs phase difference calculation according to the data written into the original data register by the time-to-digital converter, and writes the calculated phase difference into the read register.
5. An apparatus for achieving phase consistency of output of multiple second pulse signals, comprising:
the control module is used for generating a plurality of paths of second pulse signals and outputting each path of second pulse signals to the corresponding delay module, wherein the plurality of paths of second pulse signals comprise a path of first signals and at least a path of second signals;
the control module is also used for configuring an initial delay value for the delay module;
the delay module is used for carrying out delay processing on the received second pulse signal according to the delay value configured by the control module and outputting the second pulse signal subjected to delay processing to the interface module;
the interface module is used for carrying out level conversion on the received second pulse signal, outputting the second pulse signal after the level conversion in two paths, wherein one path of second pulse signal is output to an external interface, and the other path of second pulse signal is output to the control module to form a loop signal;
the control module is further used for outputting each group of loop signals to the phase discrimination module, and each group of signals to be detected comprises a loop signal of the first signal and a loop signal of one path of second signal;
the phase discrimination module is used for carrying out phase difference measurement on the received loop-back signal;
the control module is also used for generating a time delay value for phase compensation according to the phase difference measurement result and configuring the time delay value to the corresponding time delay module;
the delay module delays the second pulse signal according to the initial delay value, and the phase of the first signal lags behind the phase of the second signal.
6. The apparatus for achieving phase consistency of multiple second pulse signal output according to claim 5, wherein said delay module comprises:
a decoding register for storing the delay value from the control module;
a control register for storing an enable signal from the control module;
and the time delay control module is used for carrying out phase compensation on the second pulse signal according to the time delay value under the action of the enabling signal.
7. The apparatus for achieving phase consistency of multiple second pulse signal output according to claim 5, wherein said phase discrimination module comprises:
the control module configuration register is used for storing configuration information from the control module;
reading a register;
an original data register;
the analog processing unit is used for digitally encoding the two loops of signals from the control module, extracting input waveform information and outputting the waveform information to the first wave unit;
the first wave unit is used for judging whether the waveform information meets the quality requirement or not, and outputting the waveform information to the time-to-digital converter when the waveform information meets the quality requirement;
the time-to-digital converter is used for extracting the phase difference of the received waveform information according to the phase difference measurement stepping setting set in the control module configuration register, and writing the data obtained by the phase difference extraction into the original data register;
the arithmetic logic unit is used for performing phase difference calculation according to the data written into the original data register by the time-to-digital converter and writing the calculated phase difference into the read register;
and the SPI interface is used for realizing communication between the phase discrimination module and the control module.
8. The apparatus for achieving phase consistency of multiple second pulse signals output according to claim 5, wherein the wires of each loop signal are equal in length.
9. The apparatus for achieving phase consistency of a multi-path pulse per second signal output of claim 5, further comprising:
and the clock source is used for outputting a clock signal to the control module.
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