CN117389511A

CN117389511A - Rounding method, rounding system and rounding computer equipment for decimal operation

Info

Publication number: CN117389511A
Application number: CN202311352812.8A
Authority: CN
Inventors: 咸有龙; 周圣骐; 刘刚; 马思杰; 薛源; 刘洋; 张稚
Original assignee: Hexin Technology Co ltd; Shanghai Hexin Digital Technology Co ltd
Current assignee: Hexin Technology Co ltd; Shanghai Hexin Digital Technology Co ltd
Priority date: 2023-10-18
Filing date: 2023-10-18
Publication date: 2024-01-12

Abstract

The invention relates to the technical field of data processing and discloses a rounding method, a rounding system and a rounding computer device for decimal operation, wherein the method comprises the steps of obtaining an operand, an operation type, an operation result and a rounding mode corresponding to decimal operation, wherein the operand comprises a first operand and a second operand, the operation type comprises addition operation and subtraction operation, and the rounding mode is a decimal standard rounding mode; generating a rounding value according to the operation type, the operation result, the operand and a preset rule; and selecting a corresponding rounding threshold according to the rounding mode, comparing the rounding value with the rounding threshold, and determining rounding of the operation result according to a comparison result. The invention can quickly and accurately realize the rounding of the operation result, and reduce the calculation time of the processor, thereby improving the execution efficiency of the processor.

Description

Rounding method, rounding system and rounding computer equipment for decimal operation

Technical Field

The present invention relates to the field of data processing technologies, and in particular, to a rounding method, a rounding system, and a computer device for decimal operation.

Background

The decimal 64 precision (16-digit) and 128 precision (34-digit) formats and specifications of decimal floating point (Decimal Floating Point, DFP) units are described in the IEEE754 standard revisions issued in 2008 (IEEE 754-2008), which provides a theoretical basis for the use of decimal floating points. Decimal floating point numbers generally do not directly represent mantissas by binary numbers, but rather use a coded form such as BCD codes, which represent 1 decimal number by 4-bit binary numbers, so that conversion between binary and decimal numbers can be performed quickly.

In actual decimal addition and subtraction calculation, because of the limited bit width of data, rounding problems of calculation results are encountered in many cases, and different rounding modes are used for rounding the results according to different rounding modes unlike rounding in the conventional thinking. Of course, the rounding logic of "rounding" is also embodied in specific rounding. If the rounded value is exact, then the result should be the same in all rounding modes; conversely, depending on the rounding mode, different results may occur. However, the IEEE standard only gives a standard mode of floating point rounding, and there is no specific implementation manner, i.e. how to implement these rounding modes quickly when a processor operates, and in fact, not only decimal floating point operations, but also decimal fixed point operations have the problems described above, so a method for quickly rounding and determining the number of bits of the calculation result of decimal operations is needed.

Disclosure of Invention

In order to solve the technical problems, the invention provides a rounding method, a rounding system and a rounding computer device for decimal operation, which can solve the problem that the calculation result of decimal addition and subtraction operation cannot be rounded quickly, realize reasonable and effective quick rounding of decimal operation, and further achieve the technical effect of improving the calculation efficiency of a processor.

In a first aspect, the present invention provides a method of rounding a decimal operation, the method comprising:

acquiring an operand, an operation type, an operation result and a rounding mode corresponding to decimal operation, wherein the operand comprises a first operand and a second operand, the operation type comprises addition operation and subtraction operation, and the rounding mode is a decimal number standard rounding mode;

generating a rounding value according to the operation type, the operation result, the operand and a preset rule;

and selecting a corresponding rounding threshold according to the rounding mode, comparing the rounding value with the rounding threshold, and determining rounding of the operation result according to a comparison result.

Further, the step of generating a rounding value according to the operation type, the operation result, the operand and a preset rule includes:

When the operation type is addition operation, judging whether the operation result generates a carry, and if not, generating a rounding value according to the protection number and the sticky number of the second operand;

if the carry is generated, generating a rounding value according to the sum of the units of the first operand and the second operand and the guard number and the sticky number of the second operand;

when the operation type is subtraction operation, judging whether the highest bits of the first operand and the second operand are equal, and if the highest bits are equal, generating a rounding value according to the protection number and the sticky number of the second operand;

and if the highest bits are not equal, generating a rounding value according to the unit number, the guard number and the sticky number of the second operand.

Further, the step of generating the rounding value according to the guard number and the sticky number of the second operand includes:

when the operation type is addition operation and the operation result does not generate carry, the protection number of the second operand is represented by a four-bit binary number, and the blocking number of the second operand is represented by a one-bit binary number, wherein when the blocking number is zero, the one-bit binary number is zero, and when the blocking number is not zero, the one-bit binary number is 1; sequentially combining the four-bit binary number and the one-bit binary number, converting the four-bit binary number and the one-bit binary number into decimal numbers, and taking the decimal numbers as rounding values;

When the operation type is subtraction operation and the highest bits of the first operand and the second operand are equal, the protection number of the second operand is represented by a four-bit binary number, and the sticky number of the second operand is represented by a one-bit binary number, wherein the one-bit binary number is zero; and sequentially combining the four-bit binary number and the one-bit binary number, converting the four-bit binary number and the one-bit binary number into decimal numbers, and taking the decimal numbers as rounding values.

Further, the step of generating a rounding value from the sum of the units of the first operand and the second operand, and the guard number and the sticky number of the second operand includes:

representing the last bit of the sum of the units of the first operand and the second operand by a four-bit binary number, and representing the guard number and the sticky number of the second operand by a one-bit binary number, wherein the one-bit binary number is zero when the guard number and the sticky number are both zero, and the one-bit binary number is 1 when either one of the guard number and the sticky number is not zero;

and sequentially combining the four-bit binary number and the one-bit binary number, converting the four-bit binary number and the one-bit binary number into decimal numbers, and taking the decimal numbers as rounding values.

Further, the step of generating the rounding value according to the unit number, the guard number and the sticky number of the second operand includes:

representing the ones digit of the second operand by a four-bit binary number, and representing the guard number and the sticky number of the second operand by a one-bit binary number, wherein when the guard number and the sticky number are both zero, the one-bit binary number is zero, and when any one of the guard number and the sticky number is not zero, the one-bit binary number is 1;

Further, the step of selecting a corresponding rounding threshold according to the rounding mode, comparing the rounding value with the rounding threshold, and determining the rounding of the operation result according to the comparison result includes:

comparing the rounding value with a first rounding threshold when the rounding mode is a first rounding mode, and determining rounding of the operation result according to the comparison result and the operation type, wherein the first rounding mode comprises a last rounding decoupling value mode, a last rounding far value mode and a last rounding near value mode;

And when the rounding mode is a second rounding mode, comparing the rounding value with a second rounding threshold value, and determining rounding of the operation result according to a comparison result, wherein the second rounding mode comprises a far value taking mode, a near value taking mode and a short precision taking mode.

Further, the step of rounding the operation result and determining the operation result according to the comparison result and the operation type comprises:

when the operation type is addition operation, if the rounding value is smaller than the first rounding threshold value, the operation result is kept unchanged, if the rounding value is larger than the first rounding threshold value, the number of the operation result is increased by 1, and if the rounding value is equal to the first rounding threshold value, rounding of the operation result is determined according to the rounding mode;

when the operation type is subtraction operation, if the rounding value is smaller than the first rounding threshold value, adding 1 to the number of units of the operation result, if the rounding value is larger than the first rounding threshold value, keeping the operation result unchanged, and if the rounding value is equal to the first rounding threshold value, determining rounding of the operation result according to the rounding mode.

Further, the step of rounding the operation result and determining the operation result according to the comparison result includes:

and if the rounding value is equal to the second rounding threshold value, the operation result is kept unchanged, otherwise, rounding of the operation result is determined according to the rounding mode.

In a second aspect, the present invention provides a rounding system for decimal operations, the system comprising:

the data acquisition module is used for acquiring an operand corresponding to decimal operation, an operation type, an operation result and a rounding mode, wherein the operand comprises a first operand and a second operand, the operation type comprises addition operation and subtraction operation, and the rounding mode is a decimal standard rounding mode;

the numerical value generation module is used for generating a rounding value according to the operation type, the operation result, the operand and a preset rule;

and the rounding judging module is used for selecting a corresponding rounding threshold value according to the rounding mode, comparing the rounding value with the rounding threshold value and determining the rounding of the operation result according to the comparison result.

In a third aspect, embodiments of the present invention further provide a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the above method when executing the computer program.

The invention provides a rounding method, a rounding system and a rounding computer device for decimal operation, which can quickly round the calculation result of decimal operation, reduce the part of time for mantissa calculation in the whole arithmetic operation and further improve the execution efficiency of a processor.

Drawings

FIG. 1 is a flow diagram of a rounding method for decimal operation in an embodiment of the present invention;

FIG. 2 is a rounding schematic of a decimal floating point addition operation in an embodiment of the present invention;

FIG. 3 is a rounding schematic of a decimal floating point subtraction operation in an embodiment of the present invention;

fig. 4 is a schematic flow chart of step S20 in fig. 1;

fig. 5 is a schematic flow chart of step S30 in fig. 1;

FIG. 6 is a schematic diagram of a rounding system for decimal operation in accordance with one embodiment of the present invention;

fig. 7 is a schematic diagram of another configuration of a rounding system for decimal operation in an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Since the mantissa of a floating point number generates more bit width than the standard definition during operation, the intermediate calculation result of the mantissa must be rounded. The rounding process is typically to add a rounding carry to the least significant L bits of the mantissa, according to standard defined rules, to the intermediate calculation of the mantissa. For computers, the numbers are represented in binary, so it is necessary to determine on the L bits whether a rounding carry of 1 needs to be added. The conventional processing method is to complete the rounding process by using an integer adder, but this results in an increase of the settlement process, which is reflected in the circuit, namely, the delay of the circuit is increased and the area of the circuit is increased, and in fact, not only the floating point number has the problem, but also the fixed point number has the problem, so in order to solve the problem, the invention provides a method capable of quickly rounding the operation result of decimal operation.

Before describing the technical scheme of the invention, technical keywords related to the technical scheme are described:

POWER: performance Optimization With Enhanced RISC is one of the most common several CPU architectures;

The decimal number standard rounding mode includes RNE, RNA, RNZ, RAZ, RTZ and RPS, and the decimal number includes a decimal floating point number and a decimal fixed point number, wherein:

RNE: the Round to neutral, ties to Even, the last rounding to Even mode, defined as taking the Nearest value, if the two values are equally close, then taking the Even value;

RNA: the Round to neutral, ties away from, the most recently rounded get far value mode, defined as getting the closest value, if the two values are equally close, then get the furthest value from zero;

RNZ: round to neutral, ties topard, most recently rounded to get a near value pattern, defined as getting the Nearest value, if the two values are equally near, then getting the Nearest value to zero;

RAZ: the Round away from0, takes a far value pattern, defined as taking the value furthest from zero;

RTZ: round toward 0, takes a near value pattern, defined as taking the value nearest to zero;

RPS: round to prepare for shorter precision, a shorter precision mode with a closer value, is defined as taking a closer value, and if the selected value is not precise and the number of units is 0 or 5, then 1 is added for output.

In order to quickly implement the above decimal standard rounding mode, referring to fig. 1, a rounding method for decimal operation according to a first embodiment of the present invention includes steps S10 to S30:

Step S10, an operand corresponding to decimal operation, an operation type, an operation result and a rounding mode are obtained, wherein the operand comprises a first operand and a second operand, the operation type comprises addition operation and subtraction operation, and the rounding mode is a decimal standard rounding mode.

And step S20, generating a rounding value according to the operation type, the operation result, the operand and a preset rule.

The decimal floating point number comprises sign bits, exponent bits and mantissa bits, and the operands need to be shifted because the exponents of different operands may be different, and the operand A is set to be shifted left, and the operand B is set to be shifted right when the shift of the operand A is insufficient to offset the difference value of the exponents. The addition and subtraction calculation flow of decimal numbers and the specific representation method of decimal floating point numbers can be according to a conventional calculation method, and will not be described herein. It should be noted that, because the decimal floating point number and the decimal fixed point number have no difference in rounding implementation, the fixed point number and the floating point number have only sign numbers and mantissas, and no shift is needed in the calculation process, the embodiment provided by the invention uses a more complex decimal floating point number as an example to illustrate, and the rounding implementation of the fixed point number is consistent with that of the floating point number, and will not be described in detail later.

The rounding mode in the present invention is based on the POWER architecture, and the operands used in the calculation include an operand a and an operand B, where L (Least significant digit, least significant) of the operand is a first number of units, G (Guard digit) is a second number of units, S (Sticky digit) is a first number of units, and since the operand a is always shifted left and the operand B is shifted right, the Guard number of the operand a is 0 (binary 0000).

In the actual calculation process, the calculation result of decimal floating point addition is divided into two cases, please refer to fig. 2, one is that the highest order in the calculation result does not generate a carry, such as 222+111=333, and the resultThe width of the original data is still maintained, and the other is that the highest bit in the calculated result generates a carry, such as 222+911=1133, and the data bit width of the result is increased by one digit, namely four bits, and the result can be expressed as 113×10 ¹ 。

Similarly, in the case where the decimal floating point subtraction is based on the operand a being greater than or equal to the operand B, that is, the subtraction is always enough, the calculation result is a number greater than or equal to 0, and this is also divided into two cases, referring to fig. 3, one is that the first number of the operand a and the operand B is the same, that is, the highest order is equal, and the first number of the calculation result is 0 (binary 0000). The other is that the first digit of operand A is larger than the first digit of operand B, i.e. the most significant digits are not equal, where the first digit of the result is a number greater than 0.

According to different operation types and different conditions of the operation types, different rounding value generation rules are designed, so that whether an operation result is rounded or not is judged through the rounding value. The invention provides rounding value generation rules under different conditions, and specific steps are shown in fig. 4:

step S201, when the operation type is addition operation, determining whether the operation result generates a carry, and if no carry is generated, generating a rounding value according to the protection number and the sticky number of the second operand.

In this embodiment, for the case that the operation result of the addition operation does not generate a carry, the protection number and the Sticky number of the second operand, that is, the operand B, are used to generate the corresponding rounding value, and since the operation result does not generate a carry and the Guard number of the operand a is 0, the rounding of the operation result is determined according to the Guard number and the stick number of the operand B in this case, and the rounding mode is selected, wherein the specific steps of generating the rounding value according to the Guard number and the stick number of the operand B are as follows:

step S2011, representing the protection number of the second operand with a four-bit binary number, and representing the blocking number of the second operand with a one-bit binary number, wherein when the blocking number is zero, the one-bit binary number is zero, and when the blocking number is not zero, the one-bit binary number is 1;

Step S2012 sequentially combines the four-bit binary number and the one-bit binary number, converts the four-bit binary number and the one-bit binary number into a decimal number, and uses the decimal number as a rounding value.

In the invention, the rounding value is expressed by five-bit binary number, namely, a 5-bit number, the first 4 bits depend on the Guard number of the operand B under the condition that addition is not carried, the 5 th bit depends on the stick number of the operand B, the Guard number needs to know the value of the Guard number and then converts the value of the Guard number into 4-bit binary number, and the specific value of the stick number does not need to be known, and only needs to know whether the value of the Guard number is 0 or not: when the Sticky number is 0, the last bit of the 5bit number is 0; when the number of sticks is not 0, the last bit of the 5-bit number is 1, so that the two kinds of sticks can be distinguished. And sequentially combining the generated 4bit number and 1bit number to obtain a five-bit binary rounding value, and converting the five-bit binary rounding value into a decimal number to obtain a rounding value corresponding to the condition that addition is not carried. That is, the rounding judgment of the operation result is performed by the rounding value corresponding to the Guard number and the stick number of the operand, and the rounding value under the condition of no carry of addition can be simply and quickly obtained by the rounding value generation rule under the condition of not increasing the computational complexity, so that the subsequent judgment of rounding the operation result is facilitated.

Step S202, if a carry is generated, generating a rounding value according to the sum of the units of the first operand and the second operand, and the guard number and the sticky number of the second operand.

When the addition operation generates a carry, the generation rule in this case is different from the generation rule of the above-described case where no carry is generated, because the case of the operand is different, and specific generation rules include:

step S2021, representing the last bit of the sum of the units of the first operand and the second operand by a four-bit binary number, and representing the guard number and the sticky number of the second operand by a one-bit binary number, wherein when both the guard number and the sticky number are zero, the one-bit binary number is zero, and when either one of the guard number and the sticky number is not zero, the one-bit binary number is 1;

step S2022 sequentially combines the four-bit binary number and the one-bit binary number, converts the four-bit binary number into a decimal number, and takes the decimal number as a rounding value.

In this embodiment, since the calculation result generates a carry, whether the number of units of the calculation result is added with 1 carry needs to be determined according to the sum of the number of units of the operand a and the operand B, the Guard number and the stick number of the operand B, and the rounding mode of addition, and similar to the above steps, since the rounding value is a 5-bit number, the sum of the number of units of the operand a and the operand B can be used as the first 4-bit number, and the last bit is determined by the Guard number and the stick number of the operand B.

Further, in the actual execution process, the sum of the units of the operand A, B is a number between 0 and 19, when the number is between 0 and 9, the number is directly converted into 4bit binary, when the number is more than or equal to 10, a carry is generated actually, and whether rounding is performed is determined according to the last bit of the sum, namely, the last bit of the sum is converted into the 4bit number; for the Guard number and the stick number, since the Guard number and the stick number correspond to 1bit number, we do not need to know the specific value of the Guard number and the stick number, and only need to know whether the Guard number and the stick number are all 0, namely when the Guard number and the stick number are all 0, the last bit of the 5bit number is 0; when either the Guard number or the stick number is not 0, the last bit of the 5-bit number is 1.

Then, the 4bit number and the 1bit number are sequentially combined to obtain a 5bit binary number, and the 5bit binary number is converted into a decimal number, so that a rounding value corresponding to the situation of generating carry by addition can be obtained. That is, the rounding value under the condition of generating carry by addition can be obtained quickly according to the sum of the units of the operand A and the operand B, the Guard number and the stick number of the operand B, and the rounding value generation rule provided by the embodiment is not only efficient and convenient, but also can provide accurate information for subsequent rounding judgment.

Step S203, when the operation type is subtraction operation, judging whether the highest bit of the first operand and the highest bit of the second operand are equal, and if the highest bit is equal, generating a rounding value according to the protection number and the sticky number of the second operand;

in the two cases of subtraction operation, the first case is that the highest bits of two operands are equal, the defined ones are the ten bits of the original operands a and B, the rounding value generation rule corresponding to this case is to generate the rounding value by the Guard number and the stick number of the operand B, that is, the rounding value generation rule of this condition is practically consistent with the rounding value generation rule under the condition of no carry addition, that is, the first 4 bits depend on the Guard number of the operand B, the 5 th bit depends on the stick number of the operand B, for the Guard number we need to know the value thereof, then convert the value thereof into a 4bit binary number, for the stick number we need not know the specific value thereof, and it is only necessary to know whether or not it is 0, specifically, when the stick number is 0, the last bit of the 5bit number is 0; when the number of Sticky is not 0, the last bit of the 5bit number is 1, so that the two kinds of Sticky can be distinguished. Further, in order to unify the rounding flow, in the subtraction operation, since only the last two bits are reserved, and in fact, the L bits and the G bits are reserved, we can set the stick number of the operand B to 0 (binary is 0000), at this time, the last 1bit is only zero, that is, the one-bit binary is zero, so long as the first 4bit value is determined according to the stick number of the operand B, thereby further reducing the operation steps while maintaining the accuracy of the data.

Finally, the generated 4bit number and 1bit number are sequentially combined to obtain a 5bit binary number, and the 5bit binary number is converted into a decimal number, so that a rounding value corresponding to the highest subtraction bit is obtained. The embodiment provides a convenient and efficient rounding value generation rule, which can provide accurate information for subsequent rounding judgment.

In step S204, if the most significant bits are not equal, a rounding value is generated according to the unit number, the guard number, and the sticky number of the second operand.

In the second case of subtraction, that is, in the case where the most significant bits of the two operands are not equal, the generation rule of the rounding value is different from the generation rule because the operands are different, and the specific steps are as follows:

step S2041, representing the single digit of the second operand by a four-bit binary number, and representing the guard number and the sticky number of the second operand by a one-bit binary number, wherein when the guard number and the sticky number are both zero, the one-bit binary number is zero, and when any one of the guard number and the sticky number is not zero, the one-bit binary number is 1;

step S2042 sequentially combines the four-bit binary number and the one-bit binary number, converts the four-bit binary number and the one-bit binary number into a decimal number, and takes the decimal number as a rounding value.

In this embodiment, the units defined in this case are also the tenth bits of the original operands a and B, and in the case that the subtraction most significant bits are not equal, the corresponding rounding value generation rule is to generate the rounding value according to the units of the reduction, the Guard number and the Sticky number, where the first 4 bits of the rounding value correspond to the units of the operand B, i.e. are converted into 4bit binary numbers according to the values thereof, the last 1bit number is the Guard number and the stick number depending on the operand B, the last 1bit number is generated in the same manner as the step of generating the carry by the addition, and when the Guard number and the stick number are both 0, the last 1bit is 0, otherwise 1. Further, since the stick number of the operand B is uniformly set to 0 (binary expressed as 0000), the value of the last 1bit number can be determined practically only from the Guard number of the operand B.

Finally, the 4bit number and the 1bit number are sequentially combined to obtain a 5bit binary number, and after the 5bit binary number is converted into a decimal number, the corresponding rounding value under the condition that the highest bit of subtraction is unequal can be obtained. The rounding value generation rule provided by the embodiment can conveniently and efficiently obtain the rounding value under the condition that the highest bits of the subtraction are unequal, provides accurate information for subsequent rounding judgment, and further improves the execution efficiency of the processor.

And step S30, selecting a corresponding rounding threshold value according to the rounding mode, comparing the rounding value with the rounding threshold value, and determining rounding of the operation result according to a comparison result.

After the rounding values under the four conditions are obtained through the above steps, the determination of whether to perform rounding can be performed in conjunction with the pre-selected rounding mode. From the above description, IEEE provides six decimal standard rounding modes, where RNE, RNA and RNZ are the most recent rounding modes and only the values are selected differently, and the values of the rag, RTZ and PRS are all selected according to different rules, so that according to the definition of the modes, they can be divided into two main classes, one class includes RNE, RNA and RNZ, and the other class includes rag, RTZ and PRS, where the definition of the modes is different and the decision thresholds and decision conditions corresponding to the different classes are also different, and the specific steps are shown in fig. 5:

step S301 compares the rounding value with a first rounding threshold and determines the rounding of the operation result according to the comparison result and the operation type when the rounding mode is a first rounding mode including a last rounding decoupling value mode, a last rounding more distant value mode and a last rounding more recent value mode.

For the RNE, RNA or RNZ mode, the mode definition is the latest rounding, which can be regarded as a rounding-like operation, namely, determining which direction to approach according to whether the mode is close to 0 or close to 1, so as to determine whether to round, at this time, we can take the rounding value as a judgment value, and perform the latest rounding according to the rounding value, so as to determine whether to add 1 to the single digit of the operation result, and since the rounding value is the actual value of a decimal number, the mode definition is between 0 and 19, 10 can be selected as a first threshold value to be compared with the rounding value, so that the rounding judgment can be performed according to the comparison result. Further, due to the difference of the operation steps of the addition operation and the subtraction operation, the judgment conditions will also be different, specifically:

step S3011, when the operation type is addition operation, if the rounding value is smaller than the first rounding threshold, the operation result is kept unchanged, if the rounding value is larger than the first rounding threshold, the number of units of the operation result is increased by 1, and if the rounding value is equal to the first rounding threshold, rounding of the operation result is determined according to the rounding mode;

Step S3012, when the operation type is subtraction operation, adding 1 to the number of units of the operation result if the rounding value is smaller than the first rounding threshold, keeping the operation result unchanged if the rounding value is larger than the first rounding threshold, and determining rounding of the operation result according to the rounding mode if the rounding value is equal to the first rounding threshold.

In addition, the number of units of the result is increased by 1 carry above the threshold and the result remains unchanged below the threshold, this determination being better understood, i.e. similar to the rounding determination, taking the rounded value in the case where addition does not produce carry as an example, as shown in table 1 below:

table 1 rounded value table in case of addition without carry generation

According to the above determination procedure, the table 1 is divided into two parts, namely, an upper part and a lower part, by taking the decimal number 10 as a boundary, wherein when the rounding value is smaller than 10, the operation result is kept unchanged, when the rounding value is larger than 10, 1 is added to the unit number of the operation result, and when the rounding value is equal to 10, the case can be considered as a tie, namely, when the two values are similar in the definition of the rounding mode, and in the case, the rounding mode is combined to determine whether carry operation is performed.

For example, if the preselected rounding mode is RNZ, it is known that "take closest value according to its definition, if two values are equally close, take closest value to zero", then take closest value to zero for tie case, then the single digit need not add 1; if the RNA mode is selected, that is, "take closest value, if two values are similar, take furthest value from zero", because take furthest value from zero, then the number of units of the operation result needs to be added with 1 carry.

That is, in the RNZ mode, if the number of guard is not less than 6 but not more than 0, and the number of guard is not less than 5, the arithmetic result is added with 1 carry; in the RNA mode, when the number of guard is not less than 5 but not more than 0, the number of guard is not less than 5, and the number of guard is not less than 5, then 1 is added to the operation result to generate a carry, that is, the rounding determination result is different in the tie case according to the rounding mode.

For the RNE mode, the mode is "take closest value, if two values are similar, take even value", when Guard number is 5 and the stick number is 0, it is in the tie state at this time, according to its mode definition, specific rounding behavior needs to be determined according to parity condition of the digits of the operation result, namely:

The unit number is an even number: 0000. 0010, 0100, 0110, 1000; after the carry is obtained are 0001, 0011, 0101, 0111, 1001.

The unit number is an odd number: 0001. 0011, 0101, 0111, 1001; after the carry is obtained are 0010, 0100, 0110, 1000, 0000.

The last 1bit and 0 after the carry is obtained are logically ANDed, so that the single digit of the calculated result can be ensured to be even. Namely, for the tie situation of the RNE mode, the number of units is even, and the original value of the operation result is kept unchanged; the number of units is odd, and the number of units of the operation result is increased by 1, wherein the number of units refers to the number of units of the operation result generated by adding the operands A and B.

Similarly, for the case where the addition produces a carry, the rounded values of Table 2 below are taken as examples:

table 2 round value table in case of addition to generate carry

In the case of addition to carry, although the generation rule of the rounded value is different from that of addition to carry, the judgment manner of rounding is consistent, that is, rounding of the operation result is determined according to the rounding mode and the first threshold value: for RNZ mode, when the number of the guard is greater than or equal to 6 or not greater than 0 and the number of the guard is greater than or equal to 5, adding 1 carry to the unit number of the operation result; for the RNA mode, adding 1 to the unit number of the operation result when the number of the guard is greater than or equal to 5 and the number of the guard is not greater than 0; for RNE mode, carry is generated when the number of the Guard is 0, the number of the Guard is more than or equal to 6 or the number of the Guard is not 0, and the number of the Guard is more than or equal to 5, and when the number of the Guard is 5 and the number of the Guard is 0, the number of units is even, so that the original value of the operation result is kept unchanged; the number of units is odd, and the number of units of the operation result is increased by 1.

For subtraction, since subtraction and addition are actually opposite operations, since addition is to determine the arithmetic result by one digit plus 1 based on a larger number, then for subtraction, the rounding value can be actually considered as a subtracted number, in subtraction, the larger number will not add 1 carry to the arithmetic result, and subtracting a smaller number may generate carry of the arithmetic result, based on this theory, carry judgment in subtraction is actually opposite to addition, specifically, taking the rounding value under subtraction in tables 3 and 4 as an example, described below:

guard number	The 5bit number Sticky number is equal to 0	Decimal number representation
			0	00000	0
1	00010	2
			2	00100	4
3	00110	6
			4	01000	8
5	01010	10
			6	01100	12
7	01110	14
			8	10000	16
9	10010	18

Table 3 rounding value table in case of subtracting the highest bit and the like

Table 4 rounding table in case of subtracting the highest bit inequality

Also, the decimal number 10 is used as a boundary, and although the generation rule of the rounding value is different for the case where the highest order is equal and the highest order is not equal under the subtraction operation, the method of judging according to the rounding mode and the rounding value is the same, namely, when the rounding value is smaller than 10, 1 carry is added to the unit number of the operation result, and when the rounding value is larger than 10, the operation result is kept unchanged. For the case of the tie, whether to add 1 to the single digit of the operation result is still determined according to the definition of the rounding mode, that is, the tie judgment step of the addition operation may be referred to for the case of the tie, and the description is not repeated here. For example, in the subtraction operation, when the selected rounding mode is the RNZ mode, 1 carry is added to the unit number of the operation result when the number of the Sticky is 0 and the number of the Guard is 4 or less in the case where the highest order is equal, and 1 carry is added to the unit number of the operation result when the number of the Guard is 0 and the number of the unit is 4 or less or the number of the Guard is not 0 and the number of the unit is 4 or less in the case where the highest order is not equal; when the rounding mode is the RNA mode, in the case of the highest bit being equal, when the stick number is 0 and the Guard number is less than or equal to 5, 1 carry is added to the unit number of the operation result, in the case of the highest bit being unequal, when the Guard number is 0 and the unit number is less than or equal to 4, or when the Guard number is not 0 and the unit number is not equal to 4, 1 carry is added to the unit number of the operation result, and other cases can be determined according to the above-mentioned determination steps, which will not be repeated here. Through the steps, the invention carries out different classification and combination on the operation type and the rounding mode, can quickly judge the rounding of the operation result under various combination conditions, has high accuracy of the judgment result, reduces the calculation time of the processor, and improves the execution efficiency of the processor.

Step S302, comparing the rounding value with a second rounding threshold when the rounding mode is a second rounding mode, and determining rounding of the operation result according to the comparison result, wherein the second rounding mode comprises a far value taking mode, a near value taking mode and a short precision taking mode.

Further, when the preselected rounding mode is RAZ, RTZ or PRS, these modes are different in terms of whether or not to generate carry based on the degree of accuracy of the operation result, and the condition for judging whether or not the operation result is accurate is also different for different operation types, specifically, for the case that the addition top bit is not carried, the result is accurate when the Guard number and the stick number of the operand B are both 0; in the case that the most significant bit of the addition has a carry, the result is accurate when the sum of the units of the operand A, B and the Guard number and the stick number of the operand B are both 0; for the case of the highest subtraction bit being equal, the result is accurate when the Guard number of the operand B is 0; for the case where the subtraction most significant bits are not equal, then both the bits of operand B and Guard numbers are 0 are required to determine that the result is accurate. It will be apparent that these exact conditions of the result may correspond substantially to a rounded value, so that when the rounded value is 0, it is sufficient to indicate that the result is accurate, and that the result is kept unchanged, whereas in the non-zero case, it is biased, and that it is necessary to determine whether the result is rounded according to the bias, that is, the present invention uses the rounded value to characterize the result as accurate, and uses the comparison of the rounded value with the threshold value to characterize the accuracy of the result, and at this time the second threshold value may be set to zero, and when the rounded value is zero, the result is accurate, and when the rounded value is non-zero, it is necessary to determine the rounding according to the definition of the rounding mode.

Based on this theory, it is known that, for the addition operation or the subtraction operation, the judgment in the above modes is not different, and is substantially determined according to the operation result, taking the rounding value of table 1 as an example, if the selected rounding mode is the RAZ mode, that is, "taking the value farthest from zero", the operation result will remain unchanged only when the rounding value is equal to the threshold value zero, and otherwise the number of units of the operation result will be increased by 1; if the selected rounding mode is RTZ mode, namely 'take the value nearest to zero', the operation result will remain unchanged when the rounding value is equal to the threshold value zero, and when the rounding value is greater than zero, the operation result will remain unchanged when the rounding value is greater than the threshold value according to the definition; if the selected rounding mode is the RPS mode, namely ' getting a closer value ', if the selected value is inaccurate, and the number of units is 0 or 5, adding 1 for output ', and when the rounding value is not zero, indicating that the operation result is inaccurate, judging whether the number of units of the operation result is 0 or 5, if yes, adding 1 for output, otherwise, directly outputting without carry, thereby meeting the definition of the RPS mode.

The rounding method for decimal operation provided by the embodiment is different from the rounding method implementation in the prior art which focuses on binary operation, and the method is used for quickly acquiring the corresponding rounding value according to the corresponding rounding value generation rule under different conditions aiming at decimal addition and subtraction operation, so that the decimal standard rounding mode can be quickly realized according to the rounding value, namely, the execution step of the standard rounding mode is provided. Furthermore, the invention not only can be applied to processors under the POWER architecture, but also can realize the quick rounding judgment of the operation result according to the rounding mode provided by the invention for each type of processor architecture, so that the invention has extremely high adaptability; in addition, the method provided by the invention can be applied to decimal floating point operation, and can be used for rounding operation results in a decimal fixed point addition and subtraction mode, and for actual rounding realization, even if different data bit widths are used, the rounding method provided by the invention can be used for rounding operation results, so that the technical scheme of the invention has extremely high expandability.

Referring to fig. 6, based on the same inventive concept, a rounding system for decimal operation according to a second embodiment of the present invention includes:

the data obtaining module 10 is configured to obtain an operand corresponding to a decimal operation, an operation type, an operation result and a rounding mode, where the operand includes a first operand and a second operand, the operation type includes an addition operation and a subtraction operation, and the rounding mode is a decimal standard rounding mode;

the value generating module 20 is configured to generate a rounding value according to the operation type, the operation result, the operand and a preset rule;

and the rounding judging module 30 is used for selecting a corresponding rounding threshold value according to the rounding mode, comparing the rounding value with the rounding threshold value and determining rounding of the operation result according to a comparison result.

The rounding system provided by the invention can quickly realize the rounding of the calculation result, and reduces the part of time for mantissa calculation in the whole arithmetic operation, thereby improving the execution efficiency of a processor.

Referring to fig. 7, in a preferred embodiment, the value generation module 20 further includes:

a first generating module 201, configured to determine whether the operation result generates a carry when the operation type is addition operation, and generate a rounding value according to the protection number and the sticky number of the second operand if no carry is generated;

a second generating module 202, configured to determine whether the highest bits of the first operand and the second operand are equal when the operation type is subtraction operation, and if the highest bits are equal, generate a rounding value according to the protection number and the sticky number of the second operand;

In the embodiment, the decimal addition and the decimal subtraction are respectively classified in calculation type, different rounding schemes are provided, rounding judgment can be quickly realized in each classification by providing the rounding value generation rule of the operation of different classifications, and the accuracy of the judgment result is improved.

Further, in another preferred embodiment, the first generating module 201 is further configured to represent the guard number of the second operand with a four-bit binary number and the sticky number of the second operand with a one-bit binary number, where the one-bit binary number is zero when the sticky number is zero and the one-bit binary number is 1 when the sticky number is not zero; and sequentially combining the four-bit binary number and the one-bit binary number, converting the four-bit binary number and the one-bit binary number into decimal numbers, and taking the decimal numbers as rounding values.

Further, in another preferred embodiment, the first generating module 201 is further configured to represent the last bit of the sum of the units of the first operand and the second operand with a four-bit binary number, and represent the guard number and the sticky number of the second operand with a one-bit binary number, where the one-bit binary number is zero when both the guard number and the sticky number are zero, and the one-bit binary number is 1 when either one of the guard number and the sticky number is not zero; and sequentially combining the four-bit binary number and the one-bit binary number, converting the four-bit binary number and the one-bit binary number into decimal numbers, and taking the decimal numbers as rounding values.

Further, in another preferred embodiment, the second generating module 202 is further configured to, when the operation type is an addition operation and the operation result does not generate a carry, represent the number of units of the second operand with a four-bit binary number, and represent the guard number and the sticky number of the second operand with a one-bit binary number, where the one-bit binary number is zero when both the guard number and the sticky number are zero, and the one-bit binary number is 1 when either the guard number and the sticky number are not zero; sequentially combining the four-bit binary number and the one-bit binary number, converting the four-bit binary number and the one-bit binary number into decimal numbers, and taking the decimal numbers as rounding values; when the operation type is subtraction operation and the highest bits of the first operand and the second operand are equal, the protection number of the second operand is represented by a four-bit binary number, and the sticky number of the second operand is represented by a one-bit binary number, wherein the one-bit binary number is zero; and sequentially combining the four-bit binary number and the one-bit binary number, converting the four-bit binary number and the one-bit binary number into decimal numbers, and taking the decimal numbers as rounding values.

In the above embodiment, specific generation rules of the rounding values in the case of each operation classification are respectively given, so that corresponding rounding values can be quickly generated without increasing the computational complexity, and accurate data support is provided for rounding determination of subsequent operation results.

Further, in another preferred embodiment, the rounding determination module 30 further includes:

a first judging module 301, configured to compare the rounding value with a first rounding threshold when the rounding mode is a first rounding mode, and determine rounding of the operation result according to the comparison result and the operation type, where the first rounding mode includes a last rounding decoupling value mode, a last rounding remote value mode, and a last rounding near value mode;

the second determining module 302 is configured to compare the rounding value with a second rounding threshold when the rounding mode is a second rounding mode, and determine rounding of the operation result according to the comparison result, where the second rounding mode includes a far value mode, a near value mode, and a near value shorter precision mode.

In this embodiment, different standard rounding modes are classified, and different comparison thresholds are provided according to different classification modes, so that definition of rounding modes under different standards can be reasonably and efficiently implemented.

Further, in another preferred embodiment, the first determining module 301 is further configured to, when the operation type is an addition operation, if the rounding value is smaller than the first rounding threshold, keep the operation result unchanged, if the rounding value is greater than the first rounding threshold, add 1 to the unit number of the operation result, and if the rounding value is equal to the first rounding threshold, determine rounding of the operation result according to the rounding mode;

Further, in another preferred embodiment, the second determining module 302 is further configured to, if the rounding value is equal to the second rounding threshold, keep the operation result unchanged, and otherwise determine rounding of the operation result according to the rounding mode.

In the above embodiment, the threshold comparing step under various combination conditions is provided, and the rounding condition of the operation result can be rapidly judged for the combination of different rounding modes and different operation types through the comparison result of the rounding value and the threshold, and the implementation mode of each standard rounding mode can be rapidly realized through the above embodiment, so that the time for calculating the mantissa in the whole arithmetic operation is reduced, and the execution efficiency of the processor is improved.

Technical features and technical effects of the rounding system for decimal operation according to the embodiment of the present invention are the same as those of the method according to the embodiment of the present invention, and are not described herein. Each of the modules in the rounding system for decimal operations described above may be implemented in whole or in part in software, hardware, and combinations thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.

In addition, the embodiment of the invention also provides computer equipment, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor realizes the steps of the method when executing the computer program.

In summary, according to the rounding method, system and computer equipment for decimal operation provided by the embodiment of the invention, the method is implemented by acquiring an operand, an operation type, an operation result and a rounding mode corresponding to the decimal operation, wherein the operand comprises a first operand and a second operand, the operation type comprises addition operation and subtraction operation, and the rounding mode is a decimal standard rounding mode; generating a rounding value according to the operation type, the operation result, the operand and a preset rule; and selecting a corresponding rounding threshold according to the rounding mode, comparing the rounding value with the rounding threshold, and determining rounding of the operation result according to a comparison result. The invention can quickly and accurately realize the rounding of the operation result, and reduce the calculation time of the processor, thereby improving the execution efficiency of the processor.

In this specification, each embodiment is described in a progressive manner, and all the embodiments are directly the same or similar parts referring to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments. It should be noted that, any combination of the technical features of the foregoing embodiments may be used, and for brevity, all of the possible combinations of the technical features of the foregoing embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The foregoing examples represent only a few preferred embodiments of the present application, which are described in more detail and are not thereby to be construed as limiting the scope of the invention. It should be noted that modifications and substitutions can be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and substitutions should also be considered to be within the scope of the present application. Therefore, the protection scope of the patent application is subject to the protection scope of the claims.

Claims

1. A method of rounding a decimal operation, comprising:

2. The method of rounding a decimal operation of claim 1 wherein the step of generating a rounding value based on the operation type, the operation result, the operand, and a preset rule comprises:

3. The method of rounding a decimal operation of claim 2 wherein the step of generating a rounding value based on the guard number and the sticky number of the second operand includes:

4. The method of rounding a decimal operation of claim 2 wherein the step of generating a rounding value based on the sum of the number of units of the first operand and the second operand, and the guard number and the sticky number of the second operand comprises:

5. The rounding method of claim 2, wherein said step of generating a rounding value based on the ones, protections and sticky numbers of said second operand comprises:

6. The method of rounding a decimal operation of claim 1 wherein the steps of selecting a corresponding rounding threshold value based on the rounding mode, comparing the rounding value to the rounding threshold value, and determining the rounding of the operation result based on the comparison result comprise:

7. The method of rounding a decimal operation of claim 6 wherein the step of determining the rounding of the operation result based on the comparison result and the operation type includes:

8. The method of rounding a decimal operation of claim 6 wherein the step of determining the rounding of the operation result based on the comparison result includes:

9. A rounding system for decimal operations, said system employing the rounding method of any one of claims 1 to 8, comprising:

10. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any one of claims 1 to 8 when the computer program is executed by the processor.