CN117368676A

CN117368676A - Test circuit, test system, test method, and semiconductor device

Info

Publication number: CN117368676A
Application number: CN202210760104.7A
Authority: CN
Inventors: 侯闯明
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-06-30
Filing date: 2022-06-30
Publication date: 2024-01-09
Also published as: WO2024000644A1

Abstract

The embodiment of the application provides a test circuit, a test system, a test method and a semiconductor device, wherein the test circuit comprises a ring oscillation circuit and a mirror image circuit; the ring oscillation circuit comprises a plurality of first reversing units which are sequentially cascaded, each first reversing unit comprises a first input end and a first output end, and the first input end and the first output end of at least one first reversing unit are connected with the mirror image circuit; the mirror circuit is used for receiving a first voltage signal corresponding to the first input end of the first reversing unit and a second voltage signal corresponding to the first output end, and mirroring the overturning current of the transistor in the first reversing unit according to the first voltage signal and the second voltage signal when the first input end of the first reversing unit is subjected to level overturning. The current of the transistor in the first reversing unit can be mirrored through the mirror circuit. In this way, the current between different transistors in one first inversion unit can be removed, which is helpful to improve the accuracy of the test flip current.

Description

Test circuit, test system, test method, and semiconductor device

Technical Field

The embodiment of the application relates to the technical field of semiconductors, in particular to a test circuit, a test system, a test method and a semiconductor device.

Background

MOS (metal-oxide-semiconductor field-effect transistor, metal-oxide-semiconductor field effect transistor) is widely used in the field of semiconductor technology, for example, PMOS and NMOS connected in series may form an inverter, which is a CMOS with inversion function. The effective drive currents of PMOS and NMOS in CMOS can assist in analyzing CMOS, for example, parasitic capacitance of CMOS can be analyzed according to the effective drive currents to determine the influence of ion doping on parasitic capacitance and resistance of CMOS, thereby obtaining a higher speed circuit.

In the existing CMOS technology, to obtain the best noise margin, the device widths of PMOS and NMOS are typically adjusted so that the switching voltage of the logic gate formed by the transistors is half the operating voltage. When the effective driving current of the PMOS is measured, the grid electrode, the source electrode and the drain electrode of the PMOS are independently led out to apply half of working voltage to the source electrode and the grid electrode, and at the moment, the channel current measured at the drain electrode can be used as the effective driving current of the PMOS. Similarly, the effective drive current of the NMOS can be measured. It can be seen that the effective drive current can also be understood as a switching current.

However, the transconductance of the different transistors is different, so that the midpoint of the transfer curve of the logic gate is not at half the operating voltage. And during the time of logic level inversion, the transistor sequentially goes through the oversaturation region and the linear region, so that a single dc test at a certain fixed bias voltage cannot reflect its equivalent inversion current. And the level inversion time is short, and the inversion layer carriers in the channel have certain generation time and annihilation time. These causes all lead to inaccurate obtaining of real overturning current through simple direct current test when level overturning occurs, so that the accuracy of the tested overturning current is lower.

Disclosure of Invention

The embodiment of the application provides a test circuit, a test system, a test method and a semiconductor device, which can improve the test accuracy of the overturning current.

In a first aspect, embodiments of the present application provide a test circuit, including a ring oscillator circuit and a mirror circuit;

the ring oscillation circuit comprises a plurality of first reversing units which are sequentially cascaded, each first reversing unit comprises a first input end and a first output end, and the first input end and the first output end of at least one first reversing unit are connected with the mirror image circuit;

The mirror circuit is configured to receive a first voltage signal corresponding to the first input end of the first inverting unit and a second voltage signal corresponding to the first output end, and mirror an inversion current of a transistor in the first inverting unit according to the first voltage signal and the second voltage signal when the first input end of the first inverting unit is level-inverted.

Optionally, the mirror circuit includes a mirror control circuit and at least one mirror test circuit;

the mirror image control circuit comprises at least one control signal output end, wherein the control signal output end is connected with the mirror image test circuit in a one-to-one correspondence manner, the mirror image control circuit is used for sending a mirror image control signal to the mirror image test circuit through the control signal output end, and the mirror image control signal is used for indicating the overturning state of the first reversing unit;

each mirror image test circuit is also connected with a first input end and a first output end of one first reversing unit, and is used for determining whether the first input end of the first reversing unit is subjected to level inversion according to the mirror image control signal, and mirroring the overturn current of a transistor in the first reversing unit according to the first voltage signal and the second voltage signal when the level inversion occurs.

Optionally, the mirror control circuit includes a plurality of second reversing units that are cascaded in turn, the number of the second reversing units is the same as the number of the first reversing units, and the mirror control circuit and the ring oscillation circuit work under the same power supply voltage;

each second reversing unit comprises a second input end, at least one second input end is used as the control signal output end to be connected with the mirror image test circuit, and the second reversing units are used for sending the voltage signals of the second input ends of the second reversing units to the mirror image test circuit as the mirror image control signals.

Optionally, the mirror image test circuit includes a mirror image transistor and a test control circuit, where the test control circuit is connected to the control signal output end, the first input end, the first output end, and the mirror image transistor, and the test control circuit is configured to determine, according to the mirror image control signal sent by the mirror image control circuit, whether level inversion occurs at the first input end, and when level inversion occurs, control an operating voltage of the mirror image transistor according to the received first voltage signal and the received second voltage signal, so that a current of the mirror image transistor is the same as a current of the transistor in the first reverse unit.

Optionally, the test control circuit includes a selection signal generating circuit and a voltage control circuit;

the selection signal generation circuit is connected with the mirror image control circuit and the voltage control circuit, and is used for outputting a selection signal according to the mirror image control signal sent by the mirror image control circuit, and the selection signal is used for indicating whether the level of the first input end is about to be subjected to level inversion or not;

the voltage control circuit is respectively connected with the selection signal generation circuit, the first input end, the first output end and the mirror transistor, and is used for controlling the grid voltage signal of the mirror transistor to be consistent with the first voltage signal and controlling the drain voltage signal of the mirror transistor to be consistent with the second voltage signal when the selection signal indicates that the first input end is subjected to level inversion.

Optionally, the voltage control circuit includes a first selection circuit, a second selection circuit, and a first delay circuit;

the control input end of the first selection circuit is connected with the selection signal generation circuit and is used for receiving the selection signal; the control input end of the second selection circuit is connected with the output end of the first delay circuit, the input end of the first delay circuit is connected with the output end of the selection signal generation circuit, and the control input end of the second selection circuit is used for receiving the delayed selection signal;

One of the data input ends of the first selection circuit is connected with the first input end, and the output end of the first selection circuit is connected with the grid electrode of the mirror image transistor and is used for taking the first voltage signal as the grid electrode voltage signal of the mirror image transistor when the selection signal indicates that the level of the first input end is in level inversion;

one of the data input ends of the second selection circuit is connected with the first output end, and the output end of the second selection circuit is connected with the drain electrode of the mirror image transistor and is used for taking the second voltage signal as the drain voltage signal of the mirror image transistor when the selection signal indicates that the level of the first input end is in level inversion.

Optionally, when the mirror transistor is a PMOS transistor, the other data input terminal of the first selection circuit is connected to a power supply voltage signal, and when the selection signal indicates that the level of the first input terminal does not flip, the first selection circuit is further configured to use the power supply voltage signal as a gate voltage signal of the mirror transistor;

the other data input end of the second selection circuit is grounded, and the second selection circuit is used for grounding the drain electrode of the mirror transistor when the selection signal indicates that the level of the first input end is not in level inversion.

Optionally, when the mirror transistor is an NMOS transistor, the other data input terminal of the first selection circuit is grounded, and the first selection circuit is further configured to control the gate of the mirror transistor to be grounded when the selection signal indicates that the level of the first input terminal does not flip;

the other data input end of the second selection circuit is connected with a power supply voltage signal, and the second selection circuit is further used for taking the power supply voltage signal as a drain voltage signal of the mirror image transistor when the selection signal indicates that the level of the first input end is not in level inversion.

Optionally, the test circuit further comprises: the input end of the second delay circuit and the enabling input end of the mirror image control circuit are connected with the same enabling signal, the second delay circuit is used for delaying the received enabling signal for a preset time and outputting the enabling signal to the enabling input end of the ring oscillation circuit through the output end of the second delay circuit, and the second delay circuit is used for controlling the oscillation signal generated by the ring oscillation circuit to lag behind the mirror image control signal generated by the mirror image control circuit.

Optionally, the second delay circuit comprises an even number of cascaded inverters.

Optionally, the selection signal generating circuit includes a nor gate and an inverter circuit, two input ends of the nor gate are respectively connected with the second input end of the second inverting unit and the output end of the inverter circuit, and the input end of the inverter circuit is connected with the second input end of the second inverting unit, and when the selection signal is a high level signal, the level of the first input end is indicated to be turned from a high level to a low level.

Optionally, the selection signal generating circuit includes a nand gate and an inverter circuit, two input ends of the nand gate are respectively connected with the second input end of the second inverter unit and the output end of the inverter circuit, and the input end of the inverter circuit is connected with the second input end of the second inverter unit, and when the selection signal is a low level signal, the level of the first input end is indicated to be turned from low level to high level.

Optionally, the inverting circuit includes an odd number of cascaded inverters.

Optionally, the first inverting unit of the first stage includes a first nand gate, the remaining first inverting units include a first not gate, two input ends of the first nand gate are respectively used as the enabling input end of the ring oscillating circuit and a first input end of the first inverting unit, an output end of the first nand gate is used as a first output end of the first inverting unit, and an input end and an output end of the first not gate are respectively used as a first input end and a first output end of the corresponding first inverting unit.

Optionally, the second inverting unit of the first stage includes a second nand gate, the remaining second inverting units include a second not gate, two input ends of the second nand gate are respectively used as the enabling input end of the mirror control circuit and a second input end of the second inverting unit, an output end of the second nand gate is used as a second output end of the second inverting unit, and an input end and an output end of the second not gate are respectively used as a second input end and a second output end of the corresponding second inverting unit.

Optionally, the first not gate and the second not gate each include a first transistor and a second transistor of different types, and a power input end of the first not gate and a source electrode of the first transistor are both connected to the same power voltage signal;

in any one of the first NOT gate and the second NOT gate, the gate of the first transistor is connected with the gate of the second transistor and serves as the input end of the corresponding NOT gate; the drain electrode of the first transistor is connected with the drain electrode of the second transistor and serves as the output end of the corresponding NOT gate, and the source electrode of the second transistor is grounded.

Optionally, when the mirror transistor is a PMOS transistor, the source of the mirror transistor and the first inverting unit are connected to a power voltage signal with the same size; when the mirror transistor is an NMOS transistor, the source of the mirror transistor is grounded.

Optionally, the first delay circuit includes an odd number of cascaded inverters.

In a second aspect, an embodiment of the present application provides a test system, including an enable signal generating circuit and the test circuit of the first aspect, where an output end of the enable signal generating circuit is connected to the test circuit, and an enable signal generated by the enable signal generating circuit is used to drive the test circuit to operate.

Optionally, the test circuit further comprises a frequency dividing element and an output buffer element, wherein the input end of the frequency dividing element is connected with one first output end of the ring oscillation circuit of the test circuit, and the output buffer element is connected with the output end of the frequency dividing element.

In a third aspect, an embodiment of the present application provides a testing method for the testing system of the foregoing second aspect, where the testing method includes:

driving the test circuit to operate by an enable signal;

during the operation process of the test circuit, acquiring the current of a mirror transistor in the test circuit and the oscillation frequency of the ring oscillation circuit;

Determining an equivalent parameter of a transistor in a first inverting unit of the ring oscillator circuit from a current of the mirror transistor and the oscillation frequency, the equivalent parameter comprising at least one of: equivalent capacitance and equivalent resistance.

In a fourth aspect, embodiments of the present application provide a semiconductor device including the test system of the foregoing second aspect.

The test circuit, the test system, the test method and the semiconductor device provided by the embodiment of the application can mirror the current of the transistor in the first reverse unit through the mirror circuit. In this way, the current between different transistors in one first inversion unit can be removed, which is helpful to improve the accuracy of the test flip current.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the embodiments of the application and together with the description, serve to explain the principles of the embodiments of the application.

FIG. 1 is a schematic diagram of a ring oscillator according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a current flow between adjacent inverters in the ring oscillator circuit of FIG. 1 according to one embodiment of the present disclosure;

FIG. 3 is a schematic diagram of another current flow between adjacent inverters in the ring oscillator circuit of FIG. 1 provided in accordance with an embodiment of the present application;

FIG. 4 is a schematic diagram of a test circuit according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a ring oscillator according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of another test circuit according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of the mirror image test circuit of FIG. 6 according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a mirror test circuit when the mirror transistor provided in the embodiment of the present application is a PMOS transistor;

fig. 9 is a schematic structural diagram of a mirror test circuit when the mirror transistor provided in the embodiment of the present application is an NMOS transistor;

FIG. 10 is a signal timing diagram of the mirrored test circuit of FIG. 8 provided in an embodiment of the present application;

FIG. 11 is a signal timing diagram of the mirror test circuit of FIG. 9 provided in an embodiment of the present application;

FIG. 12 is a schematic diagram of a test system according to an embodiment of the present application;

fig. 13 is a flowchart illustrating steps of a testing method according to an embodiment of the present application.

Specific embodiments thereof have been shown by way of example in the drawings and will herein be described in more detail. These drawings and the written description are not intended to limit the scope of the inventive concepts of the embodiments in any way, but rather to illustrate the concepts of the embodiments of the present application to those skilled in the art by reference to the specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the embodiments of the present application. Rather, they are merely examples of apparatus and methods consistent with aspects of embodiments of the present application as detailed in the accompanying claims.

In order to test the switching current at the level switching instant, the switching current can be tested by means of a ring oscillator. Fig. 1 is a schematic structural diagram of a ring oscillator according to an embodiment of the present application. Referring to fig. 1, the ring oscillator may be formed by connecting a plurality of inverters sequentially connected in cascade, and fig. 1 illustrates a ring oscillator formed by cascading five inverters, but in practical application, the number of inverters included in the ring oscillator is not limited. The specific structure of one of the inverters is labeled in detail in fig. 1, and the structure of the remaining inverters is the same as it, and thus is not labeled in fig. 1.

As can be seen from fig. 1, the output of each inverter is connected to the input of the next inverter, thus forming a ring oscillator circuit.

Each inverter in fig. 1 is obtained by connecting PMOS and NMOS, the gate G of PMOS is connected to the gate G of NMOS, and the two connected gates G serve as input terminals of the inverter. The drain D of PMOS is connected to the drain D of NMOS and the two connected drains D serve as the output of the inverter. The source S of the PMOS is connected to the power voltage signal VDD, and the source S of the NMOS is grounded GND.

In the ring oscillator shown in fig. 1, the output terminals of some inverters are turned from high to low, and the output terminals of other inverters are turned from low to high. Thus, the time of the level inversion can be accurately captured, and the current at the time can be used as the inversion current.

Fig. 2 is a schematic diagram of a current flow between adjacent inverters in the ring oscillator circuit of fig. 1 according to an embodiment of the present application. Referring to fig. 2, in the process of inverting the level V of the input terminal of the inverter of the previous stage from the high level to the low level, the PMOS in the inverter of the previous stage is gradually turned on and generates a current I1, and the current I1 flows to the common gate of the NMOS and the PMOS of the inverter of the next stage. Under the action of the current I1, the gate voltage of the NMOS of the inverter of the subsequent stage rises. However, in this process, the NMOS in the previous stage inverter is not completely turned off, and still some current I2 flows from the PMOS of the previous stage inverter to the ground GND. The current I1 and the current I2 both flow out from the VDD terminal together, so that the inverting current of the PMOS measured at the VDD port is larger and the accuracy is lower.

FIG. 3 is another schematic diagram of current flow between adjacent inverters in the ring oscillator circuit of FIG. 1, as provided by embodiments of the present application. Referring to fig. 3, in the process of inverting the level V of the input terminal of the previous-stage inverter from the low level to the high level, the NMOS in the previous-stage inverter is gradually turned on and generates a current I3, and the current I3 reduces the level of the common gate of the next-stage inverter to 0. However, in this process, the PMOS in the previous stage inverter is not completely turned off, and still some current I4 flows from the PMOS of the previous stage inverter to the ground GND through the NMOS of the previous stage inverter. The current I3 and the current I4 flow together into GND, so that the flip current of the NMOS measured at the GND port is large.

To solve the above-described problem, the present embodiment considers mirroring the flip-flop current in the transistor by one mirroring circuit. The current thus measured includes only the current flowing through the transistor and does not include the current flowing through two transistors in the same inverter when both transistors are in an on state. Thus, the measured switching current is more accurate.

Fig. 4 is a schematic structural diagram of a test circuit according to an embodiment of the present application. Referring to fig. 4, the test circuit 100 includes a ring oscillator circuit 101 and a mirror circuit 102.

Referring to fig. 4, the ring oscillator 101 includes a plurality of first inverting units 1011 cascaded in sequence, each of the first inverting units 1011 includes a first input terminal and a first output terminal, and the first input terminal and the first output terminal of at least one of the first inverting units 1011 are connected to the mirror circuit 102. The mirror circuit 102 is configured to receive a first voltage signal corresponding to a first input terminal of the first inverting unit 1011 and a second voltage signal corresponding to a first output terminal, and mirror an inversion current of a transistor in the first inverting unit 1011 according to the first voltage signal and the second voltage signal when a level inversion occurs at the first input terminal of the first inverting unit 1011.

The first reversing unit may be any unit with a reversing function, including but not limited to: NOT gate, NAND gate, NOR gate, exclusive OR gate, controllable NOT gate, and the like. The NOT gate can be one of a PMOS tube, an NMOS tube and a CMOS tube.

In fig. 4, the ring oscillator 101 is shown as 5 first inverting units 1011, but in practical application, the number of the first inverting units is only an odd number, and the number of the first inverting units is not limited. In fig. 4, a first inverting unit 1011 is exemplarily shown as being connected to the mirror circuit 102, but in practice, a plurality of first inverting units 1011 may be connected to the mirror circuit 102 to test the switching current of the transistors in the connected first inverting units 1011. The test roll-over current may represent the roll-over current of this type of transistor when the transistors in the ring oscillator 101 are identical.

The first inverting unit 1011 is configured to perform an inverting process on a first voltage signal at a first input terminal and output the first voltage signal through a first output terminal, and the output voltage signal is referred to as a second voltage signal. There may be two types of ring oscillator circuits.

In one embodiment of the ring oscillator, as shown in fig. 4, each stage of the first inverting unit 1011 may be a not gate, and may be referred to as a first not gate, so that the first input terminal of each first inverting unit 1011 is an input terminal of the first not gate, and the first output terminal of each first inverting unit 1011 is an output terminal of the first not gate therein. Thus, the output end of each first NOT gate of the ring oscillation circuit is connected with the input end of the first NOT gate of the next stage.

In another embodiment of the ring oscillator circuit, as shown in fig. 5, the structure of the first stage inverting unit may be different from that of the other first inverting unit 1011. Fig. 5 is a schematic structural diagram of a ring oscillator according to an embodiment of the present application. The first stage first inverting unit 1011 may be a first nand gate 10112 in fig. 5, and the remaining first inverting units 1011 may be constituted by the first nand gate 10111 in fig. 5. One input of the first nand gate 10112 serves as an enable input of the ring oscillation circuit 101. The other input terminal of the first nand gate 10112 is used as a first input terminal of the corresponding first inverting unit 1011, and the output terminal of the first nand gate 10112 is used as a first output terminal of the first inverting unit 1011. The input terminal and the output terminal of the first not gate 10111 are respectively the first input terminal and the first output terminal of the corresponding first inverting unit 1011.

Referring to fig. 5, the connection between the first inverting unit 1011 is the connection between the first nand gate 10112 and the first not gate 10111 described above. The output terminal of the first nand gate 10112 is connected to the input terminal of the first nor gate 10111 in the second stage first inverting unit 1011. The other input terminal of the first nand gate 10112 is connected to the output terminal of the first nor gate 10111 in the first inverting unit 1011 of the last stage, and the output terminals of the remaining first nor gates 10111 are connected to the input terminal of the first nor gate 10111 of the next stage.

The enable input in fig. 5 is used to control the oscillation of the ring oscillator 101. In the initial state, the enable signal is a low level signal, and at this time, the ring oscillation circuit 101 shown in fig. 5 does not oscillate. When the enable signal is a high level signal, the ring oscillation circuit 101 shown in fig. 5 starts oscillation, that is, the first not gate 10111 starts operation, and the level of the first input terminal is level-inverted. When the ring oscillation circuit 101 starts to oscillate, the flip current can be tested.

It can be seen that the embodiments of the present application can flexibly control the oscillation of the ring oscillation circuit 101 by combining the enable signal and the first nand gate 10112, and can control the ring oscillation circuit 101 to stop the oscillation by the enable signal when the test flip current is not needed, which helps to save electric energy.

In an alternative embodiment, the first not gate 10111 may be an inverter including different types of first transistors and/or second transistors, for example, the first transistors may be PMOS transistors, and the second transistors may be NMOS transistors, and may also be TTL (Transistor-Transistor Logic) inverters.

Referring to fig. 5, the power input terminal of the first nand gate 10112 and the source of the first transistor of each first nor gate 10111 in the ring oscillation circuit 101 are connected to the same power voltage signal VDD to provide power to the ring oscillation circuit 101. Of course, since the ring oscillator 101 can oscillate without the first nand gate 10112, the sources of the first transistors all have access to the same power supply voltage signal VDD when the first nand gate 10112 is not present in the ring oscillator 101.

In any of the first not gates 10111 shown in fig. 5, the gate G of the first transistor PMOS is connected to the gate G of the second transistor NMOS, and is used as the input terminal of the corresponding first not gate 10111, that is, the first input terminal of the corresponding first inverting unit 1011. The drain D of the first transistor PMOS is connected to the drain D of the second transistor NMOS and serves as the output terminal of the corresponding first not gate 10111, i.e., the first output terminal of the corresponding first inverting unit 1011, and the source S of the second transistor is grounded.

Note that, in fig. 5, the internal detailed structure of the first not gate 10111 in the second stage first inverting unit 1011 is labeled, and the structures of the remaining first not gates 10111 are the same, and are not labeled in fig. 5.

The ring oscillator 101 can mirror the flip-flop current of the transistor in the mirror circuit 102 during oscillation. Fig. 6 is a schematic structural diagram of another test circuit according to an embodiment of the present application. Referring to fig. 6, the mirror circuit 102 may include: a mirror control circuit 1021 and at least one mirror test circuit 1022, the mirror control circuit 1021 being configured to control a mirror flip current of the mirror test circuit 1022. In this way, independent operation of mirror control and mirror test can be realized, modularization of the mirror circuit 102 is improved, and management and maintenance of the mirror circuit 102 are facilitated.

One mirror test circuit 1022 is shown in fig. 6 for example, but in practical applications, the number of mirror test circuits may be multiple, and the number of mirror test circuits is at most the same as the number of the first not gates 10111, so as to mirror the transistors in the first not gates 10111 and test the flip-flop current thereof.

The mirror control circuit 1021 may include at least one control signal output end, where the control signal output end is connected to the mirror test circuit 1022 in a one-to-one correspondence, and the mirror control circuit 1021 is configured to send a mirror control signal to the mirror test circuit 1022 through the control signal output end, where the mirror control signal is configured to indicate a flipped state of the first inverting unit 1011.

Each mirror test circuit 1022 is further coupled to a first input and a first output of a first inverting unit 1011, i.e., an input and an output of at least one first not gate 10111 of fig. 6. The image test circuit 1022 is configured to determine whether a first input terminal of the first inverting unit 1011 is level-inverted according to the image control signal, and mirror an inverted current of a transistor in the first inverting unit 1011 according to the first voltage signal and the second voltage signal when the level inversion occurs. When no level inversion occurs, the mirror test circuit 1022 may not mirror the inversion current, so that power may be saved.

Wherein the transistor of the mirror test circuit 1022 that is to mirror the flipped current is a transistor in the first not gate 10111.

According to the embodiment of the application, the corresponding mirror image test circuit 1022 can be set for each first reverse unit 1011, so that independent tests are performed between different mirror image test circuits 1022, coupling between different mirror image test circuits 1022 is avoided, and the accuracy of the tests is improved. In addition, the image control circuit 1021 is configured to generate an image control signal, and the image test circuit 1022 is configured to perform image according to the image control signal, so that the integration level of the circuit is improved, and circuit management and maintenance are facilitated.

Alternatively, the mirror control circuit 1021 may be a mirror circuit of the ring oscillator 101, and may have the same structure as the ring oscillator 101, and an inverting unit in the mirror control circuit 1021 may be referred to as a second inverting unit, a second input terminal of the second inverting unit may be referred to as a second input terminal, and a second output terminal of the second inverting unit may be referred to as a second output terminal. Thus, the mirror control circuit 1021 may include a plurality of second inverting units that are sequentially cascaded. Each of the second inverting units includes a second input terminal connected to the image test circuit 1022 as a control signal output terminal for transmitting the voltage signal of the second input terminal of the second inverting unit as an image control signal to the image test circuit 1022.

In order for the mirror control signal to accurately indicate the level inversion state of the first input terminal, the operating state of the mirror control circuit 1021 is required to be the same as the operating state of the ring oscillator 101. Based on this consideration, the number of the second inverting units may be the same as the number of the first inverting units 1011, and further, the mirror control circuit 1021 operates at the same power supply voltage as the ring oscillation circuit 101 to make the operating voltages of the ring oscillation circuit 101 and the mirror control circuit 1021 coincide, so that the mirror control circuit 1021 and the oscillation frequency can be ensured to coincide with the oscillation frequency of the ring oscillation circuit 101.

As with the ring oscillator 101 described above, when the ring oscillator 101 does not include the first nand gate 10112, the mirror control circuit 1021 may not include the second nand gate 10212, and each of the second inverting units in the mirror control circuit 1021 may be constituted by the second nand gate 10211. When the first stage first inverting unit 1011 in the ring oscillation circuit 101 includes the first nand gate 10112, the mirror control circuit 1021 may also include the second nand gate 10212. The first stage second inverting unit includes a second nand gate 10212, and the remaining second inverting units include a second nand gate 10211. Two input terminals of the second nand gate 10212 serve as an enable input terminal of the mirror control circuit 1021 and a second input terminal of the second inverting unit, and an output terminal of the second nand gate 10212 serves as a second output terminal of the second inverting unit. The input and output terminals of the second not gate 10211 are respectively used as the second input terminal and the second output terminal of the corresponding second inverting unit, and the second input terminal can be used as the control signal output terminal.

Correspondingly, the second NOT gate 10211 includes a first transistor PMOS and a second transistor NMOS of different types, and the power input terminal of the second NOT gate 10212 and the source S of the second transistor NMOS are connected to the same power voltage signal VDD. In any second not gate 10211, the gate G of the first transistor PMOS is connected to the gate G of the second transistor NMOS, and is used as the input terminal of the corresponding second not gate 10211, that is, the second input terminal of the second inverting unit. The drain D of the first transistor PMOS is connected to the drain D of the second transistor NMOS and serves as the output of the corresponding second inverter 10211, i.e., the second output of the corresponding second inverter unit, and the source S of the second transistor NMOS is grounded.

In summary, the mirror control circuit 1021 according to the embodiment of the present application has the same structure as the ring oscillator 101, and has the same operation state. Thus, the mirror control signal output by the mirror control circuit 1021 can accurately indicate the level inversion state of the first inversion unit 1011 in the ring oscillation circuit 101, which is helpful for improving the test accuracy of the inversion current.

It can be seen that the mirror control circuit 1021 needs to generate a control signal to cause the mirror test circuit 1022 to perform mirroring, which takes a certain time period. In order to make the first voltage signal of the ring oscillation circuit 101 and the image control signal generated by the image control circuit 1021 arrive at the image test circuit 1022 at the same time as possible, the oscillation of the image control circuit 1021 may be delayed from the oscillation of the ring oscillation circuit 101.

Optionally, referring to fig. 6, the test circuit 100 may further include: a second delay circuit 103. The input of the second delay circuit 103 and the enable input of the mirror control circuit 1021 are connected to the same enable signal, that is, the enable input of the mirror control circuit 1021 is one input of the second nand gate 10212 of the mirror control circuit 1021. The other input of the second nand gate 10212 is connected to the output of the second nor gate 10211 of the second inverting unit of the last stage. The second delay circuit 103 is configured to delay the received enable signal for a preset time, and output the delayed enable signal to the enable input terminal of the ring oscillator 101 through the output terminal of the second delay circuit 103, where the second delay circuit 103 is configured to control the oscillation signal generated by the ring oscillator 101 to lag behind the mirror control signal generated by the mirror control circuit 1021.

The preset time may be set according to the actual circuit design requirement, so that the mirror control signal reaches the mirror test circuit 1022 as early as possible before the first voltage signal, so that the mirror control signal plays a role in predicting or indicating the variation trend of the first voltage signal in the corresponding first reverse unit, so that before the first voltage signal is turned over, the gate and the drain of the mirror transistor are controlled to be connected to the voltage signal corresponding to the transistor in the first reverse unit, and the accurate mirror turning current of the mirror test circuit 1022 can be ensured.

The second delay circuit 103 may be any logic circuit, so that the processing of the logic circuit consumes a long time to achieve the purpose of delay. However, the input and output signals of the second delay circuit 103 must be the same, so that the operating state of the ring oscillator 101 at time T may be identical to the operating state of the mirror control circuit 1021 at time t+t. Wherein T is a preset time for the second delay circuit 103 to delay the enable signal. In this way, the mirror control signal can reach the mirror test circuit 1022 as early as possible before the first voltage signal, and the level inversion state of the corresponding first voltage signal can be accurately indicated by the mirror control signal, which is helpful for further improving the mirror accuracy of the mirror test circuit 1022 to the inversion current.

Alternatively, the second delay circuit 103 may include an even number of cascaded inverters, wherein an input of a first-stage inverter is used as an input of the second delay circuit 103, an output of the first-stage inverter is connected to an input of a next-stage inverter, and an output of a last-stage inverter is used as an output of the second delay circuit 103. Thus, the signal input to the second delay circuit 103 is inverted an even number of times to obtain the same signal as the input signal. But each inverter requires a certain length of time to process the signal so that a delay can be achieved.

It should be noted that the number of inverters in the second delay circuit 103 may be positively correlated according to the predetermined time to be delayed. The larger the preset time, the larger the number of inverters. Conversely, the smaller the number of inverters in the second delay circuit 103.

The second delay circuit 103 can be formed by the inverters, and the preset time of the delay can be adjusted according to the number of the inverters, so that the adjustment flexibility of the preset time can be improved.

Fig. 7 is a schematic diagram of the mirror image test circuit in fig. 6 according to an embodiment of the present application. Referring to fig. 7, the mirror test circuit 1022 may include a mirror transistor and a test control circuit. The test control circuit is connected to the control signal output of the mirror control circuit 1021, the input of the first not gate 10111 (i.e., the first input), the output of the first not gate 10111 (i.e., the first output), and the mirror transistor, respectively. The control signal output of the mirror control circuit 1021 is the second input in fig. 7 according to the previous description. Based on these connections, the test control circuit may receive a mirror control signal from the mirror control circuit 1021 to determine whether a level flip has occurred at the first input. The test control circuit may also receive a first voltage signal from the first input terminal and a second voltage signal from the second input terminal.

When the test control circuit determines that the level of the first input terminal is inverted according to the mirror control circuit 1021, the test control circuit may control the operating voltage of the mirror transistor according to the first voltage signal and the second voltage signal, so that the current of the mirror transistor is the same as the current of the transistor in the first inverting unit 1011.

Wherein the mirror transistor is the same transistor as one of the transistors in the first not gate 10111. When the transistors in the first not gate 10111 include PMOS transistors, the mirror transistors may be PMOS transistors to mirror the current of the PMOS transistors in the first not gate 10111. When the transistors in the second NOT 10211 include NMOS transistors, the mirror transistor may be an NMOS transistor to mirror the current of the first NOT NMOS transistor.

Of course, when no level inversion occurs, the test control circuit may control the mirror transistor to be turned off to save power.

According to the embodiment of the application, the same working state of the mirror transistor and the transistor in the first NOT 10111 can be controlled through the test control circuit, so that the mirror image of the current can be realized, and the current of the transistor in the first NOT 10111 can be accurately mirrored through the mirror image transistor.

Referring to fig. 7, the test control circuit may further include a selection signal generating circuit and a voltage control circuit, wherein the selection signal generating circuit is connected to the second input terminal of the mirror control circuit 1021 and the voltage control circuit.

The selection signal generating circuit is configured to receive the image control signal sent by the image control circuit 1021, and output a selection signal according to the image control signal. The select signal is used to indicate whether a level flip of the first input terminal is about to occur, including but not limited to: the high level of the selection signal indicates that level shifting is occurring, and the low level of the selection signal indicates that level shifting is occurring. The examples of the present application are not limited thereto.

The voltage control circuit is respectively connected with the selection signal generating circuit, the first input end, the first output end and the mirror image transistor. Thus, the voltage control circuit may receive the selection signal generating circuit, the first voltage signal at the first input terminal, and the second voltage signal at the first output terminal. The voltage control circuit is used for controlling the grid voltage signal of the mirror image transistor to be consistent with the first voltage signal and controlling the drain voltage signal of the mirror image transistor to be consistent with the second voltage signal when the selection signal indicates that the first input end is subjected to level inversion.

Specifically, when the mirror control signal indicates that the first input terminal of the first inverting unit is in a level inversion state, the selection signal indicates that the inversion current of the transistor in the first inverting unit needs to be mirrored. At this time, the voltage control circuit controls the gate and drain voltages of the mirror transistor to be the same as those of the transistor in the first inverting unit to be mirrored, respectively, according to the selection signal, thereby realizing mirroring of the transistor current.

In addition, since the oscillation frequency of the image control circuit is the same as that of the ring oscillation circuit, and the oscillation signal of the image control circuit is controlled by the enable signal of the second delay circuit 103, the oscillation signal of the image control circuit is earlier than the oscillation signal of the ring oscillation circuit by a preset time, that is, the signal change of the second input end of the second inverting unit in the image control circuit is earlier than the signal change of the first input end of the corresponding first inverting unit in the ring oscillation circuit, therefore, the image control signal corresponding to the second input end of the second inverting unit can indicate the change trend of the first voltage signal, and when the first inverting unit is earlier than the inversion occurs, the first selection circuit and the second selection circuit are controlled to give the first voltage signal of the gate electrode and the second voltage signal of the drain electrode in the first inverting unit to the image transistor.

It is understood that the first voltage signal is the gate voltage signals of PMOS and NMOS in the first not gate 10111, and the second voltage signal is the drain voltage signals of PMOS and NMOS in the first not gate 10111.

In addition, when the mirror transistor is a PMOS transistor, the source of the mirror transistor and the first inverting unit 1011 are connected to the same power voltage signal. Therefore, the working voltage of each pole of the mirror image transistor is identical to the working voltage of each pole of the PMOS in the first NOT gate 10111, so that the mirror image transistor and the PMOS in the first NOT gate 10111 are in the same working state, the mirror image accuracy of the mirror image transistor to the turning current of the PMOS in the first NOT gate 10111 is further ensured, and the accuracy of the turning current of the PMOS tube is improved.

When the mirror transistor is an NMOS transistor, the source of the mirror transistor is grounded. Therefore, the working voltage of each pole of the mirror image transistor is identical to the working voltage of each pole of the NMOS in the first NOT gate 10111, so that the mirror image transistor and the NMOS in the first NOT gate 10111 are in the same working state, the mirror image accuracy of the mirror image transistor to the turnover current of the NMOS in the first NOT gate 10111 is further ensured, and the accuracy of the turnover current of the NMOS tube is improved.

In an example of the embodiment of the present application, referring to fig. 7, the above-described voltage control circuit may further include a first selection circuit, a second selection circuit, and a first delay circuit. The first selection circuit is used for controlling the grid voltage signal of the mirror transistor, and the second selection circuit is used for controlling the drain voltage signal of the mirror transistor.

As can be seen from fig. 7, the control input of the first selection circuit is directly connected to the selection signal generating circuit for receiving the selection signal. And the control input end of the second selection circuit is connected with the output end of the first delay circuit, the input end of the first delay circuit is connected with the output end of the selection signal generation circuit, and the control input end of the second selection circuit is used for receiving the delayed selection signal.

It will be appreciated that the first delay circuit is configured to delay the selection signal and send the delayed selection signal to the second selection circuit, so that the control of the drain voltage signal by the second selection circuit lags the control of the gate voltage signal by the first selection circuit, which is consistent with the second voltage signal of the first not gate 10111 lagging the first voltage signal of the first not gate 10111. Thus, the time when the second selection circuit receives the selection signal lags behind the time when the first selection circuit receives the selection signal, so that the control of the drain voltage signal by the second selection circuit lags behind the control of the gate voltage signal by the first selection circuit.

It should be noted that the first delay circuit may be any logic circuit, so as to achieve the purpose of delay through the processing procedure of the logic circuit. For example, the first delay circuit includes an odd number of cascaded inverters. Considering that the second voltage signal of the same first inverting unit 10111 lags behind the first voltage signal of the first inverting unit, it is the processing duration of one inverter. Thus, one inverter can be selected to realize delay, and the selection signal can be accurately delayed by the processing time length of one inverter. Referring to fig. 10 or 11, when the processing time period of the inverter is denoted by t, the control of the gate voltage signal by the first selection circuit is performed at time t1, and the control of the drain voltage signal by the second selection circuit is performed at time t3=t1+t. In this way, the drain of the mirror transistor and the drain of the transistor in the first not gate 10111 can be identical at the same time, which helps to improve the accuracy of the mirror flip current.

Fig. 8 is a schematic structural diagram of a mirror image test circuit when the mirror image transistor provided in the embodiment of the present application is a PMOS transistor, and fig. 9 is a schematic structural diagram of a mirror image test circuit when the mirror image transistor provided in the embodiment of the present application is an NMOS transistor. Referring to fig. 8 and 9, each of the first and second selection circuits may be a multiplexer.

Referring to fig. 8, one of the data input terminals 1 of the first selection circuit is connected to a first input terminal of the first inverting unit 1011 (i.e., an input terminal of the first not gate 10111 in the first inverting unit 1011), and the other data input terminal 0 of the first selection circuit is connected to the power supply voltage signal VDD. When the selection signal is high, a level flip of the level of the first input terminal is indicated. At this time, the first selection circuit selects the first voltage signal of the input terminal of the first not gate 10111 connected to the data input terminal 1 thereof as the output signal thereof, and the output terminal of the first selection circuit is connected to the gate G of the mirror transistor PMOS, that is, the first selection circuit is configured to use the first voltage signal as the gate voltage signal of the mirror transistor PMOS.

Accordingly, when the first delay circuit is a device having an inverting function such as a CMOS inverter, the signal received from the control input terminal by the second selection circuit is an inverted signal of the selection signal. Thus, referring to fig. 8, one of the data input terminals 0 of the second selection circuit is connected to the first output terminal, and the output terminal of the second selection circuit is connected to the drain D of the mirror transistor PMOS. Thus, when the selection signal is at a high level to indicate that the level of the first input terminal is level-inverted, the second voltage signal received by the data input terminal 0 is taken as the drain voltage signal of the mirror transistor PMOS.

Referring to fig. 9, one of the data input terminals 0 of the first selection circuit is connected to the first input terminal of the first inverting unit 1011, and the other data input terminal 1 of the first selection circuit may be grounded GND. When the selection signal is low, a level flip of the level of the first input terminal is indicated. At this time, the first selection circuit selects the first voltage signal of the input terminal of the first inverting unit 10111 connected to the data input terminal 0 thereof as the output signal thereof, and the output terminal of the first selection circuit is connected to the gate G of the mirror transistor NMOS, that is, the first selection circuit is configured to use the first voltage signal as the gate voltage signal of the mirror transistor NMOS when the selection signal is at the low level to indicate that the level inversion occurs.

Accordingly, when the first delay circuit is a device having an inverting function such as a CMOS inverter, the signal received from the control input terminal by the second selection circuit is an inverted signal of the selection signal. Thus, referring to fig. 9, one of the data input terminals 1 of the second selection circuit is connected to the output terminal of the first not gate 10111, and the output terminal of the second selection circuit is connected to the drain D of the mirror transistor NMOS, for taking the second voltage signal received by the data input terminal 1 as the drain voltage signal of the mirror transistor NMOS when the selection signal is at a low level to indicate that the level of the first input terminal is level-inverted.

As can be seen from fig. 8 and 9, when the first input terminal generates the level inversion, the first selection circuit and the second selection circuit can control the operating voltages of the gate G and the drain D of the mirror transistor so as to be consistent with the voltages of the drain D of the gate G of the transistor in the first nor gate 10111, respectively. When the first input terminal does not generate level inversion, the first selection circuit and the second selection circuit can work in any state, so that the other data input terminal of the first selection circuit and the other data input terminal of the second selection circuit can be connected with any voltage signal.

However, for better power saving, the mirror transistor may be controlled to be turned off by the first selection circuit and the second selection circuit when no level inversion is generated at the first input terminal. Referring to fig. 8, when the mirror transistor is a PMOS transistor, the other data input terminal 0 of the first selection circuit may be connected to the power voltage signal VDD. Thus, the first selection circuit is further configured to take the power supply voltage signal VDD as the gate voltage signal of the mirror transistor PMOS when the selection signal is at a low level to indicate that no level inversion occurs in the level of the first input terminal. The other data input 1 of the second selection circuit is grounded GND, and the second selection circuit is configured to ground the drain of the mirror transistor when the selection signal is low to indicate that no level inversion of the level of the first input has occurred. Thus, the mirror transistor PMOS is turned off.

It can be seen that the image test circuit 1022 shown in fig. 8 is a structure when the selection signal is high to indicate a level flip. In practical applications, the level of the first input terminal may be indicated to be inverted when the selection signal is at a low level. At this time, the circuits connected to the data input terminals 1 and 0 of the first selection circuit in fig. 8 need to be exchanged, and the circuits connected to the data input terminals 1 and 0 of the second selection circuit need to be exchanged, which is described in detail herein.

Referring to fig. 9, when the mirror transistor is an NMOS transistor, the other data input terminal 1 of the first selection circuit is grounded. The first selection circuit is further configured to control the gate G of the mirror transistor NMOS to be grounded when the selection signal is at a high level to indicate that no level inversion of the level of the first input terminal occurs. In addition, the other data input terminal 0 of the second selection circuit is connected to the power supply voltage signal VDD, and the second selection circuit is further configured to use the power supply voltage signal VDD as the drain voltage signal of the mirror transistor NMOS when the selection signal is at a high level to indicate that the level of the first input terminal is not level-inverted. Thus, the mirror transistor NMOS is turned off.

The selection signal generating circuit is used for identifying the level inversion of the mirror control signal according to the delay action of the inverting circuit, namely, the level inversion of the first input terminal is identified.

It can be seen that the image test circuit 1022 shown in fig. 9 is a structure when the selection signal is low to indicate a level flip. In practical applications, the level of the first input terminal may be indicated to be inverted when the selection signal is at a high level. At this time, the circuits connected to the data input terminals 1 and 0 of the first selection circuit in fig. 9 need to be exchanged, and the circuits connected to the data input terminals 1 and 0 of the second selection circuit need to be exchanged, which is described in detail herein.

Further, as can be seen from fig. 8 and 9, the first delay circuit is an inverter having an inverting function. In practical applications, the first delay circuit may not have an inverting function, and a circuit switch connected to the data input terminals 1 and 0 of the second selection circuit in fig. 8 and 9 is required.

The first selection circuit and the second selection circuit in the image test circuit 1022 are described above, and the selection signal generation circuit is described in detail below.

As shown in fig. 8, the mirror transistor is a PMOS transistor, and when the level of the first input terminal is indicated to be inverted from high level to low level by the selection signal generated by the selection signal generating circuit, the first voltage signal and the second voltage signal are sequentially connected to the gate and the drain of the mirror transistor PMOS, so that the mirror transistor PMOS starts to be turned on. In this way, the current in the mirror transistor PMOS can mirror the turning current of the PMOS transistor in the first not gate 10111, and because the mirror transistor PMOS is not connected with the NMOS transistor, the current of the mirror transistor PMOS only includes the turning current, thereby eliminating the leakage current generated by the simultaneous conduction of the NMOS transistor and the PMOS transistor in the CMOS turning process, and obtaining the effective driving current of the PMOS transistor in the first not gate 10111.

Referring to fig. 8, the selection signal generating circuit may include a nor gate and an inverter circuit. The two input ends of the NOR gate are respectively connected with the second input end of the second reversing unit and the output end of the inverting circuit, and the input end of the inverting circuit is connected with the second input end of the second reversing unit.

Fig. 10 is a signal timing diagram of the mirror test circuit shown in fig. 8 according to an embodiment of the present application. Fig. 10 shows timings of the selection signal, the output signal of the first delay circuit, the gate voltage signal of the PMOS transistor, and the drain voltage signal of the PMOS transistor when the image control signal is inverted from the high level to the low level.

Referring to fig. 10, the mirror control signal input to the nor gate in fig. 8 is at a high level before time t1, and thus the selection signal output from the nor gate is always at a low level. The output signal of the first delay circuit is inverted from the selection signal so as to be always at a high level. Therefore, the first selection circuit in fig. 8 controls the gate voltage signal of the PMOS transistor to be the power voltage signal VDD received by the data input terminal 0, that is, the high level, and the second selection circuit controls the drain voltage signal of the PMOS transistor to be the ground signal GND received by the data input terminal 1, that is, the low level signal.

At time t1, the mirror control signal starts to flip from high to low and ends to flip at time t 2.

At time t2, the image control signal input to the nor gate is inverted to a low level, but the other input terminal of the nor gate is still low due to the inversion and delay action of the inverting circuit in fig. 8, and thus the selection signal output from the nor gate is inverted to a high level.

The high level of the selection signal continues for a period of time until the time t4 ends, and the duration of the high level is the time delay between the input and the output of the inverter circuit.

As can be seen from fig. 8, the selection signal is an input of the first delay circuit, so that referring to fig. 10, the output signal of the first delay circuit is an inverted delay signal of the selection signal.

Under the action of the high-level selection signal in fig. 10, the first selection circuit controls the gate voltage signal of the PMOS transistor to be the first voltage signal received by the data input terminal 1 from the first input terminal according to the selection signal, and at this time, after a preset time lags behind the mirror control signal generated by the second reversing unit in the mirror control circuit, the first voltage signal of the first input terminal of the first reversing unit is also turned from high level to low level, and the voltage of the PMOS gate connected to the first voltage signal is also gradually turned to low level. Meanwhile, the second selection circuit controls the drain voltage signal of the PMOS transistor to be the second voltage signal received from the first output terminal by the data input terminal 0 according to the inverted delay signal of the selection signal, that is, the output signal of the first delay circuit in fig. 10, and similarly, the voltage of the drain electrode of the PMOS transistor connected to the second voltage signal gradually changes to the high level signal.

At time t4, the selection signal starts to turn from high level to low level, so that the first selection circuit controls the gate voltage signal of the PMOS transistor to be the power voltage signal VDD received by the data input terminal 0, that is, the high level signal, according to the selection signal.

Due to the inverse delay effect of the first delay circuit in fig. 8, the control input terminal of the second selection circuit receives the inverse delay signal of the selection signal, and at time t4, the control input terminal of the second selection circuit receives the low level signal, and the second selection circuit continues to control the drain terminal of the PMOS transistor to receive the second voltage signal from the data input terminal 0 according to the inverse delay signal.

At time t5, since the output signal of the first delay circuit starts to turn to a high level, the first selection circuit controls the drain voltage signal of the PMOS transistor to be the ground signal received by the data input terminal 1, that is, a low level signal, according to the selection signal.

It can be seen that when the selection signal is a high level signal, the level of the first input terminal is instructed to flip from high level to low level.

In practical applications, the generated signal of the selection signal generating circuit may be inverted and then input to the first selection circuit and the first delay circuit as a selection signal, so that when the selection signal is a low level signal, the level of the first input end is indicated to be inverted from a high level to a low level, so that the inverted current of the PMOS transistor may be tested, at this time, the circuits connected to the data input ends 1 and 0 of the first selection circuit in fig. 8 need to be exchanged, and the circuits connected to the data input ends 1 and 0 of the second selection circuit need to be exchanged, which is not described herein.

As shown in fig. 9, the mirror transistor is an NMOS transistor, and when the level of the first input terminal is indicated to be inverted from low level to high level by the selection signal generated by the selection signal generating circuit, the first voltage signal and the second voltage signal are sequentially connected to the gate and the drain of the mirror transistor NMOS, so that the mirror transistor NMOS starts to be turned on. In this way, the current in the mirror transistor NMOS can mirror the overturn current of the NMOS tube in the first NOT gate 10111, and because the mirror transistor NMOS is not connected with the PMOS tube, the current of the mirror transistor NMOS only comprises the overturn current, so that the leakage current generated by the simultaneous conduction of the NMOS tube and the PMOS tube in the CMOS overturn process is eliminated, and the effective driving current of the NMOS tube in the first NOT gate 10111 can be obtained.

Referring to fig. 9, the selection signal generating circuit includes a nand gate and an inverter circuit, two input terminals of the nand gate are connected to the second input terminal of the second inverting unit and the output terminal of the inverter circuit, respectively, and the input terminal of the inverter circuit is connected to the second input terminal of the second inverting unit.

As can also be seen from fig. 8 and 9, a capacitor C is also connected between VDD and the control input of the second selection circuit, which capacitor C delays the signal input to the control input.

FIG. 11 is a signal timing diagram of the mirror test circuit of FIG. 9 according to an embodiment of the present application. Fig. 11 shows timings of the selection signal, the output signal of the first delay circuit, the gate voltage signal of the NMOS transistor, and the drain voltage signal of the NMOS transistor when the image control signal is inverted from the low level to the high level.

Referring to fig. 11, the mirror control signal input to the nand gate in fig. 9 is low before time t1, so that the selection signal output from the nand gate is always high. The output signal of the first delay circuit is inverted from the selection signal so as to be always at a low level. Therefore, the first selection circuit in fig. 9 controls the gate voltage signal of the NMOS transistor to be the ground signal GND received by the data input terminal 1, i.e., the low level, and the second selection circuit controls the drain voltage signal of the NMOS transistor to be the power voltage signal VDD received by the data input terminal 0, i.e., the high level signal.

At time t1, the mirror control signal starts to flip from a low level to a high level, and ends the flip at time t 2.

At time t2, the mirror control signal input to the nand gate is inverted to a high level, but the other input terminal of the nand gate is still at a high level due to the inversion and delay action of the inverting circuit in fig. 9, and thus the selection signal output from the nand gate is inverted to a low level.

The low level of the selection signal continues for a period of time until the time t4 ends, and the duration of the low level is the time delay between the input and the output of the inverter circuit.

As can be seen from fig. 9, the selection signal is an input of the first delay circuit, and the output signal of the first delay circuit is an inverted delay signal of the selection signal.

Under the action of the low-level selection signal in fig. 11, the first selection circuit controls the gate voltage signal of the NMOS transistor to be the first voltage signal received from the first input terminal by the data input terminal 0 according to the selection signal, and at this time, after a preset time lags behind the mirror control signal generated by the second reversing unit in the mirror control circuit, the first voltage signal of the first input terminal of the first reversing unit is also turned from low level to high level, and the voltage of the NMOS gate connected to the first voltage signal is also gradually turned to high level. Meanwhile, the second selection circuit controls the drain voltage signal of the NMOS transistor to be the second voltage signal received from the first output terminal through the data input terminal 1 of the second selection circuit according to the inverted delay signal of the selection signal, that is, the output signal of the first delay circuit in fig. 11, and similarly, the voltage of the drain of the NMOS connected to the second voltage signal gradually becomes the low level signal.

At time t4, since the selection signal starts to flip from low level to high level, the first selection circuit controls the gate voltage signal of the NMOS transistor to be the ground signal GND received by the data input terminal 1, that is, the low level signal, according to the selection signal.

Due to the inverse delay effect of the first delay circuit in fig. 9, the control input terminal of the second selection circuit receives the inverse delay signal of the selection signal, and at time t4, the control input terminal of the second selection circuit receives the still high level signal, and the second selection circuit continues to control the drain terminal of the NMOS transistor to receive the second voltage signal from the data input terminal 1 according to the inverse delay signal.

At time t5, since the output signal of the first delay circuit starts to flip to a low level, the second selection circuit controls the drain voltage signal of the NMOS transistor to be the power voltage signal VDD received from the data input terminal 0, that is, a high level signal, according to the selection signal.

It can be seen that when the selection signal is a low level signal, the level of the first input terminal is indicated to be inverted from low level to high level.

In practical application, the signal generated by the selection signal generating circuit can be inverted and then input into the first selection circuit and the first delay circuit as a selection signal, so that when the selection signal is a high-level signal, the level of the first input end is indicated to be turned from a low level to a high level, and the turning current of the NMOS tube can be tested.

Alternatively, the inverter circuit described above includes an odd number of cascaded inverters, and an inverter circuit composed of three inverters is exemplarily shown in fig. 8 and 9. The inverter with the odd number of cascading inverters can realize the inversion of the mirror control signal and delay, namely, can realize multiple functions through one circuit at the same time, and is beneficial to reducing the circuit cost.

Fig. 12 is a schematic structural diagram of a test system according to an embodiment of the present application. Referring to fig. 12, the test system 20 includes: an enable signal generating circuit 21 and a test circuit 100. The output terminal of the enable signal generating circuit 21 is connected to the test circuit 100, and the enable signal generated by the enable signal generating circuit 21 is used to drive the test circuit 100 to operate.

When the test circuit 100 includes the ring oscillation circuit 101 shown in fig. 5, the output terminal of the enable signal generation circuit 21 is connected to the enable input terminal in fig. 5.

Optionally, the test system 20 may further include a frequency dividing element 22 and an output buffer element 23. The input terminal of the frequency dividing element 22 is connected to one of the first output terminals of the ring oscillator 101 of the test circuit 100, and the output buffer element 23 is connected to the output terminal of the frequency dividing element 22.

The frequency dividing element 22 is used for performing frequency division processing on the oscillation signal generated by the test circuit 100, and may be, for example, a 1/2 frequency divider or the like.

The output buffer element 23 is used to buffer the signal after frequency division for output to an external device.

Fig. 13 is a flowchart of steps of a testing method according to an embodiment of the present application, which is used in the foregoing testing system. Referring to fig. 13, the test method may include S301 to S303.

S301: the test circuit is driven to operate by an enable signal.

S302: during operation of the test circuit, current of the mirror transistor in the test circuit and oscillation frequency of the ring oscillation circuit are obtained.

S303: determining an equivalent parameter of a transistor in a first inverting unit of the ring oscillator based on a current and an oscillation frequency of the mirror transistor, the equivalent parameter including at least one of: equivalent capacitance and equivalent resistance.

According to the embodiment of the application, the overturning current in the first NOT gate can be accurately tested through the current of the mirror image transistor, so that the accuracy of the equivalent capacitance and the equivalent resistance can be improved.

Embodiments of the present application also provide a semiconductor device including the test system as claimed in the foregoing claims.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments.

The foregoing is only the preferred embodiments of the present application, and is not intended to limit the scope of the embodiments of the present application, and all equivalent structures or equivalent processes using the descriptions of the embodiments of the present application and the contents of the drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the embodiments of the present application.

Claims

1. A test circuit, comprising a ring oscillator circuit and a mirror circuit;

2. The test circuit of claim 1, wherein the mirror circuit comprises a mirror control circuit and at least one mirror test circuit;

3. The test circuit of claim 2, wherein the test circuit comprises a plurality of test circuits,

the mirror image control circuit comprises a plurality of second reversing units which are sequentially cascaded, the number of the second reversing units is the same as that of the first reversing units, and the mirror image control circuit and the ring oscillation circuit work under the same power supply voltage;

4. The test circuit of claim 3, wherein,

the mirror image test circuit comprises a mirror image transistor and a test control circuit, wherein the test control circuit is respectively connected with the control signal output end, the first input end, the first output end and the mirror image transistor, and the test control circuit is used for determining whether the first input end is subjected to level inversion according to the mirror image control signal sent by the mirror image control circuit, and controlling the working voltage of the mirror image transistor according to the received first voltage signal and the received second voltage signal when the level inversion occurs, so that the current of the mirror image transistor is the same as the current of the transistor in the first reverse unit.

5. The test circuit of claim 4, wherein the test control circuit comprises a selection signal generation circuit and a voltage control circuit;

6. The test circuit of claim 5, wherein the voltage control circuit comprises a first selection circuit, a second selection circuit, and a first delay circuit;

7. The test circuit of claim 6, wherein when the mirror transistor is a PMOS transistor, the other data input of the first selection circuit is connected to a power supply voltage signal, and wherein the first selection circuit is further configured to use the power supply voltage signal as the gate voltage signal of the mirror transistor when the selection signal indicates that the level of the first input is not level-inverted;

8. The test circuit of claim 6, wherein when the mirror transistor is an NMOS transistor, the other data input of the first selection circuit is grounded, the first selection circuit further configured to control the gate of the mirror transistor to be grounded when the selection signal indicates that no level inversion occurs at the level of the first input;

9. The test circuit of claim 4, wherein the test circuit further comprises: the input end of the second delay circuit and the enabling input end of the mirror image control circuit are connected with the same enabling signal, the second delay circuit is used for delaying the received enabling signal for a preset time and outputting the enabling signal to the enabling input end of the ring oscillation circuit through the output end of the second delay circuit, and the second delay circuit is used for controlling the oscillation signal generated by the ring oscillation circuit to lag behind the mirror image control signal generated by the mirror image control circuit.

10. The test circuit of claim 9, wherein the second delay circuit comprises an even number of cascaded inverters.

11. The test circuit according to claim 7, wherein the selection signal generating circuit includes a nor gate and an inverter circuit, two input terminals of the nor gate are connected to the second input terminal of the second inverting unit and the output terminal of the inverter circuit, respectively, and the input terminal of the inverter circuit is connected to the second input terminal of the second inverting unit, and when the selection signal is a high level signal, the level of the first input terminal is instructed to be inverted from a high level to a low level.

12. The test circuit according to claim 8, wherein the selection signal generating circuit includes a nand gate and an inverter circuit, two input terminals of the nand gate are connected to the second input terminal of the second inverting unit and the output terminal of the inverter circuit, respectively, and an input terminal of the inverter circuit is connected to the second input terminal of the second inverting unit, and when the selection signal is a low level signal, the level of the first input terminal is instructed to be inverted from low level to high level.

13. A test circuit according to claim 11 or 12, wherein the inverting circuit comprises an odd number of cascaded inverters.

14. The test circuit of claim 9, wherein the first inverting unit of the first stage comprises a first nand gate, the remaining first inverting units comprise first nand gates, two inputs of the first nand gate are respectively used as the enable input of the ring oscillator circuit and a first input of the first inverting unit, an output of the first nand gate is used as a first output of the first inverting unit, and an input and an output of the first nand gate are respectively used as a first input and a first output of the corresponding first inverting unit.

15. The test circuit of claim 14, wherein the second inverting unit of the first stage comprises a second nand gate, the remaining second inverting units comprise second nand gates, two inputs of the second nand gate are respectively used as the enable input of the mirror control circuit and a second input of the second inverting unit, an output of the second nand gate is used as a second output of the second inverting unit, and an input and an output of the second nand gate are respectively used as a second input and a second output of the corresponding second inverting unit.

16. The test circuit of claim 15, wherein the first and second not gates each comprise first and second transistors of different types, the power input of the first nand gate and the source of the first transistor each having access to the same power voltage signal;

17. The test circuit of any one of claims 4 to 12, wherein when the mirror transistor is a PMOS transistor, a source of the mirror transistor and the first inverting unit are connected to a supply voltage signal having the same magnitude; when the mirror transistor is an NMOS transistor, the source of the mirror transistor is grounded.

18. The test circuit of claim 6, wherein the first delay circuit comprises an odd number of cascaded inverters.

19. A test system comprising an enable signal generating circuit and the test circuit of any one of claims 1 to 18, an output of the enable signal generating circuit being connected to the test circuit, the enable signal generated by the enable signal generating circuit being used to drive the test circuit to operate.

20. The test system of claim 19, further comprising a frequency dividing element having an input coupled to one of the first outputs of the ring oscillator of the test circuit and an output buffer element coupled to the output of the frequency dividing element.

21. A test method for the test system of claim 19 or 20, the test method comprising:

driving the test circuit to operate by an enable signal;

22. A semiconductor device comprising the test system of claim 19 or 20.