CN117352548A - LDMOS device and preparation method thereof - Google Patents

LDMOS device and preparation method thereof Download PDF

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Publication number
CN117352548A
CN117352548A CN202311308771.2A CN202311308771A CN117352548A CN 117352548 A CN117352548 A CN 117352548A CN 202311308771 A CN202311308771 A CN 202311308771A CN 117352548 A CN117352548 A CN 117352548A
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oxide
drift region
film
ldmos device
region
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祁金伟
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Suzhou Huatai Electronics Co Ltd
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Suzhou Huatai Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The embodiment of the application provides an LDMOS device and a preparation method thereof. The LDMOS device comprises: a substrate; an epitaxial layer formed over the substrate; the first doping type functional region and the drain region are formed in the epitaxial layer at intervals, and the part of the epitaxial layer between the first doping type functional region and the drain region is a drift region; an oxide first film formed over the drift region; the groove is formed downwards from the oxide first film and enters the drift region, and the length direction of the groove is consistent with the length direction of the drift region; oxide second films formed at the bottom and the side walls of the grooves, and the oxide second films form a hollow structure at the bottom and the side walls of the grooves; and the vertical layer of polysilicon is filled in the hollow structure of the oxide second film, is used as a field plate and is arranged in a floating manner. The embodiment of the application solves the technical problem of high on-resistance of the traditional LDMOS device.

Description

LDMOS device and preparation method thereof
Technical Field
The application relates to the technical field of semiconductors, in particular to an LDMOS device and a preparation method thereof.
Background
The existing super junction LDMOS device basically adopts a to-be-masked implantation technology (self-aligned mask implantation). P-type doping is injected into the drift region of the device to form a P-Picllar (P-type column region), and the doping concentration of the P type and the N type is adjusted according to the requirement. The low doped N-type drift region of the conventional LDMOS is replaced by a set of alternately arranged N-type and P-type column regions, as shown in fig. 1, a substrate 1, an N-drift region 4, a P-type column region 5,N, a P-type body region 7, a body contact region 8, a source contact region 9, a source metal 10, a gate polysilicon 11, a gate oxide 12, a drain metal 13, and a drain contact region 14. In theory, the super junction LDMOS device can obtain a very high breakdown voltage, while the highly doped N-type column region can obtain a very low on-resistance, because of the charge compensation (mutual depletion) between the P-type column region 5 and the N-type column region 6, which can be considered approximately one intrinsic type. Therefore, the super junction device can achieve a good balance between breakdown voltage and on-resistance.
In general, the P-N P-Pillar (i.e., P-type Pillar region 5 and N-type Pillar region 6) width of the super junction is approximately 1:1, but P-Pillar (P-type Pillar region 5) is not conductive and occupies chip area, thus requiring a reduction in P-Pillar (P-type Pillar region 5) width.
The super junction of the existing LDMOS device has two preparation schemes:
1. and injecting PN junction alternating arrays of the P-type column region and the N-type column region. With the implantation to form P-pilar, the implanted Boron diffuses laterally, and the mask width used for ion implantation is limited by the lithographic capability, so that the P-pilar width is difficult to reduce.
2. And etching the deep groove and epitaxially filling to form a PN junction alternating array of the P-type column region and the N-type column region. The super junction of the conventional LDMOS device can lead to P-type diffusion due to a thermal process, the width of a P-type column region is larger, and the on-resistance is high.
Therefore, the on-resistance of the conventional LDMOS device is high, which is a technical problem that needs to be solved by those skilled in the art.
The above information disclosed in the background section is only for enhancement of understanding of the background of the application and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.
Disclosure of Invention
The embodiment of the application provides an LDMOS device and a preparation method thereof, which are used for solving the technical problem of high on-resistance of the traditional LDMOS device.
According to a first aspect of an embodiment of the present application, there is provided an LDMOS device, comprising:
a substrate of a first doping type;
an epitaxial layer of a second doping type formed over the substrate;
the first doping type functional region and the drain region are formed in the epitaxial layer at intervals, and the part of the epitaxial layer between the first doping type functional region and the drain region is a drift region;
an oxide first film formed over the drift region;
the groove is formed downwards from the oxide first film and enters the drift region, and the length direction of the groove is consistent with the length direction of the drift region;
oxide second films formed at the bottom and the side walls of the grooves, and the oxide second films are surrounded into a hollow structure at the bottom and the side walls of the grooves;
and the vertical layer of polysilicon is filled in the hollow structure of the oxide second film, is used as a field plate and is arranged in a floating manner.
According to a second aspect of the embodiments of the present application, there is provided a method for manufacturing an LDMOS device, including the steps of:
by adopting the technical scheme, the embodiment of the application has the following technical effects:
forming an epitaxial layer of a second doping type over the substrate;
forming first doping type functional regions and drain regions which are arranged at intervals in the epitaxial layer, wherein the part of the epitaxial layer between the first doping type functional regions and the drain regions is a drift region;
forming an oxide first film over the drift region;
forming a groove through a groove etching process after gluing and developing on the oxide first film, wherein the length direction of the groove is consistent with the length direction of the drift region;
forming an oxide second film at the bottom and the side wall of the groove, wherein the oxide second film surrounds a hollow structure at the bottom and the side wall of the groove;
filling the hollow structure of the oxide second film to form a polysilicon vertical layer; the vertical layer of polycrystalline silicon is used as a field plate, and the field plate is arranged in a floating mode.
In the LDMOS device of the embodiment of the application, the trench 11 is located in the drift region, and the length direction of the trench 11 is consistent with the length direction of the drift region. The field plate is positioned in the groove and is arranged in a floating mode. In this way, in the length direction of the drift region (corresponding to the X direction in fig. 2), the field plate can be introduced to level the electric field at the PN junction formed by the first doping type functional region and the drift region through the field plate, so that the fringe electric field at the PN junction of the first doping type functional region and the drift region is reduced, and the voltage withstand capability of the LDMOS device in the length direction of the drift region is higher. When the device length is shortened, the current path of the device in the drift region length direction is shortened while the same withstand voltage is obtained. In the thickness direction of the drift region (corresponding to the Y direction in FIG. 2), the electric field of the drift region is leveled, and the voltage withstand capability of the LDMOS device in the thickness direction of the drift region is effectively improved. Therefore, in order to achieve the same voltage withstand value, the LDMOS device of the embodiment of the application has smaller dimensions in the length direction and the thickness direction of the drift region, and the LDMOS device has smaller area, so that the on-resistance is smaller. And the width of the field plate (corresponding to the Z direction in fig. 2) is smaller, so that the conductivity of the drift region is higher, and the on-resistance is further reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
fig. 1 is a schematic diagram of a prior art superjunction LDMOS device;
fig. 2 is a schematic diagram of an LDMOS device (oxide first film 10b is not shown) according to an embodiment of the present application;
FIG. 3 is a cross-sectional view of A-A' of FIG. 2;
FIG. 4 is a cross-sectional view in the direction B-B' of FIG. 2;
fig. 5 is a schematic diagram illustrating a completion step S2 of the method for manufacturing an LDMOS device according to an embodiment of the present application;
fig. 6 is a schematic diagram illustrating a completion step S3 of the method for manufacturing an LDMOS device according to an embodiment of the present application;
fig. 7 is a schematic diagram illustrating a completion step S4 of the method for manufacturing an LDMOS device according to an embodiment of the present application;
fig. 8 is a schematic diagram illustrating a completion step S5 of the method for manufacturing an LDMOS device according to the embodiment of the application;
fig. 9 is a schematic diagram illustrating a completion step S6 of the method for manufacturing an LDMOS device according to an embodiment of the present application.
Reference numerals:
the background technology is as follows:
a substrate 1, an N drift region 4, a P-type column region 5,N type column region 6, a P-type body region 7, a body region contact region 8, a source contact region 9, a source metal 10, a gate polysilicon 11, a gate oxide layer 12, a drain metal 13 and a drain contact region 14;
in this application:
the semiconductor device comprises a substrate 1, an epitaxial layer 2, a first doping type source region 4, a second doping type source region 5, a drain region 6, a gate oxide layer 7, a gate electrode 8, a polysilicon vertical layer 91, a polysilicon lateral layer 92, an oxide first film 10b, an oxide second film 10a, a trench 11, a source metal 12 and a drain metal 13.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following detailed description of exemplary embodiments of the present application is given with reference to the accompanying drawings, and it is apparent that the described embodiments are only some of the embodiments of the present application and not exhaustive of all the embodiments. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other.
Example 1
Fig. 2 is a schematic diagram of an LDMOS device according to an embodiment of the present application, fig. 2 does not show the oxide first film 10b, and only one trench is schematically shown.
As shown in fig. 2, 3, 4 and 5, the LDMOS device of the embodiment of the application includes:
a substrate 1 of a first doping type;
an epitaxial layer 2 of a second doping type formed over the substrate 1;
the epitaxial layer 2 is formed in the epitaxial layer and is provided with a first doping type functional region and a first doping type drain region 6 at intervals in sequence, and the part of the epitaxial layer between the first doping type functional region and the drain region 6 is a drift region;
an oxide first film 10b formed over the drift region;
a trench 11, wherein the trench 11 is formed downwards from the oxide first film 10b and enters the drift region, and the length direction of the trench 11 is consistent with the length direction of the drift region;
oxide second film 10a formed at the bottom and side walls of the trench, and oxide second film 10a enclosing hollow structure at the bottom and side walls of the trench;
the vertical polysilicon layer 91 is filled in the hollow structure of the oxide second film 10a, the vertical polysilicon layer 91 is used as a field plate, and the field plate is arranged in a floating manner.
In the LDMOS device of the embodiment of the application, the trench 11 is located in the drift region, and the length direction of the trench 11 is consistent with the length direction of the drift region. The field plate is positioned in the groove and is arranged in a floating mode. In this way, in the length direction of the drift region (corresponding to the X direction in fig. 2), the electric field at the PN junction formed by the first doping type functional region and the drift region can be flattened by the field plate by introducing the field plate, so that the LDMOS device has high voltage withstand capability in the length direction of the drift region. When the device length is shortened, the current path of the device in the drift region length direction is shortened while the same withstand voltage is obtained. In the thickness direction of the drift region (corresponding to the Y direction in FIG. 2), the electric field of the drift region is leveled, and the voltage withstand capability of the LDMOS device in the thickness direction of the drift region is effectively improved. Therefore, in order to achieve the same voltage withstand value, the LDMOS device of the embodiment of the application has smaller dimensions in the length direction and the thickness direction of the drift region, and the LDMOS device has smaller area, so that the on-resistance is smaller. And the width of the field plate (corresponding to the Z direction in fig. 2) is smaller, so that the conductivity of the drift region is higher, and the on-resistance is further reduced.
The traditional LDMOS only has depletion in the X direction, the depletion in the Y direction is incomplete, and the electric field value is small. The LDMOS device of the embodiment of the application realizes two-dimensional depletion, namely depletion in the X direction, depletion in the Y direction, and larger electric field value in the Y direction, and is beneficial to improving BV.
In the technical scheme in the background art, the P-type column region has a diffusion phenomenon, and in order to realize charge balance, an N-type column region is generally: the ratio of P-type column regions is 1:1.
in the embodiment of the present application, compared with the superjunction, the field plate has no diffusion phenomenon, and the width of the drift region and the width L of the field plate Field plate The ratio of the sum is more than or equal to 5, so that the utilization rate of the drift region is improved.
In implementation, as shown in fig. 4, the trenches 11 are plural, and each trench 11 is disposed at intervals along the width direction of the drift region, and the vertical polysilicon layer is higher than the upper surface of the oxide first film 10b;
the LDMOS device further comprises:
as shown in fig. 4, a polysilicon lateral layer 92 is formed over the oxide third film 10c and the field plates, the polysilicon lateral layer 92 being connected to each of the field plates, respectively.
In this way, the polysilicon lateral layer 92 connects the field plates together so that the electric field is more uniformly dispersed across the width of the drift region.
Specifically, the polysilicon lateral layer 92 is provided floating. I.e., the polysilicon lateral layer 92 is not grounded nor connected to a voltage, thereby allowing the individual field plates to float.
In practice, as shown in FIG. 2, the drift region has a width L Drift region Width L of the field plate Field plate The ratio of the sum is more than or equal to 5:1.
In implementations, the depth of the trench is less than the depth of the drift region.
In implementation, the ratio of the depth to the width of the groove is less than or equal to 100:1.
In practice, the width of the trench 10 is 0.05 μm or more and 0.5 μm or less.
In practice, as shown in fig. 2 and 3, the first doping type functional region is a body region 3 of a first doping type;
the LDMOS device further comprises:
a first doping type source region 4;
a second doping type source region 5;
a gate oxide layer 7;
a gate electrode 8;
a source metal 12;
drain metal 13.
In implementation, the epitaxial layer 2 is an N-type epitaxial layer 2, and the substrate 1 is a P-type substrate 1.
Example two
The preparation method of the LDMOS device is used for preparing the LDMOS device in the first embodiment. The preparation method of the LDMOS device comprises the following steps:
forming an epitaxial layer 2 of a second doping type over the substrate 1;
forming first doping type functional regions and drain regions 6 which are arranged at intervals in the epitaxial layer 2, wherein the part of the epitaxial layer between the first doping type functional regions and the drain regions 6 is a drift region;
forming an oxide first film 10b over the drift region;
after the first oxide film 10b is coated with glue and developed, forming a plurality of deep trenches 11 which are distributed at intervals through a trench etching process, wherein the length direction of the trenches 11 is consistent with the length direction of a drift region;
forming an oxide second film 10a at the bottom and the side wall of the groove, wherein the oxide second film 10a surrounds a hollow structure at the bottom and the side wall of the groove;
forming a polysilicon vertical layer 91 in the hollow structure filled with the oxide second film 10 a; wherein, the vertical polysilicon layer 91 is used as a field plate, and the field plate is arranged in a floating manner.
In practice, the trenches 11 are plural, and each trench 11 is disposed at intervals along the width direction of the drift region, and the vertical polysilicon layer is higher than the upper surface of the oxide first film 10b;
the preparation method of the LDMOS device further comprises the following steps:
a polysilicon lateral layer 92 is formed over the oxide third film 10c and the field plates, wherein the polysilicon lateral layer 92 is connected to each of the field plates.
In practice, the width L of the drift region Drift region Width L of the field plate Field plate The ratio of the sum is more than or equal to 5:1.
Specifically, the depth of the groove is smaller than the depth of the drift region.
Specifically, the ratio of the depth to the width of the groove is less than or equal to 100:1.
Specifically, the width of the trench 10 is 0.05 μm or more and 0.5 μm or less.
Specifically, the epitaxial layer is an N-type epitaxial layer, and the substrate is a P-type substrate.
Specifically, the trench 10 is formed by a dry etching technique.
Specifically, the oxide first thin film 10b and the oxide second thin film 10a are formed by deposition by an ALD process.
Specifically, the first doping type functional region is a body region 3 of a first doping type;
the preparation method of the LDMOS device further comprises the following steps:
forming a first doping type source region 4;
forming a second doping type source region 5;
forming a gate oxide layer 7;
forming a gate electrode 8;
forming a source metal 12;
drain metal 13 is formed.
The following describes the preparation method of the LDMOS device according to the preparation sequence:
step S1: providing a substrate 1 with a first doping type, and forming an epitaxial layer 2 with a second doping type on the surface of the substrate 1;
step S2: performing Body lithography, implantation and annealing on the active region to form a Body region 3, wherein the ion implantation type of the Body region 3 is different from that of the second doping type material; as shown in fig. 5;
step S3: performing photoetching, ion implantation and push-well to form a second doping type source region 5 and a drain region 6 of the MOS, wherein the ion implantation type of the second doping type source region 5 and the drain region 6 is the same as the ion type of the second doping type material, and then forming a first doping type source region 4; as shown in fig. 6;
step S4: depositing an oxide first film 10b above the drift region, gluing and developing, and forming a plurality of grooves 11 which are distributed at intervals through a groove etching process; as shown in fig. 7;
step S5: oxidizing the device, forming an oxide second film 10a on the bottom and the side wall of the trench 11, and forming a gate oxide layer 7; as shown in fig. 8;
step S6: poly polysilicon with a certain thickness is deposited on the surface of the device, then polysilicon between a source electrode area, a drain electrode area, the right side of the gate and the left side area of the field plate is etched, polysilicon above the gate oxide layer 7 forms a gate electrode 8, and a medium Poly polysilicon is filled in the groove 11 to form a polysilicon vertical layer 91, so that the field plate is formed. And all field plates are connected together by a polysilicon lateral layer 92 to form an equipotential; as shown in fig. 9;
step S7: an oxide third film 10c is deposited on the surface of the device, holes are drilled in the source region and the drain region, a metal layer is deposited, and the source metal 12 and the drain metal 13 are respectively formed by etching.
ALD (Atomic Layer Deposition) is a common thin film preparation technique for controlling the growth of thin films on the nanometer scale. It is a method of growing thin film layer by layer, by alternately introducing a chemical precursor and a reactant, the thickness and composition of the thin film are precisely controlled by atomic layer.
In ALD deposition, a layer of a chemical precursor, such as a metal-organic compound, is adsorbed onto the surface of a substrate, and then the chemical precursor is decomposed by introducing a reactant, such as a gas-phase or liquid-phase oxidizing agent, to form a thin film. This process may be repeated step by step, each step forming an atomic layer of film, until the desired film thickness is achieved. Repeated ALD cycles may achieve high precision and consistent film growth.
RIE (Reactive Ion Etching) is a common dry etching technique used to prepare micro-nanostructures and patterning. It uses reactive ions generated in a high vacuum environment to etch the material surface.
In the description of the present application and its embodiments, it should be understood that the terms "top," "bottom," "height," and the like indicate an orientation or positional relationship based on that shown in the drawings, and are merely for convenience of description and to simplify the description, rather than to indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present application.
In this application and in its embodiments, the terms "disposed," "mounted," "connected," "secured," and the like are to be construed broadly and include, for example, either permanently connected, removably connected, or integrally formed, unless otherwise explicitly stated and defined as such; the device can be mechanically connected, electrically connected and communicated; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
In this application and in its embodiments, unless expressly stated or limited otherwise, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is less level than the second feature.
The above disclosure provides many different embodiments or examples for implementing different structures of the present application. The components and arrangements of specific examples are described above in order to simplify the disclosure of this application. Of course, they are merely examples and are not intended to limit the present application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not in themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize the application of other processes and/or the use of other materials.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims (10)

1. An LDMOS device, comprising:
a substrate (1) of a first doping type;
an epitaxial layer (2) of a second doping type formed on the substrate (1);
the first doping type functional region and the drain region (6) are formed in the epitaxial layer (2) at intervals, and the part of the epitaxial layer between the first doping type functional region and the drain region (6) is a drift region;
an oxide first film (10 b) formed over the drift region;
a trench (11), wherein the trench (11) is formed downwards from the oxide first film (10 b) and enters the drift region, and the length direction of the trench (11) is consistent with the length direction of the drift region;
an oxide second film (10 a) formed at the bottom and the side wall of the trench, and the oxide second film (10 a) encloses a hollow structure at the bottom and the side wall of the trench;
and the vertical polysilicon layer (91) is filled in the hollow structure of the oxide second film (10 a), the vertical polysilicon layer (91) is used as a field plate, and the field plate is arranged in a floating way.
2. The LDMOS device according to claim 1, wherein the trenches (11) are plural, and each trench (11) is arranged at intervals in a width direction of the drift region, the polysilicon vertical layer being higher than an upper surface of the oxide first film (10 b);
the LDMOS device further comprises:
and a polysilicon lateral layer (92) formed on the oxide third film (10 c) and the field plates, wherein the polysilicon lateral layer (92) is respectively connected with each field plate.
3. The LDMOS device of claim 2, wherein the drift region has a width L Drift region Width L of the field plate Field plate The ratio of the sum is more than or equal to 5:1.
4. The LDMOS device of claim 2, wherein a depth of the trench is less than a depth of the drift region.
5. The LDMOS device of claim 2, wherein a ratio of a depth to a width of the trench is 100:1 or less.
6. The LDMOS device according to claim 2, wherein the width of the trench (10) is 0.05 μm or more and 0.5 μm or less.
7. The LDMOS device of claim 2, wherein the epitaxial layer is an N-type epitaxial layer and the substrate is a P-type substrate.
8. The preparation method of the LDMOS device is characterized by comprising the following steps of:
forming an epitaxial layer (2) of a second doping type over the substrate (1);
forming first doping type functional regions and drain regions (6) which are arranged at intervals in the epitaxial layer (2), wherein the part of the epitaxial layer between the first doping type functional regions and the drain regions (6) is a drift region;
forming an oxide first film (10 b) over the drift region;
after the first oxide film (10 b) is coated with glue and developed, forming a groove (11) through a groove etching process, wherein the length direction of the groove (11) is consistent with the length direction of a drift region;
forming an oxide second film (10 a) at the bottom and the side wall of the groove, wherein the oxide second film (10 a) surrounds a hollow structure at the bottom and the side wall of the groove;
forming a polysilicon vertical layer (91) in the hollow structure filled with the oxide second film (10 a); the polysilicon vertical layer (91) is used as a field plate, and the field plate is arranged in a floating mode.
9. The method for manufacturing the LDMOS device according to claim 8, wherein the plurality of trenches (11) are provided, each trench (11) is provided at an interval along a width direction of the drift region, and the polysilicon vertical layer is higher than an upper surface of the oxide first film (10 b);
the preparation method of the LDMOS device further comprises the following steps:
a polysilicon lateral layer (92) is formed over the oxide third film (10 c) and the field plates, wherein the polysilicon lateral layer (92) is connected to each of the field plates.
10. The method of manufacturing an LDMOS device of claim 9, wherein the width L of the drift region Drift region Width L of the field plate Field plate The ratio of the sum is more than or equal to 5:1.
CN202311308771.2A 2023-10-10 2023-10-10 LDMOS device and preparation method thereof Pending CN117352548A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117976724A (en) * 2024-04-02 2024-05-03 华南理工大学 LDMOS device and preparation method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117976724A (en) * 2024-04-02 2024-05-03 华南理工大学 LDMOS device and preparation method

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