CN117348761A - Capacitance detection circuit and touch detection device - Google Patents
Capacitance detection circuit and touch detection device Download PDFInfo
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- CN117348761A CN117348761A CN202311250334.XA CN202311250334A CN117348761A CN 117348761 A CN117348761 A CN 117348761A CN 202311250334 A CN202311250334 A CN 202311250334A CN 117348761 A CN117348761 A CN 117348761A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
- G01R19/16557—Logic probes, i.e. circuits indicating logic state (high, low, O)
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
- G01R27/2605—Measuring capacitance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/033—Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor
- G06F3/0354—Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor with detection of 2D relative movements between the device, or an operating part thereof, and a plane or surface, e.g. 2D mice, trackballs, pens or pucks
- G06F3/03547—Touch pads, in which fingers can move on a surface
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0416—Control or interface arrangements specially adapted for digitisers
- G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
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Abstract
The application relates to a capacitance detection circuit and touch detection equipment. The capacitance detection circuit is connected with a first touch pad and a second touch pad in the peripheral circuit; the circuit comprises a coarse adjustment capacitor array, a fine adjustment capacitor array, a logic circuit and a comparator; the comparator compares the voltage difference between the first touch panel and the second touch panel and generates and outputs a first comparison signal to the logic circuit; the logic circuit generates a first control signal according to the first comparison signal and controls the coarse adjustment capacitor array to work according to the first control signal so as to adjust the equivalent capacitance difference between the first touch panel and the second touch panel to be reduced to a target range through the coarse adjustment capacitor array; the logic circuit is further configured to obtain a second comparison signal generated by the comparator, generate a second control signal according to the second comparison signal, and control the fine-tuning capacitor array to sample a current equivalent capacitance difference between the first touch pad and the second touch pad according to the second control signal. The adoption of the capacitance detection circuit can improve the sensitivity of touch detection.
Description
Technical Field
The present disclosure relates to the field of touch detection technologies, and in particular, to a capacitance detection circuit and a touch detection device.
Background
The capacitive touch key is widely applied to various fields such as automobiles, household appliances, security protection and the like. The detection technology widely adopted by the touch keys at present is a touch key detection technology based on RC ring vibration, which mainly converts capacitance change into digital signals for touch detection, so that the detection technology is also called as a capacitance-to-digital converter.
However, the touch key detection technology based on RC ring vibration has the problem of low detection sensitivity.
Disclosure of Invention
Based on this, it is necessary to provide a capacitance detection circuit and a touch detection apparatus that enhance the sensitivity of touch detection.
In a first aspect, the present application provides a capacitance detection circuit connected to a first touch pad and a second touch pad in a peripheral circuit; the capacitance detection circuit comprises a coarse capacitance array, a fine capacitance array, a logic circuit and a comparator; the comparator is used for comparing the voltage difference between the first touch panel and the second touch panel, generating a first comparison signal according to the comparison result and outputting the first comparison signal to the logic circuit; the logic circuit is used for generating a first control signal according to the first comparison signal and controlling the coarse adjustment capacitor array to work according to the first control signal so as to adjust the equivalent capacitance difference between the first touch panel and the second touch panel to be reduced to a target range through the coarse adjustment capacitor array; and under the condition that the equivalent capacitance difference between the first touch panel and the second touch panel is reduced to the target range, the logic circuit is further used for acquiring a second comparison signal generated by the comparator, generating a second control signal according to the second comparison signal, and controlling the fine-tuning capacitor array to sample the current equivalent capacitance difference between the first touch panel and the second touch panel according to the second control signal.
In one embodiment, the peripheral circuit further includes a first parasitic capacitance circuit corresponding to the first touch pad and a second parasitic capacitance circuit corresponding to the second touch pad; the capacitance detection circuit also comprises a first bridge circuit connected with the first touch pad and a second bridge circuit connected with the second touch pad; the coarse tuning capacitor array comprises a plurality of first switch arrays; the first control signal includes M first single bit signals; the logic circuit is specifically used for: according to a first clock signal input by an external controller, controlling the first parasitic capacitance circuit, the second parasitic capacitance circuit, the first bridge circuit and the second bridge circuit to form a bridge, sequentially acquiring M first single-bit signals according to the first comparison signal based on successive approximation logic, and sequentially controlling each first switch array in the coarse adjustment capacitance array to work according to the M first single-bit signals; wherein, the value of M is the same as the number of the first switch arrays.
In one embodiment, the second control signal comprises N second single bit signals; the fine tuning capacitor array comprises a first fine tuning capacitor array connected with the first touch pad and a second fine tuning capacitor array connected with the second touch pad; the first fine-tuning capacitor array comprises first capacitors respectively connected with N second single-bit signals; the second fine-tuning capacitor array comprises second capacitors connected with N third single-bit signals opposite to the N second single-bit signals respectively; the logic circuit is specifically used for: according to a second clock signal input by an external controller, based on successive approximation logic, N second single-bit signals are successively acquired according to the second comparison signals, N third single-bit signals are generated, the grounding or power supply of each first capacitor is sequentially controlled according to the N second single-bit signals, and the grounding or power supply of each second capacitor is sequentially controlled according to the N third single-bit signals.
In one embodiment, the logic circuit is coupled to an external controller; the logic circuit is specifically used for: and under the condition that the second clock signal is ended, outputting the N second single-bit signals to an external controller so that the external controller calculates the current equivalent capacitance difference according to the N second single-bit signals.
In one embodiment, the capacitance detection circuit further includes an offset compensation capacitance circuit, the offset compensation capacitance circuit being connected to the logic circuit; the logic circuit is further configured to: and controlling the offset compensation capacitance circuit to be connected with the first touch pad or the second touch pad according to the highest bit of the first control signal.
In one embodiment, the offset compensation capacitor circuit includes a third capacitor, and a capacitance value of the third capacitor is greater than or equal to a capacitance value of a parasitic capacitor generated by the coarse tuning capacitor array.
In one embodiment, the offset compensation capacitor circuit further includes a second switch and a third switch, the third capacitor is connected in parallel with the second switch, one end of the third capacitor is grounded, the other end of the third capacitor is connected with one end of the third switch, and the third switch is connected with the first touch pad or the second touch pad under the control of the highest bit of the first control signal.
In one embodiment, the most significant first switch array in the coarse tuning capacitor array includes two first switches, and the two first switches in the most significant first switch array are controlled by the most significant first single bit signal of the first control signal; the other first switch arrays in the coarse adjustment capacitor array respectively comprise two first switches and a fourth capacitor, and the two first switches in the other first switch arrays are sequentially controlled by other bit first single-bit signals of the first control signal.
In one embodiment, one end of each other first switch array is grounded, and the other end of each other first switch array is connected with the highest first switch array; for each other first switch array, the fourth capacitor is connected in parallel with the first switch in the other first switch arrays, one end of the fourth capacitor is grounded, the other end of the fourth capacitor is connected with one end of the second first switch, and the other end of the second first switch is connected with the highest first switch array.
In a second aspect, the present application also provides a touch detection device comprising a peripheral circuit as described in any one of the above aspects and a capacitance detection circuit.
In the capacitance detection circuit and the touch detection device, the capacitance detection circuit is connected with the first touch panel and the second touch panel in the peripheral circuit; the capacitance detection circuit comprises a coarse capacitance array, a fine capacitance array, a logic circuit and a comparator; the comparator is used for comparing the voltage difference between the first touch panel and the second touch panel, generating a first comparison signal according to the comparison result and outputting the first comparison signal to the logic circuit; the logic circuit is used for generating a first control signal according to the first comparison signal, and controlling the coarse adjustment capacitor array to work according to the first control signal so as to adjust the equivalent capacitance difference between the first touch panel and the second touch panel to be reduced to a target range through the coarse adjustment capacitor array; and under the condition that the equivalent capacitance difference between the first touch panel and the second touch panel is reduced to a target range, the logic circuit is further used for acquiring a second comparison signal generated by the comparator, generating a second control signal according to the second comparison signal, and controlling the fine-tuning capacitor array to sample the current equivalent capacitance difference between the first touch panel and the second touch panel according to the second control signal. Therefore, based on the combination of the coarse adjustment capacitance array and the fine adjustment capacitance array, the equivalent capacitance difference between the first touch panel and the second touch panel is reduced to the target range through the coarse adjustment capacitance array, and then when the fine adjustment capacitance array samples the current equivalent capacitance difference between the first touch panel and the second touch panel, the current equivalent capacitance difference required to be sampled is small, so that the sampling can be realized through a small data bit width, the sampling time is shortened, and the sensitivity of the detection process is improved. And because the equivalent capacitance difference between the first touch pad and the second touch pad is reduced to the target range after coarse adjustment, the working frequency of the coarse adjustment capacitance array is far smaller than that of the fine adjustment capacitance array, and the fine adjustment capacitance array is used for sampling most of the time, so that the power consumption of the capacitance detection circuit is effectively saved.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a capacitive sensing circuit according to an embodiment;
FIG. 2 is a schematic diagram of another capacitance detection circuit according to an embodiment;
FIG. 3 is a schematic diagram of another capacitance detection circuit according to an embodiment;
FIG. 4 is a schematic diagram of a portion of a coarse tuning calibration process according to an embodiment;
FIG. 5 is a schematic diagram of a coarse tuning capacitor array according to an embodiment;
FIG. 6 is a schematic diagram of another capacitance detection circuit according to an embodiment;
FIG. 7 is a schematic diagram of a offset compensation capacitor circuit according to an embodiment;
FIG. 8 is a schematic diagram of another offset compensation capacitor circuit according to an embodiment;
FIG. 9 is a schematic diagram of another capacitance detection circuit according to an embodiment;
FIG. 10 is a schematic diagram of a fine-tuning capacitor array according to an embodiment;
FIG. 11 is a schematic diagram of another capacitance detection circuit according to an embodiment;
FIG. 12 is a waveform diagram illustrating a fine-tuning calibration process according to an embodiment.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that the terms "first," "second," and the like, as used herein, may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the present application. Both the first resistor and the second resistor are resistors, but they are not the same resistor.
It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.
It is understood that "at least one" means one or more and "a plurality" means two or more. "at least part of an element" means part or all of the element.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.
The capacitive touch key is widely applied to the fields of automobiles, household appliances, security protection and the like. Compared with the physical key, the key has the advantages of smoothness, beautiful appearance, easy cleaning, long service life and the like. The principle of the capacitive touch key is to detect the equivalent capacitance between an internal probe and the key surface, and once the change amount of the equivalent capacitance is detected to exceed the set threshold value, the existence of the finger press is judged. From a technical perspective, most capacitive touch keys in the industry today are based on two principles.
The first is an RC ring oscillator configuration, i.e., the resonant frequency of the ring oscillator is inversely proportional to the magnitude of the touch key equivalent capacitance. If the finger touches the key, the resonance frequency of the ring oscillator is reduced, the resonance frequency of the ring oscillator is digitized through the on-chip reference frequency, and whether the finger touches or not can be judged by setting a proper threshold value. However, this method has disadvantages of low determination speed, need of a reference clock, and poor common mode interference resistance, and thus, detection sensitivity thereof is generally low. High performance systems employing capacitive touch keys generally require some resistance to common mode interference, and are now capable of filtering alternating current interference signals between human body ground potential and circuit ground potential.
The basic analog circuit of the capacitive touch key with almost all structures cannot filter alternating current interference signals input by fingers, because the interference signals are input by a single end, namely are homologous to target signals, the system cannot directly distinguish the target signals and the interference signals, high-frequency interference signals can be filtered out only by a digital filter at a later stage, the low-frequency target signals are reserved for implementation, and the analog circuit has a relatively difficult implementation of such low-frequency cutoff frequency. The reason that the common-mode interference resistance of the RC ring-vibration touch key circuit is poor is that the RC ring-vibration touch key circuit does not have a sampling clock to control sampling time sequence, and if stronger interference exists at the moment of overturning the comparator, the comparator is easy to generate error clock signals due to multiple times of false overturning. Another problem with RC ring structures is that they are sensitive to parasitic resistance of the wire, and even when the comparator is flipped, current flows through the load capacitance, and thus the voltage drop due to parasitic resistance introduces errors. This is even more problematic because the body resistance is large and there is also a large parasitic resistance between the body's ground and the circuit's ground. In summary, the touch key detection technology based on RC ring vibration is not suitable for applications with certain requirements on common-mode interference resistance, and even if digital filtering is adopted, alternating-current interference signals cannot be filtered.
The second is a touch key detection technology based on charge sharing, i.e. a fixed frequency clock is used to periodically charge-share a periodically charged touch key capacitor and a large integral capacitor, so that the charge of the touch capacitor is periodically transferred to the large integral capacitor, the voltage of the integral capacitor is gradually increased from zero voltage of the first clock, and when the voltage is increased to a preset valueAnd when one integration period is finished, outputting the corresponding clock accumulation number. Different touch key capacitances correspond to different clock accumulation numbers, so that the change amount of the touch key capacitance can be detected, and whether the finger touches or not is judged. But the disadvantages are more obvious: firstly, a single large integrating capacitor is needed, and one pin is consumed, so that the cost is increased; and secondly, under the condition that only one pin is allowed, multiple touch keys are required for general application, and the multiple touch keys can only share one integrating capacitor, so that the sampling speed is greatly reduced, and the method is not suitable for sampling application with higher speed. In addition, to obtain higher sensitivity, the integral value must be increased, which results in an increase in C only INT Which in turn results in a further reduction in sampling speed.
In view of this, in this embodiment of the present application, a capacitance detection circuit is provided, and a differential structure is adopted, so that the capacitance detection circuit has a better capability of resisting common-mode interference, and can improve sensitivity and accuracy of touch detection, and has high sampling speed and low power consumption.
In one embodiment, as shown in fig. 1, a schematic structural diagram of a capacitance detection circuit provided in an embodiment of the present application is shown. The capacitance detection circuit 100 is connected to a first touch panel 201 and a second touch panel 202 in the peripheral circuit 200; the capacitance detection circuit 100 includes a coarse capacitance array 101, a fine capacitance array 102, a logic circuit 103, and a comparator 104. The comparator 104 is configured to compare a voltage difference between the first touch panel 201 and the second touch panel 202, generate a first comparison signal according to a comparison result, and output the first comparison signal to the logic circuit 103; a logic circuit 103, configured to generate a first control signal according to the first comparison signal, and control the coarse capacitance array 101 to operate according to the first control signal, so as to adjust an equivalent capacitance difference between the first touch pad 201 and the second touch pad 202 to be reduced to a target range through the coarse capacitance array 101; in the case that the equivalent capacitance difference between the first touch pad 201 and the second touch pad 202 is reduced to the target range, the logic circuit 103 is further configured to obtain a second comparison signal generated by the comparator 104, generate a second control signal according to the second comparison signal, and control the fine capacitance array 102 to sample the current equivalent capacitance difference between the first touch pad 201 and the second touch pad 202 according to the second control signal.
Wherein, record C touch1 And C touch2 Is the equivalent capacitance between the finger after the finger touches and the first touch panel 201 and the second touch panel 202, respectively. Typically, only one finger touches, so only one of the capacitances is present, and the other capacitance is zero. It should be noted that touching two touch panels simultaneously also forms a capacitance difference, but it can be considered to be approximately the same as touching only one of them.
C touch1 And C touch2 Is equivalent to GND, is different from the ground V of the circuit SS . Touch capacitance C touch1 Or C touch2 The value of (2) is typically small, especially in the case of a blank touch, possibly as low as 100fF. Note that the name of both touchpads is V S1 And V S2 V is also used in the following description S1 And V S2 The voltages of the two touch pads are characterized separately.
Assuming initially no finger touch, C touch1 And C touch2 Is 0. Voltage value V corresponding to the first touch panel 201 S1 Is to the ground parasitic capacitance C S1 Voltage value V corresponding to the second touch panel 202 S2 Is to the ground parasitic capacitance C S2 It is not possible to be identical, in the extreme case the difference may reach several pF, if V is directly aimed at S1 And V S2 The equivalent capacitance of (2) is sampled, so that high sensitivity is achieved, the large detection range is covered, the data bit width is required to be high, and the single sampling time is long. The reason is that in order to improve the detection sensitivity of the touch capacitance, the minimum value of the unit detection capacitance must be reduced, but V S1 And V S2 The large difference in initial parasitic capacitance in turn requires that the sampling device (e.g. capacitive digitizer CDC) have a detection capability higher than the large difference in parasitic capacitance. In general, a compromise between detection sensitivity and maximum detection range is required, and a high number of conversion bits is required even if possible, which results in a need to consume a large power consumption and a long conversion time. Based on the above, the embodiment of the application adopts a mode of combining coarse adjustment and fine adjustment。
In the rough adjustment stage, a first comparison signal generated as a result of comparison of the voltage difference between the first touch panel 201 and the second touch panel 202 by the comparator 104 is received by the logic circuit 103, starting at a certain point of time of initial power-up or setting. The logic circuit 103 generates a first control signal according to the first comparison signal and sends the first control signal to the coarse tuning capacitor array 101, so as to control the coarse tuning capacitor array 101 to operate through the first control signal.
Initially, in order to enhance the sensitivity of the capacitance detection circuit 100, the coarse capacitance array 101 is connected to one of the first touch pad 201 and the second touch pad 202, and illustratively, the coarse capacitance array 101 is connected to the first touch pad 201 in fig. 1.
In the course of operation of the coarse capacitance array 101, parasitic capacitances C for the two ports S1 And C S2 Sampling and correcting the equivalent capacitance difference between the first touch pad 201 and the second touch pad 202, that is, correcting and shrinking the equivalent capacitance difference between the first touch pad 201 and the second touch pad 202, and locking the data after the correction is completed. After the rough adjustment is finished, the equivalent capacitance can be reduced to the target range under the condition that the finger does not touch. Alternatively, the target range may refer to a range that is half of the maximum range of fine-tuning.
Optionally, the coarse tuning stage, that is, the stage in which the coarse tuning capacitor array 101 operates, is performed without touching any key by a finger, so as to prevent the introduction of correction errors.
In the coarse tuning stage, the fine tuning capacitor array 102 is not operated, and after the coarse tuning stage is completed, the fine tuning capacitor array 102 starts to operate.
The fine capacitive array 102 is connected to both the first touch pad 201 and the second touch pad 202. In the fine tuning stage, the comparator 104 continues to compare the voltage difference between the first touch panel 201 and the second touch panel 202, and at this time generates a second comparison signal according to the comparison result and outputs the second comparison signal to the logic circuit 103. The logic circuit 103 generates a second control signal according to the second comparison signal to control the operation of the fine capacitor array 102 based on the second control signal. That is, the logic circuit 103 logically controls the fine capacitive array 102 to sample the equivalent capacitance value remaining after the coarse adjustment, that is, the current equivalent capacitance value between the first touch pad 201 and the second touch pad 202.
It will be appreciated that the value of the equivalent capacitance difference that needs to be sampled in the fine tuning stage is small because the coarse tuning has already been performed, and therefore a too high number of bits is not required even if a high sampling sensitivity is achieved.
It should be noted that in the embodiment of the present application, the coarse tuning capacitor array 101 may generally be operated only once for a long time, since the purpose is to only switch C S1 And C S2 The equivalent capacitance difference between them is corrected to a smaller range. Coarse tuning correction is not required for a long period of time thereafter, for the following reasons:
after the general system circuit is manufactured, the inherent capacitance C is generated due to the asymmetry of wiring and poor consistency of manufacturing process S1 And C S2 Not all the same, it is appreciated that for a certain system circuit, C is in a standard environment S1 And C S2 Has been fixed from changing. Although it varies with environmental factors such as temperature, humidity, time, etc., C S1 And C S2 The absolute value of (c) will change but the difference between the two will change less and a fine adjustment can be used for correction. Therefore, in the embodiment of the present application, the coarse tuning capacitor array 101 may generally only operate once when the system is started or after a fixed time interval. The fixed time may be, for example, a longer period of time, which may be set by default in the system, or user-defined.
The fine-tuning capacitor array 102 is mainly used for sampling the current equivalent capacitance difference in all the rest time, so that the rest error after coarse tuning correction can be perfectly covered only by 2-3 times larger than the minimum sensitivity of coarse tuning, and the high sampling sensitivity can be achieved without high bit number.
In the embodiment of the present application, the fine-tuning capacitor array 102 is in a real-time working state for sampling V S1 And V S2 Small current equivalent capacitance difference between them, i.e. C caused by finger touch touch1 Or C touch2 A small capacitance increase of (a).
The mode of coarse adjustment and fine adjustment can be adopted in the initial C S1 And C S2 On the basis of larger capacitance difference, the higher sensitivity is realized by using fewer quantized bit numbers, and compared with CDC using only a high-bit single loop, the CDC has low power consumption and high sampling speed.
In the capacitance detection circuit 100 and the touch detection device described above, the capacitance detection circuit 100 is connected to the first touch panel 201 and the second touch panel 202 in the peripheral circuit 200; the capacitance detection circuit 100 includes a coarse capacitance array 101, a fine capacitance array 102, a logic circuit 103, and a comparator 104; the comparator 104 is configured to compare a voltage difference between the first touch panel 201 and the second touch panel 202, generate a first comparison signal according to a comparison result, and output the first comparison signal to the logic circuit 103; a logic circuit 103, configured to generate a first control signal according to the first comparison signal, and control the coarse capacitance array 101 to operate according to the first control signal, so as to adjust an equivalent capacitance difference between the first touch pad 201 and the second touch pad 202 to be reduced to a target range through the coarse capacitance array 101; in the case that the equivalent capacitance difference between the first touch pad 201 and the second touch pad 202 is reduced to the target range, the logic circuit 103 is further configured to obtain a second comparison signal generated by the comparator 104, generate a second control signal according to the second comparison signal, and control the fine capacitance array 102 to sample the current equivalent capacitance difference between the first touch pad 201 and the second touch pad 202 according to the second control signal. In this way, based on the combination of the coarse capacitive array 101 and the fine capacitive array 102, the equivalent capacitance difference between the first touch pad 201 and the second touch pad 202 is reduced to the target range through the coarse capacitive array 101, so when the fine capacitive array 102 samples the current equivalent capacitance difference between the first touch pad 201 and the second touch pad 202, the current equivalent capacitance difference required to be sampled is small, and therefore, the sampling can be realized through a smaller data bit width, the sampling time is reduced, and the sensitivity of the detection process is improved. Moreover, since the equivalent capacitance difference between the first touch pad 201 and the second touch pad 202 is reduced to the target range after the coarse adjustment, the operating frequency of the coarse adjustment capacitive array 101 is far smaller than that of the fine adjustment capacitive array 102, and the fine adjustment capacitive array 102 is used for sampling most of the time, so that the power consumption of the capacitive detection circuit 100 is effectively saved.
The first control signal generated by the logic circuit 103 and other arrangements of the peripheral circuit 200 will be described first.
In one embodiment, as shown in fig. 2, a schematic structural diagram of another capacitance detection circuit provided in an embodiment of the present application is shown. The peripheral circuit 200 further includes a first parasitic capacitance circuit 203 corresponding to the first touch pad 201 and a second parasitic capacitance circuit 204 corresponding to the second touch pad 202; the capacitance detection circuit 100 further includes a first bridge circuit 105 connected to the first touch panel 201 and a second bridge circuit 106 connected to the second touch panel 202; the coarse capacitance array 101 includes a plurality of first switch arrays; the first control signal includes M first single bit signals; logic circuit 103, specifically for: according to a first clock signal CLKS input by an external controller, the first parasitic capacitance circuit 203, the second parasitic capacitance circuit 204, the first bridge circuit 105 and the second bridge circuit 106 are controlled to form a bridge, M first single-bit signals are sequentially obtained according to first comparison signals based on successive approximation logic, and each first switch array in the coarse adjustment capacitance array 101 is sequentially controlled to work according to the M first single-bit signals; wherein, the value of M is the same as the number of the first switch arrays.
Referring to fig. 2, the capacitance C in the first parasitic capacitance circuit 203 S1 One end of (a) is connected to the first touch panel 201 (V is used in fig. 2) S1 Representation) is connected, the other end is connected with the ground V of the circuit SS . Capacitance C in the second parasitic capacitance circuit 204 S2 And the second touch pad 202 (using V in fig. 2) S2 Representation) is connected, the other end is connected with the ground V of the circuit SS 。
In the first bridge circuit 105, a bridge capacitor C is included F1 One end of which is connected with the first touch panel 201 and the other end of which is connected with the switch S 2 The method comprises the steps of carrying out a first treatment on the surface of the Switch S 2 Is a single-pole double-throw switch, the fixed end of which is connected with a reference voltage V REF1 And V SS The method comprises the steps of carrying out a first treatment on the surface of the Further a switch S in the first bridge circuit 105 4 One end of which is connected to the first touch panel 201 and the other end of which is connected to V SS 。
In the second bridge circuit 106, a bridge capacitor C is included F2 One end of which is connected to the second touch panel 202 and the other end of which is connected to the switch S 3 The method comprises the steps of carrying out a first treatment on the surface of the Switch S 3 Is a single-pole double-throw switch, the fixed end of which is connected with a reference voltage V REF1 And V SS The method comprises the steps of carrying out a first treatment on the surface of the Further a switch S in the second bridge circuit 106 5 One end of which is connected to the second touch panel 202 and the other end of which is connected to V SS 。
Wherein each switch in the first bridge circuit 105 and the second bridge circuit 106 is connected to the logic circuit 103, and the logic circuit 103 may be connected to an external controller.
In the rough adjustment stage, the logic circuit 103 generates a RESET signal RESET with a narrow pulse width at the rising edge of the first CLKS under the drive of the system slow clock CLKS, thereby controlling S 4 And S is 5 Closing, V S1 And V S2 Reset to V SS . I.e. capacitor C S1 And C S2 Is cleared to zero; s, S 2 And S is 3 Select and lead to V SS I.e. bridge capacitance C F1 And C F2 Is cleared.
After a short time the RESET signal is released, the logic circuit 103 then controls S 2 And S is 3 Select and lead to V REF1 I.e. C F1 And C F2 Is not in accordance with V S1 And V S2 Connected polar plate and V REF1 Connecting; at this time, C F1 ，C S1 ，C F2 ，C S2 Forming a bridge. Thus, suppose C F1 =C F2 The on-chip large capacitance mismatch is small, there is small difference and the effect on the result is small, then V S1 And V S2 Synchronous increase of V S1 And V S2 Is proportional to C S2 And C S1 Is a difference in (c). Further, the logic circuit 103 may control the coarse tuning capacitor array 101 to perform coarse tuning.
In the embodiment of the present application, the logic circuit 103 may be a successive approximation logic circuit. Thus, the logic circuit 103 can successively obtain M according to the first comparison signal based on successive approximation logicFirst single bit signal D coar <M-1：0>And sequentially controls the operation of each first switch array in the coarse tuning capacitor array 101 according to the M first single bit signals. The value of M is the same as the number of the first switch arrays, so that each first single-bit signal can correspondingly control one first switch array.
The general coarse adjustment is carried out in V S1 And V S2 A configurable switched capacitor array to ground is arranged on both sides in such a way that a larger base capacitance is introduced, on both sides of which the control signal controls the capacitance to increase or decrease, but the introduced base capacitance results in poor sensitivity of the overall CDC. Because the base capacitance corresponds to the parasitic capacitance C S1 Or C S2 While it is generally desirable that the smaller and better the parasitic capacitance, to obtain a larger V with the same finger touch capacitance S1 And V S2 I.e. to increase the sensitivity of the whole CDC.
In view of this, in the embodiment of the present application, during RESET, the logic circuit 103 incorporates the coarse capacitance array 101 into one of the first touch pad 201 and the second touch pad 202 to ensure that the sensitivity of the capacitance detection circuit 100 is high. Please refer to fig. 3, which illustrates another schematic diagram of a capacitance detection circuit. The capacitance detection circuit 100 includes a switch S 1 . Switch S 1 One end of the single-pole double-throw switch is connected with the coarse adjustment capacitor array 101, the other fixed end is connected with the first touch pad 201, and the other fixed end is connected with the second touch pad 202. Thus, during RESET, the logic circuit 103 controls S 1 Is connected to either the first touch pad 201 or the second touch pad 202 such that the coarse capacitive array 101 is initially incorporated into V S1 Or V S2 Is one of the following.
With continued reference to fig. 3, the following is a complete description of the flow of one coarse tuning correction:
during RESET, the control logic has incorporated coarse capacitance array 101 into V S1 Or V S2 Is one of the following. In practical applications, the polarity can be switched. For analysis herein, assume that the most significant first single bit signal D coar <M-1>When equal to 1, the coarse tuning capacitor array 101 is incorporated into V S1 ；D coar <M-1>When equal to 0, the coarse tuning capacitor array 101 is incorporated into V S2 。
Suppose D coar <M-1>The initial value is 1, i.e. coarse tuning capacitor array 101 is incorporated into V S1 However, all trimming capacitors in the trimming capacitor are in an off state, and only small parasitic capacitors exist. During the remaining phase of CLKS, comparator 104 compares V S1 And V S2 And outputs a single-bit first comparison signal DAT. Wherein, due to the structure of the bridge and C F1 =C F2 If C S1 Less than C S2 V is then S1 Greater than V S2 DAT thus outputs a logic 1; if C S1 Greater than C S2 V is then S1 Less than V S2 So that DAT outputs a logic 0.
Then enter the second CLKS period, its RESET flow is the same as the first CLKS period. The logic circuit 103 generates the highest order first single bit signal D based on the DAT signal output before the end of the first CLKS coar <M-1>And outputs it to the corresponding first switch array, and D in the period coar <M-1>Remains unchanged, i.e. if dat=1 is obtained before the end of the first period, D in the second period coar <M-1>Or 1, the coarse tuning capacitor array 101 is also connected to V S1 The method comprises the steps of carrying out a first treatment on the surface of the If dat=0 is obtained before the end of the first period, D in the second period coar <M-1>Switching from 1 to 0, i.e. coarse capacitive array 101 to V S2 。
D during the period in which RESET in the second CLKS has not been released coar <M-2>The highest first switch array of the coarse tuning capacitor array 101 is turned on, and the highest coarse tuning capacitor in the highest first switch array is connected to the capacitor bridge with the size of 2 M-2 C C . Wherein C is C The LSB (Least Significant Bit, lowest order) of the coarse capacitance.
Suppose D coar <M-1>Equal to 1, if DAT is 1 immediately before the end of the CLKS period, then a ratio of C is indicated S2 Small C S1 At the same timeCoupled with a highest coarse tuning capacitor 2 M-2 C C Still after that is than C S2 If the value is small, the highest coarse tuning capacitor 2 in the next CLKS period M-2 C C Or whether access should continue. If DAT is 0 immediately before the end of the CLKS period, then a ratio of C is indicated S2 Small C S1 In parallel with a highest coarse adjustment capacitor 2 M-2 C C Post ratio C S2 And if so, the highest coarse tuning capacitor should not be connected in the next CLKS period. Thus, at the next CLKS start phase, the next highest order first single bit signal D is generated from the DAT signal coar <M-2>Will be fed to its corresponding second highest first switch array and remain of the same polarity.
Suppose D coar <M-1>Equal to 0, if DAT is 1 immediately before the end of the CLKS period, then a ratio of C is indicated S1 Small C S2 In parallel with a highest coarse adjustment capacitor 2 M-2 C C Post ratio C S1 If the value is larger, the highest capacitance is indicated not to be connected continuously in the next CLKS period; if DAT is 0 immediately before the end of the CLKS period, then a ratio of C is indicated S1 Small C S2 In parallel with a highest coarse adjustment capacitor 2 M-2 C C Post ratio C S1 If it is smaller, it indicates that the next higher order single bit signal D should be inverted coar <M-2>To the first switch array of its corresponding next highest order.
The third cycle flow is referred to as the second cycle. Sequentially performing the above processes until the last period to complete the coarse adjustment correction process to obtain corresponding M first single-bit signals D coar <M-1:0>. Referring to FIG. 4, a C provided in an embodiment of the present application is shown S1 Less than C S2 In the case of (2), wherein en_coar is an enable signal for the coarse tuning correction process.
After the system is started or one or more times of coarse adjustment is started at a set time point, coarse adjustment data is obtained and locked after the coarse adjustment is completed, that is, the first control signal of the coarse adjustment capacitor array 101 is locked until the next coarse adjustment is started. Alternatively, the time system is in the fine correction phase except for the coarse correction phase, except for the system shutdown.
The following continues to describe the structure of the rough adjustment capacitor array 101.
Fig. 5 is a schematic structural diagram of a coarse tuning capacitor array according to an embodiment of the present application. The highest first switch array in the coarse tuning capacitor array 101 comprises two first switches, and the two first switches in the highest first switch array are subjected to a highest first single-bit signal D of a first control signal coar <M-1>Control, wherein the first switch can be identified by the control signal corresponding to the first switch, such as two first switches-D in FIG. 5 coar <M-1>And D coar <M-1>Wherein the sign indicates the polarity of the signal, -D coar <M-1>And D coar <M-1>Polarity opposite, if D coar <M-1>Equal to 1, then-D coar <M-1>Equal to 0.
The other first switch arrays in the coarse tuning capacitor array 101 respectively comprise two first switches and a fourth capacitor, and the two first switches in the other first switch arrays are sequentially controlled by other bit first single bit signals of the first control signal. For example, in FIG. 5, the next highest other first switch array includes two first switches D coar <M-2>and-D coar <M-2>Comprising a fourth capacitor C M-2 . The second lower first switch array comprises two first switches D coar <1>and-D coar <1>Comprising a fourth capacitor C 1 . The lowest first switch array comprises two first switches D coar <0>and-D coar <0>Comprising a fourth capacitor C 0 。
In addition, as shown in fig. 5, one end of each other first switch array is grounded to the ground V SS The method comprises the steps of carrying out a first treatment on the surface of the The other end is connected with the highest first switch array, namely, one end of two first switches included in the highest first switch array. For each other first switch array, a fourth capacitor therein is connected to a first switch (e.g. -D coar <0>) In parallel, one end of the fourth capacitor is grounded, and the other end of the fourth capacitor is connected with the second first switch (e.g. D coar <0>) The other end of the second first switch is connected with the highest first switch array.
In FIG. 5, S 1 And S in FIG. 3 1 Is the same.
In addition, the coarse tuning capacitor array 101 is incorporated into V at the first CLKS S1 All trimming capacitors in the capacitor are not opened, which is equivalent to not connecting any capacitor to V S1 And (3) upper part. In practical circuits this is not possible because of the parasitic capacitance of the switch array to ground, assumed to be C P . Present analysis C P Effects on coarse circuit tuning correction:
if the system circuit is perfectly matched initially, C S2 =C S1 ，C F1 =C F2 Then in ideal case after releasing the bridge V S1 =V S2 . At this time due to C P The addition of (C) results in V S1 The capacitance is slightly larger than V S2 Dat=0 before the end of the first CLKS period. The first switch array is switched and incorporated into V at the beginning of the second CLKS S2 The foregoing rough adjustment flow is then performed. However, at this time C P The addition of (C) results in V S2 The capacitance is slightly larger than V S2 Therefore, the coarse capacitance array 101 with only increased capacitance can only obtain DAT of 1, i.e., D coar <M-2:0>All 0 s, i.e. all fourth capacitances are open. The consequence of this is that after the entire coarse tuning process is completed, V S2 Ratio of capacitance V S1 Large C of (2) P . If C P A larger and coarsely adjusted minimum stepping capacitance C C The final coarse sensitivity is then dependent on C P . In practice the worst case is not C S2 = C S1 But C S2 And C S1 The absolute value of the difference is slightly smaller than C P At the moment, the coarse tuning sensitivity can only reach 2C P 。
In view of this, in the embodiment of the present application, the coarse tuning capacitor array 101 is besideA misalignment compensation capacitance circuit is added to solve the above problem by introducing a deliberate mismatch. The explanation is as follows: if C S2 =C S1 ，C F1 =C F2 Then at the first CLKS pair V S1 Adding coarse tuning capacitor array 101 to introduce parasitic capacitance C P At the same time, the switch capacitor C in the offset compensation capacitor circuit OS Incorporated into V S2 And (3) upper part. If do C OS =C P The parasitic capacitance is cancelled out as is ideal. In practice, complete cancellation may not be possible, C may be provided OS Greater than C P And (3) obtaining the product. Since the coarse tuning capacitor array 101 has only the function of increasing the capacitance and no function of decreasing the capacitance, C OS Greater than C P The extra portion that is not offset during the coarse tuning stage is compensated by the coarse tuning capacitor array 101.
In one embodiment, as shown in fig. 6, a schematic structural diagram of another capacitance detection circuit provided in an embodiment of the present application is shown. Wherein the capacitance detection circuit 100 further includes an offset compensation capacitance circuit 107 connected to the logic circuit 103; the logic circuit 103 is also used for generating a first single-bit signal D according to the highest bit (i.e. highest bit coar <M-1>) The misalignment compensation capacitance circuit 107 is connected to the first touch panel 201 or the second touch panel 202.
Wherein the offset compensation capacitor circuit 107 includes a third capacitor C OS The capacitance value of the third capacitor is equal to or larger than the capacitance value of the parasitic capacitor generated by the rough adjustment capacitor array 101. The offset compensation capacitance circuit 107 further includes a second switch and a third switch, the third capacitor is connected in parallel with the second switch, one end of the third capacitor is grounded, the other end of the third capacitor is connected with one end of the third switch, and the third switch is connected with the first touch pad 201 or the second touch pad 202 under the control of the highest bit of the first control signal.
When the offset compensation capacitance circuit 107 is connected to the first touch pad 201 and the second touch pad 202, the polarity of the highest first single-bit signal controlled by the second switch and the third switch is different. Please refer to the drawingsFig. 7 and fig. 8 respectively show schematic structural diagrams of an offset compensation capacitor circuit provided in an embodiment of the present application. In fig. 7, the offset compensation capacitor circuit 107 is connected to the first touch pad 201, wherein the second switch is connected to the second switch via the switch D coar <M-1>Control, third switch S 0 acceptor-D coar <M-1>And (5) controlling. In FIG. 8, the offset compensation capacitor circuit 107 is connected to the second touch pad 202, wherein the second switch is-D coar <M-1>Control, third switch S 0 Subject D coar <M-1>And (5) controlling.
D after the rough adjustment is completed coar <M-1:0>Is stored in logic circuit 103 or an external controller connected to logic circuit 103 and locked, and does not perform the coarse tuning process for a long period of time later, the specific time may depend on the user, and the remaining time is the fine tuning process.
The fine-tuning capacitor array 102 and the fine-tuning calibration procedure are described further below.
In one embodiment, as shown in fig. 9, a schematic structural diagram of another capacitance detection circuit provided in an embodiment of the present application is shown. Wherein the fine capacitive array 102 comprises a first fine capacitive array 102a connected to the first touch pad 201 and a second fine capacitive array 102b connected to the second touch pad 202. The second control signal comprises N second single-bit signals D fine <N-1:0>. The first fine capacitor array 102a includes first capacitors respectively connected to N second single-bit signals, i.e., each first capacitor is respectively subjected to N second single-bit signals D fine <N-1:0>Controlling; the second fine-tuning capacitor array 102b includes second capacitors connected to N third single-bit signals opposite to the N second single-bit signals, respectively, that is, each second capacitor is subjected to N third single-bit signals-D fine <N-1:0>And (5) controlling. Fig. 10 is a schematic structural diagram of a fine-tuning capacitor array according to an embodiment of the present application.
The logic circuit 103 is specifically configured to sequentially obtain N second single-bit signals and generate N third single-bit signals according to the second clock signal CLKF input by the external controller based on the successive approximation logic, sequentially control the grounding or the power supply of each first capacitor according to the N second single-bit signals, and sequentially control the grounding or the power supply of each second capacitor according to the N third single-bit signals.
Referring to fig. 9 and 10, the one-time fine adjustment correction flow is as follows:
assume that coarse capacitance array 101 is incorporated into C S1 And is connected with C S1 The equivalent capacitance after parallel connection is C S1 ， . Assuming that the finger is not touching, V S1 Capacitance of C S1 ， ，V S2 Capacitance of C S2 . The N CLKF periods correspond to one CLKS period.
At the initial stage of the rising edge of CLKS, a RESET narrow pulse signal for resetting and clearing is generated, and the control logic clears the charges of all the capacitors at the RESET stage, including C touch1 ，C touch2 ，C F1 ，C F2 ，C S1 ，C S2 . First capacitance C of first fine capacitor array 102a in FIG. 10 11 ~C 1(N-1) N bit control signal D of (2) fine <N-1:0>All 0, the second capacitance C of the second fine capacitor array 102b 21 ~C 2(N-1) N bit control signal-D of (2) fine <N-1:0>Also all 0, only in the RESET remaining phase D corresponding to the first CLKF fine <N-1:0>and-D fine <N-1:0>At the same time 0, D at other times fine <N-1:0>and-D fine <N-1:0>Are logically opposite signals in one-to-one correspondence with each other.
Subsequent RESET release, C F1 And C F2 Control switch S of (2) 2 And S3 will C F1 ，C F2 Corresponding plate voltage to V REF1 The specific implementation circuit is shown in FIG. 10, wherein S 2 Corresponding to R STD A signal that is 0 when RESET is 1. V after RESET release REF1 。V REF1 Is the supply voltage of the delay unit DL.
After RESET release, V S1 And V S2 The voltage of (C) rises instantaneously as a result of C F1 、C S1 、C touch1 、C 11 ~C 1(N-1) And the possibly accessed coarse capacitance array 101 forms a capacitance divider circuit; similarly, C F2 、C S2 、C touch2 、C 21 ~C 2(N-1) And possibly the coarse capacitive array 101, form a capacitive divider circuit.
Suppose C F1 =C F2 However, the coarse capacitance array 101 does not completely cancel C S1 And C S2 Previous difference and the finger can only touch one of the touch pads relatively, C touch1 Not equal to C touch2 Thus V S1 Not equal to V S2 。
The second comparison signal outputs V during the period from the start of the rising edge of the first CLKF to the end thereof S1 And V S2 If V is S1 Greater than V S2 The logic circuit 103 outputs a logic 1; if V S1 Less than V S2 Then a logic 0 is output and this signal is instantaneously supplied to D as in fig. 10 at the end of the clock fine <N-1>and-D fine <N-1>And the first capacitor and the second capacitor are respectively corresponding to each other.
D during the period from the start of the rising edge of the second CLKF to the end thereof fine <N-1>Hold the value sent at the end of the last cycle, -D fine <N-1>Being its logically opposite value. At this time, D fine <N-2:0>and-D fine <N-2:0>Or remain all 0. The DAT signal at the end of the second CLKF is sampled and sent to D fine <N-2>and-D fine <N-2>. And during the third CLKF period D fine <N-2>and-D fine <N-2>The value of the third CLKF ending instant sample DAT remains unchanged and is sent to D fine <N-3>and-D fine <N-3>By analogy and at the end of the Nth CLKF clock the DAT signal obtained corresponds to D fine <0>and-D fine <0>。
In one embodiment, as shown in fig. 11, a schematic structural diagram of another capacitance detection circuit provided in an embodiment of the present application is shown. The logic circuit 103 is connected with the external controller 300; the logic circuit 103 is specifically configured to output N second single-bit signals to the external controller 300 when the second clock signal ends, so that the external controller 300 calculates the current equivalent capacitance difference according to the N second single-bit signals.
That is, the DAT signal obtained at the end of the Nth CLKF clock corresponds to D fine <0>and-D fine <0>Thereafter, all D's are obtained fine <N-1:0>The logic circuit 103 outputs N second single-bit signals D fine <N-1:0>To the external controller 300, optionally, the signal processing circuit of the external controller 300 may filter it and calculate the current equivalent capacitance difference. Optionally, the logic circuit 103 may further calculate M first single-bit signals D coar <M-1:0>To the external controller 300 for storage.
In addition, as shown in FIG. 12, the embodiment of the present application provides a method for generating a voltage at V S1 Is slightly less than V S2 The waveform of the correction flow is fine-tuned twice in this case. Wherein en_fine is an enable signal in the FINE correction mode. CLKF is the divide-by-N of CLKS.
In the embodiment of the application, based on the fully differential structure, for V SS The common mode interference can be effectively filtered out; the system clock CLKF is used for controlling, so that the problem that the sampling clock is disordered due to CS interference in the CDC of the ring oscillator structure is avoided. Compared with the CDC of the capacitor sharing structure, the capacitor detection circuit in the application does not need a separate off-chip integrated capacitor, can work in multiple paths in parallel, and greatly improves the speed. The method adopts a mode of combining coarse adjustment with fine adjustment, and most of the time, the coarse adjustment part does not work, and only the fine adjustment work, so that the sensitivity is high, and the power consumption is saved. In addition, the coarse tuning structure adopts a single-side coarse tuning mode, so that the problem of parasitic capacitance increase caused by a double-side coarse tuning mode is avoided, and meanwhile, the coarse tuning compensation sensitivity is improved by adding the offset compensation structure.
In one embodiment, the present application also provides a touch detection device. The touch detection device includes peripheral circuitry and capacitance detection circuitry as in any of the embodiments described above. The implementation of the solution to the problem provided by the touch detection device is similar to the implementation described in the above capacitive detection circuit, so the specific limitation of the touch detection device may be referred to the limitation of the capacitive detection circuit hereinabove, and will not be repeated here.
It will be appreciated that the coarse capacitance array, the fine capacitance array, the peripheral circuit, the offset capacitance circuit, etc. may take other forms, and are not limited to those already mentioned in the above embodiments, as long as they achieve the functions required to be achieved.
In the description of the present specification, reference to the term "some embodiments," "other embodiments," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the present application. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application shall be subject to the appended claims.
Claims (10)
1. A capacitance detection circuit, which is characterized in that the capacitance detection circuit is connected with a first touch pad and a second touch pad in a peripheral circuit; the capacitance detection circuit comprises a coarse capacitance array, a fine capacitance array, a logic circuit and a comparator;
the comparator is used for comparing the voltage difference between the first touch panel and the second touch panel, generating a first comparison signal according to a comparison result and outputting the first comparison signal to the logic circuit;
the logic circuit is used for generating a first control signal according to the first comparison signal and controlling the coarse adjustment capacitor array to work according to the first control signal so as to adjust the equivalent capacitance difference between the first touch panel and the second touch panel to be reduced to a target range through the coarse adjustment capacitor array;
And under the condition that the equivalent capacitance difference between the first touch panel and the second touch panel is reduced to the target range, the logic circuit is further used for acquiring a second comparison signal generated by the comparator, generating a second control signal according to the second comparison signal, and controlling the fine-tuning capacitor array to sample the current equivalent capacitance difference between the first touch panel and the second touch panel according to the second control signal.
2. The capacitance detection circuit according to claim 1, wherein the peripheral circuit further includes a first parasitic capacitance circuit corresponding to the first touch panel and a second parasitic capacitance circuit corresponding to the second touch panel; the capacitance detection circuit further comprises a first bridge circuit connected with the first touch pad and a second bridge circuit connected with the second touch pad; the coarse tuning capacitor array comprises a plurality of first switch arrays; the first control signal includes M first single bit signals;
the logic circuit is specifically configured to:
according to a first clock signal input by an external controller, controlling the first parasitic capacitance circuit, the second parasitic capacitance circuit, the first bridge circuit and the second bridge circuit to form a bridge, sequentially acquiring M first single-bit signals according to the first comparison signals based on successive approximation logic, and sequentially controlling each first switch array in the coarse adjustment capacitance array to work according to the M first single-bit signals;
Wherein the value of M is the same as the number of the first switch arrays.
3. The capacitance detection circuit according to claim 1, wherein the second control signal includes N second single bit signals; the fine tuning capacitor array comprises a first fine tuning capacitor array connected with the first touch pad and a second fine tuning capacitor array connected with the second touch pad; the first fine-tuning capacitor array comprises first capacitors respectively connected with N second single-bit signals; the second fine-tuning capacitor array comprises second capacitors connected with N third single-bit signals opposite to the N second single-bit signals respectively;
the logic circuit is specifically configured to:
according to a second clock signal input by an external controller, based on successive approximation logic, N second single-bit signals are sequentially acquired according to the second comparison signals, N third single-bit signals are generated, the first capacitors are sequentially controlled to be grounded or connected with a power supply according to the N second single-bit signals, and the second capacitors are sequentially controlled to be grounded or connected with the power supply according to the N third single-bit signals.
4. The capacitance detection circuit according to claim 3, wherein the logic circuit is connected to an external controller; the logic circuit is specifically configured to:
And outputting the N second single-bit signals to an external controller under the condition that the second clock signal is ended, so that the external controller calculates the current equivalent capacitance difference according to the N second single-bit signals.
5. The capacitance detection circuit according to claim 1, further comprising an offset compensation capacitance circuit connected to the logic circuit; the logic circuit is further configured to:
and controlling the offset compensation capacitance circuit to be connected with the first touch pad or the second touch pad according to the highest bit of the first control signal.
6. The capacitance detection circuit according to claim 5, wherein the offset compensation capacitance circuit includes a third capacitance having a capacitance value equal to or larger than a capacitance value of a parasitic capacitance generated by the coarse capacitance array.
7. The capacitance detection circuit according to claim 6, wherein the offset compensation capacitance circuit further includes a second switch and a third switch, the third capacitor is connected in parallel with the second switch, one end of the third capacitor is grounded, the other end of the third capacitor is connected to one end of the third switch, and the third switch is connected to the first touch pad or the second touch pad under control of a highest bit of the first control signal.
8. The capacitance detection circuit according to claim 2, wherein a highest order first switch array of the coarse tuning capacitance array includes two first switches, the two first switches of the highest order first switch array being controlled by a highest order first single bit signal of the first control signal;
the other first switch arrays in the coarse adjustment capacitor array respectively comprise two first switches and a fourth capacitor, and the two first switches in the other first switch arrays are sequentially controlled by other bit first single-bit signals of the first control signals.
9. The capacitive sensing circuit of claim 8, wherein,
one end of each other first switch array is grounded, and the other end of each other first switch array is connected with the highest first switch array;
for each other first switch array, the fourth capacitor is connected in parallel with a first switch in the other first switch arrays, one end of the fourth capacitor is grounded, the other end of the fourth capacitor is connected with one end of a second first switch, and the other end of the second first switch is connected with the highest first switch array.
10. A touch detection device comprising a peripheral circuit according to any one of claims 1 to 9 and a capacitance detection circuit according to any one of claims 1 to 9.
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