CN117318721A - Quantization method and device based on analog-to-digital converter and analog-to-digital converter - Google Patents
Quantization method and device based on analog-to-digital converter and analog-to-digital converter Download PDFInfo
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- H03M1/12—Analogue/digital converters
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- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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Abstract
The application discloses a quantization method and device based on an analog-to-digital converter and the analog-to-digital converter. The analog-to-digital converter comprises N quantization capacitors and M coupling capacitors. The N quantization capacitors are configured as at least two capacitor arrays, and any two capacitor arrays are bridged by a coupling capacitor. The quantization method based on the analog-to-digital converter comprises the following steps: configuring N+2 bits of data to quantize N bits of data corresponding to N quantization capacitors; based on the capacitance weight corresponding to the N-th quantization capacitor in the N-th quantization capacitors, configuring the fault tolerance range of the N-th bit data corresponding to the N-th quantization capacitor, wherein the sum of the weights of the n+2bit data is equal to 2 N The method comprises the steps of carrying out a first treatment on the surface of the And determining the actual weight of the coupling capacitor and the actual weight of any capacitor array based on the preset maximum weight of the coupling capacitor and the preset maximum weight of at least one capacitor array. By the method, the fault tolerance of the capacitor for quantization in the analog-to-digital converter can be increased, so that the mode is improvedAccuracy of the digitizer.
Description
Technical Field
The present disclosure relates to the field of analog-to-digital conversion technologies, and in particular, to a quantization method and apparatus based on an analog-to-digital converter, and an analog-to-digital converter.
Background
The principle of a successive approximation analog-to-digital converter (SAR ADC) is to quantize an input signal by a binary search algorithm, and control the output voltage of the DAC to successively approximate an analog input voltage by using the DAC, a comparator and a digital logic control part. The SAR ADC can achieve the performances of speed, power consumption, integration level and the like, so that the SAR ADC becomes a research hotspot in the field of ADC design at home and abroad in recent years.
The basic working principle of SARADC is based on a binary search algorithm, and charge storage of a capacitor array is utilized to sequentially redistribute charges, so that the binary search algorithm is completed. However, when the capacitor is mismatched due to factors such as process, some weight errors are caused, so that the original binary weight capacitor is separated from the double relation, and thus the code error may be caused, and the error code word cannot be corrected in the subsequent steps, so that the overall performance of the SARADC is affected.
Disclosure of Invention
The application aims to provide a quantization method and device based on an analog-to-digital converter and the analog-to-digital converter, which can increase the fault tolerance of a capacitor used for quantization in the analog-to-digital converter, thereby improving the precision of the analog-to-digital converter.
To achieve the above object, in a first aspect, the present application provides a quantization method based on an analog-to-digital converter, where the analog-to-digital converter includes N quantization capacitors and M coupling capacitors, the N quantization capacitors are configured as at least two capacitor arrays, and any two capacitor arrays are bridged by one coupling capacitor, and N, M is an integer greater than or equal to 1, and the method includes:
configuring N+2 bits of data to quantize N bits of data corresponding to the N quantization capacitors;
based on the capacitance weight corresponding to the N-th quantization capacitor in the N-th quantization capacitors, configuring the fault tolerance range of the N-th bit data corresponding to the N-th quantization capacitor, wherein the sum of the weights of the n+2bit data is equal to 2 N ；
And determining the actual weight of the coupling capacitor and the actual weight of any capacitor array based on the preset maximum weight of the coupling capacitor and the preset maximum weight of at least one capacitor array.
In an optional manner, the configuring the fault tolerance range of the nth bit data corresponding to the nth quantization capacitor based on the capacitance weight corresponding to the nth quantization capacitor in the N quantization capacitors includes:
each capacitance weight is configured to satisfy: c (C) n ≤C n-1 +C n-2 +…C 0 Wherein C represents the capacitance weight, C n Representing the N-th capacitance weight, wherein N is more than 1 and less than or equal to N;
the fault tolerance range of the nth bit data is determined as follows:R n representing the fault tolerance range of the nth bit data, C i Representing the ith capacitance weight.
In an optional manner, the determining the actual weight of the coupling capacitor and the actual weight of any capacitor array based on the preset maximum weight of the coupling capacitor and the preset maximum weight of at least one capacitor array includes:
determining a correspondence between the at least two capacitive arrays and the coupling capacitance;
determining at least one weight combination based on a preset maximum weight of the coupling capacitor, a preset maximum weight of at least one capacitor array and the corresponding relation, wherein any weight combination in the at least one weight combination comprises the weight of the coupling capacitor and the weight of any capacitor array;
based on the at least one weight combination, an actual weight of the coupling capacitance and an actual weight of any capacitive array are determined.
In an alternative manner, the at least one capacitive array includes a first capacitive array and a second capacitive array, and m=1;
the determining the correspondence between the at least two capacitive arrays and the coupling capacitance includes:
the corresponding relation is：Wherein C is Mt Weight of the first capacitor array, C total As the total weight, C Lt C, as the weight of the second capacitor array a Is the weight of the coupling capacitance.
In an alternative manner, the preset maximum weight of the at least one capacitive array includes the maximum weight of the second capacitive array;
the determining at least one weight combination based on the preset maximum weight of the coupling capacitor, the preset maximum weight of the at least one capacitor array and the corresponding relation comprises the following steps:
configuring the weight of the second capacitor array to be a first integer value greater than zero, wherein the first integer value is less than or equal to the maximum weight of the second capacitor array;
the weight of the coupling capacitor is configured to be a first value larger than zero, and the first value is smaller than or equal to the preset maximum weight of the coupling capacitor;
and determining j x k weight combinations based on k values between the first integer value and the maximum weight of the second capacitor array, j values between the first value and the preset maximum weight of the coupling capacitor and the corresponding relation, wherein j and k are integers more than or equal to 1.
In an alternative manner, the determining j×k weight combinations based on k values between the first integer value and the maximum weight of the second capacitor array, j values between the first value and the preset maximum weight of the coupling capacitor, and the correspondence relation includes:
configuring the weight of the coupling capacitance as a numerical value Cx, wherein x is increased from 1 to j, the numerical value Cx is equal to the first numerical value when x=1, the numerical value Cx is equal to the maximum weight of the preset coupling capacitance when x=j, and Cx is any numerical value of the j numerical values;
configuring the weight of the second capacitor array as a numerical value Cy, wherein y is increased from 1 to k, the numerical value Cy is equal to the first integer numerical value when y=1, the numerical value Cy is equal to the preset maximum weight of the second capacitor array when y=k, and the numerical value Cy is any numerical value of the k numerical values;
and determining j x k weight combinations based on the numerical value Cx and the numerical value Cy and the corresponding relation.
In a second aspect, the present application provides a quantization device based on an analog-to-digital converter, where the analog-to-digital converter includes N quantization capacitors and M coupling capacitors, the N quantization capacitors are configured as at least two capacitor arrays, and any two capacitor arrays are bridged by one coupling capacitor, and N, M is an integer greater than or equal to 1, where the device includes:
the first configuration unit is used for configuring N+2 bits of data to quantize N bits of data corresponding to the N quantization capacitors;
a second configuration unit configured to configure a fault tolerance range of the N-th bit data corresponding to the N-th quantization capacitor based on a capacitance weight corresponding to the N-th quantization capacitor, and a sum of weights of the n+2bit data is equal to 2 N ；
The weight determining unit is used for determining the actual weight of the coupling capacitor and the actual weight of any capacitor array based on the preset maximum weight of the coupling capacitor and the preset maximum weight of at least one capacitor array.
In a third aspect, the present application provides a control processing unit, including:
at least one processor and a memory communicatively coupled to the at least one processor, the memory storing instructions executable by the at least one processor to enable the at least one processor to perform the method as described above.
In a fourth aspect, the present application provides an analog-to-digital converter comprising:
the device comprises N quantized capacitors and M coupling capacitors, wherein the N quantized capacitors are configured into at least two capacitor arrays, and any two capacitor arrays are bridged by one coupling capacitor, wherein N, M is an integer more than or equal to 1; and a control processing unit as described above.
In a fifth aspect, the present application provides a non-transitory computer-readable storage medium storing computer-executable instructions that, when executed by a processor, cause the processor to perform a method as described above.
The beneficial effects of this application are: according to the quantization method based on the analog-to-digital converter, on one hand, N-bit data corresponding to N quantization capacitors are quantized through configuration of N+2-bit data, and on the basis of capacitance weights corresponding to the N-th quantization capacitors in the N quantization capacitors, the fault tolerance range of the N-th bit data corresponding to the N-th quantization capacitors is configured, and the sum of the weights of the N+2-bit data is equal to 2 N To realize the configuration of the fault tolerance range of the N bit data corresponding to the N quantization capacitors; on the other hand, dividing the N quantized capacitors into at least two capacitor arrays, bridging any two capacitor arrays through a coupling capacitor, and determining the actual weight of the coupling capacitor and the actual weight of any capacitor array based on the preset maximum weight of the coupling capacitor and the preset maximum weight of at least one capacitor array so as to realize segmentation of the N quantized capacitors. Therefore, the fault tolerance of the capacitor used for quantization in the analog-to-digital converter can be increased, and the accuracy of the analog-to-digital converter is further improved.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.
Fig. 1 is a schematic structural diagram of an analog-to-digital converter according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a control processing unit according to a first embodiment of the present disclosure;
fig. 3 is a flowchart of a quantization method based on an analog-to-digital converter according to an embodiment of the present application;
FIG. 4 is a schematic diagram of an implementation of step 303 shown in FIG. 3 provided in example one of the present application;
FIG. 5 is a schematic diagram of a portion of the structure shown in FIG. 1 after being simplified;
FIG. 6 is a schematic diagram of an implementation of step 402 shown in FIG. 4 provided in one embodiment of the present application;
FIG. 7 is a schematic diagram of an implementation of step 603 shown in FIG. 6 provided in example one of the present application;
fig. 8 is a flowchart of a quantization method based on an analog-to-digital converter according to a second embodiment of the present application;
fig. 9 is a schematic structural diagram of a quantization device based on an analog-to-digital converter according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The embodiment of the application provides an analog-to-digital converter. The analog-to-digital converter comprises N quantization capacitors, M coupling capacitors and a control processing unit. The N quantization capacitors are configured into at least two capacitor arrays, and any two capacitor arrays are bridged by one coupling capacitor. Wherein N, M is an integer not less than 1.
Referring to fig. 1, fig. 1 schematically illustrates one configuration of an analog-to-digital converter 100. And at least two capacitor arrays are exemplified as comprising two capacitor arrays, while m=1.
As shown in FIG. 1, the N quantization capacitors include a first quantization capacitor C 1 Second quantization capacitor C 2 … Nth quantization capacitor C N . Wherein the first quantization capacitor C 1 To the L-th quantization capacitor C L Is matched withSet as the first capacitor array 20, the L+1st quantization capacitor C L+1 To the Nth quantization capacitor C N Configured as a second capacitive array 30. The first capacitor array 20 and the second capacitor array 30 are bridged by a coupling capacitor Ca 1. Thereby realizing the two segmentation of the N quantization capacitors. Of course, the N quantization capacitors may be divided into three or more segments by adding a coupling capacitor, which is not particularly limited in the embodiment of the present application.
In this embodiment, the analog-to-digital converter 100 further comprises a switch array 40. The switch array 40 includes at least one switch connected between each quantization capacitor and various voltages (including reference voltage VREF, common mode voltage VCM, and ground GND voltage). The switch array 40 is controlled by the control processing unit 10 to switch the switch states to establish or disconnect the connection with different voltages (including the reference voltage VREF, the common mode voltage VCM, and the ground GND voltage), so as to implement voltage conversion of each quantization capacitor.
Referring to fig. 2, fig. 2 schematically illustrates one configuration of the control processing unit 10. Among them, the control processing unit 10 may employ a micro control unit (Microcontroller Unit, MCU) or a digital signal processing (Digital Signal Processing, DSP) controller, etc.
As shown in fig. 2, the control processing unit 10 includes at least one processor 11 and a memory 12, where the memory 12 may be internal to the control processing unit 10, or external to the control processing unit 10, and the memory 12 may be a remotely located memory, and connected to the control processing unit 10 through a network.
The memory 12 serves as a non-volatile computer-readable storage medium for storing non-volatile software programs, non-volatile computer-executable programs, and modules. The memory 12 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created according to the use of the terminal, etc. In addition, memory 12 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 12 may optionally include memory located remotely from processor 11, which may be connected to the terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The processor 11 performs various functions of the terminal and processes the data by running or executing software programs and/or modules stored in the memory 12 and invoking the data stored in the memory 12, thereby performing overall monitoring of the terminal, for example, implementing the analog-to-digital converter based quantization method described in any of the embodiments of the present application.
The number of processors 11 may be one or more, one processor 11 being exemplified in fig. 2. The processor 11 and the memory 12 may be connected by a bus or other means. The processor 11 may include a Central Processing Unit (CPU), a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a controller, a Field Programmable Gate Array (FPGA) device, or the like. The processor 11 may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
Referring to fig. 3, fig. 3 is a quantization method based on an analog-to-digital converter according to an embodiment of the present application. The analog-to-digital converter comprises N quantized capacitors and M coupling capacitors, wherein the N quantized capacitors are configured into at least two capacitor arrays, any two capacitor arrays are bridged by one coupling capacitor, and N, M is an integer more than or equal to 1. The specific structure of the analog-to-digital converter may refer to the description of fig. 1, and will not be described herein.
As shown in fig. 3, the quantization method based on the analog-to-digital converter includes the following steps:
step 301: n+2 bits of data are configured to quantize N bits of data corresponding to the N quantization capacitors.
Step 302: based on the capacitance weight corresponding to the N-th quantization capacitor in the N-th quantization capacitors, configuring the fault tolerance range of the N-th bit data corresponding to the N-th quantization capacitor, and N+2bit dataThe sum of the weights of (2) N 。
Wherein the sum of the weights of the n+2bit data is equal to 2N:
specifically, the conversion times can be increased by quantizing the Nbit data through the n+2bit data, and then the voltage range of the search interval at the rear side can be overlapped with the voltage range of the previous stage to a certain extent by combining the fault tolerance range set later, and the previous stage can be corrected in the subsequent conversion if the comparison error occurs, so that the effective voltage is output. In the related art, since the set conversion times are consistent with the resolution, the search interval is not overlapped redundantly, and the judgment error caused by the factors such as the mismatch of the capacitor cannot be recovered in the later judgment, and then the output effective voltage cannot be outputted. As can be seen, the embodiments of the present application can have higher accuracy than the related art.
In some embodiments, the specific implementation process of configuring the fault tolerance range of the nth bit data corresponding to the nth quantization capacitor in the capacitor weight corresponding to the nth quantization capacitor in the step 302 includes the following steps: each capacitance weight is configured to satisfy: c (C) n ≤C n-1 +C n-2 +…C 0 Wherein C represents a capacitance weight, cn represents an nth capacitance weight, and N is more than 1 and less than or equal to N; the fault tolerance range of the nth bit data is determined as follows:rn represents the fault tolerance range of the nth bit data, and Ci represents the ith capacitance weight.
Specifically, under the condition that the total capacitance weight is unchanged, the current bit is corrected in subsequent quantization when the current bit is in error by making the weight value of the current bit smaller than or equal to the sum of the weights. Most of the conventional redundancy methods expand redundancy range by adding additional redundancy bits (i.e., increasing capacitance), however, this method results in an increase in area and a decrease in quantization speed. The method and the device can improve the building speed of the analog-to-digital converter without increasing the area, and increase the fault tolerance range of each bit of data.
Further, in this embodiment, the maximum error that the nth bit data can be corrected is:wherein V is max_e_n Representing the maximum error, V R Representing the step voltage of the input.
Step 303: and determining the actual weight of the coupling capacitor and the actual weight of any capacitor array based on the preset maximum weight of the coupling capacitor and the preset maximum weight of at least one capacitor array.
Specifically, the preset maximum weight of the coupling capacitor and the preset maximum weight of the at least one capacitor array may be set according to practical application, which is not limited in the embodiment of the present application.
Specifically, after determining the fault tolerance range of each data in step 302, a segmentation process for N quantization capacitors is further implemented. First, it is structurally necessary to configure N quantization capacitors as at least two capacitor arrays, and bridge between any two capacitor arrays through one coupling capacitor. If the N quantized capacitances are configured as two capacitance arrays (respectively denoted as a first capacitance array and a second capacitance array) as shown in fig. 1, step 303 may specifically determine the actual weights of the coupling capacitance, the first capacitance array and the second capacitance array based on the preset maximum weight of the coupling capacitance and the preset maximum weight of the first capacitance array, or step 303 may specifically determine the actual weights of the coupling capacitance, the first capacitance array and the second capacitance array based on the preset maximum weight of the coupling capacitance and the preset maximum weight of the second capacitance array.
In another embodiment, as shown in fig. 4, the specific implementation process of determining the actual weight of the coupling capacitor and the actual weight of any capacitor array in step 303 based on the preset maximum weight of the coupling capacitor and the preset maximum weight of at least one capacitor array may include the following steps:
step 401: the correspondence between at least two capacitive arrays and coupling capacitances is determined.
Step 402: and determining at least one weight combination based on the preset maximum weight of the coupling capacitor, the preset maximum weight of the at least one capacitor array and the corresponding relation, wherein any weight combination in the at least one weight combination comprises the weight of the coupling capacitor and the weight of any capacitor array.
Step 403: based on the at least one weight combination, an actual weight of the coupling capacitance and an actual weight of any of the capacitive arrays is determined.
Specifically, the correspondence between at least two capacitor arrays and the coupling capacitor is a relationship between the weight of each capacitor array in the at least two capacitor arrays and the weight and total weight of the coupling capacitor. Wherein the total weight refers to the total capacitance weight in the embodiments of the present application, using C total Representing, and total weight C when the analog-to-digital converter includes N quantization capacitances total Is 2 N 。
In some embodiments, when the at least one capacitor array includes a first capacitor array and a second capacitor array and m=1, for example, when the analog-to-digital converter is as shown in fig. 1, the specific implementation process of determining the correspondence between the at least two capacitor arrays and the coupling capacitor in step 401 includes the following steps: the corresponding relation is as follows:wherein CMt is the weight of the first capacitor array, ctotal is the total weight, CLt is the weight of the second capacitor array, and Ca is the weight of the coupling capacitor.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating a portion of the structure shown in fig. 1 after being simplified. Wherein the first quantization capacitor C 1 Second quantization capacitor C 2 … L-th quantization capacitor C L The equivalent weight of the whole body is the capacitance C Mt The method comprises the steps of carrying out a first treatment on the surface of the L+1th quantization capacitor C L+1 L+2th quantization capacitor C L+2 … Nth quantization capacitor C N Generalized overall weightsThe heavy equivalent is capacitor C Lt 。
The corresponding relation among the weights of the first capacitor array, the second capacitor array and the coupling capacitor array can be obtained according to charge conservation:
then, by setting C Lt And C a To obtain C Mt . In some embodiments, the maximum weight of the at least one capacitor array preset in step 303 and step 402 includes the maximum weight of the second capacitor array, i.e. a C is preset Lt Is a maximum value of (a). Then, as shown in fig. 6, the specific implementation process of determining at least one weight combination in step 402 based on the preset maximum weight of the coupling capacitor, the preset maximum weight of the at least one capacitor array, and the correspondence relationship includes the following steps:
step 601: the weight of the second capacitor array is configured to be a first integer value greater than zero, and the first integer value is less than or equal to the maximum weight of the second capacitor array.
Step 602: the weight of the coupling capacitor is configured to be a first value larger than zero, and the first value is smaller than or equal to the preset maximum weight of the coupling capacitor.
Step 603: and determining j weight combinations based on k values between the first integer value and the maximum weight of the second capacitor array, j values between the first value and the preset maximum weight of the coupling capacitor and a corresponding relation, wherein j and k are integers which are more than or equal to 1.
Specifically, first set C Lt Is an integer value greater than zero (i.e. is a first integer value C Lt1 ) And set C a A value greater than zero (i.e. a first value C a1 ). Then, based on the preset rule, determining the first integer value and C Lt Maximum value (denoted as C) Ltmax ) K values between, a first value and C a Maximum value (denoted as C) amax ) J values in between. For example, the first integer value C Lt1 One at a time is marked as a numerical value until equal to C Lt Maximum C of (2) Ltmax A total of k values of C can be obtained Lt1 、C Lt1 +1、C Lt1 +2…C Ltmax The method comprises the steps of carrying out a first treatment on the surface of the The same will apply the first value C a1 One at a time is marked as a numerical value until equal to C a Maximum C of (2) amax A total of j values of C can be obtained a1 、C a1 +1、C a1 +2…C amax . Then based on C Lt1 、C Lt1 +1、C Lt1 +2…C Ltmax These k values are equal to C a1 、C a1 +1、C a1 +2…C amax These j values and corresponding relations(denoted as equation (1)) j x k weight combinations can be obtained, wherein each weight combination comprises one C Lt And a C a And a C Mt 。
Specifically, referring to fig. 7, in some embodiments, the specific implementation process of determining the j×k weight combinations in step 603 based on k values between the first integer value and the maximum weight of the second capacitor array, j values between the first value and the preset maximum weight of the coupling capacitor, and the correspondence may include the following steps:
step 701: the weight of the coupling capacitance is configured as a value Cx, wherein x is increased from 1 to j, and the value Cx is equal to a first value when x=1, and is equal to the preset maximum weight of the coupling capacitance when x=j, and Cx is any value of the j values.
Step 702: the weight of the second capacitor array is configured to be a value Cy, wherein y is increased from 1 to k, the value Cy is equal to the first integer value when y=1, the value Cy is equal to the preset maximum weight of the second capacitor array when y=k, and the value Cy is any one of the k values.
Step 703: and determining j weight combinations based on the numerical value Cx and the numerical value Cy and the corresponding relation.
Specifically, first, y=1 is set, at which time cy=a first integer value C Lt1 . And x=1 is set, where cx=a first value C a1 . Thereafter C is carried out Lt1 And C a1 Substituting the first capacitor array into the formula (1) to obtain the weight of the first capacitor array, which is marked as C Mt1 . C is C Lt1 、C a1 And C Mt1 The first weight combination is noted.
Next, holding cy=c Lt1 Unchanged, set x=2, when cx=c a2 . C is C Lt1 And C a2 Substituting the first capacitor array into the formula (1) to obtain the weight of the second first capacitor array, which is marked as C Mt2 . C is C Lt1 、C a2 And C Mt2 And noted as the second weight combination.
In the above manner, x is sequentially equal to 3 and 4 … j, so that j-2 weight combinations can be obtained in total, and j weight combinations can be obtained by adding the first weight combination and the second weight combination.
Next, y=2 is set, and the above procedure of setting x from 1 to j is repeated, so that j weight combinations can be obtained. In summary, in the process of increasing y from 1 to k, j×k weight combinations can be obtained in total.
Finally, each weight in the more suitable weight combinations is selected from the j-k weight combinations to be respectively used as the actual weight of the coupling capacitor, the actual weight of the first capacitor array and the actual weight of the second capacitor array.
For a better understanding of the present application, the following description will be given with the method flow shown in fig. 8.
As shown in fig. 8, first, given C respectively Lt An initial value (integer value C Lt1 ) And given C a An initial value (value C a1 May or may not be an integer). Then set C Lt Cy=cy, and cy=c when y=1 Lt1 That is to say C Lt First set to initial value C Lt1 . Then set C a Cx=c, and cx=c when x=1 a1 That is to say C a First set to initial value C a1 . Then C is carried out Lt1 And C a1 Substituted into the above formula (1), i.e. the correspondenceCan obtain a C Mt . At this time judge C a Whether it is the maximum value. If C a If not, then x=x+1 is set, i.e. x=2 is set, then C a ＝C a2 Then C is carried out Lt2 And C a2 Substituting the above formula (1) to obtain C Mt . And so on until x=j, then C a For maximum value, j weight combinations can be determined, and C is determined Lt Whether it is the maximum value. If C Lt If not, then y=y+1 is set, i.e. y=2 is set, then C Lt ＝C Lt2 . Then re-executing the process of increasing x from 1 to x until y=k, then C Lt For maximum value, j×k weight combinations can be determined.
Therefore, the fault tolerance range is set for the data corresponding to each quantized capacitor while the capacitors are segmented, and the integral fault tolerance capacity of the quantized capacitors can be improved, so that the precision of the analog-to-digital converter is improved. Second, the area can be saved without adding an additional redundant capacitor as in the related art.
Referring to fig. 9, fig. 9 is a schematic structural diagram of a quantization device based on an analog-to-digital converter according to an embodiment of the present application. The analog-digital converter comprises N quantization capacitors and M coupling capacitors, and N, M is an integer more than or equal to 1. The specific structure of the analog-to-digital converter may refer to the description of fig. 1, and will not be described herein.
As shown in fig. 9, the quantization apparatus 900 based on an analog-to-digital converter includes a first configuration unit 901, a second configuration unit 902, and a weight determination unit 903. The first configuration unit 901 is configured to quantize N bits of data corresponding to the N quantization capacitors with n+2 bits of data. The second configuration unit 902 is configured to configure a fault tolerance range of an nth bit data corresponding to an nth quantization capacitor based on a capacitor weight corresponding to the nth quantization capacitor in the N quantization capacitors, and a sum of weights of n+2bit data is equal to 2 N . The weight determining unit 903 is configured to determine an actual weight of the coupling capacitor and an actual weight of any one of the capacitor arrays based on a preset maximum weight of the coupling capacitor and a preset maximum weight of at least one of the capacitor arrays.
Since the apparatus embodiments and the method embodiments are based on the same concept, on the premise that the contents do not conflict with each other, the contents of the apparatus embodiments may refer to the method embodiments, which are not described herein.
Embodiments of the present application also provide a non-transitory computer-readable storage medium storing computer-executable instructions that, when executed by a computer, cause the computer to perform the analog-to-digital converter-based quantization method of any of the embodiments above.
Embodiments of the present application also provide a computer program product comprising a computer program stored on a computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, cause the computer to perform the analog-to-digital converter based quantization method of any of the embodiments above.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; the technical features of the above embodiments or in the different embodiments may also be combined under the idea of the present application, the steps may be implemented in any order, and there are many other variations of the different aspects of the present application as described above, which are not provided in details for the sake of brevity; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. The quantization method based on the analog-to-digital converter is characterized in that the analog-to-digital converter comprises N quantization capacitors and M coupling capacitors, the N quantization capacitors are configured into at least two capacitor arrays, any two capacitor arrays are bridged by one coupling capacitor, and N, M is an integer more than or equal to 1, and the method comprises the following steps:
configuring N+2 bits of data to quantize N bits of data corresponding to the N quantization capacitors;
based on the capacitance weight corresponding to the N-th quantization capacitor in the N-th quantization capacitors, configuring the fault tolerance range of the N-th bit data corresponding to the N-th quantization capacitor, wherein the sum of the weights of the n+2bit data is equal to 2 N ；
And determining the actual weight of the coupling capacitor and the actual weight of any capacitor array based on the preset maximum weight of the coupling capacitor and the preset maximum weight of at least one capacitor array.
2. The method of claim 1, wherein the configuring the fault tolerance range of the nth bit data corresponding to the nth quantization capacitor based on the capacitance weight corresponding to the nth quantization capacitor of the N quantization capacitors comprises:
each capacitance weight is configured to satisfy: c (C) n ≤C n-1 +C n-2 +…C 0 Wherein C represents a capacitance weight, cn represents an nth capacitance weight, and N is more than 1 and less than or equal to N;
the fault tolerance range of the nth bit data is determined as follows:R n representing the fault tolerance range of the nth bit data, C i Representing the ith capacitance weight.
3. The method of claim 1, wherein determining the actual weight of the coupling capacitance and the actual weight of any one of the capacitor arrays based on the preset maximum weight of the coupling capacitance and the preset maximum weight of the at least one capacitor array comprises:
determining a correspondence between the at least two capacitive arrays and the coupling capacitance;
determining at least one weight combination based on a preset maximum weight of the coupling capacitor, a preset maximum weight of at least one capacitor array and the corresponding relation, wherein any weight combination in the at least one weight combination comprises the weight of the coupling capacitor and the weight of any capacitor array;
based on the at least one weight combination, an actual weight of the coupling capacitance and an actual weight of any capacitive array are determined.
4. A method according to claim 3, wherein the at least one capacitive array comprises a first capacitive array and a second capacitive array, and M = 1;
the determining the correspondence between the at least two capacitive arrays and the coupling capacitance includes:
the corresponding relation is as follows:wherein C is Mt Weight of the first capacitor array, C total As the total weight, C Lt C, as the weight of the second capacitor array a Is the weight of the coupling capacitance.
5. The method of claim 4, wherein the predetermined maximum weight of the at least one capacitive array comprises a maximum weight of the second capacitive array;
the determining at least one weight combination based on the preset maximum weight of the coupling capacitor, the preset maximum weight of the at least one capacitor array and the corresponding relation comprises the following steps:
configuring the weight of the second capacitor array to be a first integer value greater than zero, wherein the first integer value is less than or equal to the maximum weight of the second capacitor array;
the weight of the coupling capacitor is configured to be a first value larger than zero, and the first value is smaller than or equal to the preset maximum weight of the coupling capacitor;
and determining j x k weight combinations based on k values between the first integer value and the maximum weight of the second capacitor array, j values between the first value and the preset maximum weight of the coupling capacitor and the corresponding relation, wherein j and k are integers more than or equal to 1.
6. The method of claim 5, wherein said determining j x k combinations of weights based on k values between the first integer value and a maximum weight of the second capacitive array, j values between the first value and a maximum weight of the preset coupling capacitance, and the correspondence comprises:
configuring the weight of the coupling capacitance as a numerical value Cx, wherein x is increased from 1 to j, the numerical value Cx is equal to the first numerical value when x=1, the numerical value Cx is equal to the maximum weight of the preset coupling capacitance when x=j, and Cx is any numerical value of the j numerical values;
configuring the weight of the second capacitor array as a numerical value Cy, wherein y is increased from 1 to k, the numerical value Cy is equal to the first integer numerical value when y=1, the numerical value Cy is equal to the preset maximum weight of the second capacitor array when y=k, and the numerical value Cy is any numerical value of the k numerical values;
and determining j x k weight combinations based on the numerical value Cx and the numerical value Cy and the corresponding relation.
7. A quantization device based on an analog-to-digital converter, wherein the analog-to-digital converter includes N quantization capacitors and M coupling capacitors, the N quantization capacitors are configured as at least two capacitor arrays, and any two capacitor arrays are bridged by one coupling capacitor, and N, M is an integer greater than or equal to 1, the device includes:
the first configuration unit is used for configuring N+2 bits of data to quantize N bits of data corresponding to the N quantization capacitors;
a second configuration unit configured to configure a fault tolerance range of the N-th bit data corresponding to the N-th quantization capacitor based on a capacitance weight corresponding to the N-th quantization capacitor, and a sum of weights of the n+2bit data is equal to 2 N ；
The weight determining unit is used for determining the actual weight of the coupling capacitor and the actual weight of any capacitor array based on the preset maximum weight of the coupling capacitor and the preset maximum weight of at least one capacitor array.
8. A control processing unit, characterized by comprising:
at least one processor and a memory communicatively coupled to the at least one processor, the memory storing instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-6.
9. An analog-to-digital converter, comprising:
the device comprises N quantized capacitors and M coupling capacitors, wherein the N quantized capacitors are configured into at least two capacitor arrays, and any two capacitor arrays are bridged by one coupling capacitor, wherein N, M is an integer more than or equal to 1;
and a control processing unit as claimed in claim 8.
10. A non-transitory computer readable storage medium storing computer executable instructions which, when executed by a processor, cause the processor to perform the method of any of claims 1-6.
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