CN117316773B - Preparation method of palladium/tungsten diselenide Schottky transistor - Google Patents
Preparation method of palladium/tungsten diselenide Schottky transistor Download PDFInfo
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- CN117316773B CN117316773B CN202311594680.XA CN202311594680A CN117316773B CN 117316773 B CN117316773 B CN 117316773B CN 202311594680 A CN202311594680 A CN 202311594680A CN 117316773 B CN117316773 B CN 117316773B
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- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 title claims abstract description 175
- ROUIDRHELGULJS-UHFFFAOYSA-N bis(selanylidene)tungsten Chemical compound [Se]=[W]=[Se] ROUIDRHELGULJS-UHFFFAOYSA-N 0.000 title claims abstract description 115
- 229910052763 palladium Inorganic materials 0.000 title claims abstract description 43
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 7
- 238000005566 electron beam evaporation Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 132
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 87
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 87
- 238000010438 heat treatment Methods 0.000 claims description 44
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 24
- 239000013078 crystal Substances 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 16
- 238000004528 spin coating Methods 0.000 claims description 11
- 239000000843 powder Substances 0.000 claims description 10
- 238000001704 evaporation Methods 0.000 claims description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 8
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 claims description 8
- 229910052786 argon Inorganic materials 0.000 claims description 8
- 239000007789 gas Substances 0.000 claims description 8
- 239000001257 hydrogen Substances 0.000 claims description 8
- 229910052739 hydrogen Inorganic materials 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 239000003513 alkali Substances 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000012546 transfer Methods 0.000 abstract description 21
- 239000000126 substance Substances 0.000 abstract description 5
- 238000010276 construction Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 description 17
- AFCARXCZXQIEQB-UHFFFAOYSA-N N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]-2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidine-5-carboxamide Chemical compound O=C(CCNC(=O)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F)N1CC2=C(CC1)NN=N2 AFCARXCZXQIEQB-UHFFFAOYSA-N 0.000 description 13
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 10
- 238000011144 upstream manufacturing Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 4
- 238000001816 cooling Methods 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 230000008020 evaporation Effects 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 238000002156 mixing Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000004506 ultrasonic cleaning Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 239000004205 dimethyl polysiloxane Substances 0.000 description 3
- 235000013870 dimethyl polysiloxane Nutrition 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 3
- CXQXSVUQTKDNFP-UHFFFAOYSA-N octamethyltrisiloxane Chemical compound C[Si](C)(C)O[Si](C)(C)O[Si](C)(C)C CXQXSVUQTKDNFP-UHFFFAOYSA-N 0.000 description 3
- 238000004987 plasma desorption mass spectroscopy Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 229910052723 transition metal Inorganic materials 0.000 description 3
- -1 transition metal chalcogenides Chemical class 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000033228 biological regulation Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 229910021389 graphene Inorganic materials 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 238000001000 micrograph Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000005693 optoelectronics Effects 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- NQTSTBMCCAVWOS-UHFFFAOYSA-N 1-dimethoxyphosphoryl-3-phenoxypropan-2-one Chemical compound COP(=O)(OC)CC(=O)COC1=CC=CC=C1 NQTSTBMCCAVWOS-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000004630 atomic force microscopy Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000013500 performance material Substances 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000004098 selected area electron diffraction Methods 0.000 description 1
- 239000011669 selenium Substances 0.000 description 1
- 238000000101 transmission high energy electron diffraction Methods 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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Abstract
The invention discloses a preparation method of a palladium/tungsten diselenide Schottky transistor, and relates to the technical field of integrated circuit manufacturing. The invention adopts an electron beam evaporation method to realize the construction of the Pd film, adopts a chemical vapor deposition method to grow, and realizes the WSe with sub-centimeter level through the adjustment of a chemical growth window 2 Is then transferred by wet method to WSe 2 Transfer to Pd film to allow WSe 2 Forming Van der Waals interface with Pd to realize Schottky contact, and Pd/WSe constructed by Pd contact 2 Schottky transistor with 100 times higher on/off ratio of transfer characteristic and 10 reduced off current ‑9 A, exhibit more excellent transistor performance.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a preparation method of a palladium/tungsten diselenide Schottky transistor.
Background
The semiconductor industry has developed under the direction of moore's law to date, undergoing multiple microshutter. The size of transistors has heretofore reached the size of a few nanometers, accompanied by increased difficulty in quantum tunneling and processing. However, heterogeneous integration and architecture design of two-dimensional materials including graphene, mxnes, transition metal chalcogenides (TMDCs), and h-BN, etc. through two-dimensional materials is currently considered as one of the most effective approaches to extend moore's law for the next decade. For the growth of two-dimensional materials for integrated circuits, molecular epitaxy is typically utilized, which involves strong chemical bond interactions, often with lattice matching limitations and requirements for process compatibility. By utilizing Van der Waals interaction in the vertical direction of the two-dimensional material, stacking and assembling of various performance materials can be realized, and the two-dimensional material can be used for replacing a keyless integration mode. For example, metal-semiconductor contacts are realized by van der Waals bonds and van der Waals heterojunction.
Transition metal chalcogenides (TMDCs), e.g. WSe 2 、MoS 2 、WS 2 、PdSe 2 The material is a star material for the research of optoelectronic devices, and the optoelectronic devices which avoid van der Waals bonding of lattice mismatch can be manufactured through structural design, so that unique performance is realized. Metal-semiconductor contacts create problems with fermi pinning effects and interface disorder, which are major contributors to achieving high performance in two-dimensional electronic devices.
Doping is currently a common means for changing the work function and band structure of semiconductors to reduce the metal-semiconductor contact resistance and, however, doping modulation of the defect engineering of TMDCs to achieve contacts with low resistance is difficult to achieve accurately. Of course, it is difficult to perfectly integrate multiple two-dimensional materials with different structures or lattice parameters together while avoiding interfacial disorder and fermi level pinning effects, which is caused by doping and defects at the contact interface due to the presence of metal contacts, and clean van der Waals contact between metal and semiconductor can effectively reduce fermi level pinning.
Existing technologyIn operation, CN114975687a discloses a two-dimensional photovoltaic device based on ideal schottky contact and a method for manufacturing the same, the two-dimensional photovoltaic device comprising: vertically stacking a metal top electrode (palladium) from top to bottom, taking a photosensitive two-dimensional semiconductor (tungsten diselenide) and a two-dimensional material as a bottom electrode, and forming ideal Schottky contact between the metal top electrode and the photosensitive two-dimensional semiconductor through van der Waals contact by utilizing a fixed-point transfer method, wherein the fixed-point transfer method comprises the following steps: spin-coating PMMA on Si/SiO by vapor deposition 2 And (3) removing the PMMA and the metal top electrode on the substrate by using PDMS, and then transferring the PMMA and the metal top electrode to the photosensitive two-dimensional semiconductor at fixed points. However, the above patent uses PDMS and PMMA to assist the spot transfer, which is unavoidable and results in damage to the contact surface.
Therefore, it is necessary to select a suitable metal as a contact and TMDC as a channel transconductance material so that van der waals contact is formed between the two to avoid interface disorder and fermi level pinning effects, thereby achieving improvement of performance of the two-dimensional photovoltaic device.
Disclosure of Invention
Aiming at the prior art, the invention aims to provide a preparation method of a palladium/tungsten diselenide Schottky transistor. The invention adopts an electron beam evaporation method to realize the construction of the Pd film, adopts a chemical vapor deposition method to grow, and realizes the WSe with sub-centimeter level through the adjustment of a chemical growth window 2 Is then transferred by wet method to WSe 2 Transfer to Pd film to allow WSe 2 Forming Van der Waals interface with Pd to realize Schottky contact, and Pd/WSe constructed by Pd contact 2 Schottky transistor with 100 times higher on/off ratio of transfer characteristic and 10 reduced off current -9 A, exhibit more excellent transistor performance.
In order to achieve the above purpose, the invention adopts the following technical scheme:
in a first aspect of the present invention, a method for preparing a palladium/tungsten diselenide schottky transistor is provided, comprising the steps of:
(1) By WO 2.9 Pre-buried seed crystal treatment is carried out on the pretreated substrate by the solution, and the solution is adoptedChemical vapor deposition method for growing WSe on substrate with embedded seed crystal 2 Obtaining a substrate/tungsten diselenide film;
(2) Spin-coating PMMA on the substrate/tungsten diselenide film, heating to obtain the substrate/tungsten diselenide/PMMA film, and then removing the substrate by alkali etching to obtain the tungsten diselenide/PMMA film;
(3) Depositing metal palladium on the surface of the substrate to obtain a substrate/palladium film;
(4) Transferring the tungsten diselenide/PMMA film in the step (2) onto a substrate/palladium film, and heating to obtain the substrate/Pd/tungsten diselenide/PMMA;
(5) Placing the substrate/Pd/tungsten diselenide/PMMA in acetone to wash off the PMMA, and heating to obtain the substrate/Pd/tungsten diselenide;
(6) And (3) evaporating an Au electrode and a Ti electrode on the surface of the substrate/Pd/tungsten diselenide to obtain the Pd/tungsten diselenide Schottky transistor.
Preferably, the substrate is made of Si/SiO 2 The method comprises the steps of carrying out a first treatment on the surface of the The grid electrode of the palladium/tungsten diselenide Schottky transistor is Si in the substrate; palladium film used in palladium/tungsten diselenide Schottky transistor channel and WSe 2 Together as a channel transconductance material for the transistor.
Preferably, in the step (1), the method for preprocessing the substrate is as follows: the substrate is ultrasonically cleaned by acetone and isopropanol to remove organic matters on the surface of the substrate.
Preferably, the substrate has dimensions of 1.5cm by 1.5cm.
Preferably, in step (1), the WO 2.9 The concentration of the solution was 0.003g/L.
Preferably, in the step (1), WSe is grown on the substrate of the pre-buried seed crystal by a chemical vapor deposition method 2 The operation of (1) is as follows: reversely buckling a substrate with pre-buried seed crystals on WO 2.9 And (3) forming contact on the powder, placing the powder in a high temperature area, placing selenium powder in a low temperature area, introducing mixed gas of hydrogen and argon, heating and raising the temperature, and maintaining the temperature for tungsten diselenide growth to obtain the substrate/tungsten diselenide film.
Further preferred, WO 2.9 The mass ratio of the powder to the selenium powder is9:50。
Further preferably, the volume ratio of argon to hydrogen in the mixed gas is 10:1.
Further preferably, the heating temperature rise time is 10min, the temperature of the high temperature area after heating temperature rise is 800-850 ℃, and the temperature of the low temperature area is 550-650 ℃.
Further preferably, the tungsten diselenide growth time is 8-12min.
Preferably, in the step (2), spin coating parameters are: the spin coating is carried out for 10s at 600r/min and then for 50s at a spin coating speed of 1000-1500 r/min.
Preferably, in the step (2), the thickness of the PMMA film in the substrate/tungsten diselenide/PMMA film is 100-300nm.
Preferably, in the step (2), the heating time is 50-70 ℃ and the heating time is 8-12min.
Preferably, in the step (2), the alkali etching is performed by using a potassium hydroxide solution with a concentration of 0.2 g/L.
Preferably, in the step (3), the method of immersing the surface of the substrate in the metal palladium is an electron beam evaporation method.
Preferably, in the step (3), the thickness of the palladium film in the substrate/palladium film is 1-5nm.
Preferably, in the step (5), the heating temperature is 50-70 ℃ and the heating time is 8-12min.
Preferably, in the step (6), au electrodes and Ti electrodes are evaporated on the surface of the evaporation substrate/Pd/tungsten diselenide by using a mask.
Preferably, in the step (6), the thickness of the Au electrode is 5nm and the thickness of the Ti electrode is 50nm.
In a second aspect of the present invention, a palladium/tungsten diselenide schottky transistor is fabricated using the fabrication method described above.
The invention has the beneficial effects that:
the invention adopts an electron beam evaporation method to realize the construction of the Pd film, adopts a chemical vapor deposition method to grow, and realizes the WSe with sub-centimeter level through the adjustment of a chemical growth window 2 Is then transferred by wet method to WSe 2 Transfer to Pd film to makeObtaining WSe 2 And a van der Waals interface is formed with Pd to realize Schottky contact.
The invention adopts the mode of pre-embedding seed crystals to grow WSe 2 Reducing WSe grown on a substrate 2 Is capable of achieving the prepared WSe 2 Is of a single film structure and ensures a large area, which is beneficial to observing WSe 2 Is also advantageous for improving the performance of the transistor. Meanwhile, the invention discloses that the WSe is realized by Pd film contact for the first time 2 Double regulation of transfer characteristic and output characteristic of single crystal transistor, controllable enhancement of p-type transfer characteristic by changing thickness of Pd film, and WSe 2 Transferred to Pd film, and the two materials are used as channel transconductance material of transistor to prevent Fermi pinning and make the transistor excellent in performance
Compared with WSe 2 Transistor and Pd/WSe 2 The invention adopts Pd film contact to construct Pd/WSe 2 Schottky transistor with 100 times higher on/off ratio of transfer characteristic and 10 reduced off current -9 A, it can be seen that the palladium-tungsten diselenide Schottky transistor prepared by the method provided by the invention has more excellent transistor performance. Pd/WSe disclosed in the invention 2 The preparation method of the Schottky transistor has the advantages of low cost, high efficiency and easy realization of batch, and is suitable for realizing WSe 2 The metal/semiconductor contact design method provides effective examples for application in integrated circuits and has wide application prospect.
Drawings
Fig. 1: the preparation flow diagram of the palladium/tungsten diselenide Schottky transistor is shown in the specification.
Fig. 2: (a) Pd/WSe prepared in example 1 2 WSe in Schottky junction 2 A schematic crystal structure; (b) Pd/WSe prepared in example 1 2 WSe in Schottky junction 2 Mechanical microphotographs of the crystals; (c) Pd/WSe prepared in example 1 2 WSe in Schottky junction 2 Atomic force microscopy of crystals.
Fig. 3: (a) Pd/WSe prepared in example 1 2 In Schottky junctionsWSe 2 A high resolution transmission electron microscope image of the crystal; (b) Pd/WSe prepared in example 1 2 WSe in Schottky junction 2 A selected area electron diffraction pattern of the crystal; (c-g) Pd/WSe obtained in example 1 2 EDS imaging of schottky junction.
Fig. 4: (a) WSe of comparative example 1 2 A transfer characteristic change map of the schottky transistor; (b-d) Pd/WSe prepared in examples 1-3, respectively 2 Transfer characteristic change diagram of schottky transistor.
Fig. 5: (a) Pd/WSe prepared in example 1 2 A device structure schematic diagram of the schottky transistor; (b) Comparative example 1 WSe 2 A rectification output characteristic diagram of the Schottky transistor; (c) Pd/WSe prepared in example 1 2 A rectified output characteristic diagram of a schottky transistor.
Fig. 6: (a) Pd/WSe prepared in example 1 2 Schematic plan structure of the device of the schottky transistor; (b) Ti, au, pd and WSe 2 A schematic diagram of the work function band relationship of (a); (c) Pd/WSe prepared in example 1 2 Band change and carrier behavior at schottky contacts are schematically illustrated.
Detailed Description
It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
As described in the background art, transition metal sulfur compounds (TMDCs) are used as materials for preparing two-dimensional electronic devices, and doping is used for changing the work function and the energy band structure of semiconductors to reduce the metal-semiconductor contact resistance, but TMDCs are difficult to precisely realize by doping regulation to realize low-resistance contacts, and the metal-semiconductor contacts generate the problems of fermi pinning effect and interface disorder, which are the main reasons for influencing the realization of high performance of the two-dimensional electronic devices.
Based on the above, in order to avoid interface disorder and fermi level pinning effect, the invention selects Pd film as a contact point to constructPd/WSe 2 A Schottky transistor and a method of manufacturing the same. Specifically, as shown in FIG. 1, the invention adopts an electron beam evaporation method to realize the construction of a Pd film with the thickness of 1-5nm, and then adopts a chemical vapor deposition method and chemical growth window adjustment to prepare the sub-centimeter WSe 2 Then the WSe is transferred by wet method 2 Transfer to Pd film to allow WSe 2 And a van der Waals interface is formed with Pd to realize Schottky contact.
Patent CN114975687a discloses a two-dimensional photovoltaic device based on ideal schottky contact and a method for manufacturing the same, although Pd and WSe are disclosed in the patent 2 Realizing Schottky contact, functionally, the Pd film is used as a top electrode, the top electrode does not participate in the channel transconductance of a carrier, the Schottky contact is formed between the top electrode and a two-dimensional semiconductor material, and the top electrode material is Ti, the Pd film is used in a transistor channel and is used with WSe 2 Commonly used as channel transconductance materials of transistors; in addition, in the transfer process, PMMA is spin-coated on a substrate on which a metal top electrode is evaporated, PDMS is used for stripping the PMMA and the metal top electrode, and then the metal top electrode is transferred onto a two-dimensional semiconductor at a fixed point, wherein in the transfer process, a Pd film is stripped from the substrate and then transferred onto a two-dimensional semiconductor material, and the stripping transfer inevitably causes damage to a contact surface, and the fixed point transfer which is not the volume in the patent does not damage the surface of the material, so that ideal Schottky contact is formed; in the invention, the tungsten diselenide/PMMA film is directly transferred onto the substrate/palladium film to form the substrate/Pd/tungsten diselenide/PMMA, and then the PMMA is cleaned by acetone to obtain the substrate/Pd/tungsten diselenide, so that the transfer of the Pd film is not involved in the transfer process, and the structural damage can be well avoided.
In order to enable those skilled in the art to more clearly understand the technical solutions of the present application, the technical solutions of the present application will be described in detail below with reference to specific embodiments.
The test materials used in the examples of the present invention are all conventional in the art and are commercially available.
Example 1: pd/WSe 2 Preparation of schottky transistor
(1) To Si/SiO 2 Cutting substrate to 1.5cm×1.5cm, ultrasonic cleaning with acetone and isopropanol to remove organic matters on the surface of substrate, and treating with WO with concentration of 0.003g/L 2.9 Pre-burying seed crystals on the substrate by the solution; placing the substrate after pre-buried seed crystal treatment in a tube furnace and reversely buckling the substrate in WO 2.9 Placing the powder in a high temperature area at the downstream of a tube furnace, placing selenium powder in a low temperature area at the upstream of the tube furnace, introducing argon and hydrogen into the mixed gas obtained by mixing according to the volume ratio of 10:1, heating from room temperature to 830 ℃ at the high temperature area at the downstream of the tube furnace, maintaining the temperature at 600 ℃ at the low temperature at the upstream of the tube furnace for 10min to grow tungsten diselenide, stopping heating after the growth is completed, cooling for half an hour, and taking out to obtain the substrate/tungsten diselenide film;
(2) Transferring the substrate/tungsten diselenide film to a spin coater, adding 2 drops of PMMA solution, accelerating and rotating for 10s at 600r/min, and spin-coating for 50s at 1200r/min to uniformly spread PMMA, forming a PMMA film on the surface of the substrate/tungsten diselenide film, wherein the thickness of the PMMA film is 100nm, transferring the PMMA film formed on the surface of the substrate/tungsten diselenide film coated with the PMMA film to a heating table, and heating for 10min at 60 ℃ to obtain the substrate/tungsten diselenide/PMMA film;
placing the substrate/tungsten diselenide/PMMA film in potassium hydroxide solution with the concentration of 0.2g/L for etching to remove the substrate, so as to obtain the tungsten diselenide/PMMA film;
(3) Si/SiO using electron beam film plating instrument 2 Depositing metal Pd on the substrate by evaporation to obtain a substrate/palladium film with the Pd film thickness of 1 nm;
(4) Transferring the tungsten diselenide/PMMA film prepared in the step (2) onto a substrate/palladium film, and heating to attach the tungsten diselenide/PMMA film to form Pd/WSe 2 Contacting to obtain a substrate/Pd/tungsten diselenide/PMMA;
(5) Placing the substrate/Pd/tungsten diselenide/PMMA in an acetone solution to clean and remove PMMA, and placing the substrate/Pd/tungsten diselenide/PMMA on a heating table to heat at 60 ℃ for 10min to obtain the substrate/Pd/tungsten diselenide;
(6) At substrate/Pd-The surface of tungsten diselenide is evaporated with Au electrode with the thickness of 5nm and Ti electrode with the thickness of 50nm through a mask plate to obtain Pd/WSe 2 A schottky transistor.
Example 2: pd/WSe 2 Preparation of schottky transistor
(1) To Si/SiO 2 Cutting substrate to 1.5cm×1.5cm, ultrasonic cleaning with acetone and isopropanol to remove organic matters on the surface of substrate, and treating with WO with concentration of 0.003g/L 2.9 Pre-burying seed crystals on the substrate by the solution; placing the substrate after pre-buried seed crystal treatment in a tube furnace and reversely buckling the substrate in WO 2.9 Placing the powder in a high temperature area at the downstream of a tube furnace, placing selenium powder in a low temperature area at the upstream of the tube furnace, introducing argon and hydrogen into the mixed gas obtained by mixing according to the volume ratio of 10:1, heating from room temperature to 800 ℃ at the high temperature area at the downstream of the tube furnace, maintaining the temperature at 550 ℃ at the low temperature at the upstream of the tube furnace for 12min to grow tungsten diselenide, stopping heating after the growth is completed, cooling for half an hour, and taking out to obtain the substrate/tungsten diselenide film;
(2) Transferring the substrate/tungsten diselenide film to a spin coater, adding 2 drops of PMMA solution, accelerating and rotating for 10s at 600r/min, and spin-coating for 50s at 1000r/min to uniformly spread PMMA, forming a PMMA film on the surface of the substrate/tungsten diselenide film, wherein the thickness of the PMMA film is 200nm, transferring the PMMA film formed on the surface of the substrate/tungsten diselenide film coated with the PMMA film to a heating table, and heating for 12min at 50 ℃ to obtain the substrate/tungsten diselenide/PMMA film;
placing the substrate/tungsten diselenide/PMMA film in potassium hydroxide solution with the concentration of 0.2g/L for etching to remove the substrate, so as to obtain the tungsten diselenide/PMMA film;
(3) Si/SiO using electron beam film plating instrument 2 Depositing metal Pd on the substrate by evaporation to obtain a substrate/palladium film with the Pd film thickness of 3 nm;
(4) Transferring the tungsten diselenide/PMMA film prepared in the step (2) onto a substrate/palladium film, and heating to attach the tungsten diselenide/PMMA film to form Pd/WSe 2 Contacting to obtain a substrate/Pd/tungsten diselenide/PMMA;
(5) Placing the substrate/Pd/tungsten diselenide/PMMA in an acetone solution to clean and remove PMMA, and placing the substrate/Pd/tungsten diselenide/PMMA on a heating table to heat at 50 ℃ for 12min to obtain the substrate/Pd/tungsten diselenide;
(6) Evaporating Au electrode with thickness of 5nm and Ti electrode with thickness of 50nm on the surface of substrate/Pd/tungsten diselenide by using mask plate to obtain Pd/WSe 2 A schottky transistor.
Example 3: pd/WSe 2 Preparation of schottky transistor
(1) To Si/SiO 2 Cutting substrate to 1.5cm×1.5cm, ultrasonic cleaning with acetone and isopropanol to remove organic matters on the surface of substrate, and treating with WO with concentration of 0.003g/L 2.9 Pre-burying seed crystals on the substrate by the solution; placing the substrate after pre-buried seed crystal treatment in a tube furnace and reversely buckling the substrate in WO 2.9 Placing the powder in a high temperature area at the downstream of a tube furnace, placing selenium powder in a low temperature area at the upstream of the tube furnace, introducing argon and hydrogen into the mixed gas obtained by mixing according to the volume ratio of 10:1, heating from room temperature to 850 ℃ in the high temperature area at the downstream of the tube furnace, keeping the temperature at 650 ℃ in the low temperature area at the upstream of the tube furnace, growing tungsten diselenide for 8min, stopping heating after the growth is completed, cooling for half an hour, and taking out to obtain the substrate/tungsten diselenide film;
(2) Transferring the substrate/tungsten diselenide film to a spin coater, adding 2 drops of PMMA solution, accelerating and rotating for 10s at 600r/min, and spin-coating for 50s at 1500r/min to uniformly spread PMMA, forming a PMMA film on the surface of the substrate/tungsten diselenide film, wherein the thickness of the PMMA film is 300nm, transferring the PMMA film formed on the surface of the substrate/tungsten diselenide film coated with the PMMA film to a heating table, and heating at 70 ℃ for 8min to obtain the substrate/tungsten diselenide/PMMA film;
placing the substrate/tungsten diselenide/PMMA film in potassium hydroxide solution with the concentration of 0.2g/L for etching to remove the substrate, so as to obtain the tungsten diselenide/PMMA film;
(3) Si/SiO using electron beam film plating instrument 2 Depositing metal Pd on the substrate by evaporation to obtain a substrate/palladium film with the Pd film thickness of 5 nm;
(4) Transferring the tungsten diselenide/PMMA film prepared in the step (2) onto a substrate/palladium film, and heating to attach the tungsten diselenide/PMMA film to form Pd/WSe 2 Contacting to obtain a substrate/Pd/tungsten diselenide/PMMA;
(5) Placing the substrate/Pd/tungsten diselenide/PMMA in an acetone solution to clean and remove the PMMA, and placing the substrate/Pd/tungsten diselenide/PMMA on a heating table to heat at 70 ℃ for 8min to obtain the substrate/Pd/tungsten diselenide;
(6) Evaporating Au electrode with thickness of 5nm and Ti electrode with thickness of 50nm on the surface of substrate/Pd/tungsten diselenide by using mask plate to obtain Pd/WSe 2 A schottky transistor.
Comparative example 1: WSe (Wireless sensor set) 2 Schottky transistor
(1) To Si/SiO 2 Cutting substrate to 1.5cm×1.5cm, ultrasonic cleaning with acetone and isopropanol to remove organic matters on the surface of substrate, and treating with WO with concentration of 0.003g/L 2.9 Pre-burying seed crystals on the substrate by the solution; placing the substrate after pre-buried seed crystal treatment in a tube furnace and reversely buckling the substrate in WO 2.9 Placing the powder in a high temperature area at the downstream of a tube furnace, placing selenium powder in a low temperature area at the upstream of the tube furnace, introducing argon and hydrogen into the mixed gas obtained by mixing according to the volume ratio of 10:1, heating from room temperature to 830 ℃ at the high temperature area at the downstream of the tube furnace, maintaining the temperature at 600 ℃ at the low temperature at the upstream of the tube furnace for 10min to grow tungsten diselenide, stopping heating after the growth is completed, cooling for half an hour, and taking out to obtain the substrate/tungsten diselenide film;
(2) Transferring the substrate/tungsten diselenide film to a spin coater, adding 2 drops of PMMA solution, accelerating and rotating for 10s at 600r/min, and spin-coating for 50s at 1200r/min to uniformly spread PMMA, forming a PMMA film on the surface of the substrate/tungsten diselenide film, wherein the thickness of the PMMA film is 100nm, transferring the PMMA film formed on the surface of the substrate/tungsten diselenide film coated with the PMMA film to a heating table, and heating for 10min at 60 ℃ to obtain the substrate/tungsten diselenide/PMMA film;
placing the substrate/tungsten diselenide/PMMA film in potassium hydroxide solution with the concentration of 0.2g/L for etching to remove the substrate, so as to obtain the tungsten diselenide/PMMA film;
(3) Transferring the tungsten diselenide/PMMA film prepared in the step (2) onto a substrate, and heating to attach the tungsten diselenide/PMMA film to obtain the substrate/tungsten diselenide/PMMA;
(4) Placing the substrate/tungsten diselenide/PMMA in an acetone solution to clean and remove the PMMA, and placing the substrate/tungsten diselenide/PMMA on a heating table to heat at 60 ℃ for 10min to obtain the substrate/tungsten diselenide;
(5) Evaporating Au electrode with thickness of 5nm and Ti electrode with thickness of 50nm on the surface of the substrate/tungsten diselenide through a mask plate to obtain WSe 2 And a transistor.
Test example 1:
Pd/WSe prepared in example 1 2 Pd/WSe in Schottky junction transistors 2 The schottky junction was structurally characterized as shown in fig. 2 and 3.
As can be seen from FIG. 2 (a), WSe 2 Having a planar hexagonal structure similar to graphene, each W atom being sandwiched between two Se atoms as a covalent bond between different layers, WSe, from a side view 2 Connected by van der Waals bonds. As can be seen from FIG. 2 (b), WSe grown using the buried seed strategy 2 With very thin and uniform thickness, theoretically, a single layer of WSe 2 The thickness was about 0.73 a nm a, and as can be seen from FIG. 2 (c), the WSe was obtained 2 Substantially consistent with the theoretical monolayer thickness.
By comparing FIG. 3 (a) WSe 2 Is measured to have a spacing of 0.28. 0.28 nm, corresponding to WSe 2 This is consistent with the results in FIG. 3 (b) SAED. Pd/WSe can be seen from FIG. 3 (c-g) 2 Uniform contact between the two.
Test example 2
The schottky junction transistors prepared in examples 1 to 3 and comparative example 1 were subjected to an electrical property analysis, and the results are shown in fig. 4 to 6.
As can be seen from FIG. 4, WSe was obtained after contact with 1nm, 3nm, 5nm Pd film 2 The transfer curve of (c) changes from bipolar to p-type, indicating that holes act as carriers. This variation has a significant enhancement with Pd layer thickness, up to 10 a current rise for the device -9 A, the on/off current is raised by several orders of magnitude from the corresponding, and the turn-off capability is correspondingly enhanced.
As can be seen from FIG. 5, in the formation of Pd/WSe 2 Variation of output characteristics before and after contact, i.e. Pd/WSe formation 2 After contact, the transistor has the ability to rectify. The output characteristic of a field effect transistor is used to characterize the relationship between the drain current and drain-source voltage of the transistor at a particular gate-source voltage, i.e., the output performance of the transistor. Specifically, the output characteristic curve reflects the drain current as a function of drain-source voltage at different gate-source voltages. By analyzing the output characteristic curve, the key performance parameters such as the working state, amplifying capability, saturation characteristic and the like of the transistor can be known, and an important reference is provided for circuit design.
As can be seen from FIG. 6, the Pd/WSe prepared in example 1 2 The planar structure of the device of the schottky transistor is schematically shown, as can also be seen from fig. 6, by WSe 2 The depletion region resistance in the layer is much higher than elsewhere, which results in the applied voltage acting almost on the WSe 2 And over the depletion region of the layer. When paired Pd/WSe-based 2 When +0.1V voltage is applied to the schottky transistor, the hole barrier on the semiconductor side increases, resulting in a decrease in forward current. This stable space charge creates a built-in electric field that is enhanced with simultaneous widening of the depletion region, which results in a rectifying action.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (10)
1. The preparation method of the palladium/tungsten diselenide Schottky transistor is characterized by comprising the following steps of:
(1) By WO 2.9 The solution is used for carrying out pre-buried seed crystal treatment on the pretreated substrate, and chemical vapor deposition method is adopted to form the substrate with pre-buried seed crystalLong WSe 2 Obtaining a substrate/tungsten diselenide film;
(2) Spin-coating PMMA on the substrate/tungsten diselenide film, heating to obtain the substrate/tungsten diselenide/PMMA film, and then removing the substrate by alkali etching to obtain the tungsten diselenide/PMMA film;
(3) Depositing metal palladium on the surface of the substrate to obtain a substrate/palladium film;
(4) Transferring the tungsten diselenide/PMMA film in the step (2) onto a substrate/palladium film, and heating to obtain the substrate/Pd/tungsten diselenide/PMMA;
(5) Placing the substrate/Pd/tungsten diselenide/PMMA in acetone to wash off the PMMA, and heating to obtain the substrate/Pd/tungsten diselenide;
(6) Evaporating an Au electrode and a Ti electrode on the surface of the substrate/Pd/tungsten diselenide to obtain a Pd/tungsten diselenide Schottky transistor;
the substrate is Si/SiO 2 The method comprises the steps of carrying out a first treatment on the surface of the The grid electrode of the palladium/tungsten diselenide Schottky transistor is Si in the substrate; palladium film used in palladium/tungsten diselenide Schottky transistor channel and WSe 2 Together as a channel transconductance material for the transistor.
2. The method of manufacturing a palladium/tungsten diselenide schottky transistor of claim 1 wherein said WO 2.9 The concentration of the solution was 0.003g/L.
3. The method of fabricating a palladium/tungsten diselenide schottky transistor of claim 1 wherein in step (1), chemical vapor deposition is used to grow WSe on a substrate with embedded seed crystals 2 The operation of (1) is as follows: reversely buckling a substrate with pre-buried seed crystals on WO 2.9 And (3) forming contact on the powder, placing the powder in a high temperature area, placing selenium powder in a low temperature area, introducing mixed gas of hydrogen and argon, heating and raising the temperature, and maintaining the temperature for tungsten diselenide growth to obtain the substrate/tungsten diselenide film.
4. The method of manufacturing a palladium/tungsten diselenide schottky transistor of claim 3 wherein WO 2.9 Powder and method for producing the sameThe mass ratio of the selenium powder is 9:50; in the mixed gas, the volume ratio of argon to hydrogen is 10:1; the heating temperature-rising time is 10min, the temperature of a high temperature area after heating temperature-rising is 800-850 ℃, and the temperature of a low temperature area is 550-650 ℃; the growth time of the tungsten diselenide is 8-12min.
5. The method of fabricating a palladium/tungsten diselenide schottky transistor of claim 1 wherein in step (2), spin-coating parameters are: the coating is firstly rotated for 10s at 600r/min and then is coated for 50s at a rotating speed of 1000-1500 r/min.
6. The method of fabricating a palladium/tungsten diselenide schottky transistor according to claim 1, wherein in the step (2), the thickness of the PMMA film in the substrate/tungsten diselenide/PMMA film is 100-300nm;
the heating time is 50-70deg.C, and the heating time is 8-12min.
7. The method of fabricating a palladium/tungsten diselenide schottky transistor of claim 1 wherein in step (3), the method of immersing the surface of the substrate with metallic palladium is electron beam evaporation; the thickness of the palladium film in the substrate/palladium film is 1-5nm.
8. The method of manufacturing a palladium/tungsten diselenide schottky transistor of claim 1 wherein in step (5), the heating temperature is 50-70 ℃ and the heating time is 8-12min.
9. The method of fabricating a palladium/tungsten diselenide schottky transistor of claim 1 wherein in step (6), the Au electrode has a thickness of 5nm and the ti electrode has a thickness of 50nm.
10. The palladium/tungsten diselenide schottky transistor prepared by the preparation method of any one of claims 1 to 9.
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