CN117316768A

CN117316768A - Volume-free fluorine doping method

Info

Publication number: CN117316768A
Application number: CN202310529835.5A
Authority: CN
Inventors: 陈学儒; 徐志安; 林宗达; 赖蓓盈; 许家玮
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-08-24
Filing date: 2023-05-11
Publication date: 2023-12-29

Abstract

The present disclosure relates to a volumetric-free fluorine incorporation method. A method comprising: removing the dummy gate stack to form a trench between the gate spacers; depositing a gate dielectric extending into the trench; and performing a first treatment process on the gate dielectric. The first treatment process is performed using a fluorine-containing gas. A first drive-in process is performed to drive fluorine in the fluorine-containing gas into the gate dielectric. The method further comprises the steps of: performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas; and performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric. After the second drive-in process, a conductive layer is formed to fill the trench.

Description

Volume-free fluorine doping method

Technical Field

The present disclosure relates to a volumetric-free fluorine incorporation method.

Background

Semiconductor devices are used in a variety of electronic applications such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by: an insulating or dielectric layer, a conductive layer, and a semiconductor material layer are sequentially deposited over a semiconductor substrate, and the various material layers are patterned using photolithography to form circuit components and elements thereon.

The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems and requirements arise that should be resolved.

Disclosure of Invention

According to one embodiment of the present disclosure, there is provided a method of forming a semiconductor device, comprising: removing the dummy gate stack to form a trench between the gate spacers; depositing a gate dielectric extending into the trench; performing a first treatment process on the gate dielectric, wherein the first treatment process is performed using a fluorine-containing gas; performing a first drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric; performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas; performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric; and forming a conductive layer to fill the trench after the second drive-in process.

According to another embodiment of the present disclosure, there is provided a method of forming a semiconductor device, including: forming a dummy gate stack on a top surface and sidewalls of a multi-layer stack, wherein the multi-layer stack includes a plurality of sacrificial layers and a plurality of nanostructures positioned alternately; removing the dummy gate stack to form a recess in the dielectric layer; removing the plurality of sacrificial layers; depositing a gate dielectric around the plurality of nanostructures; depositing a work function layer on the gate dielectric; executing a plurality of loops, wherein each loop of the plurality of loops comprises: forming a plurality of fluorine-containing layers, each fluorine-containing layer being on one of the gate dielectrics; driving fluorine in the plurality of fluorine-containing layers into the gate dielectric; and removing the plurality of fluorine-containing layers; and forming a conductive layer after the plurality of cycles, wherein the conductive layer includes portions in gaps between the plurality of nanostructures.

According to another embodiment of the present disclosure, there is provided a method of forming a semiconductor device, including: forming a nanostructure in a trench, wherein gate spacers are located on opposite sides of the trench; depositing a gate dielectric extending into the trench to surround the nanostructure, wherein the gate dielectric comprises a high-k dielectric material; and performing a plurality of cycles after depositing the gate dielectric, wherein each cycle of the plurality of cycles comprises: use WF for use in the world ₆ Performing a treatment process on the gate dielectric as a first process gas; and after the treatment process, using NF ₃ An etching process is performed as a second process gas.

Drawings

Aspects of the disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawing figures. It should be noted that the various features are not drawn to scale according to industry standard practices. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-4, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 11A, 11B, 12A, 12B, 13A, 13B, 14-18, 19A, 19B, 20A, 20B, 21A, 21B, 21C, 21D, and 21E illustrate intermediate stages of forming a Gate All Around (GAA) transistor according to some embodiments.

Fig. 22-25 illustrate some fluorine incorporation processes according to some embodiments.

Fig. 26-27 illustrate distributions of atomic percent fluorine according to some embodiments.

Figure 28 illustrates a process flow for forming GAA transistors according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature on or over a second feature includes forming embodiments of the first feature and the second feature in direct contact, and may also include forming additional features between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms such as "beneath," "below," "under," "overlying," "upper" and the like may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other directions) and the spatially relative descriptors used herein interpreted accordingly.

Methods of incorporating fluorine into a gate dielectric in a transistor are provided. According to some embodiments, nanostructures are formed. A plurality of gate dielectrics including a plurality of high-k dielectric layers are formed over the nanostructures. A fluorine incorporation process is performed to incorporate fluorine into the high-k dielectric layer such that the high-k dielectric layer may be passivated and the defect therein repaired. The fluorine incorporation process may include a removal process so that the fluorine incorporation process does not result in the formation of additional layers in the gaps between the nanostructures. Thus, the gap can be filled with the conductive layer without difficulty.

In the description of the present disclosure, gate All Around (GAA) transistors are provided to explain the concepts of the present disclosure. Embodiments of the present disclosure may also be applied to other types of transistors, such as planar transistors, fin field effect transistors (finfets), and the like. The embodiments discussed herein are provided for the purpose of providing examples to enable or use the subject matter of the present disclosure, and those of ordinary skill in the art will readily appreciate modifications that may be made while remaining within the intended scope of the various embodiments. Like reference numerals are used to denote like elements throughout the various views and illustrative embodiments. Although method embodiments may be discussed as being performed in a specific order, other method embodiments may be performed in any logical order.

Fig. 1-4, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 11A, 11B, 12A, 12B, 13A, 13B, 14-18, 19A, 19B, 20A, 20B, 21A, 21B, 21C, 21D, and 21E illustrate various views at intermediate stages in forming GAA transistors according to some embodiments. The corresponding process is also schematically reflected in the process flow 200 shown in fig. 28.

Referring to FIG. 1, a perspective view of a wafer 10 is shown. Wafer 10 includes a multi-layer structure including a multi-layer stack 22 on a substrate 20. According to some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, etc., and other substrates and/or structures may be used, such as semiconductor-on-insulator (SOI), strained SOI, silicon germanium-on-insulator, etc. The substrate 20 may be doped as a p-type semiconductor, although in other embodiments it may be doped as an n-type semiconductor.

According to some embodiments, the multi-layer stack 22 is formed by a series of deposition processes for depositing alternating materials. The corresponding process is shown as process 202 in process flow 200 shown in fig. 28. According to some embodiments, the multi-layer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

According to some embodiments, the first semiconductor material of the first layer 22A is formed of or includes SiGe, ge, si, gaAs, inSb, gaSb, inaias, inGaAs, gaSbP, gaAsSb, etc. According to some embodiments, the deposition of the first layer 22A (e.g., siGe) is by epitaxial growth, and the corresponding deposition method may be Vapor Phase Epitaxy (VPE), molecular Beam Epitaxy (MBE), chemical Vapor Deposition (CVD), low Pressure CVD (LPCVD), atomic Layer Deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced Pressure CVD (RPCVD), or the like. According to some embodiments, the first layer 22A is formed to be aboutAnd about->A first thickness in the range between. However, any suitable thickness may be used while remaining within the scope of the embodiments.

Once the first layer 22A has been deposited over the substrate 20, a second layer 22B is deposited over the first layer 22A. According to some embodiments, the second layer 22B is formed of or includes a second semiconductor material, such as Si, siGe, ge, gaAs, inSb, gaSb, inaias, inGaAs, gaSbP, gaAsSb, combinations thereof, or the like, wherein the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments in which the first layer 22A is silicon germanium, the second layer 22B may be formed of silicon, and vice versa. It will be appreciated that any suitable combination of materials may be used for the first layer 22A and the second layer 22B.

According to some embodiments, the second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to a similar thickness as the first layer 22A. The second layer 22B may also be formed to a different thickness than the first layer 22A. According to some embodiments, second layer 22B may be formed, for example, at aboutAnd about->A second thickness in the range between.

Once the second layer 22B has been formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multi-layer stack 22 until the desired topmost layer of the multi-layer stack 22 has been formed. According to some embodiments, the first layers 22A have the same or similar thickness as each other and the second layers 22B have the same or similar thickness as each other. The first layer 22A may also have the same or different thickness as the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process and is alternatively referred to as a sacrificial layer 22A throughout the specification. According to an alternative embodiment, the second layer 22B is sacrificial and is removed in a subsequent process.

According to some embodiments, some pad oxide layers and hard mask layers (not shown) are formed over the multi-layer stack 22. These layers are patterned and used for subsequent patterning of the multi-layer stack 22.

Referring to fig. 2, a portion of the multi-layer stack 22 and underlying substrate 20 are patterned in an etching process(s) to form trenches 23. The corresponding process is shown as process 204 in process flow 200 shown in fig. 28. The trench 23 extends into the substrate 20. The remainder of the multi-layer stack is referred to hereinafter as multi-layer stack 22'. Below the multi-layer stack 22', portions of the substrate 20 are left behind and are referred to hereinafter as substrate strips 20'. The multi-layer stack 22' includes semiconductor layers 22A and 22B. Hereinafter, semiconductor layer 22A may be alternatively referred to as a sacrificial layer, and semiconductor layer 22B may be alternatively referred to as a nanostructure. Portions of the multi-layer stack 22 'and underlying substrate strips 20' are collectively referred to as semiconductor strips 24.

In the above embodiments, the GAA transistor structure may be patterned by any suitable method. For example, one or more lithographic processes may be used to pattern structures, including double patterning or multiple patterning processes. Typically, a dual-pattern or multi-pattern process combines a lithographic and a self-aligned process, allowing for creation of patterns with a smaller pitch than, for example, what can be obtained using a single direct lithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate, and a photolithography process is used to pattern the sacrificial layer. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers can then be used to pattern the GAA structure.

Fig. 3 illustrates the formation of isolation regions 26, which isolation regions 26 are also referred to throughout this specification as Shallow Trench Isolation (STI) regions. The corresponding process is shown as process 206 in process flow 200 shown in fig. 28. STI region 26 may include liner oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high Density Plasma Chemical Vapor Deposition (HDPCVD), CVD, or the like. STI region 26 may also include a dielectric material over the liner oxide, wherein the dielectric material may be formed using Flowable Chemical Vapor Deposition (FCVD), spin-on, HDPCVD, or the like. A planarization process, such as a Chemical Mechanical Polishing (CMP) process or a mechanical polishing process, may then be performed to level the top surface of the dielectric material and the remainder of the dielectric material is STI regions 26.

STI region 26 is then recessed such that the top of semiconductor stripe 24 protrudes above the top surface 26T of the remainder of STI region 26 to form protruding fin 28. Protruding fins 28 include the top of the multi-layer stack 22 'and substrate strip 20'. The recess of STI region 26 may Is performed by a dry etching process in which, for example, NF ₃ And NH ₃ Is used as the etching gas. During the etching process, the plasma body may be generated. Argon may also be included. In accordance with an alternative embodiment of the present disclosure, the recessing of STI regions 26 is performed by a wet etching process. For example, the etching chemistry may include HF.

Referring to fig. 4, a dummy gate stack 30 and gate spacers 38 are formed on the top surface and sidewalls of (protruding) fin 28. The corresponding process is shown as process 208 in process flow 200 shown in fig. 28. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 over the dummy gate dielectric 32. The dummy gate dielectric 32 may be formed by: the surface portions of protruding fins 28 are oxidized to form an oxide layer, or a dielectric layer such as a silicon oxide layer is deposited. For example, the dummy gate electrode 34 may be formed using polycrystalline silicon or amorphous silicon, and other materials such as amorphous carbon may also be used. Each dummy gate stack 30 may also include a hard mask layer(s) 36 over the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or multiple layers thereof. The dummy gate stack 30 may span a single or multiple protruding fins 28 and STI regions 26 between the protruding fins 28. The length direction of the dummy gate stack 30 is perpendicular to the length direction of the protruding fins 28. The formation of the dummy gate stack 30 includes: a dummy gate dielectric layer is formed, a dummy gate electrode layer is deposited over the dummy gate dielectric layer, one or more hard mask layers are deposited, and the formed layers are then patterned by a patterning process(s).

Next, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. According to some embodiments of the present disclosure, the gate spacers 38 are made of a material such as silicon nitride (SiN), silicon oxide (SiO ₂ ) Dielectric materials of silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), and the like, and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers. The process of forming the gate spacers 38 may include: depositing one or more dielectric layers andand then performing a anisotropic etching process(s) on the dielectric layer(s). The remainder of the dielectric layer(s) is gate spacer 38.

Fig. 5A and 5B show cross-sectional views of the structure shown in fig. 4. Fig. 5A shows a reference section A1-A1 in fig. 4 that cuts through the portion of the protruding fin 28 not covered by the dummy gate stack 30 and the gate spacers 38 and is perpendicular to the gate length direction. Gate spacers 38 are also shown on the sidewalls of protruding fins 28. Fig. 5B shows a reference section B-B in fig. 4, which is parallel to the length direction of the protruding fin 28.

Referring to fig. 6A and 6B, portions of protruding fins 28 not directly below dummy gate stack 30 and gate spacers 38 are recessed by an etching process to form recesses 42. The corresponding process is shown as process 210 in process flow 200 shown in fig. 28. For example, C may be used ₂ F ₆ ，CF ₄ ，SO ₂ ，HBr、Cl ₂ And O ₂ HBr, cl ₂ 、O ₂ And CH (CH) ₂ F ₂ A dry etching process is performed to etch the multi-layer semiconductor stack 22 'and underlying substrate strip 20'. The bottom of recess 42 is at least flush with the bottom of multilayer semiconductor stack 22', or may be lower than the bottom of multilayer semiconductor stack 22' (as shown in fig. 6B). The etching may be anisotropic such that the sidewalls of the multi-layer semiconductor stack 22' facing the recess 42 are vertical and straight, as shown in fig. 6B.

Referring to fig. 7A and 7B, the sacrificial semiconductor layer 22A is laterally recessed to form a lateral recess 41, which lateral recess 41 is recessed from the edges of the respective upper and lower nanostructures 22B. The corresponding process is shown as process 212 in process flow 200 shown in fig. 28. The lateral recessing of the sacrificial semiconductor layer 22A may be achieved by a wet etching process using an etchant that is more selective to the material of the sacrificial semiconductor layer 22A (e.g., silicon germanium (SiGe)) relative to the material of the nanostructures 22B and the substrate 20 (e.g., silicon (Si)). For example, in embodiments where the sacrificial semiconductor layer 22A is formed of silicon germanium and the nanostructures 22B are formed of silicon, the wet etching process may be performed using an etchant such as hydrochloric acid (HCl). The wet etching process may be performed using a dipping process, a spraying process, etc., and may be performed using any suitable process temperature (e.g., between about 400 ℃ and about 600 ℃) and a suitable process time (e.g., between about 100 seconds and about 1,000 seconds). According to alternative embodiments, the lateral recessing of the sacrificial semiconductor layer 22A is performed by a isotropic dry etching process, or a combination of dry and wet etching processes.

Fig. 8A and 8B illustrate the formation of the inner spacer 44. The corresponding process is shown as process 214 in process flow 200 shown in fig. 28. The forming process comprises the following steps: the spacer layer extending into the recess 41 is deposited and an etching process is performed to remove the portion of the inner spacer layer outside the recess 41, leaving the inner spacer 44 in the recess 41. The inner spacer 44 may be formed of, or include, siOCN, siON, siOC, siCN, or the like. The inner spacers 44 may also be porous such that they have a lower k value, e.g., lower than about 3.5. According to some embodiments, the etching of the spacer layer may be performed by a wet etching process, wherein the etching chemistry may include H ₂ SO ₄ Diluted HF, ammonia solution (NH) ₄ OH, ammonia in water), or the like, or a combination thereof.

Referring to fig. 9A and 9B, epitaxial source/drain regions 48 are formed in the recesses 42. The corresponding process is shown as process 216 in process flow 200 shown in fig. 28. According to some embodiments, the source/drain regions 48 may stress the nanostructures 22B that serve as channels for the respective GAA transistors, thereby improving performance. According to some embodiments, the respective transistors are n-type and the epitaxial source/drain regions 48 are formed accordingly n-type by doping the n-type dopants. For example, silicon phosphorus (SiP), silicon carbon phosphorus (SiCp), and the like may be grown to form epitaxial source/drain regions 48. After recess 42 is filled with epitaxial region 48, further epitaxial growth of epitaxial region 48 causes epitaxial region 48 to expand horizontally and facets may be formed. Further growth of epitaxial regions 48 may also be such that adjacent epitaxial regions 48 merge with one another.

After the epitaxial process, the epitaxial region 48 may be further implanted with n-type impurities to form source and drain regions, which are also denoted by reference numeral 48. According to an alternative embodiment of the present disclosure, the implantation process is skipped when epitaxial region 48 is in-situ doped with n-type impurities during the epitaxial process, and epitaxial region 48 is also a source/drain region.

Fig. 10A, 10B, and 10C show cross-sectional views of the structure after formation of a Contact Etch Stop Layer (CESL) 50 and an interlayer dielectric (ILD) 52. Fig. 10A, 10B and 10C are obtained by the same sections as the sections A2-A2, B-B and A1-A1 in fig. 4, respectively. The corresponding process is shown as process 218 in process flow 200 shown in fig. 28. The CESL 50 may be formed of silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed using CVD, ALD, or the like. ILD 52 may comprise an dielectric material formed using, for example, FCVD, spin-on, CVD, or any other suitable deposition method. ILD 52 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material formed using tetraethyl orthosilicate (TEOS) as a precursor, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped Silicate Glass (USG), or the like.

In a subsequent process, a replacement gate stack is formed to replace the dummy gate stack 30. Referring to fig. 11A and 11B, a planarization process such as a CMP process or a mechanical polishing process is performed to make the top surface of the ILD 52 flush. The corresponding process is shown as process 220 in process flow 200 shown in fig. 28. According to some embodiments, the planarization process may remove the hard mask 36 to expose the dummy gate electrode 34, as shown in fig. 11B. According to alternative embodiments, the planarization process may expose the hard mask 36 and stop on the hard mask 36. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 34 (or hard mask 36), gate spacers 38, and ILD 52 are level with each other within process variations.

Next, the dummy gate electrode 34 (and hard mask 36, if any) is removed in one or more etching processes, thereby forming a recess 58, as shown in fig. 12A and 12B. The corresponding process is shown as process 222 in process flow 200 shown in fig. 28. Portions of the dummy gate dielectric 32 in the recess 58 are also removed. According to some embodiments, the dummy gate electrode 34 and the dummy gate dielectric 32 are removed by a dry etching process. For example, the etching process may be performed using a reactive gas(s) that selectively etches the dummy gate electrode 34 at a faster rate than the ILD 52. Each recess 58 exposes and/or covers a portion of the multi-layer stack 22' that includes a future channel region in a subsequently completed nanofet. Respective portions of the multi-layer stack 22' are located between adjacent pairs of epitaxial source/drain regions 48.

Sacrificial layer 22A is then removed to extend recesses 58 between nanostructures 22B, and the resulting structure is shown in fig. 13A and 13B. The corresponding process is shown as process 224 in process flow 200 shown in fig. 28. The sacrificial layer 22A may be removed by performing isotropic etching processes (e.g., wet etching processes) using an etchant having selectivity to the material of the sacrificial layer 22A. The nanostructure 22B, substrate 20, STI region 26 remain relatively unetched compared to sacrificial layer 22A. According to some embodiments in which the sacrificial layer 22A comprises, for example, siGe and the nanostructure 22B comprises, for example, si or SiC, tetramethyl ammonium hydroxide (TMAH), ammonium hydroxide (NH may be used ₄ OH), and the like, the sacrifice layer 22A is removed. It should be appreciated that while fig. 13A and subsequent figures show the cross-section of the nanostructure 22B as rectangular, the nanostructure 22B may have rounded corners, as shown by the dashed lines in fig. 13A.

Referring to fig. 14, a gate dielectric 62 is formed. The corresponding process is shown as process 226 in process flow 200 shown in fig. 28. According to some embodiments, each gate dielectric 62 includes an interface layer 62A and a high-k dielectric layer 62B on interface layer 62A. Interface layer 62A may be formed of or include silicon oxide, which may be deposited by a conformal deposition process such as ALD or CVD. According to an alternative embodiment, interface layer 62A is formed by thermal oxidation. When formed by thermal oxidation, the portion of interfacial layer 62A on the top surface of STI region 26 will not form. According to some embodiments, high-k dielectric layer 62B includes one or more dielectric layers. For example, the high-k dielectric layer(s) 62B may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof.

Fig. 15 shows the formation of the work function layer 64. The corresponding process is shown as process 228 in process flow 200 shown in fig. 28. The work function layer 64 may be an n-type work function layer when the transistor being produced is an n-type transistor, or the work function layer 64 may be a p-type work function layer when the transistor being produced is a p-type transistor. According to some embodiments, the work function layer 64 is an n-type work function layer, and may be formed of or include TiAlC, tiAl, tiAlN, taAl, taAlN, taAlC, and the like. Alternatively, the work function layer 64 is a p-type work function layer, and may be formed of or include TiN, taN, tiSiN, WCN, MOCN, or combinations thereof. According to some embodiments, a cap layer (not shown), such as a TiN layer or TiSiN layer, is formed between (and in contact with) the work function layer 64 and the gate dielectric 62. According to an alternative embodiment, the work function layer 64 is in physical contact with the gate dielectric 62 without a cap layer therebetween. The formation of the work function layer 64 may include Atomic Layer Deposition (ALD), chemical Vapor Deposition (CVD), and the like.

According to some embodiments, as shown in fig. 15, the work function layer 64 is formed prior to the subsequent fluorine incorporation process 68 shown in fig. 16. The corresponding fluorine incorporation process 68 will also be discussed in subsequent paragraphs with reference to fig. 22 and 24. According to an alternative embodiment, the work function layer 64 is formed after a subsequent fluorine incorporation process 68 as shown in fig. 16. The corresponding fluorine incorporation process 68 will be discussed in the subsequent paragraphs with reference to fig. 23 and 25. The work function layer 64 is shown as a dashed line in fig. 15 to indicate that the work function layer 64 may or may not be formed at this time and when the fluorine incorporation process 68 is performed.

Referring to fig. 16, a fluorine incorporation process 68 is performed. The corresponding process is shown as process 230 in process flow 200 shown in fig. 28. The fluorine incorporation process 68 is used to incorporate fluorine into the high-k dielectric layer 62B such that the high-k dielectric layer 62B is passivated and the defects in the high-k dielectric layer 62B are repaired. The fluorine-containing layer 66 may be formed by a fluorine incorporation process 68, according to some embodiments.

Fig. 22-24 illustrate details of some example fluorine incorporation processes 68 according to various embodiments. The portions of the structure shown in fig. 22-24 may correspond to the regions 70 as shown in fig. 16.

Fig. 22 shows a fluorine incorporation process 68 performed after formation of the work function layer 64. Thus, the work function layer 64 is a surface layer with the gate dielectric layer 62 (including the high-k dielectric layer 62B and the interface layer 62A) and the nanostructures 22B below the work function layer 64. The fluorine incorporation process 68 may include a use including tungsten fluoride (WF) ₆ ) A fluorine-containing gas, and a treatment process 302 performed on the fluorine-containing gas. According to some embodiments, the treatment process 302 is performed in a vacuum chamber and is performed using a pure fluorine-containing gas without the addition of other gases, or is performed using a substantially pure fluorine-containing gas, e.g., an atomic percent of fluorine-containing gas of greater than about 90%, 95%, or 99% of all gases in the vacuum chamber. According to an alternative embodiment, a carrier gas is added to the fluorine-containing gas. The carrier gas may include N ₂ Ar, he or a combination thereof. The treatment process 302 may also be performed in a furnace, which may be vacuum or non-vacuum.

According to some embodiments, the treatment process 302 includes a thermal treatment process performed at an elevated wafer temperature, which may be in a range between about 250 ℃ and about 600 ℃. According to an alternative embodiment, the process 302 includes plasma processing performed in a vacuum chamber. The pressure in the vacuum chamber may be in a range between about 0.5Torr and about 50 Torr. The duration of the treatment process 302 may range between about 1 second and about 600 seconds. According to yet other alternative embodiments, the treatment process 302 includes both a thermal treatment process and a plasma treatment process.

As a result of the treatment process 302, fluorine-containing gas may be adsorbed at the surface of the work function layer 64, which may (or may not) result in deposition of the fluorine-containing layer 66. When using WF ₆ When fluorine-containing layer 66 also includes tungsten. Other gases (e.g. SiH ₄ 、B ₂ H ₆ 、H ₂ Etc., or combinations thereof) may also be added to the process gas used in the treatment process 302 to aid in the deposition of the fluorine-containing layer 66. The resulting fluorine-containing layer 66 may be a continuous layer that overlies the underlying layerThe cap range is equal to 100%. Alternatively, the fluorine-containing layer 66 may have a coverage of less than 100% of the underlying layer, with portions of the underlying layer exposed through the fluorine-containing layer 66, as shown in FIG. 22.

Referring further to fig. 22, a fluorine drive-in process 304 is performed. The fluorine drive-in process 304 may be performed in-situ in the same environment (e.g., vacuum chamber or furnace) in which the treatment process 302 is performed. Alternatively, the fluorine drive-in process 304 may be performed ex situ in an environment different from the environment in which the treatment process 302 is performed. For example, the fluorine drive-in process 304 may be performed in another vacuum chamber or furnace. The fluorine drive-in process 304 may be performed at an elevated wafer temperature, which may be greater than or equal to the wafer temperature of the treatment process 302. For example, the wafer temperature in the fluorine drive-in process 304 may be in a range between about 400 ℃ and about 650 ℃. During the fluorine drive-in process 304, a material such as N may be conducted ₂ Gases such as Ar, he, ne, etc., to prevent the work function layer 64 from being oxidized.

The fluorine-containing gas used in the treatment process 302 may be stopped during the fluorine drive-in process 304. Alternatively, the fluorine-containing gas is also conducted, but at a flow rate lower than that of the fluorine-containing gas in the process. In the drive-in process 304, the pressure of the vacuum chamber (if used) may be in a range between about 0.5Torr and about 760Torr (atmospheric pressure). The fluorine drive-in process 304 may last for a period of time in a range between about 1 second and about 600 seconds.

According to an alternative embodiment, the fluorine drive-in process is not performed. Since the treatment process 302 includes a thermal treatment process and/or a plasma treatment process, fluorine may still diffuse into the work function layer 64 and the gate dielectric layer 62 during the treatment process 302.

In the fluorine drive-in process 304, fluorine and tungsten are driven (diffused) into the work function layer 64, the gate dielectric 62, and possibly the nanostructures 22B. Tungsten is heavier than fluorine and therefore has a lower diffusion rate than fluorine. Thus, after the fluorine drive-in process 304, the fluorine-containing layer 66 has some non-diffused remaining portions. The residue removal process 306 is performed to remove the residue of the fluorine-containing layer 66. In the residue removal process 306, a fluorine-containing process gas (e.g., WF) is used in the treatment process 302 ₆ ) Stopping. According to some embodiments, a gas comprising nitrogen fluoride (NF may be used ₃ ) Is used to perform the residue removal process 306. According to some embodiments, the residue removal process 306 is performed in a vacuum chamber and is performed using pure or substantially pure etching gas, without the addition of other gases. For example, among all gases in the vacuum chamber, an etching gas (e.g., NF ₃ ) May be greater than about 90%, 95%, or 99% atomic percent. According to an alternative embodiment, a carrier gas is added to the etching gas, e.g. NF ₃ . The carrier gas may include N ₂ Ar, he, etc.

According to some embodiments, the residue removal process 306 includes a thermal etching process performed at an elevated wafer temperature, which may be in a range between about 250 ℃ and about 600 ℃. According to some embodiments, the residue removal process 306 includes a plasma etching process performed in a vacuum chamber. The vacuum chamber pressure may be in a range between about 0.5Torr and about 50 Torr. The remaining fluorine-containing layer 66 may be completely removed as a result of the etching process or may be partially removed leaving only a small residual portion.

The treatment process 302, the fluorine drive-in process 304, and the residue removal process 306 are collectively referred to as a fluorine incorporation cycle 310. According to some embodiments, after the fluorine incorporation cycle 310, the process continues back to the process 302 and one or more fluorine incorporation cycles 310 are performed. The total number of fluorine incorporation cycles 310 may be 2, 3, 4, 5 or more.

The incorporation of fluorine by the fluorine incorporation cycle 310, wherein the fluorine-containing layer 66 is removed in each cycle, has several advantages. The gaps between adjacent nanostructures 22B have a smaller spacing S1 (fig. 15), particularly after formation of the gate dielectric layer 62 and the work function layer 64. The fluorine-containing layer 66 may be thick in order to diffuse enough fluorine into the gate dielectric layer. However, the thick fluorine-containing layer 66 is likely to block gaps, and the fluorine-containing layer 66 deposited on the overlying nanostructure 22B is likely to merge with the fluorine-containing layer 66 deposited on the underlying nanostructure 22B. The merging may prevent subsequent layers from being deposited into the gap, resulting in reduced performance and reduced reliability.

By performing the residue removal process 306 in each fluorine incorporation cycle 310, the gap is cleared before the merging occurs. In addition, the fluorine drive-in process 304 may provide a lower fluorine concentration in the residual fluorine-containing layer 66. By removing the fluorine-containing layer 66 and forming a new fluorine-containing layer 66, fluorine is replenished and more fluorine may diffuse into the high-k dielectric layer 62, thereby improving the efficiency of the defect repair process.

Referring further to fig. 22, after the fluorine incorporation cycle 310, a cleaning process 308 is performed. The cleaning process 308 may remove tungsten from the work function layer 64 if tungsten is not completely removed in the prior residue removal process 306. The cleaning process 308 may include a wet etching process or a dry etching process. According to some embodiments, the cleaning process 308 is performed using an etching chemistry comprising an oxygen-containing agent solution, which may include deionized water and an oxidizing agent(s). For example, the etching chemistry may include H ₂ O ₂ ；DiO ₃ ；NH ₄ OH、H ₂ O ₂ And H ₂ Mixtures of O, NH ₄ OH and O ₃ Is a mixture of (C), HCl and H ₂ O ₂ Is a mixture of (2), HCl and O ₃ And the like. The concentration of the oxidizing agent in the oxygen-containing agent solution can range between about 20% and about 50%. The temperature at which the cleaning process 308 is performed may be in a range between about 18 ℃ and about 80 ℃.

Fig. 23 shows a fluorine incorporation process 68 according to an alternative embodiment. The process shown in fig. 23 is substantially the same as the process shown in fig. 22 except that in fig. 23 a fluorine incorporation process 68 is performed on the gate dielectric layer 62 and is performed prior to forming the work function layer 64. Details of the fluorine incorporation process 68 are not repeated here.

Fig. 24 shows a fluorine incorporation process 68 according to an alternative embodiment. The process shown in fig. 24 is substantially the same as that shown in fig. 22, except that NF ₃ Is used in the treatment process 302 rather than using WF ₆ To perform the process 302. In addition, a residual fluorine-containing layer 66 (which contains adsorbed NF ₃ ) Is thin. After the drive-in process 304, the residue is even thinner. Therefore, no residue is performedAnd (5) a residue removing process.

As shown in fig. 24, a process 302 is performed. The process 302 is substantially the same as the process 302 discussed with reference to fig. 22, except that NF ₃ Substituted WF ₆ As a fluorine-containing gas. After the treatment process 302, the process is stopped, such as NF ₃ Such as a flow of fluorine-containing gas or a reduced flow rate, and the drive-in process 304 is performed. Details of the drive-in process 304 may be found in the drive-in process 304 of FIG. 22. The drive-in process 304 may also be performed at a higher (or equal) wafer temperature than the processing process 302. The treatment process 302 and the drive-in process 304 are collectively referred to as a fluorine incorporation cycle 310. The fluorine incorporation cycle 310 is repeated.

Fig. 25 shows a fluorine incorporation process 68 according to yet other alternative embodiments. The process shown in fig. 25 is substantially the same as the process shown in fig. 24 except that in the process shown in fig. 25, a fluorine incorporation process 68 is performed on the gate dielectric layer 62 and is performed before the work function layer 64 is formed. Details of the fluorine incorporation process 68 may be found in the foregoing discussion and are not repeated here.

Fig. 17 shows the structure after the fluorine incorporation process 68 discussed with reference to fig. 22-25. The work function layer 64 may or may not have been formed in a preceding process. If the work function layer 64 has been formed, the process continues as shown in FIG. 18. Otherwise, if the work function layer 64 is not formed, the work function layer 64 will be formed after the fluorine incorporation process 68 and before the process shown in FIG. 18. The corresponding process is shown as process 232 in process flow 200 shown in fig. 28.

Referring to fig. 18, a conductive layer 78 is formed over the work function layer 64. The corresponding process is shown as process 234 in process flow 200 shown in fig. 28. The conductive layer 78 may or may not include a barrier layer such as a TiN layer. If conductive layer 78 has not been completely filled, conductive layer 78 may further include a filler metal that fills remaining recesses 58. The conductive layer 78 may include a metal-containing material, such as cobalt, ruthenium, aluminum, tungsten, combinations thereof, and/or multilayers thereof.

Referring to fig. 19A and 19B, after filling the recess 58, a planarization process, such as a CMP process or a mechanical polishing process, is performed to remove the excess portions of the material of the gate dielectric 62 and the gate electrode 80, which are over the top surface of the ILD 52. The remaining portion of conductive layer 78 forms part of gate electrode 80. The gate electrode 80 and the gate dielectric 62 are collectively referred to as a gate stack 82.

Next, as shown in fig. 20A and 20B, the gate stack 82 is recessed, forming a recess over the gate stack 82 and between opposing portions of the gate spacers 38. A gate mask 84 (comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, etc.) is filled in each recess, followed by a planarization process to remove the excess portion of dielectric material that extends beyond ILD 52. The corresponding process is shown as process 236 in process flow 200 shown in fig. 28.

As further shown in fig. 20A and 20B, ILD 86 is deposited over ILD 52 and gate mask 84. The corresponding process is shown as process 238 in process flow 200 shown in fig. 28. An etch stop layer (not shown) may or may not be deposited prior to formation of ILD 86. According to some embodiments, ILD 86 is formed by FCVD, CVD, PECVD, or the like. ILD 86 is formed of a dielectric material that may be selected from the group consisting of silicon oxide, PSG, BSG, BPSG, USG, and the like.

In fig. 21A and 21B, ILD 86, ILD 52, CESL 50 and gate mask 84 are etched to form recesses (occupied by contact plugs 88A and 88B) that expose the surface of epitaxial source/drain regions 48 and/or gate stack 82. The recess may be formed by etching using a anisotropic etching process.

After forming the recess, a silicide region 90 is formed over the epitaxial source/drain regions 48 (fig. 21B). The corresponding process is shown as process 240 in process flow 200 shown in fig. 28. According to some embodiments, silicide regions 90 are formed by: a metal layer (not shown) capable of reacting with underlying epitaxial source/drain regions 48 (e.g., silicon germanium, or germanium) is first deposited to form a silicide and/or germanide region, and then a thermal annealing process is performed to form the silicide region 90. The metal may include nickel, cobalt, titanium, tantalum, platinum, tungsten, and the like. The unreacted portion of the deposited metal is then removed, for example by an etching process.

Contact plugs 88B are then formed over the silicide regions 90. In addition, a contact plug 88A (which may also be referred to as a gate contact plug) is also formed in the recess, and is located above the gate electrode 80 and contacts the gate electrode 80. The corresponding process is shown as process 242 in process flow 200 shown in fig. 28. Although fig. 21B shows the contact plugs 88A and 88B on the same cross section, in various embodiments, the contact plugs 88A and 88B may be formed on different cross sections, thereby reducing the risk of shorting to each other. Thus forming GAA transistor 92.

Fig. 21C shows a perspective view of the structure shown in fig. 20A and 20B, wherein the cross-sectional views shown in fig. 21A and 21B are obtained from the cross-sections 21A-21A and 21B-21B in fig. 21C, respectively. Fig. 21D and 21E show horizontal cross-sectional views of the structure shown in fig. 21A, 21B and 21C, wherein the horizontal cross-sectional views are obtained from horizontal planes 21D-21D and 21E-21E in fig. 21B, respectively.

Fig. 26 shows the atomic percent fluorine in the gate stack 82, wherein the X-axis represents the distance in the direction of arrow 94 in fig. 21B, in accordance with some embodiments. Fig. 26 corresponds to an embodiment in which the work function layer 64 is formed prior to performing the fluorine incorporation process 68. Since the fluorine-containing layer 66 (fig. 16, 22 and 24) is removed, the peak atomic percent fluorine is likely to be at the outer surface of the work function layer 64 before the conductive layer 78 is formed. As fluorine diffuses into the conductive layer 78, the peak atomic percent fluorine in the final transistor 92 may be in the work function layer 64 (as shown by dashed line 106) or at the interface between the work function layer 64 and the conductive layer 78 (as shown by solid line 104). Furthermore, the atomic percent fluorine in the conductive layer 78 is likely to be steeper than the atomic percent fluorine in the work function layer 64 and the gate dielectric 62.

Fig. 27 shows the atomic percent fluorine in the gate stack 82, wherein the X-axis also represents the distance in the direction of arrow 94 in fig. 21B, in accordance with some embodiments. Fig. 27 corresponds to an embodiment in which the work function layer 64 is formed after the fluorine incorporation process 68. Since the fluorine-containing layer 66 (fig. 16, 22 and 24) is removed, the peak atomic percent fluorine is likely to be at the outer surface of the gate dielectric 62 prior to forming the conductive layer 78. Due to diffusion, in the final transistor 92, the peak atomic percent fluorine may be in the gate dielectric 62 (as shown by dashed line 110) or at the interface between the gate dielectric 62 and the work function layer 64 (as shown by solid line 108). Furthermore, the atomic percent fluorine in the work function layer 64 and the conductive layer 78 is likely to be steeper than the atomic percent fluorine in the gate dielectric 62.

As can be appreciated by combining fig. 13B and 16, ILD 52 and gate spacer 38 have been formed at the time of performing fluorine incorporation process 68, and thus fluorine is also incorporated. The surface of the fluorine-receiving ILD 52 and gate spacer 38 has a higher fluorine concentration than the deeper portions. For example, in the direction of arrow 95 in fig. 21B, the fluorine concentration may continuously decrease, similarly to the distribution of the left side portion of the fluorine distribution in fig. 26 and 27.

Embodiments of the present disclosure have several advantageous features. Defects in the high-k dielectric layer are repaired by incorporating fluorine in the gate dielectric. The fluorine-containing layer is repeatedly removed by a cyclic fluorine-containing doping process including removal of the fluorine-containing layer, and a new fluorine-containing layer having a higher fluorine concentration is replenished. Thus, the efficiency of adding fluorine to the gate dielectric is higher.

According to some embodiments of the present disclosure, a method comprises: removing the dummy gate stack to form a trench between the gate spacers; depositing a gate dielectric extending into the trench; performing a first treatment process on the gate dielectric, wherein the first treatment process is performed using a fluorine-containing gas; performing a first drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric; performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas; performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric; and forming a conductive layer to fill the trench after the second drive-in process.

In one embodiment, the method further comprises: removing the first fluorine-containing layer formed due to the first process after the first drive-in process; and removing the second fluorine-containing layer formed due to the second treatment process after the second driving process. In one embodiment, the method further comprises: after the second fluorine-containing layer is removed, a cleaning process is performed to further remove residues of the first fluorine-containing layer and the second fluorine-containing layer. In one embodiment, the fluorine-containing gas comprises tungsten fluoride, and the first fluorine-containing layer and the second fluorine-containing layer further comprise tungsten therein.

In one embodiment, the fluorine-containing gas comprises nitrogen fluoride. In one embodiment, the method further comprises: and depositing a work function layer on the gate dielectric, wherein the first and second treatment processes are performed on the work function layer. In one embodiment, the method further comprises: a work function layer is deposited on the gate dielectric after the first and second processing processes. In one embodiment, the first drive-in process includes an annealing process. In one embodiment, the method further comprises: performing a third treatment process on the gate dielectric after the second drive-in process, wherein the third treatment process is performed using the fluorine-containing gas; and performing a third drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric.

According to some embodiments of the present disclosure, a method comprises: forming a dummy gate stack on a top surface and sidewalls of a multi-layer stack, wherein the multi-layer stack includes a plurality of sacrificial layers and a plurality of nanostructures positioned alternately; removing the dummy gate stack to form a recess in the dielectric layer; removing the plurality of sacrificial layers; depositing a gate dielectric around the plurality of nanostructures; depositing a work function layer on the gate dielectric; executing a plurality of loops, wherein each loop of the plurality of loops comprises: forming a plurality of fluorine-containing layers, each fluorine-containing layer being on one of the gate dielectrics; driving fluorine in the plurality of fluorine-containing layers into the gate dielectric; and removing the plurality of fluorine-containing layers; and forming a conductive layer after the plurality of cycles, wherein the conductive layer includes portions in gaps between the plurality of nanostructures.

In one embodiment, forming the plurality of fluorine-containing layers includes using WF ₆ The gate dielectric is treated as a process gas. In one embodiment, the removing the plurality of fluorine-containing layers is using NF ₃ As an etching gas. In one embodiment, the plurality of fluorine-containing layers formed prior to the driving are completely removed in each of the plurality of cycles.

In one embodiment, the fluorine drive-in includes an annealing process. In one embodiment, forming the plurality of fluorine-containing layers is performed at a first wafer temperature, and the fluorine driving-in is performed at a second wafer temperature different from the first wafer temperature. In one embodiment, removing the plurality of fluorine-containing layers is performed by a dry etching process, and wherein the method further comprises: after the plurality of cycles, a wet etching process is performed to etch residues of the plurality of fluorine-containing layers. In one embodiment, the plurality of loops is performed on the work function layer.

According to some embodiments of the present disclosure, a method comprises: forming a nanostructure in a trench, wherein gate spacers are located on opposite sides of the trench; depositing a gate dielectric extending into the trench to surround the nanostructure, wherein the gate dielectric comprises a high-k dielectric material; and performing a plurality of cycles after depositing the gate dielectric, wherein each cycle of the plurality of cycles comprises: use WF for use in the world ₆ Performing a process on the gate dielectric as a first process gas; and after the treatment process, using NF ₃ An etching process is performed as a second process gas. In one embodiment, the method further comprises: an drive-in process is in each of the plurality of cycles, wherein the drive-in process is performed after the treatment process and before the etching process. In one embodiment, the treatment process makes a layer containing tungsten and fluorine remain on the gate dielectric, and wherein,the etching process is such that the tungsten and fluorine containing layer is etched.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Example 1 is a method of forming a semiconductor device, comprising: removing the dummy gate stack to form a trench between the gate spacers; depositing a gate dielectric extending into the trench; performing a first treatment process on the gate dielectric, wherein the first treatment process is performed using a fluorine-containing gas; performing a first drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric; performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas; performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric; and forming a conductive layer to fill the trench after the second drive-in process.

Example 2 is the method of example 1, further comprising: removing the first fluorine-containing layer formed due to the first process after the first drive-in process; and removing the second fluorine-containing layer formed due to the second treatment process after the second driving process.

Example 3 is the method of example 2, further comprising, after removing the second fluorine-containing layer, performing a cleaning process to further remove residues of the first fluorine-containing layer and the second fluorine-containing layer.

Example 4 is the method of example 2, wherein the fluorine-containing gas comprises tungsten fluoride, and the first fluorine-containing layer and the second fluorine-containing layer further comprise tungsten therein.

Example 5 is the method of example 1, wherein the fluorine-containing gas comprises nitrogen fluoride.

Example 6 is the method of example 1, further comprising: and depositing a work function layer on the gate dielectric, wherein the first and second treatment processes are performed on the work function layer.

Example 7 is the method of example 1, further comprising: a work function layer is deposited on the gate dielectric after the first and second processing processes.

Example 8 is the method of example 1, wherein the first drive-in process includes an annealing process.

Example 9 is the method of example 1, further comprising: performing a third treatment process on the gate dielectric after the second drive-in process, wherein the third treatment process is performed using the fluorine-containing gas; and performing a third drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric.

Example 10 is a method of forming a semiconductor device, comprising: forming a dummy gate stack on a top surface and sidewalls of a multi-layer stack, wherein the multi-layer stack includes a plurality of sacrificial layers and a plurality of nanostructures positioned alternately; removing the dummy gate stack to form a recess in the dielectric layer; removing the plurality of sacrificial layers; depositing a gate dielectric around the plurality of nanostructures; depositing a work function layer on the gate dielectric; executing a plurality of loops, wherein each loop of the plurality of loops comprises: forming a plurality of fluorine-containing layers, each fluorine-containing layer being on one of the gate dielectrics; driving fluorine in the plurality of fluorine-containing layers into the gate dielectric; and removing the plurality of fluorine-containing layers; and forming a conductive layer after the plurality of cycles, wherein the conductive layer includes portions in gaps between the plurality of nanostructures.

Example 11 is the method of example 10, wherein forming the plurality of fluorine-containing layers comprises: use WF for use in the world ₆ The gate dielectric is treated as a process gas.

Example 12 is the method of example 11, wherein removing the plurality of fluorine-containing layers is using NF ₃ As an etching gas.

Example 13 is the method of example 10, wherein, in each of the plurality of cycles, the plurality of fluorine-containing layers formed prior to the driving are completely removed.

Example 14 is the method of example 10, wherein the fluorine drive-in comprises an annealing process.

Example 15 is the method of example 14, wherein forming the plurality of fluorine-containing layers is performed at a first wafer temperature, and the fluorine driving-in is performed at a second wafer temperature different from the first wafer temperature.

Example 16 is the method of example 10, wherein removing the plurality of fluorine-containing layers is performed by a dry etching process, and wherein the method further comprises: after the plurality of cycles, a wet etching process is performed to etch residues of the plurality of fluorine-containing layers.

Example 17 is the method of example 10, wherein the plurality of loops is performed on the work function layer.

Example 18 is a method of forming a semiconductor device, comprising: forming a nanostructure in a trench, wherein gate spacers are located on opposite sides of the trench; depositing a gate dielectric extending into the trench to surround the nanostructure, wherein the gate dielectric comprises a high-k dielectric material; and performing a plurality of cycles after depositing the gate dielectric, wherein each cycle of the plurality of cycles comprises: use WF for use in the world ₆ Performing a treatment process on the gate dielectric as a first process gas; and after the treatment process, using NF ₃ An etching process is performed as a second process gas.

Example 19 is the method of example 18, further comprising: an drive-in process in each of the plurality of cycles, wherein the drive-in process is performed after the treatment process and before the etching process.

Example 20 is the method of example 18, wherein the treatment process is such that a layer comprising tungsten and fluorine remains on the gate dielectric, and wherein the etching process is such that the layer comprising tungsten and fluorine is etched.

Claims

1. A method of forming a semiconductor device, comprising:

Removing the dummy gate stack to form a trench between the gate spacers;

depositing a gate dielectric extending into the trench;

performing a first treatment process on the gate dielectric, wherein the first treatment process is performed using a fluorine-containing gas;

performing a first drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric;

performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas;

performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric; a kind of electronic device

After the second drive-in process, a conductive layer is formed to fill the trench.

2. The method of claim 1, further comprising:

removing the first fluorine-containing layer formed due to the first process after the first drive-in process; a kind of electronic device

After the second driving process, the second fluorine-containing layer formed due to the second treatment process is removed.

3. The method of claim 2, further comprising, after removing the second fluorine-containing layer, performing a cleaning process to further remove residues of the first fluorine-containing layer and the second fluorine-containing layer.

4. The method of claim 2, wherein the fluorine-containing gas comprises tungsten fluoride and the first fluorine-containing layer and the second fluorine-containing layer further comprise tungsten therein.

5. The method of claim 1, wherein the fluorine-containing gas comprises nitrogen fluoride.

6. The method of claim 1, further comprising: and depositing a work function layer on the gate dielectric, wherein the first and second treatment processes are performed on the work function layer.

7. The method of claim 1, further comprising: a work function layer is deposited on the gate dielectric after the first and second processing processes.

8. The method of claim 1, wherein the first drive-in process comprises an annealing process.

9. A method of forming a semiconductor device, comprising:

forming a dummy gate stack on a top surface and sidewalls of a multi-layer stack, wherein the multi-layer stack includes a plurality of sacrificial layers and a plurality of nanostructures positioned alternately;

removing the dummy gate stack to form a recess in the dielectric layer;

removing the plurality of sacrificial layers;

depositing a gate dielectric around the plurality of nanostructures;

Depositing a work function layer on the gate dielectric;

executing a plurality of loops, wherein each loop of the plurality of loops comprises:

forming a plurality of fluorine-containing layers, each fluorine-containing layer being on one of the gate dielectrics;

driving fluorine in the plurality of fluorine-containing layers into the gate dielectric; a kind of electronic device

Removing the plurality of fluorine-containing layers; a kind of electronic device

After the plurality of cycles, a conductive layer is formed, wherein the conductive layer includes portions in gaps between the plurality of nanostructures.

10. A method of forming a semiconductor device, comprising:

forming a nanostructure in a trench, wherein gate spacers are located on opposite sides of the trench;

depositing a gate dielectric extending into the trench to surround the nanostructure, wherein the gate dielectric comprises a high-k dielectric material; a kind of electronic device

After depositing the gate dielectric, performing a plurality of cycles, wherein each cycle of the plurality of cycles comprises:

use WF for use in the world ₆ Performing a treatment process on the gate dielectric as a first process gas; a kind of electronic device

After the treatment process, NF is used ₃ An etching process is performed as a second process gas.