CN117280461A

CN117280461A - Semiconductor package structure and method for fabricating the same

Info

Publication number: CN117280461A
Application number: CN202180097973.XA
Authority: CN
Inventors: 郭茂; 徐朋慧; 俞子贇; 张晓东; 黄京; 王珊珊
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-07-09
Filing date: 2021-07-09
Publication date: 2023-12-22
Also published as: WO2023279391A1

Abstract

The present disclosure relates to a semiconductor package structure and a method of fabricating the same. The semiconductor package structure includes: a semiconductor chip (10) having a first face (11) with a conductive region (12) and a passivation layer (60) overlying the first face (11); a first material layer (30) disposed on the passivation layer (60); a molding compound (40) at least comprising a molding layer (41) formed on the first material layer (30), wherein the elastic modulus of the material of the first material layer is smaller than that of the molding compound; and a conductive post (20) electrically coupled to the conductive region (12) through the plastic layer (41) and the first material layer (30).

Description

Semiconductor package structure and method for fabricating the same

Technical Field

The present disclosure relates to the field of semiconductor packaging, and more particularly to a fan-out type package structure and a method of fabricating the same

Background

With the rapid growth of the semiconductor industry, various chip packaging techniques have been proposed for application to different packaged chips. Conventional packaging techniques include, for example, fan-in package (FIP) and Fan-out package (FOP). FIP is smaller in size and is typically used for smaller pin count packaged chips. However, as the functionality of the chip (die) increases, the number of pins required for the chip increases accordingly, and thus more and more packaged chips begin to use FOP.

FOP is one of advanced packages with a large number of I/os and good integration flexibility. In a fan-out wafer level package, the chips are surrounded by a suitable material that expands the footprint of the package to match the rewiring layers (Redistribution Layer, RDL) used to fan out the IO interface. The fan-out wafer level package supports a fan-out area with greater flexibility and a more free solder ball pitch than the fan-in wafer level package. However, the packaging effect of conventional packaging processes such as FOP is still not ideal.

Disclosure of Invention

It is an object of the present disclosure to provide an improved semiconductor package structure that at least alleviates the drawbacks of the prior art semiconductor package structure that are prone to cracking during the packaging process and/or improves the reliability of the semiconductor package structure.

According to a first aspect of the present disclosure, a semiconductor molding compound is provided. The semiconductor plastic package material comprises: a semiconductor chip having a first face with a conductive region and a passivation layer overlying the first face; the first material layer is arranged on the passivation layer; the plastic packaging material at least comprises a plastic packaging layer formed on the first material layer, wherein the elastic modulus of the material of the first material layer is smaller than that of the plastic packaging material; and a conductive post electrically coupled to the conductive region through the plastic layer and the first material layer.

With the semiconductor structure of the present disclosure, the conductive pillars penetrate two materials of different elastic moduli. By virtue of the mixing of the two materials, stresses from the package can be relieved, the risk of ELK cracking is reduced, the resistance to conductive pillar cracking is enhanced, and the reliability of the package is improved.

In some embodiments, the molding compound encapsulates at least a side portion of the semiconductor chip and the first material layer to form a molded body.

In some embodiments, further comprising: and a rewiring layer positioned on the plastic sealing layer, wherein the circuits in the rewiring layer are in electrical contact with the conductive posts. In this way, the two materials of different moduli of elasticity described above can be defined between the first side of the semiconductor chip and the redistribution layer to achieve a more compact semiconductor molding compound.

In some embodiments, the first material layer comprises a polymer layer; and the thickness of the plastic sealing layer is larger than that of the polymer layer. In these embodiments, a relatively thin polymer layer may be sufficient to buffer stresses from the encapsulation material. Meanwhile, the semiconductor chip can be protected by the packaging material with a larger elastic modulus.

In some embodiments, the ratio of the thickness of the plastic layer to the thickness of the polymer layer is in the range of 4:1 to 1:1. With this thickness ratio, the stress from the package can be further optimally relieved, reducing the risk of cracking

In some embodiments, further comprising: and the metal layer is arranged between the conductive region and the conductive column. The provision of the metal layer can improve adhesion and conductivity of the conductive pillars on the conductive regions of the semiconductor chip.

According to a second aspect of the present disclosure, a circuit assembly is provided. The circuit assembly includes: a circuit board; and the semiconductor package structure according to the first aspect, mounted on the circuit board.

According to a third aspect of the present disclosure, an electronic device is provided. The electronic device includes: a power supply circuit; and a circuit assembly according to the second aspect, powered by the power supply circuit.

According to a fourth aspect of the present disclosure, a method of fabricating a semiconductor package is provided. The preparation method comprises the following steps: providing a semiconductor chip having a first face with a conductive region and a passivation layer covering the first face, the passivation layer having a first opening exposing the conductive region; forming a first material layer having a second opening on the passivation layer, the second opening and the first opening being aligned with each other; forming a conductive pillar on the conductive region exposed by the second opening such that the conductive pillar is electrically coupled to the conductive region; and plastic packaging the semiconductor chip with the first material layer and the conductive columns to form a plastic packaging material, wherein the plastic packaging material at least comprises a plastic packaging layer formed on the first material layer, the conductive columns penetrate through the plastic packaging layer and the first material layer and are electrically coupled with the conductive areas, and the elastic modulus of the material of the first material layer is smaller than that of the plastic packaging material.

In some embodiments, further comprising: molding the semiconductor chip with the first material layer includes: so that the plastic package material at least wraps the side part of the semiconductor chip and the first material layer.

In some embodiments, further comprising: a redistribution layer is formed on the plastic layer, wherein the wires in the redistribution layer are electrically coupled with the conductive pillars exposed from the plastic layer.

In some embodiments, forming a conductive pillar over the conductive region exposed by the second opening comprises: forming a metal layer on the exposed conductive region; and forming the conductive pillars on the metal layer.

In some embodiments, forming the conductive pillars on the metal layer comprises: forming a mask layer on the metal layer; patterning the mask layer to form conductive pillar openings, the conductive pillar openings being aligned with the conductive regions; forming the conductive posts within the conductive post openings; removing the mask layer; and etching the exposed metal layer.

In some embodiments, the first material layer is a polymer layer, and the thickness of the plastic layer is greater than the thickness of the polymer layer.

In some embodiments, the ratio of the thickness of the plastic layer to the thickness of the polymer layer is between 4:1 to 1:1.

It should be understood that what is described in this summary is not intended to limit the critical or essential features of the embodiments of the disclosure nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals denote like or similar elements, in which:

fig. 1 is a schematic block diagram of an example electronic device that may use the semiconductor package structures of the present disclosure.

Fig. 2 is a schematic perspective view of the example electronic device shown in fig. 1 as an example smart phone.

Fig. 3 shows a schematic block diagram of a typical fan-out package structure.

Fig. 4A shows a schematic view of a conventional molding compound surrounding a copper pillar structure.

Fig. 4B is a schematic view showing a conventional structure in which a high polymer material surrounds a copper pillar.

Fig. 5 schematically depicts a schematic diagram of a semiconductor package structure embodying the concepts of the present disclosure.

Fig. 6A and 6B are schematic diagrams illustrating polymer layers (e.g., PI layers) having different opening morphologies.

Fig. 7A to 7G illustrate an exemplary process of the semiconductor package structure of the present disclosure based on fig. 6A.

Fig. 8 shows a process flow of a fabrication method of a semiconductor package structure according to an example embodiment of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.

In the specification, the meaning of "coupled/connected" of a component with another component includes indirect coupling/connection via a third component and direct coupling/connection between two components. Further, "electrically coupled/connected" is meant to include both physically electrically connected and physically disconnected concepts. It will be understood that when an element is referred to as being "first" or "second," it is not limited thereto. They may be used only for distinguishing between one element and another and not for limiting the order or importance of the elements. In some cases, a first element may be termed a second element without departing from the scope of the claims set forth herein. Likewise, the second element may also be referred to as the first element.

As used herein, directional terms such as up, down, left, right, etc. are determined in the drawings. In addition, the vertical direction refers to the above-described upward and downward directions, and the horizontal direction refers to a direction perpendicular to the above-described upward and downward directions. In this case, the vertical section refers to a case taken along a plane in the vertical direction, and an example thereof may be a sectional view shown in the drawings. In addition, the horizontal cross section refers to a case taken along a plane in the horizontal direction, and an example thereof may be a plan view shown in the drawings.

The terminology used herein is for the purpose of describing exemplary embodiments only and is not intended to be limiting of the disclosure. In this case, the singular includes the plural unless the context requires otherwise.

The application environment of the semiconductor package structure of the present disclosure will be first described below. Fig. 1 is a schematic block diagram of an example electronic device that may use the semiconductor package structures of the present disclosure. Referring to fig. 1, an electronic device 1000 may house a motherboard 1010 therein. Motherboard 1010 may include chip-related components 1020, network-related components 1030, and other components 1040, etc., physically and electrically coupled thereto. These components may be connected to other components to be described later to form various signal lines 1090.

The chip related component 1020 may include: a memory chip such as a volatile memory (e.g., dynamic Random Access Memory (DRAM)), a nonvolatile memory (e.g., read Only Memory (ROM)), a flash memory, or the like; an application processing chip such as a central processing unit (e.g., central Processing Unit (CPU)), a graphics processor (e.g., graphics Processing Unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, etc.; logic chips such as analog to digital converters (ADCs) or Application Specific Integrated Circuits (ASICs), etc. However, the chip-related component 1020 is not limited thereto, but may also include other types of chip-related components. Furthermore, the chip related components 1020 may be combined with each other.

The network-related component 1030 may be compatible with protocols such as wireless fidelity (Wi-Fi) (institute of electrical and electronics engineers (IEEE) 802.11 family, etc.), worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, long Term Evolution (LTE), evolution data optimized (Ev-DO), high speed packet access+ (hspa+), high speed downlink packet access+ (hsdpa+), high speed uplink packet access+ (hsupa+), enhanced Data GSM Environment (EDGE), global system for mobile communications (GSM), global Positioning System (GPS), general Packet Radio Service (GPRS), code Division Multiple Access (CDMA), time Division Multiple Access (TDMA), digital Enhanced Cordless Telecommunications (DECT), bluetooth, 3G, 4G, and 5G protocols, as well as any other wireless protocols and wired protocols specified after the above. However, the network-related component 1030 is not so limited, but may also include various other wireless or wired standards or protocols. Further, network-related components 1030 may be combined with each other along with the chip-related components 1020 described above. It should be noted here that although the network related component 1030 is shown here, in some embodiments, some of the above-described network protocols may also be implemented in some of the processing chips described above.

Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), and the like. However, other components 1040 are not limited thereto, but may also include passive components or the like for various other purposes. Further, other components 1040 may be combined with each other along with the chip-related components 1020 or the network-related components 1030 described above. For example, in some embodiments, some power amplifier structures (PA), radio frequency inductors, or filter structures may be integrated in some of the chips described above. By way of example only, these chips may include, for example, radio frequency front end chips.

Depending on the type of electronic device 1000, electronic device 1000 may include other components that may or may not be physically or electrically connected to motherboard 1010. Such other components may include, for example, a camera module 1050, an antenna 1060, a display 1070, a battery 1080, an audio decoder (not shown), a video decoder (not shown), a power amplifier (not shown), a compass (not shown), an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a mass storage unit (e.g., a hard disk drive) (not shown), a Compact Disk (CD) drive (not shown), a Digital Versatile Disk (DVD) drive (not shown), and so forth. However, these other components are not limited thereto, but may also include other components or the like for various purposes according to the type of the electronic device 1000.

The electronic device 1000 may be a smart phone, a Personal Digital Assistant (PDA), a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, or an automobile component, etc. However, the electronic device 1000 is not limited thereto, but may be any other electronic device capable of processing data. The electronic device 1000 is merely illustrative and is not limiting of the scope of the disclosure. Other electronic devices are possible, for example, may include more or fewer components or parts.

Fig. 2 is a schematic perspective view of the example electronic device 1000 shown in fig. 1 as an example smart phone. Referring to fig. 2, a semiconductor package for various purposes may be used in various electronic devices 1000 as described above. For example, the motherboard 1110 may be housed in the main body 1101 of the smart phone 1100, and various electronic components 1120 may be physically or electrically connected to the motherboard 1110. Further, other components (such as the camera module 1130) that may or may not be physically or electrically connected to the motherboard 1110 may be housed in the main body 1101. Some of the electronic components 1120 may be chip-related components, and the semiconductor package 100 may be, for example, an application processor in the chip-related components, but is not limited thereto. The electronic device is not necessarily limited to the smart phone 1100, but may be other electronic devices as described above.

In general, a semiconductor chip has a large number of fine circuits integrated therein. However, the semiconductor chip itself cannot be used as a finished semiconductor product, and may be damaged by external physical impact or chemical impact. Therefore, the semiconductor chip may not be used as it is, but the semiconductor chip may be packaged and used in an electronic device or the like in a packaged state.

Here, in terms of electrical connection, since there is a difference in circuit width between the semiconductor chip and the motherboard of the electronic device, it is necessary to perform semiconductor packaging. In particular, the size of the connection pads of the semiconductor chip and the interval between the connection pads of the semiconductor chip are very small, and the size of the component mounting pads of the motherboard and the interval between the component mounting pads of the motherboard used in the electronic device are significantly larger than the size of the connection pads of the semiconductor chip and the interval between the connection pads of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the motherboard, and a packaging technique for buffering a difference in circuit width between the semiconductor chip and the motherboard is required.

Fig. 3 shows a schematic diagram of a fan-out package structure. As shown in fig. 3, the fan-out package FOP realizes high density interconnection of the chip and the redistribution layer (Redistribution Layer, RDL) through high density copper pillars (Cu pilar), which is a low cost structure and has received much attention in recent years and is mass produced on some products. In some implementations, there are two main ways to form a structure around the copper pillar, namely, the plastic package material as shown in fig. 4A surrounds the copper pillar structure (Through Molding Pilar); the other is a polymer material surrounding the copper pillar structure (Through Polymer Pillar) as shown in fig. 4B.

The plastic package material shown in fig. 4A surrounds the copper pillar structure (Through Molding Pilar), because the plastic package material has a large elastic modulus, the package thermal stress is directly conducted into the chip, and ELK (Extreme low K) cracks are easily generated on the chip; in the polymer material surrounding the copper pillar structure (Through Polymer Pillar) shown in fig. 4B, the elastic modulus of the polymer material is low, and bump cracks (bump cracks) are likely to occur. In addition, when the polymer material layer is relatively thick, there is also a risk of ELK cracks.

To this end, the present disclosure contemplates the use of a multi-layer material to enclose a conductive pillar, such as a copper pillar, wherein the multi-layer material includes at least both a molding compound (which is formed, for example, of an epoxy molding compound EMC) that molds the semiconductor chip and a first material (which is, for example, a polymeric material formed of a polymeric material) interposed between a surface of the semiconductor and the molding compound, wherein the conductive pillar is electrically coupled with the RDL layer through the multi-layer material, and the modulus of elasticity of the first material is substantially lower than that of the molding compound. By virtue of the arrangement in which such a multi-layer material surrounds the conductive pillars, on the one hand, the first material can relieve stress from the molding compound and the package, and on the other hand, it does not deteriorate reliability of the bumps such as the conductive pillars due to thinning of the layer thickness of the first material such as the polymer material, compared with the case of fig. 4B described above. Therefore, with the concepts of the present disclosure, the goals of reducing cracks and improving chip reliability can be achieved.

Fig. 5 schematically depicts a schematic diagram of a semiconductor package 1 embodying the concepts of the present disclosure. The semiconductor package 1 may be a fan-out package. It should be appreciated that while the present disclosure is described primarily around a fan-out package structure, the scope of application of the present disclosure includes, but is not limited to, fan-out package structures, but may encompass other package structures in addition to fan-out package structures, such as, in some embodiments, fan-in package structures as well.

The semiconductor package 1 is used for packaging a semiconductor chip 10. The semiconductor chip 10 may have a first face 11 and a second face 13 opposite to each other. The first face 11 may be provided with conductive areas 12, such as I/O terminals, which are also referred to as active faces; correspondingly, the second face 13 is also referred to as passive face. In an example embodiment of the fan-out type package structure of the present disclosure, a passivation layer 60 may be formed on the first side 11 of the semiconductor chip 10 as a part of the semiconductor chip 10, thereby protecting the metallization structure on the first side 11 of the semiconductor chip 10, and the passivation layer 60 may have a first opening 61 exposing the conductive region 12. Then, a first material layer 30, such as a polymer material, may be formed on the passivation layer 60 and have the second opening 31 aligned with the first opening 61 described above. Next, a conductive pillar 20, such as a copper pillar, may be formed on the conductive region 12 via the first opening 61 and the second opening 31. Subsequently, a plastic package structure may be formed on an outer surface of the semiconductor chip 10 (e.g., including the second face 13 and/or the side portion of the semiconductor chip 10) by the plastic molding compound 40 (e.g., EMC), thereby achieving protection of the semiconductor chip 10 as a whole. In particular, the molding compound 40 may be at least molded over the first material layer 30 to form a molding layer 41, wherein the conductive pillars 20 may be electrically coupled with the RDL layer 50 located over the molding compound 40 throughout both the first material layer 30 and the molding layer 41, thereby enabling redistribution of the conductive regions 12, such as I/O terminals, of the semiconductor chip 10 outside the chip.

It will be appreciated that the above-described semiconductor package structure 1 thus defines between the first side 11 of the semiconductor chip 10 and the RDL layer 50 layers of at least two materials, namely a first material layer and a plastic layer, wherein the material of the first material layer may have a modulus of elasticity that is less than the modulus of elasticity of the material of the plastic layer. Compared to the semiconductor package structure of fig. 4A and 4B, as previously described, the package structure of the present disclosure can alleviate stress from the plastic compound and the package and avoid undesired cracks caused by selecting a single material by surrounding a conductor structure such as a copper pillar with a multi-layer material including both the first material (e.g., polymer material) and the plastic compound, thereby improving reliability of the semiconductor package structure.

To better exploit the advantages of the above-described multi-layer material, in a further embodiment, the thickness of the plastic layer 41 may be greater than or equal to the thickness of the first material layer 30. In particular, the ratio of the thickness of the molding layer 41 to the thickness of the first material layer 30 may be in the range of 4:1 to 1:1, such as a ratio of 3:1, 2:1, 1.5:1, or 1:1. It should be understood that the above ratio is merely an example, and the ratio of the thicknesses of the plastic layer and the first material layer may be reasonably selected according to the elastic modulus of both layers. Thus, in even some embodiments, it is possible that the thickness of the plastic layer 41 is smaller than the thickness of the first material layer 30.

In the above-described embodiment, although the conductive pillar 20 may be formed directly over the conductive region 12 via both the first opening 61 and the second opening 31, in some embodiments, a metal layer 80 (not shown in fig. 5, see later fig. 7A) may also be formed between the conductive region 12 and the conductive pillar 20 such that the conductive pillar 20 is electrically coupled with the conductive region 12 via the metal layer 80.

With the above arrangement, it is then possible to use the standardized ball layout as it is in the fan-out package structure, so that the fan-out semiconductor package can be mounted on a motherboard such as the above-described electronic device without using a separate interposer.

An exemplary process for the semiconductor package structure as contemplated in fig. 5 is described below in connection with fig. 6A, 6B, and 7A through 7G.

First, as shown in fig. 6A to 6B, a semiconductor chip 10 having a first face 11 and a passivation layer 60 may be provided. The semiconductor die 10 may be a semiconductor die on a wafer. The semiconductor chip 10 may have a semiconductor substrate, for example. The integrated circuit may be formed in or on the substrate. The term "semiconductor substrate" may be defined as any structure comprising a semiconductor material including, but not limited to, bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon germanium substrate. Other semiconductor materials may also be used, including group III elements, group IV elements, and group V elements. An integrated circuit, as used herein, refers to an electronic circuit having a plurality of individual circuit components, such as transistors, diodes, resistors, capacitors, inductors, and other active and passive semiconductor devices.

The semiconductor chip 10 may further include an interlayer dielectric layer and a metallization structure overlying the integrated circuit. The interlayer dielectric in the metallization structure may comprise a low-k dielectric metal, undoped glass (USG), nitrided poly, nitrided oxide poly, or other commonly used materials. The dielectric constant (k value) of the low-k dielectric material may be, for example, less than about 3.9, or less than about 2.8. The metal lines in the metallization structure may be formed of copper or a copper alloy. The semiconductor chip 10 may further be provided with a conductive region 12 on the first side 11, which may be a top metallization layer formed on a top interlayer dielectric layer. Suitable materials for the conductive regions may include, but are not limited to, copper, aluminum, copper alloys, or other mobile (mobile) conductive materials. In some embodiments, the conductive regions 12 may be bond pad electrical regions that may be used in a bonding process to connect an integrated circuit on an associated chip to an external component.

Further, a passivation layer 60 may be formed on the first side 11 of the semiconductor chip 10, which may be used to protect metallization structures on the first side 11 of the semiconductor chip 10. In some embodiments, the passivation layer 60 may be formed of an inorganic material, which may be selected from Undoped Silicon Glass (USG), silicon nitride, silicon oxynitride, silicon oxide, and combinations thereof, for example. In still other embodiments, it is also possible that the passivation layer 60 is formed of an organic material. The passivation layer 60 may be patterned to form a first opening 61 exposing the conductive region 12.

Next, a first material layer 30 having a second opening 31 may be formed on the passivation layer 60, the second opening 31 may be aligned with the first opening 61, whereby the conductive region 12 may be exposed via both the second opening 31 and the first opening 61. The first material layer 30 may be formed, for example, of a polymer having a relatively small modulus of elasticity to thereby relieve stresses in the subsequent molding compound and package. For example only, the polymer may be Polyimide (PI). The second opening 31 for exposing the conductive region 12 may be formed, for example, by means of exposure, development, and curing.

In the embodiment of forming the first material layer 30 on the passivation layer 60, the opening morphology of the second opening 31 may have two types with respect to the first opening 61: as shown in fig. 6A, the first material layer 30 may cover sidewalls of the first opening 61 formed by the passivation layer 60, and thereby form a second opening 31 smaller than the first opening 61; alternatively, as shown in fig. 6B, the first material layer 30 may be patterned to form the second opening 31 larger than the first opening 61. Regardless of the manner of opening, the positions of the second opening 31 and the first opening 61 need to be aligned with each other, and the distinction between them has no effect on subsequent processing. For convenience of description, the following process of the semiconductor package structure of the present disclosure will be further described with reference to the opening topography of fig. 6A only.

Referring to fig. 7A, a metal layer 80 may be formed on the first material layer 30 and the exposed conductive region 12. In particular, the metal layer 80 may be filled in the bottom wall and the side walls of the second opening 31 as a liner. In some embodiments, the metal layer 80 may be a two-layer construction, including an adhesion layer 81 and a seed layer 82. The adhesion layer 81 may be formed using a barrier material such as titanium, titanium nitride, tantalum nitride, and mixtures thereof, and may be formed using physical vapor deposition, sputtering, or the like. This adhesion layer 81 helps to improve the adhesion of subsequently formed metal conductive pillars on the first material layer 30. The seed layer 82 may form a single coating layer on the adhesion layer 81. The material of seed layer 82 may include copper or copper alloys, and may also include other metals such as silver, gold, aluminum, and combinations thereof. Seed layer 82 may be formed using sputtering, or other commonly used methods such as physical vapor deposition or electroless plating. By way of example only, the adhesion layer 81 in the metal layer 80 may be a Ti layer and the seed layer 82 may be a Cu layer.

Next, as shown in fig. 7B, a mask layer 90 may be formed on the metal layer 80, and the mask layer 90 may be patterned to form conductive pillar openings 91 for the conductive pillars 20. The conductive pillar opening 91 is aligned with the second opening 31 and may have a diameter greater than or equal to the diameter of the second opening 31. As an example, the mask layer 30 may be a dry film or a photoresist film. The above-described conductive pillar openings 91 may be formed by, for example, exposure, development.

Once the above-described conductive pillar openings 91 are formed, as shown in fig. 7C, the conductive pillars 20 may be formed within the conductive pillar openings 91. The forming method may include sputtering, printing, electroplating, electroless plating, and commonly used Chemical Vapor Deposition (CVD) methods. For example, electrochemical plating (ECP) may be performed to form conductive pillars. The conductive pillars may be copper pillars or copper-containing pillars, as examples. It will be appreciated that the term "copper pillar" of the present disclosure includes substantially pure elemental copper, or copper containing impurities, or copper alloys including minor amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, molybdenum, magnesium, aluminum, or zirconium.

In fig. 7D, the mask layer 90 may be removed and the exposed metal layer 80 etched. In embodiments where masking layer 90 is a dry film, it may be removed using an alkaline solution. While in embodiments where mask layer 90 is formed of photoresist, acetone, N-methyl pyrrolidone (NMP), dimethyl sulfoxide (DMSO), aminoxyethanol, and the like may be used for removal. The exposed portions of the metal layer 80 are then etched to expose the underlying first material layer 30. In some embodiments, the process of removing the exposed portion of the metal layer 80 may be a dry etch or a wet etch. For example, isotropic wet etching with amino acids (commonly referred to as lightning etching due to short duration) may be used. In this way, the conductive pillars 20 may protrude from the first material layer 30.

In embodiments where multiple semiconductor chips 10 are formed on a wafer, the wafer may be thinned, diced, and then reconstituted on carrier 5 as desired, as shown in fig. 7E. Upon reconstitution of the wafer, the individual semiconductor chips 10 are separated from each other and their sides are exposed.

Next, as shown in fig. 7F, the semiconductor chip 10 formed with at least both the first material layer 30 and the conductive pillars 20 may be subjected to plastic encapsulation to produce a molding compound 40. As shown in fig. 7F, in some embodiments, the molding compound 40 may provide at least a molding layer 41 that is located on the first material layer 30 and laterally surrounds the conductive pillars 20. In still other embodiments, the molding compound 40 may further encapsulate the side portions of the semiconductor chip and the first material layer to form a molded body. In still other embodiments, the molding compound 40 may also encapsulate the sides, the second side (i.e., the bottom side), and the first material layer of the semiconductor chip to form a molded body. It should be understood that the molding region and form of the molding compound 40 is not limited by the above examples of molding. In addition, the material forming the molding compound 40 may be an insulating material. For example, the molding compound may be a thermosetting resin such as an epoxy resin, or a thermoplastic resin, a resin (e.g., ABF, FR-4, BT, PID resin, etc.) having a reinforcing material (such as an inorganic filler) included in the thermosetting resin and the thermoplastic resin. In particular, in some embodiments, the material forming the molding compound 40 may be a material having a modulus of elasticity greater than the modulus of elasticity of the first material layer 30 mentioned above, such as an Epoxy Molding Compound (EMC).

In the above plastic encapsulation process of fig. 7F, the plastic encapsulant will inevitably cover the conductive pillars 20. Thus, in fig. 7, the molding compound over the semiconductor chip 10, i.e., on top of the conductive pillars 20, may be ground to expose the conductive pillars 20 and form a molding layer 41. In some embodiments, the desired height of the conductive posts 20 and the desired thickness of the plastic layer 41 may be achieved by this grinding, as desired for the application.

Finally, as shown in fig. 7H, RDL layer 50 may be formed over both plastic layer 41 and conductive pillars 20 using a well-established RDL formation process. RDL layer 50 may include a dielectric layer 51 and at least one layer of redistribution metal lines 52 formed in dielectric layer 51. As an example, as shown in fig. 7H, RDL layer 50 may include multiple layers of redistribution metal lines 52, wherein the top and bottom layers of redistribution metal lines 52 are exposed at the upper and lower surfaces of dielectric layer 51, respectively. The layers of redistribution metal lines 52 may be connected by a plurality of conductive pillars.

For embodiments in which RDL layer 50 includes multiple layers of redistribution metal lines 52, it may be achieved by alternating dielectric layers and redistribution metal lines. The redistribution metal line 52 may be formed by at least one of Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), sputtering, electroplating, and electroless plating. Dielectric layer 51 may be formed by at least one of spin coating, physical vapor deposition and chemical vapor deposition.

The conductive metal employed for the redistribution metal lines 52 includes, but is not limited to, copper, aluminum, titanium, and the like. Materials for dielectric layer 51 include, but are not limited to, epoxy, silicone rubber, silicone, PI, PBO, BCB, but low K dielectrics such as silicon oxide, phosphosilicate glass, fluorinated glass, and the like may also be used. Further, bump structures 70 may be formed on the upper surface of the dielectric layer 51. In the example of fig. 7H, the bump structure 70 may be, for example, a metal solder ball.

By forming RDL layer 50 in the manner described above, first material layer 30 and plastic layer 41 of two different moduli of elasticity may be interposed between semiconductor chip 10 and RDL layer 50, wherein RDL layer 50 may be electrically coupled to semiconductor chip 10 via conductive pillars 20. As previously described, such a multi-layer material comprising two different modulus of elasticity materials may help to relieve stress from the package, reduce ELK cracking, and enhance the resistance of the conductive pillars (e.g., copper pillars) to cracking. The remaining steps of the package structure or other packaging techniques are not described herein.

The process flow of the fabrication method of the semiconductor package of the present disclosure will be described in outline with reference to fig. 8.

As shown in fig. 8, at block 810, a semiconductor chip 10 may be provided, the semiconductor chip 10 may have a first side 11 having a conductive region 12 and a passivation layer 60 covering the first side, the passivation layer having a first opening 61 exposing the conductive region. As previously described, the semiconductor die 10 may be a semiconductor die on a wafer, which may have a semiconductor substrate. An integrated circuit may be formed in or on the semiconductor substrate. Conductive regions 12 on the semiconductor chip 10 may be used in a bonding process to connect the integrated circuits on the associated chip to external components. Such as, for example, a bond pad region.

The passivation layer 60 is formed for the purpose of protecting the metallization structure on the first side 11 of the semiconductor chip 10. As previously described, the material forming the passivation layer may include an inorganic material or an organic material.

At block 820, a first material layer 30 having a second opening 31 is formed on the passivation layer 60, the second opening 31 and the first opening 61 being aligned with each other.

The purpose of this first material layer 30 is to buffer the package stress from the molding compound of the semiconductor chip, so that a material with a relatively small elastic modulus can be selected here. In general, the modulus of elasticity of the material of the first material layer 30 may be selected to be less (or significantly less) than the modulus of elasticity of the molding compound. As an example, the first material layer 30 may be, for example, a high polymer material layer formed of a polymer material. Further, the polymer material may be, for example, a Polyimide (PI) material. The thickness of the first material layer 30 may be as desired. In some embodiments, the thickness of the first material layer 30 may be selected to be less than the thickness of the later formed plastic layer 41. In particular, the ratio of the thickness of the plastic layer 41 to the thickness of the first material layer 30 may be 4:1 to 1: within the range of 1, for example, 3:1 or 2:1 or 1.5:1.

In some embodiments, the opening topography of the second opening 31 of the first material layer 30 may be as previously shown in fig. 6A and 6B. In some embodiments, the size of the second opening 31 may be greater than or less than the size of the first opening 61.

At block 830, conductive pillars 20 are formed over conductive regions 12 exposed by second openings 31 such that conductive pillars 20 are electrically coupled to conductive regions 12. For example only, the conductive pillars 20 may be copper pillars or copper-containing pillars. By means of this conductive pillar 20, the semiconductor chip 10 can be electrically coupled with an RDL layer 50 to be described later.

In some embodiments, the steps in block 830 may further include: a metal layer 80 is formed on the first material layer 30 and the exposed conductive region 12, and the conductive pillars 20 are formed over the corresponding metal layer 80 of the conductive region 12. For example only, the metal layer 80 may be a Cu/Ti layer, wherein the Ti layer may be used to improve the adhesion of subsequently formed metal conductive pillars on the polymer layer 30.

In an embodiment of forming the metal layer 80, the step of forming the conductive pillar 20 may further include: forming a mask layer 90 on the metal layer 80; patterning the mask layer 90 to form conductive pillar openings 91, wherein the conductive pillar openings 91 are aligned with the locations of the conductive regions 12; and forming the conductive posts 20 within the conductive post openings 91. Further, the step of forming the conductive pillar 20 further includes: the mask layer 90 is removed and the exposed metal layer 80 is etched so that the conductive pillars 20 may protrude upward from the first material layer 30 by a certain height.

At block 840, the semiconductor chip 10 having the first material layer 30 and the conductive pillars 20 is molded to form a molding compound 40, the molding compound 40 including at least a molding layer 41 formed on the first material layer 30, wherein the conductive pillars 20 are electrically coupled with the conductive regions 12 through the molding layer 41 and the first material layer 30, and an elastic modulus of a material of the first material layer 30 is smaller than an elastic modulus of the molding compound. For example only, the material of the molding compound 40 may be EMC.

In some embodiments, forming the molding compound 40 may further include: dicing and reconstructing a wafer on which a plurality of semiconductor chips 10 are formed, and then plastic-packaging the upper and both sides of the semiconductor chips 10 on which both the first material layer 30 and the conductive pillars 20 are formed, on the reconstructed wafer. In other embodiments, there may be different forms of molding, for example, in addition to molding the first material layer over the semiconductor chip 10, in some embodiments, the molding compound 40 may also mold or encapsulate the sides of the semiconductor chip 10. In still other embodiments, the molding compound 40 may even further mold or encapsulate the second side (i.e., the bottom side) of the semiconductor chip 10. In still further embodiments, the molding compound over the semiconductor chip 10 may be ground to form the molding compound 41 and expose the conductive pillars 20.

In an embodiment of the fan-out package structure, the method may further comprise: a re-wiring layer 50 (RDL layer) is formed on the molding layer 41, wherein the wires in the re-wiring layer 50 can be electrically coupled with the conductive pillars 20 exposed from the molding layer 41. By means of the RDL layer 50, redistribution of the I/O terminals of the semiconductor chip 10 outside the chip can be achieved.

It will be readily appreciated that through the above-described process, the first material layer 30 and the plastic layer 41 will be interposed between the first face 11 and the redistribution layer 50, and the conductive pillars 20 penetrate both the first material layer 30 and the plastic layer 41, wherein the elastic modulus of the material of the first material layer 30 is smaller than the elastic modulus of the plastic layer 41.

The semiconductor package structure of the present disclosure and the fabrication method thereof have been described above in detail. It will be appreciated that by the semiconductor package structure designed in accordance with the present disclosure, and in particular having conductive pillars (e.g., copper pillars) in communication with the RDL layer throughout two fill materials of different modulus of elasticity, stress from the semiconductor package may be relieved, the risk of ELK cracking and conductive pillar (e.g., copper pillar) cracking may be reduced, and reliability of the semiconductor package structure (e.g., fan-out package structure) may be improved

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.

In addition, it should be understood that the methods, steps, or flows described above are merely examples. Although the steps of a method are described in a particular order in the specification, this does not require or imply that the operations must be performed in the particular order or that all of the illustrated operations be performed in order to achieve desirable results, and that the order in which the steps are described may be altered. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform.

In the claims, the word "comprising" does not exclude other elements, and the indefinite article "a" or "an" does not exclude a plurality. A single element or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain features are recited in mutually different embodiments or in dependent claims does not indicate that a combination of these features cannot be used to advantage. The scope of the present application encompasses any possible combination of the features recited in the various embodiments or the dependent claims without departing from the spirit and scope of the present application.

Any reference signs in the claims shall not be construed as limiting the scope of the disclosure.

Claims

A semiconductor package structure (1), comprising:

a semiconductor chip (10) having a first face (11) with a conductive region (12) and a passivation layer (60) overlying the first face (11);

a first material layer (30) disposed on the passivation layer (60);

a molding compound (40) at least comprising a molding layer (41) formed on the first material layer (30), wherein the elastic modulus of the material of the first material layer is smaller than that of the molding compound (40); and

-a conductive pillar (20) electrically coupled with the conductive region (12) through the plastic layer (41) and the first material layer (30).
The semiconductor package structure according to claim 1, wherein the molding compound (40) encapsulates at least a side portion of the semiconductor chip and the first material layer to form a molded body.
The semiconductor package structure (1) according to claim 1, further comprising:

and a rewiring layer (50) located on the plastic sealing layer (41), wherein the wires in the rewiring layer (50) are in electrical contact with the conductive posts (20).
The semiconductor package structure (1) according to claim 1, wherein the first material layer (30) comprises a polymer layer; and the thickness of the plastic layer (41) is greater than the thickness of the polymer layer (30).
The semiconductor package structure (1) according to claim 4, wherein the ratio of the thickness of the plastic layer (41) to the thickness of the polymer layer (30) is in the range of 4:1 to 1:1.
The semiconductor package structure (1) according to any one of claims 1-5, further comprising:

-a metal layer (80), said metal layer (80) being arranged between said conductive area (12) and said conductive post (20).
A circuit assembly, comprising:

a circuit board; and

the semiconductor package (1) according to any one of claims 1-6, mounted on the circuit board.
An electronic device, comprising:

a power supply circuit; and

the circuit assembly of claim 7, powered by the power supply circuit.
A method of fabricating a semiconductor package (1), comprising:

providing a semiconductor chip (10) having a first face (11) comprising a conductive region (12) and a passivation layer (60) covering the first face, the passivation layer (60) having a first opening (61) exposing the conductive region;

-forming a first material layer (30) having a second opening (31) on the passivation layer (60), the second opening (31) and the first opening (61) being aligned with each other;

-forming a conductive pillar (20) on the conductive region (12) exposed by the second opening (31) such that the conductive pillar (20) is electrically coupled to the conductive region (12); and

-plastic packaging the semiconductor chip (10) with both the first material layer (30) and the conductive pillars (20) to form a plastic package material (40), the plastic package material (40) comprising at least a plastic layer (41) formed on the first material layer (30), the conductive pillars (20) being electrically coupled with the conductive regions (12) through the plastic layer (41) and the first material layer (30), the material of the first material layer (30) having a modulus of elasticity that is less than the modulus of elasticity of the plastic package material (40).
The method of claim 9, wherein molding the semiconductor chip (10) with the first material layer (30) comprises: such that a molding compound (40) encapsulates at least a side portion of the semiconductor chip and the first material layer.
The method of claim 9, further comprising:

a rewiring layer (50) is formed on the molding layer (41), wherein lines in the rewiring layer (50) are electrically coupled to conductive pillars (20) exposed from the molding layer (41).
The method of claim 9, wherein forming a conductive pillar (20) on the conductive region (12) exposed by the second opening (31) comprises:

forming a metal layer (80) over the exposed conductive region (12); and

-forming the conductive pillars (20) on the metal layer (80).
The method of claim 12, wherein forming the conductive pillars (20) on the metal layer (80) comprises:

forming a mask layer (90) on the metal layer (80);

patterning the mask layer (90) to form conductive pillar openings (91), the conductive pillar openings (91) being aligned with the conductive regions (12);

-forming the conductive pillars (20) within the conductive pillar openings (91);

removing the mask layer (90); and

the exposed metal layer (80) is etched.
The method according to any of claims 9-13, wherein the first material layer (30) is a polymer layer, the thickness of the plastic layer (41) being greater than the thickness of the polymer layer (30).
The method according to claim 14, wherein the ratio of the thickness of the plastic layer (41) to the thickness of the polymer layer (30) is between 4:1 to 1:1.