CN117277737A

CN117277737A - Control device and control method for switching voltage regulator

Info

Publication number: CN117277737A
Application number: CN202310742484.6A
Authority: CN
Inventors: S·卡斯托瑞纳; E·布里戈; I·弗洛里亚尼
Original assignee: STMicroelectronics SRL
Current assignee: STMicroelectronics SRL
Priority date: 2022-06-22
Filing date: 2023-06-21
Publication date: 2023-12-22

Abstract

The present disclosure relates to a control apparatus and a control method for a switching voltage regulator. A control apparatus for a switching voltage regulator having a switching circuit is provided. The control device receives input and output voltages of the switching circuit and a measurement signal indicative of a current of the switching circuit. The control device comprises: a feedback module detecting an error signal indicative of a difference between the output voltage and a nominal voltage and providing a control signal in accordance with the error signal; a threshold correction module providing an offset signal and a ramp signal; and a drive signal generation module coupled to the feedback module and the threshold correction module, the drive signal generation module receiving the measurement signal, comparing the measurement signal to a threshold, and in response providing a modulation signal for driving the switching circuit. The threshold is based on the control signal, the offset signal, and the ramp signal. The threshold correction module provides an offset signal according to the input voltage or the output voltage.

Description

Control device and control method for switching voltage regulator

Technical Field

The present disclosure relates to a control apparatus for a switching voltage regulator having improved control performance, and to a control method.

Background

As is known, switching voltage regulators are capable of converting an input dc voltage to an output dc voltage using different operating schemes, and can be obtained using different topologies, with one of the most widespread topologies being a four-switch non-inverting topology.

Fig. 1 shows a switching voltage regulator 1, the switching voltage regulator 1 comprising a four-switch non-inverting switching circuit (hereinafter referred to as switching circuit 3) and a control device 5.

The switching circuit 3 is formed by a first half-bridge 7, a second half-bridge 9 and an inductor 10.

The first half-bridge 7 is formed by a first high-side switch 11 and a first low-side switch 13 (here two NMOS transistors) coupled in series between the input terminal 15 and a common node 17.

The common node 17 is coupled to a reference potential line (ground) 18 via a shunt (shunt) resistor 19.

An input voltage Vin with respect to ground 18 is applied to input terminal 15.

The second half-bridge 9 is formed by a second high-side switch 20 and a second low-side switch 22 (here also two NMOS transistors) coupled in series between an output node 24 and a common node 17.

An output voltage Vout referenced to ground 18 is present at an output node 24 and applied to a load 25.

An inductor 10 is coupled between the intermediate node of the first half-bridge 7 and the intermediate node of the second half-bridge 9.

Depending on the ratio between the input voltage Vin and the output voltage Vout, the switching voltage regulator 1 may operate in one of three modes of operation, also referred to as "buck" (if Vin > Vout, also referred to as "boost" (if Vin < Vout), and also referred to as "buck-boost" (if vin≡vout).

According to the operation mode, by properly controlling the switching of the first half-bridge 7 and the second half-bridge 9, it is in fact possible to keep the output voltage Vout at the reference voltage Vref, which is chosen by the user, for example, according to the specific application, independently of the value of the input voltage Vin.

To this end, the control means 5 are coupled to the input node 15 and to the output node 24 and receive a reference voltage Vref.

As is known, the control means 5 are designed such that they perform a current control of the switching circuit 3; in this regard, the control device 5 measures the current flowing through the shunt resistor 19 in use, which current is indicative of the current I flowing through the inductor 10 _L 。

In detail, as shown in fig. 2, the control device 5 forms a loop control circuit including: measuring the error between the output voltage Vout and the reference voltage Vref and generating a control signal I _C Loop control circuit 30 of (a); generating a current ramp I _slope Ramp generator 32 of (a); current I _L And sum current I _C +I _slope A PWM modulator 34 that compares and generates a modulation signal PWM; and drive logic 36 that generates switch control signals T1, T2, T3, T4 based on the modulation signal PWM.

In the control means 5, the modulation signal PWM has a fixed period of duration T and the PWM modulator 34, in use, is dependent on the sum current I _C +I _slope And current I _L The comparison between them modifies the duty cycle of each cycle of the modulation signal PWM.

However, applicants have found that under certain operating conditions, the current ramp I _slope The control performance of the known regulator 1 is reduced.

For example, fig. 3 shows waveforms of the known regulator of fig. 2 in use in a buck mode of operation, with valley-type (valley-type) control. In this operating mode, at the beginning of the cycle of the modulation signal PWM, the regulator 1 is in the OFF (OFF) phase, in which the current I _L And (3) reducing.

When the PWM modulator 34 detects the current I _L Equal to sum current I _C +I _slope When the PWM modulator 34 switches modulationSignal PWM, and regulator 1 enters the ON (ON) phase, in which current I _L Increasing with time.

It is known that if the duty cycle of the PWM signal is less than 50%, i.e. if the duration of the on phase is less than half the duration T, the current I _L The disturbance ΔI in (1) may lead to a current I _L Is a phenomenon of known subharmonic oscillation (subharmonic oscillation) (dashed line in fig. 3). Subharmonic oscillations may lead to instability of the regulator 1.

Ramp current I _slope The presence of (a) allows to compensate the current I in several cycles of the modulation signal PWM _L As indicated by the broken line in fig. 3. This therefore allows to prevent the regulator 1 from being affected by instabilities that may jeopardize its function.

However, applicants have found that as the current flowing in load 58 changes, the ramp current I _slope The control performance of the control device 5 is reduced and the ability of the regulator 1 to maintain the output voltage Vout at the desired value Vref is reduced. In particular, ramp current I _slope The higher the maximum current that can be regulated by the regulator 1, the lower, in particular when the difference between the input voltage Vin and the output voltage Vout is higher, for example when vin=40v and vout=5v.

Disclosure of Invention

According to the present disclosure, a control apparatus for a switching voltage regulator, and a control method for a switching voltage regulator are provided.

Drawings

For a better understanding of the present disclosure, some embodiments thereof will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

FIGS. 1 and 2 show block diagrams of known switching voltage regulators;

FIG. 3 shows waveforms of the known regulator of FIGS. 1 and 2 in use;

FIG. 4 shows a block diagram of an embodiment of the present voltage regulator including a switching circuit and a control device;

FIG. 5 shows a circuit diagram of a portion of the switching circuit and control device of the voltage regulator of FIG. 4;

FIG. 6 shows a circuit diagram of a portion of the control device of the voltage regulator of FIG. 4;

FIG. 7 shows a circuit diagram of different parts of the control device of the voltage regulator of FIG. 4;

FIG. 8 shows an example of waveforms of the voltage regulator of FIG. 4 in use;

FIGS. 9-11 provide a comparison between the number of regulators of FIG. 4 and the trend of the number of known regulators of FIG. 2;

FIG. 12 shows a block diagram of a different embodiment of the present voltage regulator including a switching circuit and a control device;

FIG. 13 illustrates a circuit diagram of a portion of the switching circuit and control device of the voltage regulator of FIG. 12, according to one embodiment; and

Fig. 14 illustrates a circuit diagram of a portion of a switching circuit and a control device of the voltage regulator of fig. 12, in accordance with various embodiments.

Detailed Description

Fig. 4 shows a block diagram of a switching voltage regulator 50 (hereinafter also referred to as regulator 50) that includes a switching circuit 53 and a control device (e.g., controller) 55 coupled to each other.

Regulator 50 has an input node 51, a reference node 52, and an output node 54, regulator 50 receiving an input voltage V from input node 51 _in Regulator 50 receives a nominal or reference voltage V from reference node 52 _ref Regulator 50 provides an output voltage V to an output node 54 _out . A load 58 is coupled to the output node 54 of the regulator 50.

In detail, the regulator 50 is a step-down and step-up type DC-DC converter configured to be based on an input voltage V _in Generating an output voltage V _out So that the output voltage V _out Will be equal to the reference voltage V _ref Reference voltage V _ref May be selected by the user depending on the particular application.

The switching circuit 53 and the control means 55 may be integrated in the same die or formed in different dies.

As shown in fig. 5, the switching circuit 53 is here a four-switch non-inverting circuit, which is specifically configured to be dependent on the input voltage V _in Whether or not to be respectively greater than, less than or approximately equal to the output voltage V _out (or reference voltage V _ref ) To operate in buck, boost, or buck-boost modes.

In detail, the switching circuit 53 is formed of a first half bridge 64 and a second half bridge 65.

The first half-bridge 64 is formed by a first high-side switch 68 and a first low-side switch 69 (here two NMOS transistors) coupled in series between the input node 51 and a common node 72.

In detail, the first high side switch 68 is coupled between the input node 51 and an intermediate node 74 of the first half bridge 64, and the first low side switch 69 is coupled between the intermediate node 74 of the first half bridge 64 and the common node 72.

Input node 51 is at an input voltage V relative to a reference potential line (ground) 78 _in 。

The common node 72 is coupled to ground 78 via a shunt resistor 80 having a resistance RS.

The second half-bridge 65 is formed by a second high-side switch 82 and a second low-side switch 83 (here also two NMOS transistors) coupled in series between the output node 54 and the common node 72.

In detail, the second high side switch 82 is coupled between the output node 54 and an intermediate node 85 of the second half-bridge 65, and the second low side switch 83 is coupled between the intermediate node 85 of the second half-bridge 65 and the common node 72.

Output node 54 provides an output voltage V relative to ground 78 _out 。

The switching circuit 53 further comprises an inductor 87, the inductor 87 having an inductance L and being coupled between the intermediate node 74 of the first half-bridge 64 and the intermediate node 85 of the second half-bridge 65.

The first high side switch 68, the first low side switch 69, the second high side switch 82 and the second low side switch 83 are each controlled by a respective switch control signal T1, T2, T3, T4.

The control device 55 is configured to perform current control of the switching circuit 53.

Control means 55 is coupled to input node 51, to output node 54 and to reference node 52.

In addition, the control device 55 is further coupled to the shunt resistor 80 for detecting a current flowing through the shunt resistor 80 in use, the current being indicative of the current I flowing through the inductor 87 _L 。

The control means 55 comprise a clock 90, the clock 90 providing a clock signal CLK, for example a periodic square wave signal. In this embodiment, the clock signal CLK has a period with a fixed duration T.

However, the clock signal CLK may have a period with a variable duration.

Referring to fig. 4 and 6, control device 55 further includes a loop control (feedback) circuit or module 92 coupled to output node 54 and to reference node 52; a PWM modulator 94 coupled to the shunt resistor 80 and providing a modulation signal PWM; and a drive logic circuit or module 96 that provides the switch control signals T1, T2, T3, T4 based on the modulation signal PWM.

Feedback circuit 92 receives output voltage V _out And reference voltage V _ref And provides the summing node 97 with the output voltage V according to the indication _out With reference voltage V _ref Error signal V of difference between _E Loop control current I of (2) _C 。

The control device 55 further comprises a threshold correction circuit or module 98 (an embodiment of which is shown in detail in fig. 7), the threshold correction circuit or module 98 being arranged to receive the input voltage V _in And output voltage V _out And includes an offset generator 100 and a ramp generator 102, the offset generator 100 providing an offset signal, here an offset current I _bias The ramp generator 102 provides a ramp signal, here a current ramp I _slope 。

Offset generator 100 provides a function of input voltage V to PWM modulator 94 _in And output voltage V _out Offset current I of difference between _bias 。

In detail, in this embodimentOffset current I _bias And at input voltage V _in And output voltage V _out The difference between them is proportional, in particular proportional.

Ramp generator 102 ramps the current I _slope Is provided to summing node 97. Current ramp I _slope May have a fixed slope, for example selected by a user of voltage regulator 50, or a variable slope that is variable during each cycle of the modulation signal PWM, for example based on one or more parameters.

In this embodiment, the current ramp I _slope With a voltage V according to the input _in And output voltage V _out The slope of the difference between.

For example, current ramp I _slope Slope of (V) and at input voltage V _in And output voltage V _out The difference between them is proportional, in particular proportional.

Referring to fig. 6, feedback circuit 92 includes a compensation module (e.g., circuit) 110 and a voltage-to-current conversion module (e.g., circuit) 111, compensation module 110 being coupled to output node 54 and to reference node 52 and providing a signal according to error signal V _E Control voltage V of (2) _c The voltage-to-current conversion module 111 provides a voltage V according to the control _c Control current I of (2) _C 。

In detail, the compensation module 110 includes an error amplifier (here an operational transconductance amplifier (operational transconductance amplifier, OTA) 114 having an output 116) and a compensation network 118 coupled to the output 116.

In this embodiment, compensation module 110 further includes a voltage divider 120 coupled between output node 54 and ground 78.

In detail, the voltage divider 120 has an intermediate node 121 and is formed by a series circuit, here with two resistors 123 coupled together at the intermediate node 121.

OTA 114 has a first input coupled to reference node 52 and a second input coupled to intermediate node 121 of voltage divider 120.

In practice, in this embodiment, the OTA 114 will reference the voltage V _ref And output voltage V _out Is compared with a part of the output voltage V _out Depending in part on the resistance value of resistor 123.

In this embodiment, the compensation network 118 is second order and is coupled between the output 116 of the OTA 114 and ground 78.

In detail, the compensation network 118 is a parallel circuit coupled between the output node 116 and ground 78, and is formed by a first branch comprising a series circuit formed by a compensation resistor 124 and a first compensation capacitor 125, and a second branch comprising a second compensation capacitor 126.

However, according to the specific transfer function desired by the compensation module 110, i.e. according to the error signal V _E Control voltage V of (2) _c The compensation network 118 may be formed of a different number and type of electrical elements. For example, the compensation network 118 may be first order, rather than second order; for example, it may be of the first order, the third order or higher.

The voltage-to-current conversion module 111 is formed by a first mirror leg 130 and a second mirror leg, here formed by a PMOS type transistor 131.

The first mirror leg 130 is a series circuit coupled between ground 78 and a supply node 133 (the supply node 133 is at a supply voltage V relative to ground 78 _CC ) And includes a first transistor 135 (here of NMOS type), a second transistor 136 (here of PMOS type), and a resistor R _C Is provided, the control resistor 137.

The gate terminal of the first transistor 135 is coupled to the output 116 of the OTA 114, i.e., at the control voltage V _C 。

A source terminal of the second transistor 136 is connected to the power supply node 133, and a gate terminal of the second transistor 136 is connected to a drain terminal.

Further, a gate terminal of the second transistor 136 is connected to a gate terminal of the transistor 131.

The first mirror leg 130 generates a voltage V according to the control voltage _C Intermediate control current I' _C 。

First mirrorThe current-to-image ratio of the image branch 130 and the second image branch 131 is 1:n such that the loop control circuit 92 provides at the output a value equal to n·i' _C Control current I of (2) _C 。

The ratio 1:n between the first and second mirrored branches 130, 131 of the voltage-to-current conversion module 111 can be modified by changing the characteristics of the transistors 131, 136, for example by appropriately sizing the transistors 131, 136 at the design stage.

The PWM modulator 94 comprises a comparator 140 having a positive input 141 and a negative input 142 and providing a comparison signal COMP, and a PWM generator 144, the PWM generator 144 generating a modulation signal PWM based on the clock signal CLK and according to the comparison signal COMP.

The PWM modulator 94 further includes: with resistance R _A The first resistor 146 being coupled between the positive input 141 of the comparator 140 and the terminal of the shunt resistor 80, the terminal of the shunt resistor 80 being here connected to the common node 72 of the switching circuit 53; having a resistance R _B The second resistor 147 is coupled between the negative input 142 of the comparator 140 and the second terminal of the shunt resistor 80, where the second terminal of the shunt resistor 80 is connected to ground 78.

In the illustrated embodiment, a positive input 141 of the comparator 140 is coupled to the output of the summing node 97 and a negative input 142 of the comparator 140 is coupled to an output 149 of the offset generator 100.

The PWM generator 144 provides a modulation signal PWM. The modulation signal PWM has a period according to the period of the duration T of the clock signal CLK, and a duty ratio that is variable at each cycle (or period) of the modulation signal PWM.

In this embodiment, for example, as shown in the graph of fig. 8, the period of the modulation signal PWM is fixed and is equal to the period T of the clock signal CLK.

However, the period of the modulation signal PWM may be different from the period of the clock signal CLK; for example, the period of the modulation signal PWM may be a multiple of the period of the clock signal CLK.

Further, in this embodiment, the rising edge of the modulation signal PWM is synchronized in time with the rising edge of the clock signal CLK.

In each cycle of the modulation signal PWM, the modulation signal PWM has a duration T _OFF First half period and duration T _ON So that t=t _ON +T _OFF 。

The first and second half cycles of the modulation signal PWM define the off and on phases, respectively, of the regulator 50.

The modulation signal PWM has a first value, here a high logic value "1", in the off-phase and a second value, here a low logic value "0", in the on-phase.

The drive logic 96 provides the switching control signals T1, T2, T3, T4 based on the modulation signal PWM in a manner known per se, in accordance with the actual operating mode of the regulator 50 (e.g. buck, boost or buck-boost mode) and in accordance with the current control mode used (e.g. peak control or valley control).

Fig. 7 shows a circuit diagram of one embodiment of correction circuit 98 in detail.

The offset generator 100 includes: a first input portion 150 coupled to input node 51; a second input section 151 coupled to the output node 54; a current differential generator 152 coupled to the first input part 150 and the second input part 151; and coupled to the current differential generator 152 and configured to shift the current I _bias An output portion 153 provided to an output node 149 of the offset generator 100.

The first input section 150 is coupled between the input node 51 and ground 78 and comprises a series circuit formed by a resistor 154 having a resistance R and by a transistor 155 (here of NMOS type).

The source terminal of transistor 155 is connected to ground 78. The drain terminal and the gate terminal of the transistor 155 are connected to each other.

In use, the current (V _in -V _gs1 ) R flows through the first input portion 150, where V _gs1 Is the voltage between the gate and source terminals of transistor 155.

The second input section 151 is coupled between the output node 54 and ground 78 and comprises a series circuit formed by a resistor 157 having a resistance R and a transistor 158 (here NMOS).

The source terminal of transistor 158 is connected to ground 78. The drain terminal and the gate terminal of the transistor 158 are connected to each other.

In use, the current (V _out -V _gs2 ) R flows through the second input portion 151, where V _gs2 Is the voltage between the gate and source terminals of transistor 158.

In this embodiment, resistors 154 and 157 have the same resistance value R. However, the resistors 154, 157 may have different resistance values R from each other in order to generate the input voltage V _in And output voltage V _out The difference between them is a disproportionate current.

The current differential generator 152 includes a first mirrored portion 159A and a second mirrored portion 159B coupled in parallel with each other between the power supply node 133 and ground 78.

The first mirror portion 159A has a node 160, and includes a transistor 161 (here, PMOS type) and a transistor 162 (here, NMOS type) coupled in series with each other at the node 160.

The second mirror portion 159B includes a transistor 164 (here, PMOS type) and a transistor 165 (here, NMOS type) coupled in series with each other.

The gate terminal of the transistor 162 of the first mirror portion 159A is connected to the gate terminal of the transistor 155 of the first input portion 150.

A gate terminal of the transistor 165 of the second mirror portion 159B is connected to a gate terminal of the transistor 158 of the second input portion 151.

The gate terminal and the drain terminal of the transistor 164 are connected to each other and to the gate terminal of the transistor 161.

The mirror ratio of the first mirror portion 159A and the second mirror portion 159B is 1:1; however, the first and second mirror portions 159A, 159B may have different mirror ratios depending on the particular application.

The output portion 153 of the threshold correction circuit 100 includes a first transistor 167 (here, PMOS type) and a second transistor 168 (here, PMOS type).

The first transistor 167 has a source terminal connected to the power supply node 133 and a drain terminal connected to the node 160 of the first mirror leg 159A of the current differential generator 152.

Further, the drain terminal and the gate terminal of the first transistor 167 are connected to each other.

The second transistor 168 has a source terminal connected to the power supply node 133 and a drain terminal forming the output 149 of the correction circuit 100.

A gate terminal of the second transistor 168 is connected to a gate terminal of the first transistor 167.

The output portion 153 has a mirror factor K between the first transistor 167 and the second transistor 168 _b Mirror image factor K _b May be selected according to a particular application, for example, by appropriately sizing the first transistor 167 and the second transistor 168 at the design stage.

In practice, in use, the current (V _in -V _out ) R flows through the first transistor 167 to the node 160, and the second transistor 168 is coupled on the output 149 to the output node represented by K _b ·(V _in -V _out ) Offset current I given by R _bias Mirroring is performed.

The ramp generator 102 includes an input portion formed here by a PMOS type transistor 170, a ramp circuit 171, and a ramp current I _slope An output portion 172 provided to an output node 173 of the ramp circuit 102.

A source terminal of the transistor 170 is connected to the power supply node 133, and a gate terminal of the transistor 170 is connected to a gate terminal of the first transistor 167 of the output portion of the offset generator 100.

In practice, the gate terminals of transistors 167, 168 and 170 are at the same voltage V _b 。

The input portion of the ramp generator 102 has a mirror factor m with respect to the first transistor 167 of the output portion of the offset generator 100. For example, the mirror factor m may be adjusted by modifying the dimensions of the transistors 167, 170 during the design phase.

The ramp circuit 171 includes: a transistor 174, here an NMOS type, the drain terminal and the gate terminal of the transistor 174 being connected to each other and to the drain terminal of the transistor 170; and a parallel circuit coupled between the source terminal of transistor 174 and ground 78 and formed by capacitor 175 and switch 176.

The switch 176 is controlled by a ramp control signal CMD, which can be generated by the control device 55 from the clock signal CLK or from the modulation signal PWM.

The output portion 172 of the ramp generator 102 comprises a first branch 180 and a second branch, the first branch 180 being coupled to the transistor 174, the second branch being formed here by a PMOS type transistor 181, the second branch forming the output node 173 of the ramp generator 102.

The first branch 180 is a series circuit coupled between the power supply node 133 and ground 78 and includes a first transistor 182 (here of PMOS type), a second transistor 183 (here of NMOS type), and a resistor R ₂ Is provided for the resistor 184.

A gate terminal of the second transistor 183 is connected to a gate terminal of the transistor 174 of the ramp circuit 171. The gate terminal and the drain terminal of the first transistor 182 are connected to each other.

A source terminal of the transistor 181 is connected to the power supply node 133, and a gate terminal of the transistor 181 is connected to a gate terminal of the first transistor 182.

In practice, transistor 181 will ramp current I at the output _slope And provided to node 173 of ramp generator 102.

In use, when switch 176 is open, ramp current I _slope Has a time-dependent value of h (V _in -V _out ) The increasing trend given by/R.t, where h is a scaling factor, which may depend on, for example, the mirror factor m, the size of the transistors 181, 182, the resistance R of the resistor 184 ₂ And the capacitance C of the capacitor 175.

In practice, in this embodiment, the ramp current I _slope The rising slope of (a) is equal to h (V) _in -V _out ) R; i.e. ramp current I _slope Rising slope of (c) and at input voltage V _in And output voltage V _out Between which are locatedIs proportional to the difference in (c).

The description will be made below with reference to fig. 8 when the regulator 50 is in the step-down operation condition (V _in >V _out ) And the control device 55 operates the regulator 50 when operating in the valley current control mode.

In buck mode with valley current control, the first half period T of duration is in each cycle of the modulation signal PWM _OFF The last half period T preceding the duration in time _ON . In practice, the on phase of the regulator 50 follows the off phase in each cycle of the modulation signal PWM.

In the on phase, the drive logic 96 provides switch control signals T1, T2, T3, and T4 such that the first high side switch 68 and the second high side switch 82 are closed and the first low side switch 69 and the second low side switch 83 are open.

In the off phase, the drive logic 96 provides switch control signals T1, T2, T3, and T4 such that the first high side switch 68 and the second low side switch 83 are open and the first low side switch 69 and the second high side switch 82 are closed.

In practice, during the on phase, an inductor current I flows through the inductor 87 _L Follow current path I from input node 51 to output node 54 _ON As indicated by the dashed arrow in fig. 5. During the off phase, an inductor current I flows through the inductor 87 _L Follow current path I from ground 78 to output node 54 _OFF As indicated by the dashed arrow in fig. 5.

At the start time t of the nth cycle of the modulation signal PWM ₀ That is, on the rising edge of the clock signal CLK, the regulator 50 is in the off-phase.

During the off phase, the inductor current I _L From ground 78 to common node 72 through shunt resistor 80.

During the off phase, the inductor current I _L Decreasing over time to be linear and of slope equal to-V _out The trend of/L decreases to a first approximation.

During the off phase, the signal CMD keeps the switch 176 open.

Referring to time t at which the nth cycle starts ₀ Ramp current I _slope Can be represented by formula I _slope ＝h·(V _in -V _out )/R·(t-t ₀ ) Representation, wherein t ₀ Is the moment when the nth cycle starts.

Referring to fig. 6, during the off phase, the voltage v+ on the positive input 141 of the comparator 140 drops relative to ground 78, given by:

V+＝-I _L ·R _s +RA·(N·I’ _c +I _slope )

and the voltage V-on the negative input 142 of the comparator 140 drops relative to ground 78, given by:

V-＝I _bias ·R _B 。

when the voltage V+ is equal to the voltage V- (time t in FIG. 8 ₁ ) The comparator 140 triggers and switches the comparison signal COMP. In response, the PWM generator 144 switches the modulation signal PWM to a low value of "0". The regulator 50 enters the on phase.

Time t ₁ And time t ₀ The time interval between determines the duration T of the off phase of the regulator 50 _OFF 。

During the on phase, i.e. at time t ₁ And t ₂ Between, inductor current I _L Increase over time to be linear and slope with (V _in -V _out ) The proportional trend of/L increases to a first approximation.

The ramp generator 102 may be designed such that during the off phase, the ramp current I _slope Is higher than or equal to half the slope of the inductor current IL during the next turn-on phase; for example by modifying the scaling factor h and/or the resistor R during the design phase.

The signal CMD may drive the closing of the switch 176 at the beginning of the on phase of the nth cycle of the regulator 50 or drive the closing of the switch 176 during the on phase of the nth cycle of the regulator 50, for example near the end of the nth cycle of the regulator 50.

The timing of the closing of the signal CMD driving the switch 176 may be selected according to the discharge time of the capacitor 175, for example, such that the capacitor 176 is completely discharged at the beginning of the next n+1th cycle.

In the following discussion, the inductor current I _L So that at time t of the nth cycle ₁ Voltages V+ and V-have the same value and are referred to as threshold current I _th 。

Thus, at time t ₁ We have V+ (t ₁ )＝V-(t ₁ ) The method comprises the following steps:

-I _th ·R _s +R _A ·(N·I′ _c +I _slope (T _OFF ))＝R _B ·I _bias 。

thus, at time t when the modulation signal PWM transitions from the off-phase (pass) to the on-phase ₁ It can be written as:

and

In practice, the threshold current I of the transition from the off-phase to the on-phase in the nth cycle is determined _th According to the control current I _C Ramp current I _slope And offset current I _bias 。

Control voltage V _c Can be represented by formula V _c ＝I _C ·R _c +V _gs Representation, wherein V _gs Is the gate-to-source voltage of transistor 135, R _c Is the resistance of resistor 137 (fig. 6).

Further (fig. 8), an output current I is provided to a load 58 at an output node 54 _out Can be according to the relation I _out ＝I _th +ΔI/2 is expressed as inductor current I during the Nth cycle _L Wherein Δi/2 can in turn be represented in a manner known per se by the formula:

wherein V is _out /V _in Is the duty cycle of the modulation signal PWM in the Nth cycle, and f _sw Is the frequency of the modulation signal PWM, i.e. here equal to 1/T.

Thus, by controlling the voltage V _C Combining equations (2) and (3) can result in:

in practice, the offset current I _bias The presence of (1) allows compensation by the ramp current I _slope And control voltage V caused by current oscillation DeltaI _c Is provided.

In detail, the ramp current I _slope Slope and offset current I of (2) _bias Both according to the input voltage V _in And output voltage V _out This fact of difference between them allows to improve the control voltage V _c Is a dynamic interval of (a).

Furthermore, the applicant has found that the ramp current I _slope Slope and offset current I of (2) _bias Both are connected with the input voltage V _in And output voltage V _out The fact that the difference between them is proportional, in particular proportional, allows to further improve the control voltage V _c Is a dynamic interval of (a).

Fig. 9-11 show a voltage V of the known regulator 1 from fig. 1 and 2 _C According to the output voltage V _out According to input voltage V _in And according to the output current I _out Control voltage V of regulator 50 of (2) _C Trend of (3).

In detail, fig. 9 shows the control voltage V of both the known regulator 1 (dashed line) and the regulator 50 (solid line) _C With input voltage V _in An example of a trend of change, in which the current I is output _out Equal to 2A, output electricityPressure V _out Equal to 5V.

It is noted that the regulator 50 allows the acquisition of a voltage V according to the input voltage _in Control voltage V of (2) _c While the control voltage V of the known regulator 1 is approximately constant _c With input voltage V _in Is highly dependent on (a) is provided.

Fig. 10 shows the control voltage V of both the known regulator 1 (dashed line) and the regulator 50 (solid line) _C With output voltage V _out An example of a trend of change, in which the current I is output _out Equal to 2A, input voltage V _in Equal to 20V. It can be noted that, in comparison with the known regulator 1, the regulator 50 allows to obtain a voltage V according to the output voltage _out Control voltage V of (2) _C Is less variable.

Fig. 11 shows the control voltage V of both the known regulator 1 (dashed line) and the regulator 50 (solid line) _C With input voltage V _in An example of a trend of change, in which the current I is output _out With different values (5A, 10A, 20A and 40A).

Control voltage V of regulator 50 and known regulator 1 _C Depending on the output current I _out The method comprises the steps of carrying out a first treatment on the surface of the In practice, both the regulator 50 and the known regulator 1 are current controlled. However, even at the output current I _out The regulator 50 also allows to eliminate the control voltage V at different values of (a) _C For input voltage V _in To a first approximation).

Control voltage V of control device 55 _C For input voltage V _in The fact that the dependency of (a) is low allows the control means 55 to have a wider input voltage V than the input voltage of the known control means 5 given the same loop gain _in In-range and higher output current I _out The values work normally.

In addition, control voltage V _C For input voltage V _in Even at the input voltage V _in In the presence of a step of, for example, even a step of a few tens of volts, a control voltage V is required _C To apply the output voltage V with a small variation _out Maintained at reference value V _ref Where it is located.

Thus, the control device 55 allows to obtain a response to the input voltage V, compared to the known control device 5 _in Is a variable, shorter response time.

Finally, it is apparent that modifications and variations can be made to the control device 55 and regulator 50 described and illustrated herein without departing from the scope of the present disclosure.

The offset generator 100 and the ramp generator 102 may be separated from each other.

For example, the ramp generator 102 may not be powered by the correction circuit 100 with a voltage V _b Control is performed, but the input voltage V can be directly received _in And output voltage V _out (as indicated by the dashed arrow in fig. 4).

For example, offset generator 100 may generate offset current I in a different manner than shown _bias 。

For example, offset current I _bias Can be applied to input voltage V _in And output voltage V _out With different dependencies, e.g. non-linear dependencies.

Alternatively, the offset current I _bias Can be based solely on the input voltage V _in Or output voltage V _out 。

Additionally or alternatively, the ramp generator 102 may generate the ramp current I in a different manner than shown _slope . For example, ramp current I _slope Can be independent of the input voltage V _in And output voltage V _out The method comprises the steps of carrying out a first treatment on the surface of the For example, it may have a constant value selected by the user according to the particular application, or it may be specific to the input voltage V _in And output voltage V _out The differences between have different dependencies, such as non-linear dependencies.

For example, the comparator 140 may be configured to trigger when the voltage v+ is equal to the voltage V-plus or minus a threshold, which may be selected during the design phase depending on the particular application.

For example, the control device 55 may use a control pattern other than the valley type discussed with reference to fig. 8; for example, it may use a peak type (peak type) control mode in the buck mode.

Further, although the operation of the control device 55 has been described with reference to a buck mode having valley control, with reference to fig. 8, the control device 55 may also be used in boost and buck-boost modes, where the control of valley, peak or other modes is known per se. In this regard, the control device 55 may include a mode detector 180 (represented by the dashed line in FIG. 4), the mode detector 180 being configured to compare the input voltage V _in And output voltage V _out (or, alternatively, an input voltage V _in And output voltage V _out ) And in response, a mode signal MOD is provided that indicates the mode (buck, boost, or buck-boost) of regulator 50. For example, the driving logic 96 may generate the switching control signals T1, T2, T3, and T4 based on the modulation signal PWM according to the mode signal MOD.

For example, the PWM modulator 94 may generate the modulation signal PWM according to the mode signal MOD.

For example, the voltage-to-current conversion module 111 may include a current-limited mirror (current-limited mirror) such that the control current I provided at the output _C Lower than or equal to a maximum value, which may be selected according to the desired maximum current flowing through the switching circuit 53.

Loop control circuit 92, PWM modulator 94, drive logic 96, and threshold correction module 98 are modules that may be implemented as analog circuits, digital circuits, or mixed signal circuits, depending on the particular application.

For example, the present regulator may be configured to operate only in buck mode (V _in >V _out ) Or boost mode (V) _in <V _out ) And (5) operating.

Fig. 12 illustrates a different embodiment of the present regulator, here indicated at 200, configured to operate only in buck mode. The regulator 200 includes a switching circuit (indicated here at 203) and a control device (indicated here at 205).

As shown in fig. 13, the switching circuit 203 is formed of only the first half bridge 64.

In practice, in this embodiment, inductor 87 has a first terminal coupled to intermediate node 74 of first half-bridge 64 and a second terminal coupled directly to output node 54.

Regulator 200 also includes an output capacitor 208 coupled between output node 54 and ground 78.

The structure of the control device 205 is similar to that of the control device 55 of fig. 4; accordingly, common elements are denoted by the same reference numerals and will not be further described.

In detail, unlike the control device 55 of fig. 4, in the control device 205 of fig. 12, a driving logic circuit (denoted by 210 here) supplies only the first switching control signal T1 and the second switching control signal T2 to the switching circuit 203 based on the modulation signal PWM.

According to various embodiments, the control device 55, 205 may receive the inductor current I directly from one of the switches of the switching circuit 53, 203 _L Especially if the control means and the switching circuit are integrated in the same die.

For example, as shown in fig. 14, for the regulator 200 of fig. 13, a pwm modulator (denoted here as 257) may be directly coupled to a first low side switch 69 of a switching circuit (denoted here as 253).

In practice, the switching circuit 253 does not include a dedicated shunt resistor, and the comparator 140 of the PWM modulator 257 uses the ON-state resistance R of the low-side switch 69 _ds As a resistance element for detecting a current flowing in the switching circuit 253.

Using one of the switches of the switching circuit as a resistive element for detecting a current flowing in the switching circuit enables the power consumption of the voltage regulator to be reduced.

The embodiments described and illustrated herein may be combined to form additional solutions.

A control device (55; 205) for a switching voltage regulator (50; 200) may be summarized as including a switching circuit (53; 203; 253) configured to receive an input voltage (V _in ) And output voltage (V) _out ) And indicating a current (I) flowing in the switching circuit _L ) Is controlled by the measuring signal of (a)The device comprises: a feedback module (92) configured to detect an indication output voltage (V _out ) And nominal voltage (V) _ref ) Error signal of difference between (V _E ) And provides a control signal (I based on the error signal _C ) The method comprises the steps of carrying out a first treatment on the surface of the A threshold correction module (98, 100, 102) configured to provide an offset signal (I _bias ) And ramp signal (I _slope ) The method comprises the steps of carrying out a first treatment on the surface of the And a drive signal generation module (94, 96;94, 210; 257) coupled to the feedback module and to the threshold correction module and configured to receive the measurement signal, to combine the measurement signal with a threshold (I _th ) The comparison is performed and in response, a modulation signal (PWM, T1, T2, T3, T4; t1, T2), the threshold value being dependent on the control signal, on the offset signal and on the ramp signal, wherein the threshold correction module (98, 100) may be configured to provide a signal dependent on the input voltage (V _in ) And/or according to the output voltage (V _out ) Is provided.

The threshold correction module (100) may be configured to provide an offset signal according to a difference between the input voltage and the output voltage.

Offset signal (I) _slope ) May be proportional to the input voltage and to the output voltage.

The switching circuit (53; 203; 253) may comprise a resistive element (80; 69), the drive signal generation module (94, 96;94, 210; 257) comprising a comparator having a first input (141) configured to be coupled to a first terminal of the resistive element and a second input (142) configured to be coupled to a second terminal of the resistive element, the comparator being configured to receive a control signal (I _C ) And ramp signal (I _slope ) And receiving an offset signal (I at a second input _bias )。

The feedback module (92) may include a compensation module (110) configured to based on the error signal (V _E ) Generating a control voltage (V) _c ) The voltage-to-current conversion module is configured to convert the voltage (V) based on the control voltage (V _c ) A control signal is generated.

The ramp signal may have a slope, and the threshold correction module (98, 102) is configured to modify the slope of the ramp signal as a function of the input voltage and/or as a function of the output voltage.

The ramp signal may have a slope, and the threshold correction module is configured to modify the slope of the ramp signal according to a difference between the input voltage and the output voltage.

The threshold correction module may include an offset generator (100) and a ramp generator (102) coupled to the offset generator, the offset generator configured to provide an offset signal based on the input voltage and the output voltage, and to provide a ramp control signal (V) indicative of a difference between the input voltage and the output voltage _b ) The ramp generator (102) is configured to generate a ramp signal based on the ramp control signal.

A switching voltage regulator (50; 200) may be summarized as including the control device (55; 205) described above and a switching circuit (53; 203; 253) including at least one half-bridge (64, 65) and an inductor (87) coupled to an intermediate node (74, 85) of the half-bridge, the half-bridge including first and second switches (68, 69, 82, 83) coupled in series between a connection node (51, 54) and a common reference potential node (72; 78), wherein the first and second switches may be controlled by first and second switch control signals (T1, T2, T3, T4) generated by a drive signal generation module (94, 96;94, 210), respectively, based on a modulation signal (PWM).

The connection node may be configured to receive an input voltage (V _in ) At least one half-bridge is a first half-bridge (64), the switching circuit further comprises a second half-bridge (65), the second half-bridge (65) comprising a first half-bridge (51) coupled in series to a second half-bridge (65) configured to provide an output voltage (V _out ) Third and fourth switches (82, 83) between the output node (54) and the common reference potential node, the inductor being coupled between intermediate nodes (74, 85) of the first and second half-bridges, wherein the first, second, third and fourth switches may be controlled by first, second, third and fourth switch control signals (T1, T2, T3, T4), respectively, generated by the drive signal generation module (94, 96) based on the modulation signal (PWM).

A control method for a switching voltage regulator (50; 200) may be summarized as including a switching circuit (53; 203; 253) and a control device (55; 205) and configured to receive an input voltage (V _in ) And is configured to provide an output voltage (V _out ) The control method comprises the following steps: detecting an indication output voltage (V _out ) And nominal voltage (V) _ref ) Error signal of difference between (V _E ) The method comprises the steps of carrying out a first treatment on the surface of the Providing a control signal (I _C ) The method comprises the steps of carrying out a first treatment on the surface of the Providing a ramp signal (I _slope ) The method comprises the steps of carrying out a first treatment on the surface of the Providing an offset signal (I _bias ) The method comprises the steps of carrying out a first treatment on the surface of the Receives a signal indicating a current (I) flowing in the switching circuit _L ) Is a measurement signal of (a); the measurement signal is compared with a threshold value (I _th ) Comparing, wherein the threshold value may be based on the control signal, based on the offset signal, and based on the ramp signal; and providing a modulation signal (PWM, T1, T2, T3, T4) for driving the switching circuit in response to a comparison between the measurement signal and a threshold value, wherein the offset signal can be based on the input voltage (V _in ) And/or output voltage (V _out )。

The offset signal may be based on a difference between the input voltage and the output voltage.

The offset signal may be proportional to the input voltage and to the output voltage.

The ramp signal may have a slope that is proportional to and/or to the input voltage as a function of the difference between the input voltage and the output voltage.

The modulation signal (PWM) may have a period (T) with a duty cycle, the method comprising modifying the duty cycle of the modulation signal in response to a comparison between the measurement signal and a threshold value.

The various embodiments described above may be combined to provide embodiments of a network. These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the present disclosure.

Claims

1. A control device for a switching voltage regulator,

wherein the switching voltage regulator includes a switching circuit configured to receive an input voltage and output an output voltage,

Wherein the control device is configured to receive the input voltage, the output voltage, and a measurement signal indicative of a current flowing in the switching circuit, and

wherein the control device comprises:

a feedback stage configured to:

detecting an error signal indicative of a difference between the output voltage and a nominal voltage; and

providing a control signal in accordance with the error signal;

a threshold correction stage configured to provide an offset signal and a ramp signal; and

a drive signal generation stage coupled to the feedback stage and the threshold correction stage and configured to:

receiving the measurement signal;

comparing the measurement signal with a threshold value, the threshold value being in accordance with the control signal, the offset signal and the ramp signal; and

providing a modulation signal for driving the switching circuit in response to comparing the measurement signal with the threshold value,

wherein the threshold correction stage is configured to provide the offset signal in dependence on the input voltage or the output voltage.

2. The control device of claim 1, wherein the threshold correction stage is configured to:

the offset signal is provided according to a difference between the input voltage and the output voltage.

3. The control device of claim 1, wherein the offset signal is proportional to the input voltage and the output voltage.

4. The control device of claim 1, wherein the switching circuit comprises a resistive element, wherein the drive signal generation stage comprises a comparator having a first input configured to be coupled to a first terminal of the resistive element and a second input configured to be coupled to a second terminal of the resistive element, and wherein the comparator is configured to: the control signal and the ramp signal are received at the first input and the offset signal is received at the second input.

5. The control device of claim 1, wherein the feedback stage comprises a compensation stage and a voltage-to-current conversion stage, wherein the compensation stage is configured to generate a control voltage based on the error signal, and wherein the voltage-to-current conversion stage is configured to generate the control signal based on the control voltage.

6. The control device of claim 1, wherein the ramp signal has a slope and the threshold correction stage is configured to modify the slope of the ramp signal as a function of the input voltage or the output voltage.

7. The control device of claim 1, wherein the ramp signal has a slope and the threshold correction stage is configured to modify the slope of the ramp signal as a function of a difference between the input voltage and the output voltage.

8. The control device of claim 1, wherein the threshold correction stage comprises an offset generator and a ramp generator coupled to the offset generator, wherein the offset generator is configured to provide the offset signal based on the input voltage and the output voltage and to provide a ramp control signal indicative of a difference between the input voltage and the output voltage, and wherein the ramp generator is configured to generate the ramp signal based on the ramp control signal.

9. A switching voltage regulator, comprising:

a switching circuit configured to receive an input voltage and output an output voltage, wherein the switching circuit comprises:

at least one half-bridge having an intermediate node and first and second switches coupled in series between a connection node and a common reference potential node, wherein the first and second switches are controlled by first and second switch control signals, respectively; and

An inductor coupled to the intermediate node; and

a control device comprising:

a feedback stage configured to:

providing a control signal in accordance with the error signal;

receiving a measurement signal indicative of a current flowing in the switching circuit;

comparing the measurement signal with a threshold value, the threshold value being in accordance with the control signal, the offset signal and the ramp signal;

providing a modulation signal for driving the switching circuit in response to comparing the measurement signal to the threshold value; and

generating the first switch control signal and the second switch control signal based on the modulation signal,

10. The switching voltage regulator of claim 9, wherein:

the connection node is an input node configured to receive the input voltage,

The at least one half bridge is a first half bridge,

the switching circuit comprises a second half-bridge comprising a third switch and a fourth switch coupled in series between an output node configured to provide the output voltage and the common reference potential node,

the inductor is coupled between intermediate nodes of the first half-bridge and the second half-bridge,

the third switch and the fourth switch are controlled by a third switch control signal and a fourth switch control signal, respectively, generated by the driving signal generation stage based on the modulation signal.

11. The switching voltage regulator of claim 9, wherein the threshold correction stage is configured to:

12. The switching voltage regulator of claim 9, wherein the offset signal is proportional to the input voltage and the output voltage.

13. The switching voltage regulator of claim 9, wherein the switching circuit comprises a resistive element, wherein the drive signal generation stage comprises a comparator having a first input configured to be coupled to a first terminal of the resistive element and a second input configured to be coupled to a second terminal of the resistive element, and wherein the comparator is configured to: the control signal and the ramp signal are received at the first input and the offset signal is received at the second input.

14. The switching voltage regulator of claim 9, wherein the feedback stage comprises a compensation stage and a voltage-to-current conversion stage, wherein the compensation stage is configured to generate a control voltage based on the error signal, and wherein the voltage-to-current conversion stage is configured to generate the control signal based on the control voltage.

15. The switching voltage regulator of claim 9, wherein the ramp signal has a slope and the threshold correction stage is configured to modify the slope of the ramp signal as a function of the input voltage or the output voltage.

16. A method for controlling a switching voltage regulator, comprising:

detecting an error signal indicative of a difference between an output voltage of the switching voltage regulator and a nominal voltage;

providing a control signal in accordance with the error signal;

providing a ramp signal;

providing an offset signal;

receiving a measurement signal indicative of a current flowing in a switching circuit of the switching voltage regulator;

comparing the measurement signal with a threshold, wherein the threshold is based on the control signal, the offset signal, and the ramp signal; and

Wherein the offset signal is dependent on an input voltage of the switching voltage regulator or the output voltage of the switching voltage regulator.

17. The method of claim 16, wherein the offset signal is according to a difference between the input voltage and the output voltage.

18. The method of claim 16, wherein the offset signal is proportional to the input voltage and to the output voltage.

19. The method of claim 16, wherein the ramp signal has a slope that is dependent on a difference between the input voltage and the output voltage or is proportional to the input voltage and to the output voltage.

20. The method of claim 16, wherein the modulated signal has a period with a duty cycle, the method comprising modifying the duty cycle of the modulated signal in response to comparing the measured signal to the threshold value.