CN117276232A - Chip packaging structure and manufacturing method - Google Patents

Chip packaging structure and manufacturing method Download PDF

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Publication number
CN117276232A
CN117276232A CN202311162054.3A CN202311162054A CN117276232A CN 117276232 A CN117276232 A CN 117276232A CN 202311162054 A CN202311162054 A CN 202311162054A CN 117276232 A CN117276232 A CN 117276232A
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CN
China
Prior art keywords
wiring layer
layer
density
chip
manufacturing
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CN202311162054.3A
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Chinese (zh)
Inventor
赵瑾
于大全
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Xiamen Yun Tian Semiconductor Technology Co ltd
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Xiamen Yun Tian Semiconductor Technology Co ltd
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Priority to CN202311162054.3A priority Critical patent/CN117276232A/en
Publication of CN117276232A publication Critical patent/CN117276232A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings

Abstract

The application relates to a chip packaging structure and a manufacturing method, wherein the chip packaging structure comprises a substrate, a glass medium layer, a mixed film high-density wiring layer and a chip which are sequentially arranged, the glass medium layer and the mixed film high-density wiring layer are used for electrically connecting the substrate and the chip, and the mixed film high-density wiring layer at least comprises a layer of high-density fine line width wiring layer and a layer of photosensitive wiring layer. The inorganic dielectric layer for preparing the high-density fine line width can be directly prepared on a substrate wafer by a deposition and etching process, the windowing capability can meet the requirement of fine spacing, compared with the process that a photosensitive material is used as the dielectric layer to prepare the fine line width, the method can greatly relieve the problem of binding force between the dielectric layer and the substrate, reduce the stress accumulation of the dielectric layer and improve the packaging process and the reliability under real service. And the side wall of the prepared high-density metal interconnection layer is smooth and has no steps, and the perpendicularity is high, so that the transmission loss can be reduced, and the high-frequency high-speed interconnection requirement can be met.

Description

Chip packaging structure and manufacturing method
Technical Field
The present disclosure relates to semiconductor packaging technology, and more particularly, to a chip packaging structure and a method for manufacturing the same.
Background
The re-wiring layer (RDL) interconnection technology is mainly applied to the technical field of chip packaging, and is used for solving the problem of high-density interconnection and improving the number of I/O signals. RDL technology re-lays out the I/O ports of the chip by depositing metal layers and dielectric layers on the wafer surface and forming corresponding metal wiring patterns to place them into new, more loosely spaced areas.
Currently, the technology of RDL interconnection based on silicon base commonly used in the art mainly adopts polymer as passivation layer/insulating layer, which is coated on the surface of the wafer, and then is filled with metal such as copper for electrical interconnection. However, the existing passivation layer is easy to cause the problem of stress accumulation, so that the bonding force between the passivation layer and the substrate is poor; the conventional RDL preparation technology has a reduction method, a semi-addition method, an embedding method and the like, and the methods have the problems of side etching, low photoetching precision and the like; in addition, the conventional RDL interconnection technology has large polymer window size and low flatness during laser processing, and is difficult to meet the requirement of high-density wiring.
Disclosure of Invention
Aiming at the problems in the background technology, the application provides a chip packaging structure and a manufacturing method, and adopts the following technical scheme:
in a first aspect, the present application proposes a chip package structure, including base plate, glass intermediate layer, mixed film high density wiring layer and the chip that set gradually, glass intermediate layer and mixed film high density wiring layer are used for electrically connecting base plate and chip, mixed film high density wiring layer includes one deck high density thin linewidth wiring layer and one deck photosensitive wiring layer at least, just photosensitive wiring layer sets up the one side that keeps away from the base plate at the thin linewidth wiring layer of high density.
By adopting the technical scheme, the chip packaging structure greatly relieves the problem of the binding force between the dielectric layer and the substrate, reduces the stress accumulation of the dielectric layer, and improves the packaging process and the reliability under real service.
Preferably, the high-density fine line width wiring layer at least comprises a wiring insulating layer made of an inorganic medium and a wiring layer formed by a metal wiring layer made of copper/aluminum, wherein the inorganic medium material can be an inorganic thin film material such as silicon oxide or silicon nitride.
Preferably, the thickness of the metal wiring layer of the high-density fine line width wiring layer is 1-3 um, and the wire pitch of the metal wiring layer is 1.5-5 um.
Preferably, the photosensitive wiring layer includes at least one wiring insulating layer made of a photosensitive polymer and a wiring layer composed of a metal wiring layer made of copper/aluminum.
Preferably, the thickness of the metal wiring layer of the photosensitive wiring layer is 3-7um, and the wire distance of the metal wiring layer is larger than 5um.
In a second aspect, the present application further provides a method for manufacturing a chip package structure, including the following steps
The steps are as follows:
s1: manufacturing a glass medium layer;
s2: manufacturing a mixed film high-density wiring layer on the surface of the glass medium layer, wherein the mixed film high-density wiring layer at least comprises a layer of high-density fine line width wiring layer and a layer of photosensitive wiring layer;
s3: packaging the chip on the mixed film high-density wiring layer;
s4: the chip, the mixed film high-density wiring layer and the glass interposer are flip-chip mounted on the substrate.
Preferably, the S1 specifically includes:
providing a substrate;
manufacturing a blind hole on a substrate;
and filling the blind holes with metal.
Preferably, in the step S2, the step of fabricating the high-density fine line width wiring layer includes:
manufacturing an inorganic medium layer on the glass medium layer;
etching a window on the inorganic dielectric layer, and manufacturing a first metal wiring layer in the window area, wherein the first metal wiring layer is connected with metal in a blind hole of the inorganic dielectric layer.
Preferably, in the step S2, the step of fabricating the photosensitive wiring layer includes:
manufacturing a photosensitive medium layer on the surface of the high-density fine line width wiring layer;
and photoetching a window on the photosensitive medium layer, and manufacturing a third metal wiring layer in the window area, wherein the third metal wiring layer is electrically connected with the first metal wiring layer.
Preferably, the S4 specifically includes:
thinning the back surface of the glass medium layer to expose the metal in the blind holes;
preparing copper columns, wherein the copper columns are connected with the metal exposed out of the back surface of the glass medium layer;
the chip, the hybrid thin film high density wiring layer and the glass interposer are flip-chip mounted on the substrate using copper pillars.
The application relates to a chip packaging structure, it is including base plate, glass intermediate layer, mixed film high density wiring layer and the chip that sets gradually, glass intermediate layer and mixed film high density wiring layer are used for electric connection base plate and chip, and mixed film high density wiring layer includes one deck high density thin linewidth wiring layer and one deck photosensitive wiring layer at least. The inorganic dielectric layer for preparing the high-density fine line width can be directly prepared on a substrate wafer by a deposition and etching process, the windowing capability can meet the requirement of fine spacing, compared with the process that a photosensitive material is used as the dielectric layer to prepare the fine line width, the method can greatly relieve the problem of binding force between the dielectric layer and the substrate, reduce the stress accumulation of the dielectric layer and improve the packaging process and the reliability under real service. In addition, the side wall of the prepared high-density metal interconnection layer is smooth and has no steps and high perpendicularity, so that the transmission loss can be reduced, and the high-frequency high-speed interconnection requirement can be met; compared with the high-density wiring layer formed by the traditional semi-addition process, the high-density metal wiring layer is embedded into the inorganic medium layer, so that higher surface flatness can be realized, and the integration requirement of a high-power chip and a large-scale integrated circuit on high flatness can be met; the intermediate layer in the structure of the invention adopts glass material, and has wider optional range of glass transition temperature, thermal expansion coefficient, modulus and the like than silicon-based material, smaller dielectric loss than silicon material, low transmission loss, capability of providing high-frequency transmission service and wider application range.
Drawings
The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments and, together with the description, serve to explain the principles of the present application. Many of the intended advantages of other embodiments and embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
Fig. 1 is a schematic structural diagram of a chip package structure according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of the blind hole according to the embodiment of the present application.
Fig. 3 is a schematic structural diagram of a hybrid thin film high density wiring layer for embodying the embodiment of the present application.
Fig. 4 is an enlarged partial schematic view of the portion a in fig. 3.
Fig. 5 is a schematic diagram of a connection portion of a chip and a mixed film high-density wiring layer in an embodiment of the present application.
Fig. 6 is a schematic top view of a multilayer wiring layer in an embodiment of the present application.
Fig. 7 is a schematic view of a manufacturing process of a glass interposer in an embodiment of the present application.
Fig. 8 is a schematic view of a process for fabricating a high-density fine-line-width wiring layer in an embodiment of the present application.
Fig. 9 is a schematic view of a manufacturing process of a photosensitive wiring layer in an embodiment of the present application.
Fig. 10 is a schematic diagram of a chip packaging process in an embodiment of the present application.
Fig. 11 is a schematic diagram of a process flow for flip-chip mounting a chip, a hybrid thin film high density wiring layer, and a glass interposer on a substrate in an embodiment of the present application.
Reference numerals illustrate: 1. a substrate; 2. a glass interposer; 3. a hybrid thin film high density wiring layer; 4. a chip; 5. a blind hole; 6. a high-density fine line width wiring layer; 7. a photosensitive wiring layer; 8. a first wiring layer; 9. a second wiring layer; 10. a third wiring layer; 11. a fourth wiring layer; 13. copper columns; 15. a chip heat dissipation structure; 16. a metal pad; 17. a first wiring insulating layer; 18. a first metal wiring layer; 19. a second wiring insulating layer; 20. a second metal wiring layer; 21. a third wiring insulating layer; 22. a third metal wiring layer; 23. a fourth wiring insulating layer; 24. a fourth metal wiring layer; 25. an inorganic dielectric layer; 26. a photosensitive dielectric layer; 27. a primer; 28. a metal cover.
Detailed Description
The present application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Referring to fig. 1, a chip package structure disclosed in the embodiments of the present application includes a glass interposer 2, a hybrid thin film high-density wiring layer 3, a chip 4, and a substrate 1.
Referring to fig. 2, in a specific embodiment, a blind via 5 is provided on the glass interposer 2, and the blind via 5 is filled with metal. In a specific embodiment, blind holes 5 are formed in a specific area on the upper surface of the wafer by a laser-induced +wet etching technology and metal filling is performed.
Referring to fig. 3, in a specific embodiment, the hybrid thin film high-density wiring layer 3 includes at least one high-density thin line width wiring layer 6 and one photosensitive wiring layer 7, the high-density thin line width wiring layer 6 is disposed on the upper surface of the glass interposer 2, and the photosensitive wiring layer 7 is disposed on the surface of the high-density thin line width wiring layer 6 on the side away from the glass interposer 2.
Referring to fig. 3 and 4, in a specific embodiment, the high-density fine line width wiring layer 6 includes a first wiring insulating layer 17 made of an inorganic medium and a first metal wiring layer 18 made of copper/aluminum. The first wiring insulating layer 17 and the first metal wiring layer 18 constitute a first layer wiring layer 8, the high-density fine line width wiring layer 6 is made of an inorganic medium as a wiring insulating layer, and the high-density fine line width wiring layer 6 is made of metal copper/aluminum as a signal transmission medium.
In a specific embodiment, the high-density fine line width wiring layer 6 includes two wiring layers, specifically, a first wiring layer 8 and a second wiring layer 9, the second wiring layer 9 is provided on the first wiring layer 8, the first wiring layer 8 includes a first wiring insulating layer 17 and a first metal wiring layer 18, and the second wiring layer 9 includes a second wiring insulating layer 19 and a second metal wiring layer 20.
In a specific embodiment, the thickness of the metal wiring layer of the high-density fine line width wiring layer 6 is 1 to 3um, and the metal wiring line width/line spacing (L/S) is 1.5 to 5um.
In a specific embodiment, the photosensitive wiring layer 7 is made by a wafer level thin film deposition, dry etching, electroplating, and chemical mechanical polishing process.
The photosensitive wiring layer 7 includes a third wiring insulating layer 21 made of a photosensitive polymer and a third metal wiring layer 22 made of copper/aluminum. The photosensitive polymer serves as a wiring insulating layer, and the metallic copper/aluminum serves as a signal transmission medium.
In a specific embodiment, the photoactive wiring layer 7 is provided with two wiring layers, specifically a third wiring layer 10 and a fourth wiring layer 11, the fourth wiring layer 11 being provided on the third wiring layer 10, the third wiring layer 10 including a third wiring insulating layer 21 and a third metal wiring layer 22, the fourth wiring layer 11 including a fourth wiring insulating layer 23 and a fourth metal wiring layer 24.
In a specific embodiment, the thickness of the metal wiring layer of the photosensitive wiring layer is set to 3-7um, and the metal wiring line width/line spacing (L/S) is greater than 5um.
In a specific embodiment, the photosensitive wiring layer 7 is made of a wafer-level coating polymer, high temperature curing, electroplating, and chemical mechanical polishing process.
In a specific embodiment, the side wall of the mixed film high-density wiring layer 3 is smooth and has no step, and the inclination angle of the side wall and the lower surface of the mixed film high-density wiring layer 3 is 85-90 degrees.
In a specific embodiment, the chip 4 is disposed on the photosensitive wiring layer 7, after the preparation of the photosensitive wiring layer 7 is completed, the integration of multiple chips 4 is realized by flip chip bonding of chips 4 with different functions, the chips 4 are packaged and protected in a plastic packaging mode, and the back plastic packaging material is ground and thinned to the back of the chips 4.
In a specific embodiment, at least two chips 4 are disposed on the photosensitive wiring layer, at least two chips 4 have micro-bumps for external interconnection, and the micro-bumps of the chips 4 are connected with the mixed film high-density wiring layer 3 (interconnection layer) formed by the high-density fine line width wiring layer 6 and the photosensitive wiring layer 7 in a flip-chip bonding manner.
Referring to fig. 5, in a specific embodiment, the lower surface of the glass interposer 2 has copper pillars 13 or solder ball bumps, and the signal transmission between the upper and lower surfaces of the glass interposer 2 is realized by a vertical glass via interconnection structure in the glass interposer 2, and the copper pillars 13 or solder ball bumps on the lower surface of the glass interposer are soldered to the substrate 1.
In a specific embodiment, the copper exposure of the TGV blind holes 5 is performed by a back thinning mode to realize the electric interconnection of the front and back sides of the substrate 1, and the copper pillars 13 are prepared by an electroplating mode and then are inverted to the substrate 1.
Referring to fig. 1, in a specific embodiment, the chip packaging structure further includes a primer 27 and a metal cover 28, where the primer 27 is disposed on the substrate 1 for filling and packaging the copper pillar 13, and the metal cover 28 is disposed on a side of the chip away from the substrate for packaging the flipped chip, the mixed film high-density wiring layer and the glass interposer.
Referring to fig. 6, the package structure further includes a chip heat dissipation structure 15 and a metal pad 16 to realize the preparation of the hybrid thin film multilayer high-density wiring of the high-thermal-conductivity substrate.
In a second aspect, the present application further discloses a method for manufacturing a chip package structure, which specifically includes the following steps:
s1: manufacturing a glass medium layer;
wherein S1 comprises:
providing a substrate;
making a blind hole 5 on the substrate;
the blind holes 5 are metal filled.
In one embodiment, a wafer with a polished and cleaned surface is provided, and is subjected to a heat treatment under a nitrogen atmosphere, and blind holes 5 are formed in a specific area on the upper surface of the wafer by a laser-induced +wet etching technique and metal filling is performed. As shown in fig. 7, the flow in this example is specifically (a) wafer cleaning and heat treatment, (b) TGV blind via preparation, and (c) blind via filling.
S2: manufacturing a mixed film high-density wiring layer on the surface of the glass intermediate layer 2, wherein the mixed film high-density wiring layer at least comprises a layer of high-density fine line width wiring layer and a layer of photosensitive wiring layer;
in S2, the manufacturing step of the high-density thin line width wiring layer 6 includes:
an inorganic medium layer 25 is manufactured on the glass medium layer 2;
a window is made in the inorganic dielectric layer 25, and a first metal wiring layer 18 is formed in the window area, and the first metal wiring layer 18 is connected to the metal in the blind via 5 of the glass interposer.
In S2, the manufacturing step of the photosensitive wiring layer 7 includes:
a photosensitive medium layer 26 is manufactured on the surface of the high-density fine line width wiring layer 6;
a window is made in the photosensitive dielectric layer 26, and a third metal wiring layer 22 is formed in the window area, and the third metal wiring layer 22 is electrically connected to the first metal wiring layer 18.
In a specific embodiment, the wafer surface of the step S1 is windowed in a required area by a damascene method through processes such as deposition of an inorganic dielectric layer and dry etching, and fine-pitch RDL metallization is realized through processes such as wafer level electroplating and CMP, so that the TGV blind holes 5 are interconnected with the fine-pitch RDL, and a first wiring layer 8 is formed; the above steps are then repeated to form a high-density fine line width wiring layer having the second layer wiring layer 9. As shown in fig. 8, the manufacturing flow of the high-density fine line width wiring layer 6 in this embodiment includes the steps of: (d) Depositing an inorganic medium layer, (e) patterning a mask layer, (f) etching, (g) removing the mask layer, (h) pattern metallization, (i) forming a first wiring layer (chemical mechanical polishing), and (j) manufacturing a second wiring layer.
In a specific embodiment, the wafer surface on which the high-density fine-line-width wiring layer 6 is manufactured is patterned by spin-coating the photosensitive dielectric layer 26, exposing to light, and windowing in a specific area, and interconnection between the photosensitive wiring layer 7 and the fine-pitch RDL is realized by electroplating filling and other processes, so as to form the photosensitive dielectric layer and the third metal wiring layer 22; then repeating the steps to form a photosensitive wiring layer 7 with a fourth wiring layer 11, and completing the manufacture of the mixed film high-density wiring; as shown in fig. 9, the manufacturing flow of the photosensitive wiring layer 7 in this embodiment includes the steps of: (k) Spin-coating a photosensitive medium layer, (i) photoetching and windowing, (m) pattern metallization, (n) manufacturing a third wiring layer (chemical mechanical polishing), and (o) manufacturing a fourth wiring layer.
S3: packaging the chip 4 on the mixed film high-density wiring layer 3;
in a specific embodiment, flip chip bonding is performed on the product prepared by the photosensitive wiring layer 7 to realize multi-chip integration of chips 4 with different functions, the chips 4 are packaged and protected in a plastic packaging mode, and the back plastic packaging material is ground and thinned to the back of the chips 4; as shown in fig. 10, the flow in this embodiment includes: and (p) sticking, (q) plastic packaging and (r) plastic packaging material thinning.
S4: the chip 4, the mixed film high-density wiring layer 3 and the glass interposer 2 are flip-chip mounted on the substrate 1.
Wherein, S4 specifically includes:
thinning the back surface of the glass interposer 2 to expose the metal in the blind holes 5;
preparing copper columns 13, wherein the copper columns 13 are connected with the metal exposed out of the back surface of the glass interposer 2;
the chip 4, the mixed film high-density wiring layer 3, and the glass interposer 2 are flip-chip mounted on the substrate 1 by using the copper pillars 13.
In a specific embodiment, copper exposure of the TGV blind hole 5 is performed by a back thinning mode to realize electrical interconnection of the front side and the back side of the substrate 1; after that, the copper pillars 13 are prepared by electroplating and then flip-chip mounted on the substrate 1. As shown in fig. 11, the flow of this embodiment includes: (s) back thinning exposed copper, (t) copper column preparation, (u) flip chip mounting to a substrate.
In summary, the present invention includes at least one of the following beneficial technical effects:
1. the inorganic dielectric layer for preparing the high-density fine line width can be directly prepared on a substrate wafer by a deposition and etching process, the windowing capability can meet the requirement of fine spacing, compared with the process that a photosensitive material is used as the dielectric layer for preparing the fine line width, the method can greatly relieve the problem of binding force between the dielectric layer and the substrate, reduce the stress accumulation of the dielectric layer and improve the packaging process and the reliability under real service. And the side wall of the prepared high-density metal interconnection layer is smooth and has no steps, and the perpendicularity is high, so that the transmission loss can be reduced, and the high-frequency high-speed interconnection requirement can be met.
2. Compared with the high-density wiring layer formed by the traditional semi-addition process, the glass interposer packaging structure for realizing high-density wiring by adopting the Damascus process can realize higher surface flatness by embedding the high-density metal wiring layer into the inorganic dielectric layer, and can meet the integration requirement of high-power chips and large-scale integrated circuits on high flatness.
3. The intermediate layer in the structure of the invention adopts glass material, and has wider optional range of glass transition temperature, thermal expansion coefficient, modulus and the like than silicon-based material, smaller dielectric loss than silicon material, low transmission loss, capability of providing high-frequency transmission service and wider application range.
While the present invention has been described with reference to the specific embodiments thereof, the scope of the present invention is not limited thereto, and any changes or substitutions will be apparent to those skilled in the art within the scope of the present invention, and are intended to be covered by the present invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
In the description of the present application, it should be understood that the terms "upper," "lower," "inner," "outer," and the like indicate an orientation or a positional relationship based on that shown in the drawings, and are merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element in question must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application. The word 'comprising' does not exclude the presence of elements or steps not listed in a claim. The word 'a' or 'an' preceding an element does not exclude the presence of a plurality of such elements. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims shall not be construed as limiting the scope.

Claims (10)

1. A chip packaging structure, characterized in that: the high-density wiring device comprises a substrate, a glass intermediate layer, a mixed film high-density wiring layer and a chip which are sequentially arranged, wherein the glass intermediate layer and the mixed film high-density wiring layer are used for electrically connecting the substrate and the chip, the mixed film high-density wiring layer at least comprises a layer of high-density fine line width wiring layer and a layer of photosensitive wiring layer, and the photosensitive wiring layer is arranged on one side, far away from the substrate, of the high-density fine line width wiring layer.
2. The chip package structure of claim 1, wherein: the high-density fine line width wiring layer at least comprises a wiring insulating layer made of inorganic medium and a wiring layer composed of metal wiring layer made of copper/aluminum.
3. The chip package structure according to claim 2, wherein: the thickness of the metal wiring layer of the high-density fine line width wiring layer is 1-3 um, and the wire distance of the metal wiring layer is 1.5-5 um.
4. A chip package structure according to claim 3, wherein: the photosensitive wiring layer includes at least one wiring insulating layer made of a photosensitive polymer and a wiring layer composed of a metal wiring layer made of copper/aluminum.
5. The chip package structure according to claim 4, wherein: the thickness of the metal wiring layer of the photosensitive wiring layer is 3-7um, and the wire distance of the metal wiring layer is larger than 5um.
6. A manufacturing method of a chip packaging structure is characterized by comprising the following steps: the method comprises the following steps:
s1: manufacturing a glass medium layer;
s2: manufacturing a mixed film high-density wiring layer on the surface of the glass medium layer, wherein the mixed film high-density wiring layer at least comprises a layer of high-density fine line width wiring layer and a layer of photosensitive wiring layer;
s3: flip-chip mounting the chip on the mixed film high-density wiring layer;
s4: the chip, the mixed film high-density wiring layer and the glass interposer are flip-chip mounted on the substrate.
7. The method for manufacturing a chip package according to claim 6, wherein: the S1 specifically comprises the following steps:
providing a substrate;
manufacturing a blind hole on a substrate;
and filling the blind holes with metal.
8. The method for manufacturing a chip package according to claim 6, wherein: in the step S2, the step of fabricating the high-density fine line width wiring layer includes:
manufacturing an inorganic medium layer on the glass medium layer;
etching a window on the inorganic dielectric layer, and manufacturing a first metal wiring layer in the window area, wherein the first metal wiring layer is connected with metal in a blind hole of the glass intermediate layer.
9. The method for manufacturing a chip package according to claim 6, wherein: in the step S2, the step of fabricating the photosensitive wiring layer includes:
manufacturing a photosensitive medium layer on the surface of the high-density fine line width wiring layer;
and photoetching a window on the photosensitive medium layer, and manufacturing a third metal wiring layer in the window area, wherein the third metal wiring layer is electrically connected with the first metal wiring layer.
10. The method for manufacturing a chip package according to claim 6, wherein: the step S4 specifically comprises the following steps:
thinning the back surface of the glass medium layer to expose the metal in the blind holes;
preparing copper columns, wherein the copper columns are connected with the metal exposed out of the back surface of the glass medium layer;
the chip, the hybrid thin film high density wiring layer and the glass interposer are flip-chip mounted on the substrate using copper pillars.
CN202311162054.3A 2023-09-11 2023-09-11 Chip packaging structure and manufacturing method Pending CN117276232A (en)

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