CN117275392A - Pixel circuit, display panel and driving method thereof - Google Patents

Pixel circuit, display panel and driving method thereof Download PDF

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Publication number
CN117275392A
CN117275392A CN202311080012.5A CN202311080012A CN117275392A CN 117275392 A CN117275392 A CN 117275392A CN 202311080012 A CN202311080012 A CN 202311080012A CN 117275392 A CN117275392 A CN 117275392A
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CN
China
Prior art keywords
voltage
capacitor
data voltage
data
light emitting
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CN202311080012.5A
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Chinese (zh)
Inventor
孙丽娜
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Tianyi Microelectronics Hangzhou Co ltd
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Tianyi Microelectronics Hangzhou Co ltd
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Priority to CN202311080012.5A priority Critical patent/CN117275392A/en
Publication of CN117275392A publication Critical patent/CN117275392A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0673—Adjustment of display parameters for control of gamma adjustment, e.g. selecting another gamma curve

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The application discloses a pixel circuit, a display panel and a driving method. The pixel circuit includes: the driving tube is characterized in that a control end of the driving tube receives data voltage, a first current end of the driving tube is connected to power supply voltage, and a second current end of the driving tube provides driving signals; the first capacitor is connected between the control end of the driving tube and the first current end and is at least used for storing data voltage; the second capacitor is connected between the data line and the first current end of the driving tube and is used for coupling in data voltage; and a light emitting element connected to the second current terminal of the driving tube to emit light according to the driving signal, wherein, in a data writing stage, a voltage on the data line is ac-converted from an initial data voltage to a final data voltage and transmitted to the first capacitor through the second capacitor, so that the first capacitor stores the data voltage. The pixel circuit adopts an alternating current mode to couple the effective data voltage into the first capacitor through the second capacitor, so that the accuracy of the data voltage can be improved, and the display effect can be improved.

Description

Pixel circuit, display panel and driving method thereof
Technical Field
The invention relates to the technical field of display, in particular to a pixel circuit, a display panel and a driving method thereof.
Background
In the field of display technology, pixel circuits are an important component of display panels. In the current display panel, the gamma voltage precision of the pixel circuit is low, so that the display gray scale (i.e. brightness) is poor, and the display effect is seriously affected.
Therefore, a pixel circuit is required to solve the above technical problems.
Disclosure of Invention
In view of the foregoing, it is an object of the present invention to provide a pixel circuit, a display panel and a driving method thereof, which can improve the accuracy of effective data voltages.
According to a first aspect of the present invention, there is provided a pixel circuit comprising:
the driving tube is characterized in that a control end of the driving tube receives data voltage, a first current end of the driving tube is connected to power supply voltage, and a second current end of the driving tube provides driving signals;
the first capacitor is connected between the control end and the first current end of the driving tube and is at least used for storing the data voltage;
the second capacitor is connected between the data line and the first current end of the driving tube and is used for coupling the data voltage; and
a light emitting element connected to the second current end of the driving tube for emitting light according to the driving signal,
in the data writing stage, the voltage on the data line is converted from the initial data voltage to the final data voltage in an alternating mode and is sent to the first capacitor through the second capacitor, so that the first capacitor stores the data voltage.
Optionally, the data voltage stored by the first capacitor is a divided voltage of an effective data voltage across the first capacitor, the effective data voltage being a difference voltage between the initial data voltage and a final data voltage,
the data voltage and the effective data voltage have a predetermined ratio, which is a ratio between a capacitance value of the first capacitor and a total capacitance value of the first capacitor and the second capacitor.
Optionally, when the effective data voltage is 0, the light emitting element does not emit light, and when the effective data voltage is not 0, the brightness of the light emitting element is at least related to the voltage amplitude of the partial voltage of the effective data voltage on the first capacitor.
Optionally, the first capacitor is further configured to store a threshold voltage of the driving transistor during the data writing phase.
Optionally, the method further comprises:
a first switching tube connected between the light emitting element and the power supply voltage; and/or
The second switch tube is connected between the data line and the second capacitor; and/or
A third switching tube connected between the anode of the light emitting element and a first reference voltage; and/or
And the fourth switching tube is connected between the control end of the driving tube and the second reference voltage.
Optionally, in the initializing stage, the third switching tube is turned on to reset the light emitting element, and the fourth switching tube is turned on to store the threshold voltage of the driving tube on the first capacitor;
in a data writing stage, the second switch tube is conducted so that the voltage on the data line is coupled in through the second capacitor, and the first capacitor stores the data voltage;
in the light emitting stage, the first switching tube is continuously or intermittently conducted to provide a driving signal to the light emitting element.
Optionally, the on/off of the first switching tube is controlled by a dimming signal, and in the lighting stage, the dimming signal is a pulse width modulation signal to control the lighting brightness of the lighting element.
Optionally, the driving transistor, the first switching transistor, the second switching transistor, the third switching transistor, and the fourth switching transistor are single crystal silicon complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) transistors, field effect transistors (Field Effect Transistor, FETs), thin film transistors (Thin Film Transistor, TFT), low temperature poly oxide (Low Temperature Polycrystalline Oxide, LTPO) transistors, or low temperature poly silicon (Low Temperature Poly-silicon, LTPS) transistors, and the first and second capacitors are metal-oxide-semiconductor capacitors, metal-insulator-metal capacitors, or metal-oxide-metal capacitors.
According to a second aspect of the present invention, there is provided a display panel comprising: a plurality of pixel circuits as described above, the plurality of pixel circuits being arranged in an array.
Optionally, the plurality of pixel circuits form a pixel array, the control ends of the first switching tubes in the pixel circuits in the same row in the pixel array share a dimming control signal, and the first current ends of the first switching tubes in the pixel circuits in the whole pixel array share a power supply voltage; the first current end of the second switching tube in the pixel circuit of the same column in the pixel array shares a data line to receive data voltage, and the control end of the second switching tube in the pixel circuit of the same row in the pixel array shares a scanning line; the control ends of the third switching tubes in the pixel circuits in the same row in the pixel array share a discharge control signal, and the first current ends of the third switching tubes in the pixel circuits in the whole pixel array share a discharge voltage; the control ends of the fourth switching tubes in the pixel circuits in the same row in the pixel array share an initialization control signal, and the first current ends of the fourth switching tubes in the pixel circuits in the whole pixel array share an initialization voltage.
According to a third aspect of the present invention, there is provided a driving method of a pixel circuit, comprising:
in a data writing stage, coupling the voltage on a data line into a first capacitor connected in series with a second capacitor through the second capacitor, so that the first capacitor stores the data voltage;
in the light emitting stage, a driving signal is generated based on the data voltage to drive the light emitting element,
in the data writing stage, the voltage on the data line is converted from an initial data voltage to a final data voltage in an alternating mode and is sent to the first capacitor through the second capacitor, so that the first capacitor stores the data voltage.
Optionally, the data voltage stored by the first capacitor is a divided voltage of an effective data voltage across the first capacitor, the effective data voltage is a difference voltage between the initial data voltage and the final data voltage,
the data voltage and the effective data voltage have a predetermined ratio, the predetermined ratio being a ratio between a capacitance value of the first capacitance and a total capacitance value of the first capacitance and the second capacitance,
the light emitting element does not emit light when the effective data voltage is 0, and the luminance of the light emitting element is at least related to the voltage magnitude of the voltage division of the effective data voltage on the first capacitor when the effective data voltage is not 0.
Optionally, the method further comprises: in an initialization phase, a threshold voltage of the drive tube is stored on the first capacitor.
According to the pixel circuit, the display panel and the driving method, the voltage provided by the data line is converted from the initial data voltage to the termination data voltage in an alternating mode, so that the first capacitor can be coupled into the first capacitor smoothly through the second capacitor, the first capacitor stores the data voltage (namely, the partial pressure of the effective data voltage on the first capacitor), the data voltage has high precision through the partial pressure of the second capacitor, the range of gamma voltage can be expanded, the adverse effect of transistor leakage on brightness and contrast is reduced, and the display panel has a better display effect.
Further, the data voltage stored in the first capacitor in the pixel circuit is a voltage division of a difference voltage (i.e., an effective data voltage) between the initial data voltage and the final data voltage on the first capacitor, when the difference voltage is 0, the light emitting element does not emit light, and when the difference voltage is not 0, the brightness of the light emitting element is at least related to a voltage amplitude of the voltage division of the difference voltage on the first capacitor, so that the regulation of the data voltage can be easily realized.
Further, the pixel circuit stores the threshold voltage of the driving tube by using the first capacitor in the initialization stage, so that the problems of uneven display caused by threshold voltage drift of the driving tube and transistor process deviation are avoided, and the display uniformity of the display panel is improved; in addition, in the data writing stage, the voltage on the data line is an alternating current signal and can be stored to the first capacitor through the second capacitor, the voltage on the data line is not directly connected to the grid electrode of the driving tube, the influence on the threshold voltage of the driving tube is reduced, and the display uniformity of the display panel is further guaranteed.
Further, the pixel circuit comprises a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a first capacitor, a second capacitor, a light-emitting element and a driving tube, has high circuit integration level and high compatibility, and can be well applied to various displays, such as a silicon-based micro OLED display with high ppi (Pixels per inch), which has extremely high requirement on the circuit integration level.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a schematic circuit configuration of a pixel circuit according to an embodiment of the present invention;
FIG. 2 shows a schematic diagram of a display panel according to an embodiment of the invention;
FIG. 3 illustrates a timing diagram of the operation of a pixel circuit according to an embodiment of the invention;
FIGS. 4a-4c show equivalent circuit diagrams of a pixel circuit at various stages, respectively, according to an embodiment of the invention;
fig. 5 shows a flow chart of a pixel circuit driving method according to an embodiment of the invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings.
Numerous specific details of the invention, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
It should be understood that a and B in the embodiments of the present application are connected/coupled, which means that a and B may be connected in series or parallel, or that a and B pass through other devices, which embodiments of the present application do not limit.
The display panel generally includes a plurality of pixel circuit structures, and the pixel circuit includes a light emitting element, a driving tube, a first switching tube, and a first capacitor. The control end of the first switching tube is connected with the scanning line and receives the scanning signal, the first current end of the first switching tube is connected with the data line and receives the data voltage, and the second current end of the first switching tube is connected with the control end of the driving tube. The first current end of the driving tube is connected with the power line and receives the power voltage, and the second current end of the driving tube is connected with the anode of the light-emitting element. The cathode of the light emitting element is connected to the common voltage line and receives the common voltage. One end of the first capacitor is connected with the second current end of the first switch tube, and the other end of the first capacitor is connected with the second current end of the driving tube. The light emitting element 110 is driven to operate in a data writing stage and a light emitting stage. In the data writing stage, the first switch tube is conducted, and the data voltage is written into the light-emitting element and stored in the first capacitor. In the light-emitting stage, the first switching tube is switched off, the driving tube is switched on, and the light-emitting element is controlled to emit light, so that picture display is realized.
However, the gamma voltage of the display panel has low accuracy, which affects the display quality; further, the difference of the threshold voltages of the driving tubes between the different pixel circuits in the display panel or the drift of the threshold voltages of the driving tubes between the pixel circuits with time can cause the difference of the currents of the light emitting elements of the respective pixel circuits, thereby resulting in poor uniformity of the display brightness and poor picture quality of the display panel.
Therefore, the application provides a pixel circuit, a display panel and a driving method thereof to solve the technical problems.
Fig. 1 shows a schematic circuit configuration of a pixel circuit according to an embodiment of the present invention.
As shown in fig. 1, the pixel circuit 100 includes a light emitting element 110, a driving transistor DRV, a first switching transistor M1, a second switching transistor M2, a first capacitor C1, a second capacitor C2, and optionally, a third switching transistor M3 and/or a fourth switching transistor M4.
The light emitting element 110 is, for example, an Organic Light Emitting Diode (OLED) or a light emitting diode (light emitting diode, LED), and its light emitting brightness is at least related to the intensity of the driving signal. For example, the luminance of the light emitting element 110 is related to the magnitude of the driving current or the driving voltage.
The first current end of the first switching tube M1 is connected to the power line AVDD to receive the power voltage, the second current end is connected to the anode of the light emitting element 110, and the control end of the first switching tube M1 is connected to the dimming control signal line EMB to receive the dimming control signal. Therefore, the on/off of the first switching tube M1 is controlled by the dimming control signal, for controlling the light emitting time of the light emitting element 110, so as to implement pulse width modulation (Pulse Width Modulation, PWM) dimming of the light emitting element. Specifically, the first switching transistor M1 is connected between the power supply voltage and the driving transistor DRV, for example, or the first switching transistor M1 is connected between the driving transistor DRV and the light emitting element 110, for example.
The control end of the second switch tube M2 is connected to the scan line SCANB to receive the scan signal, the first current end is connected to the DATA line DATA to receive the voltage on the DATA line DATA, and the voltage on the DATA line DATA is converted from the initial DATA voltage (denoted as DATA 0) to the termination DATA voltage (denoted as VDATA) in an alternating current manner during the period that the scan signal is in an active state, wherein the difference voltage between the initial DATA voltage DATA0 and the termination DATA voltage VDATA is the effective DATA voltage which can be written into the first capacitor C1. Therefore, the on and off of the first switch M1 is controlled by the scan signal, and is used to control the writing of the effective data voltage when being on.
The second capacitor C2 and the first capacitor C1 are sequentially connected in series between the DATA line DATA and the control end of the driving tube DRV, and are used for dividing the effective DATA voltage when the second switching tube M2 is turned on, so as to obtain the DATA voltage, and the DATA voltage is stored in the first capacitor C1.
In the embodiment of the present invention, the voltage provided by the DATA line DATA is converted from the initial DATA voltage DATA0 to the termination DATA voltage VDATA in an alternating manner, so that the effective DATA voltage can smoothly pass through the second capacitor C2, and the divided voltage of the effective DATA voltage is stored in the first capacitor C1.
Specifically, the data voltage stored in the first capacitor C1 is a partial voltage of a difference voltage (i.e., an effective data voltage) between the initial data voltage and the final data voltage across the first capacitor C1, the data voltage and the effective data voltage having a predetermined ratio, which is a ratio between a capacitance value of the first capacitor and a total capacitance value of the first capacitor and the second capacitor. When the effective data voltage is not 0, the brightness of the light emitting element is at least related to the voltage amplitude of the partial voltage of the effective data voltage on the first capacitor C1.
The series node between the first capacitor C1 and the second capacitor C2 is connected to the first current terminal of the driving transistor DRV, so that the first capacitor C1 stores the threshold voltage of the driving transistor DRV in the initialization phase.
The driving tube DRV is connected between the power voltage and the light emitting element 110, and a control terminal of the driving tube DRV is connected to the first capacitor C1 to receive the data voltage stored in the first capacitor C1. The driving tube DRV is used for being turned on and off based on the data voltage in the light emitting stage to provide a driving signal to the anode of the light emitting element 110, so that the light emitting element 110 emits light, and the pixel circuit 100 supports the analog gamma curve adjustment brightness and the pulse width adjustment brightness.
In some alternative embodiments, the pixel circuit 100 further includes a third switching tube M3 and/or a fourth switching tube M4.
The third switching transistor M3 has a first current terminal connected to the anode of the light emitting element 110, a second current terminal connected to the first reference voltage line VREF1 to receive the first reference voltage, and a control terminal connected to the first control signal line VCTRL1 to receive a first control signal for turning on and off based on the first control signal to periodically reset the voltage of the anode of the light emitting element 110. The third switch tube M3 can increase dynamic contrast ratio, and prevent smear caused by that charges on the anode can not be discharged quickly when the pixel emits light and changes from bright state to dark state. Meanwhile, the anode voltage of the light-emitting element is periodically reset, so that the service life of the device of the light-emitting element 110 can be prolonged, and the phenomenon of image sticking can be reduced.
The first current end of the fourth switching tube M4 is connected to the second reference voltage line VREF2 to receive the second reference voltage, the second current end is connected to the control end of the driving tube DRV, and the control end of the fourth switching tube M4 is connected to the second control signal line VCTRL2 to receive and receive the second control signal for turning on and off based on the second control signal, thereby periodically initializing the driving tube DRV.
Specifically, the control end of the first switching tube M1 is connected to the dimming control signal line EMB for receiving the dimming control signal, and the first current end of the first switching tube M1 is connected to the power line and receives the power voltage.
The control end of the second switching tube M2 is connected with the scanning line SCAMB and receives the scanning signal, the first current end of the second switching tube M2 is connected with the DATA line DATA and receives the voltage on the DATA line DATA, and the second current end of the second switching tube M2 is connected with the first end of the second capacitor C2.
The first current end of the driving tube DRV is connected to the power line AVDD via the first switching tube M1 and receives the power voltage, and the second current end of the driving tube DRV is connected to the anode of the light emitting element 110. The cathode of the light emitting diode 110 is connected to the common voltage line VCOM and receives the common voltage.
The first capacitor C1 is connected between the first current end of the driving tube DRV and the control end of the driving tube DRV.
The second capacitor C2 is connected between the first current terminal of the driving transistor DRV and the DATA line DATA.
The control terminal of the third switching tube M3 receives the first control signal, the first current terminal of the third switching tube M3 is connected to the first reference voltage line VREF1 to receive the first reference voltage, and the second current terminal of the third switching tube M3 is connected to the anode of the light emitting element 110.
The control end of the fourth switching tube M4 receives the second control signal, the first current end of the fourth switching tube M4 is connected to the second reference voltage line VREF2 to receive the second reference voltage, and the second current end of the fourth switching tube M4 is connected to the control end of the driving tube DRV.
It should be noted that the voltage difference between the first reference voltage and the common voltage is smaller than the turn-on voltage of the light emitting element 110. The second reference voltage is smaller than the difference between the power supply voltage and the absolute value VTHP of the target threshold voltage of the driving transistor DRV. In this embodiment, the second reference voltage is, for example, 3V. One scanning signal is shared by the pixel circuits located in the same row, one first control signal is shared by the pixel circuits located in the same row, one second control signal is shared by the pixel circuits located in the same row, and one dimming control signal is shared by the pixel circuits located in the same row. One DATA line DATA is shared by the pixel circuits located in the same column. In some alternative embodiments, the first reference voltage, the second reference voltage, the power supply voltage, and the common voltage are common to all pixel circuits of the display area in the entire display panel.
The first capacitor C1 and the second capacitor C2 may be MOS (metal-oxide-semiconductor) capacitors or MIM (metal-insulator-metal) capacitors or MOM (metal-oxide-metal) capacitors as storage capacitors. In the preferred embodiment, the first capacitor C1 and the second capacitor C2 are MIM metal capacitors, which may be stacked capacitors integrated on the MOS transistor, so that the area of the pixel circuit is not occupied, the overall area of the display panel is reduced, miniaturization of the display panel is better realized, and uniformity of capacitance ratios is better.
The driving tube DRV, the second switching tube M2, the first switching tube M1, the fourth switching tube M4, and the third switching tube M3 have their own source and drain electrodes symmetrical, so that the source and drain electrodes may be interchanged. Further, the control terminal of the transistor is a gate, and the first current terminal and the second current terminal are respectively a source and a drain, or are respectively a drain and a source. In the present embodiment, the driving tube DRV, the second switching tube M2, the first switching tube M1, the fourth switching tube M4, and the third switching tube M3 are PMOS (Positive-Channel Metal Oxide Semiconductor, P-channel metal oxide semiconductor) tubes. However, under the condition of process support, the control signal can be changed to an NMOS (Negative-Channel Metal Oxide Semiconductor, N-channel metal oxide semiconductor) tube or a combination of a PMOS tube and an NMOS tube, so long as the PMOS tube and the NMOS tube can be switched on and off at different stages.
Fig. 2 shows a schematic diagram of a display panel according to an embodiment of the invention. The wiring of the display panel 200 of the embodiment of the present application is exemplarily described below based on fig. 2.
As shown in fig. 2, the display panel 200 of this embodiment includes a plurality of DATA lines DATA, a plurality of dimming control signal lines EMB, a plurality of scan lines SCANB, a plurality of first control signal lines VCTRL1, a plurality of second control signal lines VCTRL2, a plurality of power supply lines AVDD, a plurality of first reference voltage lines VREF1, a plurality of second reference voltage lines VREF2, a plurality of common voltage lines VCOM, and a plurality of pixel circuits 100. The plurality of pixel circuits 100 are arranged in an array to form a pixel array.
In this embodiment, the switch S1 is connected to the front end of the power supply line AVDD common to each row of the pixel circuits 100, the switch S2 is connected to the front end of the plurality of first reference voltage lines VREF1 common to each row of the pixel circuits 100, and the switch S3 is connected to the front end of the second reference voltage line VREF2 common to each row of the pixel circuits 100. Switches with the same reference number are controlled by synchronized switching signals. In alternative embodiments, switch S1, switch S2, and switch S3 may be omitted.
Specifically, in each row of pixel circuits 100, the control end of the first switching tube M1 in each pixel circuit 100 shares one dimming control signal line EMB; the control end of the second switching tube M2 of each pixel circuit 100 shares a scan line SCANB; the control end of the third switching tube M3 in each pixel circuit 100 shares a first control signal line VCTRL1; the control terminal of the fourth switching tube M4 in each pixel circuit 100 shares a second control signal line VCTRL2.
In the whole display panel 200, the first current terminal of the first switching tube M1 in each pixel circuit 100 shares one power line AVDD; the first current end of the fourth switching tube M4 in each pixel circuit 100 shares a second reference voltage line VREF2; the first current terminal of the third switching transistor M3 in each pixel circuit 100 shares a first reference voltage line VREF1; the cathodes of the light emitting elements 110 in the respective pixel circuits 100 share one common voltage line VCOM.
In each column of pixel circuits 100, a plurality of pixel circuits 100 are commonly connected to the DATA line DATA to receive a corresponding DATA voltage.
It should be noted that, the first control signal can periodically reset the anode voltage of the light emitting element 110, so as to increase the dynamic contrast, and prevent the smear caused by the fact that the charges on the anode cannot be discharged quickly when the pixel emits light from the bright state to the dark state. Meanwhile, the anode voltage of the light-emitting element 110 is periodically reset, so that the service life of the device 110 can be prolonged, and the phenomenon of image sticking can be reduced. And by controlling the on time of the first switching tube M1 and/or the off time of the third switching tube M3, the light emitting time of the light emitting element 110 can be further controlled to adjust the brightness of the display device without changing the gamma curve.
FIG. 3 illustrates a timing diagram of the operation of a pixel circuit according to an embodiment of the invention; fig. 4a-4c show equivalent circuit diagrams of a pixel circuit at various stages, respectively, according to an embodiment of the invention. The operation flow of the pixel circuit according to the embodiment of the invention is described in detail with reference to fig. 3 to 4 c.
In the initialization stage T1, the first control signal is in an active level state, the second control signal is in an active level state, the dimming control signal is in an inactive level state, and the scanning signal is in an inactive level state. And then the first switching tube M1 is controlled to be disconnected, the second switching tube M2 is disconnected, the third switching tube M3 is conducted, and the fourth switching tube M4 is conducted. An equivalent circuit diagram of the pixel circuit in the initialization stage is shown in fig. 4 a.
In the initialization phase T1, the anode of the switching element 110 is written with a first reference voltage, thereby completing the initialization of the switching element 110; and writing a second reference voltage into the control end of the driving tube DRV, thereby finishing the initialization of the driving tube DRV.
The control end of the driving tube DRV is written with a second reference voltage, the first current end of the driving tube DRV is disconnected with the power supply voltage due to the disconnection of the first switching tube M1, and then the voltage on the first current end of the driving tube DRV is reduced and approaches to the sum value of the second reference voltage and the threshold voltage VTH1 of the driving tube DRV due to the electric leakage of the driving tube DRV. Therefore, the threshold voltage VTH1 of the driving transistor DRV is stored in the first capacitor C1 in the initialization stage. Since the first current end of the driving tube DRV is lowered for a long time, the process is completed before the data writing stage. Threshold voltage VTH 1= (1+m) ×vthp, m=lamda (AVDD-Vavddb), vavddb=vref 2+vth1, where m is an influence coefficient of the lining bias effect, VTH1 is an actual threshold voltage value of the driving transistor DRV, VTHP is a target threshold voltage value of the driving transistor DRV, AVDD is a power supply voltage value, and Vavddb is a voltage value on the first current terminal of the driving transistor DRV.
In the data writing stage T2, the first control signal is in an active level state, the second control signal is in an active level state, the dimming control signal is in an inactive level state, and the scanning signal is changed into an active level state. And then the first switching tube M1 is controlled to be disconnected, the second switching tube M2 is conducted, the third switching tube M3 is conducted, and the fourth switching tube M4 is disconnected. An equivalent circuit diagram of the pixel circuit in the data writing stage is shown in fig. 4 b.
In the DATA writing period T2, the voltage on the DATA line DATA is ac-converted from the initial DATA voltage DATA0 to the termination DATA voltage VDATA, and thus, the difference voltage between the initial DATA voltage DATA0 and the termination DATA voltage VDATA, i.e., the effective DATA voltage, can be written into the first capacitor C1 through the second capacitor C2. Therefore, the voltage of the first capacitor C1 also includes the partial voltage of the effective DATA voltage across the first capacitor C1 and the second capacitor C2, in which stage vavdb=vref 2+vth1+α (DATA 0-VDATA) =vref 2+vth1+α (DATA 0-VDATA), where α=c1/(c1+c2). DATA0 is the voltage value of the initial DATA voltage, and VDATA is the voltage value of the termination DATA voltage.
In the light emitting period T3, the first control signal is changed to an inactive level state, the second control signal is changed to an inactive level state, the dimming control signal is changed to a pulse width modulation state, and the scanning signal is changed to an inactive level state. And then the first switching tube M1 is turned on or off under the control of the dimming control signal, the second switching tube M2 is turned off, the third switching tube M3 is turned off, and the fourth switching tube M4 is turned off. An equivalent circuit diagram of the pixel circuit in the light emitting stage is shown in fig. 4 c. Alternatively, in the light emitting period T3, the first control signal may be a signal complementary to the dimming control signal so as to reset the light emitting element 110.
The driving tube DRV supplies a driving signal based on the data voltage and the power supply voltage supplied from the first capacitor C1 to make the light emitting element 110 emit light. In the lighting phase, the first current terminal of the driving tube DRV is written with the power supply voltage, i.e., vavddb=avdd. Thus, the voltage value vgate=vref 2+β (AVDD-VREF 2-VTH1- α (DATA 0-VDATA)) on the control terminal of the driving transistor DRV. Wherein β=c1/(c1+cp), C1 is the capacitance value of the first capacitor, and Cp is the parasitic capacitance value to ground of the control end of the driving transistor DRV.
In some embodiments, when C1> Cp is set, then β≡1, then Vgate=VREF 2+ (AVDD-VREF 2-VTH1- α (DATA 0-VDATA)). In this embodiment, when the load is a large current, the drive tube operates in the saturation region, and the load current I satisfies: i=k (Vgs-VTHP)/(2=k (AVDD-Vgate-VTHP)/(2=k (mvthp+α (DATA 0-VDATA))/(2), vgs is the voltage difference between the first current terminal and the control terminal of the driving tube DRV, the load current I is independent of AVDD, the correlation with the target threshold value VTHP of the driving tube DRV is greatly reduced, and the range of gamma voltages is expanded. Wherein, C1/C2 can be 1:1, or 1:2, or 2:1 or other ratio. When the load currents I of the same magnitude are supplied, the range of the data voltages of the pixel circuit 100 provided in the present application is larger, and thus the range of the gamma voltages can be expanded. According to the formula α=c1/(c1+c2), the larger α is, the smaller the load current I is affected by the data voltage, and thus the larger the expansion range of the gamma voltage is. And better dimming effect can be obtained, and the quality of picture display is improved. Where K is a coefficient related to the size of the driving tube DRV and the semiconductor process.
Fig. 5 shows a flow chart of a pixel circuit driving method according to an embodiment of the invention.
As shown in fig. 5, the driving method of the pixel circuit includes the steps of:
step S10: in an initialization phase, a threshold voltage of the drive tube is stored on the first capacitor. In this step, the first control signal is in an active level state, the second control signal is in an active level state, the dimming control signal is in an inactive level state, and the scanning signal is in an inactive level state. And then the first switching tube M1 is controlled to be disconnected, the second switching tube M2 is disconnected, the third switching tube M3 is conducted, and the fourth switching tube M4 is conducted. The drive tube DRV is disconnected. The second reference voltage is written at the first current end of the driving tube DRV through the control of the third switching tube, and after the voltage value at the first current end of the driving tube DRV is reduced, the threshold voltage of the driving tube DRV is stored in the first capacitor C1.
Step S20: in the data writing stage, the voltage on the data line is coupled into the first capacitor connected in series with the second capacitor through the second capacitor, so that the first capacitor stores the data voltage. The voltage on the data line is converted from the initial data voltage to the final data voltage in an alternating manner, so that the voltage can smoothly pass through the second capacitor C2 and be stored in the first capacitor C1. Specifically, the data voltage stored in the first capacitor C1 is a partial voltage of a difference voltage (i.e., an effective data voltage) between the initial data voltage and the final data voltage across the first capacitor, the data voltage and the effective data voltage having a predetermined ratio, which is a ratio between a capacitance value of the first capacitor and a total capacitance value of the first capacitor and the second capacitor. When the effective data voltage is not 0, the brightness of the light emitting element is at least related to the voltage amplitude of the partial voltage of the effective data voltage on the first capacitor C1.
In this step, the second control signal is in an active level state, the first control signal is in an active level state, the dimming control signal is in an inactive level state, and the scanning signal is changed to an active level state. And then the second switching tube M2 is controlled to be conducted, the first switching tube M1 is disconnected, the fourth switching tube M4 is disconnected, the third switching tube M3 is conducted, and the driving tube DRV is disconnected. The effective data voltage is written into the first capacitor C1 after a certain decay ratio, that is, the first capacitor C1 stores the data voltage.
Step S30: in the light emitting stage, a driving signal is generated based on the data voltage by using the driving tube to drive the light emitting element. In this step, the first control signal is changed to an inactive level state, the second control signal is changed to an inactive level state, the dimming control signal is changed to a pulse width modulation state, and the scanning signal is changed to an inactive level state. And then the first switching tube M1 is controlled to be turned on or off under the control of the dimming control signal, the second switching tube M2 is turned off, the third switching tube M3 is turned off, the fourth switching tube M4 is turned off, and the driving tube DRV is turned on or turned off based on the data voltage. The first switching tube M1 and/or the third switching tube M3 are/is turned on or off, so that the light-emitting time can be controlled, and the dimming function is realized.
Alternatively, in the light emitting stage, the first control signal may be a signal complementary to the dimming control signal so as to turn on the third switching tube M3 and thereby reset the light emitting element 110.
Optionally, resetting the voltage of the anode of the light emitting element at least in the initialization phase and the writing phase is further included. That is, in the present embodiment, the third switching transistor M3 is turned on in the initializing stage and the writing stage, and further discharges the anode of the light emitting element 110.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims (10)

1. A pixel circuit, comprising:
the driving tube is characterized in that a control end of the driving tube receives data voltage, a first current end of the driving tube is connected to power supply voltage, and a second current end of the driving tube provides driving signals;
the first capacitor is connected between the control end and the first current end of the driving tube and is at least used for storing the data voltage;
the second capacitor is connected between the data line and the first current end of the driving tube and is used for coupling the data voltage; and
a light emitting element connected to the second current end of the driving tube for emitting light according to the driving signal,
in the data writing stage, the voltage on the data line is converted from the initial data voltage to the final data voltage in an alternating mode and is sent to the first capacitor through the second capacitor, so that the first capacitor stores the data voltage.
2. The pixel circuit of claim 1, wherein the data voltage stored by the first capacitor is a divided voltage of an effective data voltage across the first capacitor, the effective data voltage being a difference voltage between the initial data voltage and the terminal data voltage,
the data voltage and the effective data voltage have a predetermined ratio, which is a ratio between a capacitance value of the first capacitor and a total capacitance value of the first capacitor and the second capacitor.
3. The pixel circuit according to claim 2, wherein the light emitting element does not emit light when the effective data voltage is 0, and wherein the luminance of the light emitting element is related to at least a voltage magnitude of a voltage division of the effective data voltage across the first capacitor when the effective data voltage is not 0.
4. The pixel circuit of claim 1, wherein the first capacitor is further configured to store a threshold voltage of the drive tube during the data write phase.
5. The pixel circuit of claim 1, further comprising:
a first switching tube connected between the light emitting element and the power supply voltage; and/or
The second switch tube is connected between the data line and the second capacitor; and/or
A third switching tube connected between the anode of the light emitting element and a first reference voltage; and/or
And the fourth switching tube is connected between the control end of the driving tube and the second reference voltage.
6. The pixel circuit of claim 5, wherein,
in an initialization stage, the third switching tube is conducted to reset the light emitting element, and the fourth switching tube is conducted to store a threshold voltage of the driving tube on the first capacitor;
in a data writing stage, the second switch tube is conducted so that the voltage on the data line is coupled in through the second capacitor, and the first capacitor stores the data voltage;
in the light emitting stage, the first switching tube is continuously or intermittently conducted to provide a driving signal to the light emitting element.
7. The pixel circuit of claim 6, wherein the on and off of the first switching tube is controlled by a dimming signal, which is a pulse width modulation signal during the light emitting phase to control the light emitting brightness of the light emitting element.
8. A display panel, comprising: a plurality of pixel circuits according to any one of claims 1 to 7, the plurality of pixel circuits being arranged in an array.
9. A driving method of a pixel circuit, comprising:
in a data writing stage, coupling the voltage on a data line into a first capacitor connected in series with a second capacitor through the second capacitor, so that the first capacitor stores the data voltage;
in the light emitting stage, a driving signal is generated based on the data voltage to drive the light emitting element,
in the data writing stage, the voltage on the data line is converted from an initial data voltage to a final data voltage in an alternating mode and is sent to the first capacitor through the second capacitor, so that the first capacitor stores the data voltage.
10. The driving method of claim 9, wherein the data voltage stored by the first capacitor is a divided voltage of an effective data voltage across the first capacitor, the effective data voltage being a difference voltage between the initial data voltage and the terminal data voltage,
the data voltage and the effective data voltage have a predetermined ratio, the predetermined ratio being a ratio between a capacitance value of the first capacitance and a total capacitance value of the first capacitance and the second capacitance,
the light emitting element does not emit light when the effective data voltage is 0, and the luminance of the light emitting element is at least related to the voltage magnitude of the voltage division of the effective data voltage on the first capacitor when the effective data voltage is not 0.
CN202311080012.5A 2023-08-24 2023-08-24 Pixel circuit, display panel and driving method thereof Pending CN117275392A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311080012.5A CN117275392A (en) 2023-08-24 2023-08-24 Pixel circuit, display panel and driving method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311080012.5A CN117275392A (en) 2023-08-24 2023-08-24 Pixel circuit, display panel and driving method thereof

Publications (1)

Publication Number Publication Date
CN117275392A true CN117275392A (en) 2023-12-22

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