CN117238248A

CN117238248A - Pixel circuit, display panel and display device

Info

Publication number: CN117238248A
Application number: CN202311282953.7A
Authority: CN
Inventors: 陈彩凤
Original assignee: Hubei Changjiang New Display Industry Innovation Center Co Ltd
Current assignee: Hubei Changjiang New Display Industry Innovation Center Co Ltd
Priority date: 2023-09-28
Filing date: 2023-09-28
Publication date: 2023-12-15

Abstract

The invention discloses a pixel circuit, a display panel and a display device, wherein the pixel circuit comprises: the device comprises a driving transistor, a threshold compensation module and a node control module; the first electrode of the first transistor is electrically connected with the gate of the driving transistor, the first electrode of the second transistor is electrically connected with the second electrode of the driving transistor, and the second electrode of the first transistor and the second electrode of the second transistor are electrically connected with a first node; the first end of the node control module is electrically connected with the first signal end, and the second end of the node control module is electrically connected with the first node; the first signal provided by the first signal terminal comprises a high level signal and a low level signal; in the light emitting stage, the first signal jumps from a high level signal to a low level signal, so that the node control module controls the potential of the first node according to the first signal. According to the technical scheme, the stability of the grid electrode potential of the driving transistor is improved.

Description

Pixel circuit, display panel and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a pixel circuit, a display panel, and a display device.

Background

Along with the continuous improvement of display technologies of display panels, display quality requirements of people on the display panels are also increasing. At present, the light-emitting element in the display panel has the problems of unstable light emission, flickering and the like, so that the display effect of the display panel is greatly reduced.

Disclosure of Invention

The invention provides a pixel circuit, a display panel and a display device, which are used for improving the stability of the grid potential of a driving transistor, avoiding the flickering problem of a light-emitting element and improving the light-emitting stability of the light-emitting element.

In a first aspect, an embodiment of the present invention provides a pixel circuit, including: the device comprises a driving transistor, a threshold compensation module and a node control module;

the first pole of the driving transistor is electrically connected with a first power supply end, and the driving transistor is used for providing driving current for the light-emitting element according to the data signal written by the grid electrode of the driving transistor and the first power supply signal provided by the first power supply end;

the threshold compensation module comprises a first transistor and a second transistor, wherein the grid electrodes of the first transistor and the second transistor are electrically connected with a first scanning signal end, the first electrode of the first transistor is electrically connected with the grid electrode of the driving transistor, the first electrode of the second transistor is electrically connected with the second electrode of the driving transistor, and the second electrode of the first transistor and the second electrode of the second transistor are electrically connected with a first node;

the first end of the node control module is electrically connected with the first signal end, and the second end of the node control module is electrically connected with the first node;

the first signal provided by the first signal terminal comprises a high-level signal and a low-level signal;

in the light emitting stage, the first signal jumps from the high level signal to the low level signal, so that the node control module controls the potential of the first node according to the first signal.

In a second aspect, an embodiment of the present invention provides a display panel, including a pixel circuit as described in the first aspect.

In a third aspect, an embodiment of the present invention provides a display device including the display panel according to the second aspect.

According to the scheme provided by the invention, the threshold compensation module in the pixel circuit comprises a first transistor and a second transistor, wherein the grid electrodes of the first transistor and the second transistor are electrically connected with a first scanning signal end, the first electrode of the first transistor is electrically connected with the grid electrode of the driving transistor, the first electrode of the second transistor is electrically connected with the second electrode of the driving transistor, and the second electrode of the first transistor and the second electrode of the second transistor are electrically connected with a first node; the first end of the node control module is electrically connected with the first signal end, and the second end of the node control module is electrically connected with the first node; the first signal provided by the first signal terminal comprises a high level signal and a low level signal; in the light-emitting stage, the first signal is changed from a high-level signal to a low-level signal in a jumping manner, so that the node control module controls the potential of the first node according to the first signal, when the potential of the first node is higher than the potential of the grid electrode of the driving transistor to cause the first node to leak electricity to the grid electrode of the driving transistor, in the light-emitting stage, the potential of the first node can be controlled to be reduced by adjusting the first signal from the high-level signal to the low-level signal through the node control module, the potential difference between the first node and the grid electrode of the driving transistor is reduced, the problem of electricity leakage of the grid electrode of the driving transistor is favorably improved, the grid electrode potential of the driving transistor is stabilized, the light-emitting stability of the light-emitting element is ensured, and the problem of flicker is favorably avoided.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, a brief description will be given below of the drawings required for the embodiments or the description of the prior art, and it is obvious that although the drawings in the following description are specific embodiments of the present invention, it is obvious to those skilled in the art that the basic concepts of the device structure, the driving method and the manufacturing method, which are disclosed and suggested according to the various embodiments of the present invention, are extended and extended to other structures and drawings, and it is needless to say that these should be within the scope of the claims of the present invention.

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a pixel circuit according to another embodiment of the present invention;

FIG. 5 is a timing diagram of the driving of FIG. 4;

fig. 6 is a schematic structural diagram of a pixel circuit according to another embodiment of the present invention;

FIG. 7 is a timing diagram of the driving of FIG. 6;

fig. 8 is a schematic structural diagram of a pixel circuit according to another embodiment of the present invention;

FIG. 9 is a timing diagram of the driving of FIG. 8;

fig. 10 is a schematic structural diagram of a pixel circuit according to another embodiment of the present invention;

FIG. 11 is a timing diagram of the driving of FIG. 10;

fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described by means of implementation examples with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments obtained by those skilled in the art based on the basic concepts disclosed and suggested by the embodiments of the present invention are within the scope of the present invention.

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, and as shown in fig. 1, a pixel circuit 10 includes: a driving transistor DT, a threshold compensation module 11, and a node control module 12; a first pole of the driving transistor DT is electrically connected to the first power source terminal PVDD, and the driving transistor DT is configured to supply a driving current to the light emitting element 20 according to a data signal written in a gate thereof and a first power source signal PVDD provided by the first power source terminal PVDD; the threshold compensation module 11 includes a first transistor T1 and a second transistor T2, wherein gates of the first transistor T1 and the second transistor T2 are electrically connected to the first scan signal terminal S1, a first pole of the first transistor T1 is electrically connected to a gate of the driving transistor DT, a first pole of the second transistor T2 is electrically connected to a second pole of the driving transistor DT, and a second pole of the first transistor T1 and a second pole of the second transistor T2 are electrically connected to the first node N1; the first end of the node control module 12 is electrically connected with the first signal end X1, and the second end of the node control module 12 is electrically connected with the first node N1; the first signal X1 provided by the first signal terminal X1 includes a high level signal and a low level signal; in the light emitting stage, the first signal x1 transitions from a high level signal to a low level signal, so that the node control module 12 controls the potential of the first node N1 according to the first signal x1.

The light emitting element 20 may include a sub-Micro light emitting diode (Mini-LED), a Micro light emitting diode (Micro-LED), an Organic Light Emitting Diode (OLED), and the like, which is not particularly limited in the implementation of the present invention, and fig. 1 illustrates the light emitting element 20 as an organic light emitting diode by way of example only.

The first transistor T1 and the second transistor T2 may be P-channel thin film transistors or N-channel thin film transistors, and may be set according to practical situations, which are not particularly limited herein, and fig. 1 exemplarily illustrates that the first transistor T1 and the second transistor T2 are P-channel thin film transistors.

It will be appreciated that due to the operating characteristics of the transistor, the transistor will experience a drain current phenomenon when a potential difference occurs between the source and drain of the transistor, despite the transistor being in an off state. Referring to fig. 1, since the point of the first node N1 is generally greater than the potential of the second node N2, for example, the first scan signal provided by the first scan signal terminal S1 transitions from a low level to a high level, and the first node N1 is raised to be greater than the potential of the second node N2 due to parasitic capacitance of the first transistor T1 and the second transistor T2, and even if the first transistor T1 is in an off state, the first node N1 still leaks to the second node N2. In this way, in the light emitting stage, the first node N1 leaks electricity to the second node N2, so that the potential of the gate electrode of the driving transistor DT is unstable, and the light emitting stability of the light emitting element 20 is further affected, and the flicker problem is generated, especially when the display panel is in a low gray scale state, the effect is very obvious.

Based on this, a first end of the node control module 12 may be electrically connected to the first signal terminal X1, and a second end of the node control module 12 is electrically connected to the first node N1, where the first signal X1 provided by the first signal terminal X1 includes a high level signal and a low level signal, i.e., the first signal X1 is a signal in which the high level signal and the low level signal alternate. In the light emitting stage, since the first transistor T1 and the second transistor T2 are in the off state, the potential of the first node N1 is high and the potential of the second node N2 is high, so that the potential of the first node N1 generates leakage current to the second node N2 through the first transistor T1, at this time, the potential of the first node N1 can be controlled to be reduced by adjusting the first signal x1 to jump from a high level signal to a low level signal through the node control module 12, and the potential difference between the first node N1 and the second node N2 is reduced, thereby being beneficial to improving the problem of leakage current generated by the gate electrode (i.e., the second node N2) of the driving transistor DT, stabilizing the gate electrode potential of the driving transistor DT, ensuring the light emitting stability of the light emitting element, being beneficial to avoiding the problem of flicker, and further being beneficial to improving the display effect of the display panel.

It should be noted that, in addition, the pixel circuit 10 may further include a data writing module (not shown in fig. 1, the specific setting position of the data writing module may be set according to the actual situation), and in the data writing stage, the data writing module may write the data signal to the gate electrode (i.e. the second node N2) of the driving transistor DT, and in the data writing stage, the threshold compensation module 11 is also in an on state for compensating the threshold voltage of the driving transistor DT until the voltage difference between the potential of the second node N2 and the source electrode of the driving transistor DT is equal to the threshold voltage of the driving transistor DT, and the driving transistor DT is turned off. The pixel circuit 10 may further include an initialization module (not shown in fig. 1) for initializing the gate electrode of the driving transistor DT during an initialization phase, a light emission control module (e.g., the first light emission control transistor T3 shown in fig. 1) for controlling the driving transistor DT to supply a driving current to the light emitting element 20, and the like. The specific structure of the pixel circuit 10 may be set according to actual requirements, and is not particularly limited herein.

In this embodiment, by setting that the threshold compensation module in the pixel circuit includes a first transistor and a second transistor, gates of the first transistor and the second transistor are electrically connected to the first scanning signal terminal, a first pole of the first transistor is electrically connected to a gate of the driving transistor, a first pole of the second transistor is electrically connected to a second pole of the driving transistor, and a second pole of the first transistor and a second pole of the second transistor are electrically connected to the first node; the first end of the node control module is electrically connected with the first signal end, and the second end of the node control module is electrically connected with the first node; the first signal provided by the first signal terminal comprises a high level signal and a low level signal; in the light-emitting stage, the first signal is changed from a high-level signal to a low-level signal in a jumping manner, so that the node control module controls the potential of the first node according to the first signal, when the potential of the first node is higher than the potential of the grid electrode of the driving transistor to cause the first node to leak electricity to the grid electrode of the driving transistor, in the light-emitting stage, the potential of the first node can be controlled to be reduced by adjusting the first signal from the high-level signal to the low-level signal through the node control module, the potential difference between the first node and the grid electrode of the driving transistor is reduced, the problem of electricity leakage of the grid electrode of the driving transistor is favorably improved, the grid electrode potential of the driving transistor is stabilized, the light-emitting stability of the light-emitting element is ensured, and the problem of flicker is favorably avoided.

Optionally, fig. 2 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, as shown in fig. 2, the node control module 12 includes a first capacitor C1, a first electrode plate of the first capacitor C1 is a first end of the node control module 12, and a second electrode plate of the first capacitor C1 is a second end of the node control module 12.

Specifically, in the light emitting stage, the first signal x1 jumps from a high level signal to a low level signal, and due to the coupling of the first capacitor C1, the potential of the first node N1 electrically connected to the second electrode of the first capacitor C1 is pulled down by coupling, so that the potential difference between the first node N1 and the second node N2 can be reduced, the first node N1 is prevented from leaking to the second node N2 to affect the stability of the gate potential of the driving transistor DT, the light emitting stability of the light emitting element 20 is ensured, and the display effect of the display panel is further improved.

Optionally, fig. 3 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, as shown in fig. 3, the node control module 12 includes a node control transistor T4, a gate of the node control transistor T4 is electrically connected to the second signal terminal X2, a first terminal of the node control transistor T4 is a first terminal of the node control module 12, and a second terminal of the node control transistor T4 is a second terminal of the node control module 12; the second signal X2 provided by the second signal terminal X2 is a signal for controlling the node to control the transistor T4 to be turned off.

The node control transistor T4 may be a P-type transistor or an N-type transistor, which is not limited in this embodiment of the present invention, and may be set according to actual requirements. When the node control transistor T4 is a P-type transistor, the second signal X2 provided by the second signal terminal X2 is a high level signal, and when the node control transistor T4 is an N-type transistor, the second signal X2 provided by the second signal terminal X2 is a low level signal. It can be appreciated that the N-type transistor has the characteristics of high transmittance, low electron mobility, large switching ratio, low power consumption, small leakage current in the off state, and the like, compared with the P-type transistor, and therefore, the node control transistor T4 can be set as the N-type transistor.

Specifically, since the second signal X2 provided by the second signal terminal X2 is always a signal (for example, a high level signal) for controlling the node control transistor T4 to turn off, the clock of the node control transistor T4 is kept in an off state, so that when the first signal X1 transitions from the high level signal to the low level signal in the light emitting stage, the potential of the first node N1 is coupled and pulled down due to the parasitic capacitance of the node control transistor T4, so that the potential difference between the first node N1 and the second node N2 can be reduced, the electric leakage of the first node N1 to the second node N2 is avoided, the stability of the gate potential of the driving transistor DT is influenced, the light emitting stability of the light emitting element 20 is ensured, and the display effect of the display panel is further improved.

Note that, unless otherwise specified, the following embodiments are each exemplified by the node control transistor T4.

Optionally, with continued reference to fig. 1-3, the pixel circuit 10 further includes a first light emitting control transistor T3; the grid electrode of the first light-emitting control transistor T3 is electrically connected with the light-emitting control signal end Emit, the first electrode of the first light-emitting control transistor T3 is electrically connected with the grid electrode of the driving transistor DT, and the second electrode of the first light-emitting control transistor T3 is electrically connected with the anode of the light-emitting element 20; the first light emitting control transistor T3 includes a P-channel thin film transistor; the emission control signal terminal Emit is multiplexed into the first signal terminal X1.

Specifically, the first light emitting control transistor T3 is configured to be turned on in a light emitting stage, and may supply a driving current generated by the driving transistor DT to the light emitting element 20, so that the light emitting element 20 emits light. When the first light emitting control transistor T3 is a P-channel thin film transistor, the light emitting control signal provided by the light emitting control signal terminal Emit jumps to a low level signal in the light emitting stage to control the first light emitting control transistor T3 to be turned on. Because the first signal X1 provided by the first signal end X1 is a signal in which a high level signal and a low level signal are alternately changed, and the first signal X1 is hopped from the high level signal to the low level signal in the light emitting stage, the light emitting control signal end Emit can be set to be multiplexed into the first signal end X1 so as to reduce the number of signal terminals, further reduce the number of signal lines for transmitting the first signal, and be beneficial to a narrow frame of a display panel.

In an alternative embodiment, fig. 4 is a schematic structural diagram of still another pixel circuit according to an embodiment of the present invention, and as shown in fig. 4, the pixel circuit 10 further includes a first reset transistor T5, a data writing transistor T6, and a storage capacitor Cst; the grid electrode of the first reset transistor T5 is electrically connected with the light-emitting control signal end Emit, the first pole of the first reset transistor T5 is electrically connected with the first reference voltage end Vref1, and the second pole of the first reset transistor T5 is electrically connected with the first polar plate of the storage capacitor Cst; the grid electrode of the Data writing transistor T6 is electrically connected with the second scanning signal end S2, the first electrode of the Data writing transistor T6 is electrically connected with the Data signal end Data, and the second electrode of the Data writing transistor T6 is electrically connected with the first electrode plate of the storage capacitor Cst; the second plate of the storage capacitor Cst is electrically connected to the gate electrode of the driving transistor DT.

The first reset transistor T5 may be a P-channel thin film transistor, and may be turned on or turned off according to a light emission control signal provided by a gate thereof. The data writing transistor T6 may be a P-channel thin film transistor or an N-channel thin film transistor, which is not particularly limited in the embodiment of the present invention, and may be set according to practical situations, and fig. 4 exemplarily shows that the data writing transistor T6 is a P-channel thin film transistor.

Fig. 5 is a driving timing chart of fig. 4, and in combination with fig. 4 and fig. 5, in the initialization stage T1, the first scan signal S1 provided by the first scan signal terminal S1 is a low level signal, which can control the first transistor T1 and the second transistor T2 to be turned on, and meanwhile, the light emission control signal Emit provided by the light emission control signal terminal Emit is a low level signal, which can control the first reset transistor T5 and the first light emission control transistor T3 to be turned on, so that the first reference voltage Vref1 provided by the first reference voltage terminal Vref1 is written into the first plate and the second node N2 of the storage capacitor Cst, and since the first transistor T1 and the second transistor T2 are turned on, the voltage of the second electrode of the driving transistor DT is Vref1. At this stage, since the first reference voltage vref1 is lower than the voltage value of the first power signal PVDD provided by the first power terminal PVDD, the first reference voltage vref1 is considered to be close to the voltage value of the second power signal PVEE provided by the second power terminal PVEE, so that the light-emitting element 20 does not emit light at this stage.

In the Data writing stage T2, the first scan signal S1 provided by the first scan signal terminal S1 is kept as a low level signal, so that the first transistor T1 and the second transistor T2 are continuously turned on, the second scan signal S2 provided by the second scan signal terminal S2 is at a low level, the Data writing transistor T6 is controlled to be turned on, the Data signal Vdata provided by the Data signal terminal Data can be written into the first polar plate of the storage capacitor Cst through the turned-on Data writing transistor T6, and the light emission control signal Emit provided by the light emission control signal terminal Emit is changed from a low level signal to a high level signal, so as to control the first reset transistor T5 and the first light emission control transistor T3 to be turned off. Since the voltage between the first pole and the gate of the driving transistor DT is Pvdd-vref1, which is greater than the threshold voltage Vth of the driving transistor DT, the driving transistor DT is in a conductive state, such that the first power signal Pvdd provided by the first power terminal Pvdd is written into the first node N1 through the conductive driving transistor DT and the second transistor T2, and is written into the second node N2 through the conductive first transistor T1, that is, the potentials of the first node N1 and the second node N2 are Pvdd-Vth, respectively.

In the light emitting stage T3, the first scan signal S1 provided by the first scan signal terminal S1 is changed from a low level signal to a high level signal, the first transistor T1 and the second transistor T2 are controlled to be turned off, the second scan signal S2 provided by the second scan signal terminal S2 is changed from a low level signal to a high level signal, the data writing transistor T6 is controlled to be turned off, the light emitting control signal Emit provided by the light emitting control signal terminal Emit is changed from a high level signal to a low level signal, the first reset transistor T5 and the first light emitting control transistor T3 are controlled to be turned on, the first reference voltage Vref1 provided by the first reference voltage terminal Vref1 is controlled to be written into the first polar plate of the storage capacitor Cst again, the potential of the first polar plate of the storage capacitor Cst is reduced to Vref1 by Vdata, the potential of the second node N2 is also reduced by coupling action of the storage capacitor Cst, the voltage change amount is Vdata-Vref1, the potential of the second node N2 is changed to pdd-Vref- (Vdata-Vref 1), and the voltage v-Vref is further calculated according to the saturation current (vth=vth) of the driving transistor is calculated in the saturation region ² The drive current I can be calculated, where k=0.5×c _ox * Mu is W/L, W is the width of the channel region, L is the length of the channel region, cox is the parasitic capacitance formed by the gate electrode and the active layer of the drive transistor, and mu is the mobility of the active layer of the drive transistor. The voltage signal Pvdd-Vth- (Vdata-vref 1), i.e. Vg=Pvdd-Vth- (Vdata-vref 1) of the gate of the driving transistor DT, and the source voltage signal of the driving transistor DT is Pvdd, so that the driving transistor can be further calculated by using the driving current I calculation formula of the driving transistor DTThe body tube DT generates a drive current i=k (Vdata-vref 1) ² . However, since the potential of the first node N1 is Pvdd-Vth, which is higher than the potential of the second node N2, this will cause the first node N1 to generate leakage current to the second node N2, affecting the stability of the second node N2 (i.e. the gate of the driving transistor DT). Meanwhile, since the emission control signal emit is changed from a high level signal to a low level signal, under the coupling control of the node control module 12 (e.g., the node control transistor T4), the potential of the first node N1 is pulled down to reduce the potential difference between the first node N1 and the second node N2, so as to avoid the influence of the leakage of the first node N1 to the second node N2 on the stability of the gate potential of the driving transistor DT, ensure the emission stability of the light emitting element 20, and further improve the display effect of the display panel.

In another alternative embodiment, fig. 6 is a schematic structural diagram of still another pixel circuit according to an embodiment of the present invention, and as shown in fig. 6, the pixel circuit 10 further includes a second light-emitting control transistor T7, a data writing transistor T6, and a storage capacitor Cst; the grid electrode of the second light-emitting control transistor T7 is electrically connected with the light-emitting control signal end Emit, the first electrode of the second light-emitting control transistor T7 is electrically connected with the first power supply end PVDD, and the second electrode of the second light-emitting control transistor T7 is electrically connected with the first electrode of the driving transistor DT; the grid electrode of the Data writing transistor T6 is electrically connected with the third scanning signal end S3, the first electrode of the Data writing transistor T6 is electrically connected with the Data signal end Data, and the second electrode of the Data writing transistor T6 is electrically connected with the first electrode of the driving transistor DT; the first plate of the storage capacitor Cst is electrically connected to the first power supply terminal PVDD, and the second plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor DT.

The second light-emitting control transistor T7 and the first light-emitting control transistor T3 have the same channel type and are P-channel thin film transistors.

Specifically, unlike the structure of the pixel circuit shown in fig. 4, the second pole of the Data writing transistor T6 in fig. 5 is directly and electrically connected to the first pole of the driving transistor DT, so that in the Data writing stage, the third scanning signal S3 provided by the third scanning signal terminal S3 is a low level signal, the Data writing transistor T6 can be controlled to be turned on, the first scanning signal S1 provided by the first scanning signal terminal S1 is a low level signal, and the first transistor T1 and the second transistor T2 can be controlled to be turned on, so that the Data signal Vdata provided by the Data signal terminal Data can be written to the gate (i.e., the second node N2) of the driving transistor DT through the turned-on Data writing transistor T6, the driving transistor DT, the second transistor T2 and the first transistor T1 in sequence, and stored in the storage capacitor Cst, and the potentials of the first node N1 and the second node N2 are Vdata-Vth. When the light emitting stage is entered, the first scan signal S provided by the first scan signal terminal S1 jumps from a low level signal to a high level signal, and due to parasitic capacitance of the first transistor T1 and the second transistor T2, the potential of the first node N1 is raised under the coupling effect of the parasitic capacitance, so that the potential of the first node N1 is greater than the potential of the second node N2, which will cause the first node N1 to leak current to the second node N2. Meanwhile, since the emission control signal emit is changed from a high level signal to a low level signal, under the coupling control of the node control module 12 (e.g., the node control transistor T4), the potential of the first node N1 is pulled down to reduce the potential difference between the first node N1 and the second node N2, so as to avoid the influence of the leakage of the first node N1 to the second node N2 on the stability of the gate potential of the driving transistor DT, ensure the emission stability of the light emitting element 20, and further improve the display effect of the display panel.

Optionally, with continued reference to fig. 6, the pixel circuit 10 further includes a second reset transistor T8; the gate of the second reset transistor T8 is electrically connected to the fourth scan signal terminal S4, the first pole of the second reset transistor T8 is electrically connected to the second reference voltage terminal Vref2, and the second pole of the second reset transistor T8 is electrically connected to the first pole of the driving transistor DT.

The second reset transistor T8 may be a P-channel thin film transistor, or an N-channel thin film transistor, and may be set according to practical situations, and fig. 6 only illustrates that the second reset transistor T8 is a P-channel thin film transistor.

Specifically, the fourth scan signal S4 provided by the fourth scan signal terminal S4 may control the on or off state of the second reset transistor T8, and when the second reset transistor T8 is a P-channel thin film transistor, the fourth scan signal S4 may control the on state of the second reset transistor T8 when it is a low level signal, so that the second reference voltage Vref1 provided by the second reference voltage terminal Vref2 is written into the first pole of the driving transistor DT through the on second reset transistor T8, so as to periodically reset the first pole of the driving transistor DT, thereby improving the offset or hysteresis phenomenon of the characteristics of the driving transistor after long-term operation.

For example, fig. 7 is a driving timing chart of fig. 6, and referring to fig. 6 and 7 in combination, in the initialization stage T1, the first scan signal S1 provided by the first scan signal terminal S1 is a low level signal, so as to control the first transistor T1 and the second transistor T2 to be turned on. Meanwhile, the fourth scan signal S4 provided by the fourth scan signal terminal S4 is a low level signal, and can control the second reset transistor T8 to be turned on, so that the second reference voltage Vref1 provided by the second reference voltage terminal Vref2 is written into the first pole of the driving transistor DT, and if the driving transistor DT is in the on state at this time, the second and first transistors T2 and T1 can be further written into the gate of the driving transistor DT to reset the gate of the driving transistor DT.

In the Data writing stage T2, the first scan signal S1 provided by the first scan signal terminal S1 is kept as a low level signal, the first transistor T1 and the second transistor T2 are controlled to be turned on, the third scan signal S3 provided by the third scan signal terminal S3 is a low level signal, the Data writing transistor T6 is controlled to be turned on, meanwhile, the fourth scan signal S4 is changed from a low level signal to a high level signal, the second reset transistor T8 is controlled to be turned off, so that the Data signal Vdata provided by the Data signal terminal Data can be written into the gate of the driving transistor DT through the turned-on Data writing transistor T6, the driving transistor DT, the second transistor T2 and the first transistor T1 in sequence.

In the re-lighting stage T3, the lighting control signal Emit provided by the lighting control terminal Emit jumps from a high level signal to a low level signal to control the first lighting control transistor T3 to be turned on, and the first scanning signal S provided by the first scanning signal terminal S1 jumps from the low level signal to the high level signal, and the first transistor T1The parasitic capacitance exists in the two transistors T2, and under the coupling action of the parasitic capacitance, the potential of the first node N1 is raised, so, when the light-emitting control signal emit jumps from a high level signal to a low level signal, under the coupling control of the node control module 12 (for example, the node control transistor T4), the potential of the first node N1 can be pulled down, the potential difference between the first node N1 and the second node N2 is reduced, thereby avoiding the electric leakage of the first node N1 to the second node N2 to affect the stability of the gate potential of the driving transistor DT, ensuring the light-emitting stability of the light-emitting element 20, so that the driving current I generated by the driving transistor DT can be stably transmitted to the light-emitting element 20, and can be calculated according to the driving current calculation formula provided above, where the driving current i=k is (Pvdd-Vdata) ² Thus, the light-emitting stability of the light-emitting element 20 can be ensured, and the display effect of the display panel can be improved.

Optionally, fig. 8 is a schematic structural diagram of still another pixel circuit according to an embodiment of the present invention, fig. 9 is a driving timing diagram of fig. 8, and referring to fig. 8 and 9 in combination, the pixel circuit 10 further includes a third reset transistor T9, where the third reset transistor T9 has a single gate structure; the gate of the third reset transistor T9 is electrically connected to the fifth scan signal terminal S5, the first pole of the third reset transistor T9 is electrically connected to the third reference voltage terminal Vref3, and the second pole of the third reset transistor T9 is electrically connected to the gate of the driving transistor DT.

The third reset transistor T9 may be a P-channel thin film transistor, or an N-channel thin film transistor, and may be set according to practical situations, and fig. 8 only illustrates that the third reset transistor T9 is a P-channel thin film transistor.

Specifically, in the initialization stage T1, when the fifth scan signal S5 provided by the fifth scan signal terminal S5 is a low level signal, the third reset transistor T9 is controlled to be turned on, so that the third reference voltage Vref3 provided by the third reference voltage terminal Vref3 is directly written into the gate (i.e. the second node N2) of the driving transistor DT through the turned-on third reset transistor T9, so as to reset the gate of the driving transistor DT. The specific driving timing of the pixel circuit 10 can be referred to above, and will not be described in detail herein.

It should be noted that, the third reset transistor T9 has a single gate structure, so that it is avoided that the node between the first poles (or the second poles) of the two transistors in the double gate structure and the gate of the driving transistor DT form another leakage path due to the double gate structure of the third reset transistor, and the potential stability of the gate of the driving transistor DT is further improved.

Optionally, fig. 10 is a schematic structural diagram of still another pixel circuit according to an embodiment of the present invention, fig. 11 is a driving timing diagram of fig. 10, and referring to fig. 10 and 11 in combination, the pixel circuit 10 further includes a fourth reset transistor T10; the gate of the fourth reset transistor T10 is electrically connected to the sixth scan signal terminal S6, the first pole of the fourth reset transistor T10 is electrically connected to the fourth reference voltage terminal Vref4, and the second pole of the fourth reset transistor T10 is electrically connected to the second pole of the driving transistor DT.

The fourth reset transistor T10 may be a P-channel thin film transistor, or an N-channel thin film transistor, and may be set according to practical situations, and fig. 9 only illustrates that the third reset transistor T9 is a P-channel thin film transistor.

Specifically, the initialization stage includes a first initialization stage T11 and a second initialization stage T12, and in the first initialization stage T11, the fourth scan signal S4 provided by the fourth scan signal terminal S4 is a low level signal, so that the second reset transistor T8 can be controlled to be turned on, so that the second reference voltage Vref1 provided by the second reference voltage terminal Vref2 is written into the first pole of the driving transistor DT, so as to reset the first pole of the driving transistor DT. In the second initialization stage T12, the first scan signal S1 is kept at the low level signal, the sixth scan signal S6 provided by the sixth scan signal terminal S6 is a low level signal, and the fourth reset transistor T10 can be controlled to be turned on, so that the fourth reference voltage Vref4 provided by the fourth reference voltage terminal Vref4 is written into the second pole of the driving transistor DT to reset the second pole of the driving transistor DT. Since the first scan signal S1 provided by the first scan signal terminal S1 is a low level signal in the first initialization stage T11 and the second initialization stage T12, the first transistor T1 and the second transistor T2 are controlled to be always turned on, so that the second reference voltage vref1 written into the first pole of the driving transistor DT can reset the gate of the driving transistor DT through the turned-on driving transistor DT, the second transistor T2 and the first transistor T1, or the fourth reference voltage vref4 written into the second pole of the driving transistor DT can reset the gate of the driving transistor DT through the turned-on second transistor T2 and the first transistor T1, and the third reset transistor T9 in fig. 8 is not required to be set to independently reset the gate of the driving transistor DT, thereby reducing the number of transistors in the pixel circuit 10 and lowering the cost. The specific driving timing of the pixel circuit 10 can be referred to above, and will not be described in detail herein.

Optionally, with continued reference to fig. 4, 6, 8 and 10, the pixel circuit 10 further includes a fifth reset transistor T11; the gate of the fifth reset transistor T11 is electrically connected to the seventh scan signal terminal S7, the first electrode of the fifth reset transistor T11 is electrically connected to the fifth reference voltage terminal Vref5, and the second electrode of the fifth reset transistor T11 is electrically connected to the anode of the light emitting element 20.

The fifth reset transistor T11 may be a P-channel thin film transistor, or an N-channel thin film transistor, and may be configured according to practical situations, and fig. 4, 6, 8, and 10 only exemplarily illustrate that the fifth reset transistor T11 is a P-channel thin film transistor.

Specifically, the seventh scan signal S7 provided by the seventh scan signal terminal S7 may control the fifth reset transistor T11 to be turned on or off, and when the seventh scan signal S7 is a low level signal, the fifth reset transistor T11 may be controlled to be turned on, so that the fifth reference voltage Vref5 provided by the fifth reference voltage terminal Vref5 is written into the anode of the light emitting element 20, so as to reset the anode of the light emitting element 20, avoid the influence of the voltage signal written in the previous frame, ensure the light emitting accuracy of the light emitting element 20, and further improve the display effect of the display panel.

Note that, the period in which the seventh scan signal s7 is maintained as the low level signal may be the initialization phase or the data writing phase or both the initialization phase and the data writing phase, and may be set according to the actual situation, and is not particularly limited herein.

Further optionally, with continued reference to fig. 4, 6, 8 and 10, the first scan signal terminal S1 may be multiplexed into a seventh scan signal terminal S7, so as to reduce the number of signal terminals, and further reduce the number of signal lines for transmitting the seventh scan signal, which is beneficial to a narrow frame of the display panel.

Based on the same inventive concept, embodiments of the present invention also provide a display panel including the pixel circuit 10 in any of the above embodiments. Specifically, fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present invention, as shown in fig. 12, the display panel 100 includes a display area 101, the display area 101 includes a plurality of pixel circuits 10 arranged in an array, and the pixel circuits 10 are used for driving light emitting elements (not shown in the figure) to emit light. The light emitting element may include a micro light emitting diode, for example, by setting the node control module to control the potential reduction of the first node, and reduce the potential difference between the first node and the gate of the driving transistor, thereby being beneficial to improving the problem of leakage current generated by the gate of the driving transistor, stabilizing the gate potential of the driving transistor, ensuring the light emitting stability of the light emitting element, and being beneficial to avoiding the problem of flicker.

In addition, the embodiment of the present invention further provides a display device, and fig. 13 is a schematic structural diagram of a display device provided in the embodiment of the present invention, as shown in fig. 13, the display device 200 includes the display panel 100 provided in any embodiment of the present invention, and the display device 200 provided in the embodiment of the present invention may be a mobile phone or any electronic product with a display function, including but not limited to the following categories: television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interactive terminal, etc., which are not particularly limited in this embodiment of the invention.

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements, combinations, and substitutions can be made by those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims

1. A pixel circuit, comprising: the device comprises a driving transistor, a threshold compensation module and a node control module;

2. The pixel circuit of claim 1, wherein the node control module comprises a first capacitor, a first plate of the first capacitor being a first end of the node control module, and a second plate of the first capacitor being a second end of the node control module.

3. The pixel circuit of claim 1, wherein the node control module comprises a node control transistor, a gate of the node control transistor being electrically connected to a second signal terminal, a first pole of the node control transistor being a first terminal of the node control module, a second pole of the node control transistor being a second terminal of the node control module;

the second signal provided by the second signal terminal is a signal for controlling the node to control the disconnection of the transistor.

4. The pixel circuit according to claim 1, wherein the pixel circuit further comprises a first light emitting control transistor;

the grid electrode of the first light-emitting control transistor is electrically connected with the light-emitting control signal end, the first electrode of the first light-emitting control transistor is electrically connected with the grid electrode of the driving transistor, and the second electrode of the first light-emitting control transistor is electrically connected with the anode of the light-emitting element; the first light emitting control transistor includes a P-channel thin film transistor;

the light-emitting control signal end is multiplexed into the first signal end.

5. The pixel circuit according to claim 4, further comprising a first reset transistor, a data write transistor, and a storage capacitor;

the grid electrode of the first reset transistor is electrically connected with the light-emitting control signal end, the first electrode of the first reset transistor is electrically connected with the first reference voltage end, and the second electrode of the first reset transistor is electrically connected with the first polar plate of the storage capacitor;

the grid electrode of the data writing transistor is electrically connected with the second scanning signal end, the first electrode of the data writing transistor is electrically connected with the data signal end, and the second electrode of the data writing transistor is electrically connected with the first electrode plate of the storage capacitor;

the second polar plate of the storage capacitor is electrically connected with the grid electrode of the driving transistor.

6. The pixel circuit according to claim 4, further comprising a second light emission control transistor, a data writing transistor, and a storage capacitor;

the grid electrode of the second light-emitting control transistor is electrically connected with the light-emitting control signal end, the first electrode of the second light-emitting control transistor is electrically connected with the first power end, and the second electrode of the second light-emitting control transistor is electrically connected with the first electrode of the driving transistor;

the grid electrode of the data writing transistor is electrically connected with the third scanning signal end, the first electrode of the data writing transistor is electrically connected with the data signal end, and the second electrode of the data writing transistor is electrically connected with the first electrode of the driving transistor;

the first polar plate of the storage capacitor is electrically connected with the first power supply end, and the second polar plate of the storage capacitor is electrically connected with the grid electrode of the driving transistor.

7. The pixel circuit of claim 6, wherein the pixel circuit further comprises a second reset transistor;

the grid electrode of the second reset transistor is electrically connected with the fourth scanning signal end, the first electrode of the second reset transistor is electrically connected with the second reference voltage end, and the second electrode of the second reset transistor is electrically connected with the first electrode of the driving transistor.

8. The pixel circuit of claim 6, further comprising a third reset transistor, the third reset transistor being of a single gate structure;

the grid electrode of the third reset transistor is electrically connected with the fifth scanning signal end, the first electrode of the third reset transistor is electrically connected with the third reference voltage end, and the second electrode of the third reset transistor is electrically connected with the grid electrode of the driving transistor.

9. The pixel circuit of claim 6, wherein the pixel circuit further comprises a fourth reset transistor;

the grid electrode of the fourth reset transistor is electrically connected with the sixth scanning signal end, the first electrode of the fourth reset transistor is electrically connected with the fourth reference voltage end, and the second electrode of the fourth reset transistor is electrically connected with the second electrode of the driving transistor.

10. A pixel circuit according to any one of claims 5-9, wherein the pixel circuit further comprises a fifth reset transistor;

the grid electrode of the fifth reset transistor is electrically connected with the seventh scanning signal end, the first electrode of the fifth reset transistor is electrically connected with the fifth reference voltage end, and the second electrode of the fifth reset transistor is electrically connected with the anode of the light-emitting element.

11. A display panel comprising a pixel circuit as claimed in any one of claims 1-10.

12. A display device comprising the display panel according to claim 11.