CN117221761A - Multi-board multi-channel synchronous acquisition technology based on alternating-current power frequency withstand voltage test - Google Patents
Multi-board multi-channel synchronous acquisition technology based on alternating-current power frequency withstand voltage test Download PDFInfo
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Abstract
The invention discloses a multi-board multi-channel synchronous acquisition technology based on an alternating current power frequency withstand voltage test, which comprises the steps that one AD chip is adopted as a main board to send a control signal and a clock reference signal to the other AD chip which is adopted as a slave board; for a main board, all clocks have a fixed phase relation, for a slave board, all clocks have a fixed phase relation, meanwhile, clock signals and trigger signals generated by an LMK04828 clock chip on the main board are received from an LMK04828 clock chip on the slave board, and then clocks generated by the LMK04828 clock chip on the slave board and the LMK04828 clock chip on the main board also have a fixed phase relation, finally, all clocks on two boards have a fixed phase relation, so that multi-board-card multichannel synchronous acquisition of current and voltage of a power frequency withstand voltage test is realized. The invention has the advantages that: the method has the characteristics of high efficiency, comprehensiveness, accuracy and flexibility.
Description
Technical Field
The invention relates to the technical field of alternating-current power frequency withstand voltage tests of power transformation equipment, in particular to a multi-board multi-channel synchronous acquisition technology based on an alternating-current power frequency withstand voltage test.
Background
The alternating current withstand voltage test is the most direct method for identifying the insulation strength of the electrical equipment, has decisive significance for judging whether the electrical equipment can be put into operation, and is also an important means for ensuring the insulation level of the equipment and avoiding insulation accidents. Because the alternating current withstand voltage test can fully reflect the actual condition of the electrical equipment when operating under the alternating current voltage, the insulation defect can be truly and effectively found. The ac withstand voltage test is a destructive test. Before the test, the test items such as insulation resistance, absorption ratio, leakage current, dielectric loss angle and the like must be tested, if the test result is normal, an alternating current withstand voltage test can be performed, and if the equipment insulation condition is found to be bad, the withstand voltage test is usually performed after the treatment is performed, so that the unnecessary insulation breakdown is avoided.
Disclosure of Invention
In order to solve the defects of the prior art, the invention aims to provide a multi-board multi-channel synchronous acquisition technology with high flexibility and strong expansibility based on an alternating current power frequency withstand voltage test.
In order to solve the technical problems, the technical scheme provided by the invention is as follows:
a multi-board multi-channel synchronous acquisition technology based on an alternating current power frequency withstand voltage test comprises the following steps:
s1, verifying a data synchronous acquisition technology of a multi-board card by adopting 2 4-channel signal acquisition boards, wherein each 4-channel signal acquisition board consists of a high-speed AD chip and a field programmable logic device (FPGA), the AD chip converts an external intermediate frequency signal into a digital signal and then supplies the digital signal into the FPGA for preprocessing, and the FPGA transmits a preprocessing result to a next-stage target unit;
s2, adopting one AD chip as a main board to send a control signal and a clock reference signal to the other AD chip as a slave board;
s3, adopting JESD204B technology to realize delay and synchronous acquisition of the multichannel AD chip, generating SYSREF signal when the AD chip operates, wherein the SYSREF signal can be determined by a formula (1), fBITRATE in the formula (1) is the bit rate of a serializer/deserializer in JESD204B transmission, K is the frame number of each multiframe, F is the 8-bit word number of each frame, n is any positive integer,
s4, for a main board, an on-board acquisition clock and a processing clock are generated by an on-board LMK04828 clock chip, all clocks have a fixed phase relation, for a slave board, the on-board acquisition clock and the processing clock are generated by an on-board LMK04828 clock chip, all clocks have a fixed phase relation, meanwhile, the on-board LMK04828 clock chip receives a clock signal and a trigger signal generated by the on-board LMK04828 clock chip, and further, clocks generated by the on-board LMK04828 clock chip and the on-board LMK04828 clock chip also have a fixed phase relation, and finally, all clocks on two boards have a fixed phase relation, so that multi-board-card multichannel synchronous acquisition of power frequency withstand voltage test current and voltage is realized.
Further, the number of the signal acquisition channels in the S1 is 4;
simultaneously monitoring 4 paths of currents and 4 paths of voltages (alternating current 0-250V) respectively: 1 path of test PT secondary coil current, 1 path of tested equipment grounding current, 1 path of alternating current power frequency withstand voltage test boosting operation box current and 1 path of test PT shell grounding current. 1 path of alternating current power frequency withstand voltage test boosting operation box voltage, 1 path of test PT secondary coil voltage and 2 paths of standby voltage;
the signal acquisition bandwidth and the center frequency are 550 MHz-950 MHz and 750MHz respectively;
the effective bit is not less than 9.5bit;
the signal sampling rate is not less than 1000MSPS;
amplitude consistency among channels is not more than 0.5dB (R.M.S);
the phase consistency between the channels is not more than 5 ° (r.m.s).
Further, the AD chip adopts AD9680-1000, the maximum resolution of the chip is 14 bits, the highest sampling rate is 1GSPS, the spurious-free dynamic range is 80dBc (fIN=1 GHZ), the serial output of the high-speed 2-channel JESD204B is supported, and the AD9680-1000 can sample broadband analog signals up to the second Nyquist zone, so that the demand of distortion-free sampling of signals in the range of 550 MHz-950 MHz is met.
Further, the generation of the SYSREF signal in S3 needs to meet two requirements, with respect to the setup and hold time of the device clock, and needs to be run at a proper frequency, which is generally easier for a lower-speed ADC chip, and a higher device clock rate reduces the setup and hold time of the SYSREF signal for a faster-speed ADC chip, and at this time, it may be necessary to make necessary dynamic delay adjustments to meet timing requirements under different conditions, and the SYSREF may be either a continuous signal or an intermittent signal, and its frequency must be equal to the local multi-frame clock frequency or an integer division of the local multi-frame clock frequency.
Compared with the prior art, the invention has the advantages that:
1. high efficiency: the multi-board multi-channel data tour collection system can acquire data from a plurality of channels at the same time, so that the data collection speed can be greatly increased;
2. comprehensively: the data acquisition is carried out by using a plurality of different channels, so that more comprehensive and rich data resources can be obtained;
3. accuracy: when the multi-board multi-channel data tour collection system is used, useless information can be filtered through setting rules, so that the obtained information is real and reliable;
4. flexibility: different from the traditional single channel acquisition mode, the multi-board multi-channel data tour acquisition system has higher flexibility and expandability.
Drawings
Fig. 1 is a flow chart of data reception according to the present invention.
Fig. 2 is a block diagram of a synchronous implementation of the multi-board multi-channel AD of the present invention.
Detailed Description
The following description of the technical solutions in the embodiments of the present invention will be clear and complete, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The present invention will be described in further detail with reference to the following examples in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Examples
And 2 4-channel signal acquisition boards are adopted to verify the data synchronous acquisition technology of the multi-board card. Each 4-channel signal acquisition board mainly comprises a high-speed AD chip and a field programmable logic device FPGA, wherein the AD chip converts an external intermediate frequency signal into a digital signal and then supplies the digital signal into the FPGA for preprocessing, and the FPGA transmits a preprocessing result to a next-stage target unit. The designed partial indexes are as follows:
the number of the signal acquisition channels is 4;
simultaneously monitoring 4 paths of currents and 4 paths of voltages (alternating current 0-250V) respectively: 1 path of test PT secondary coil current, 1 path of tested equipment grounding current, 1 path of alternating current power frequency withstand voltage test boosting operation box current and 1 path of test PT shell grounding current. 1 path of alternating current power frequency withstand voltage test boosting operation box voltage, 1 path of test PT secondary coil voltage and 2 paths of standby.
The signal acquisition bandwidth and the center frequency are 550 MHz-950 MHz and 750MHz respectively;
the effective bit is not less than 9.5bit;
the signal sampling rate is not less than 1000MSPS;
amplitude consistency among channels is not more than 0.5dB (R.M.S);
the phase consistency between the channels is not more than 5 ° (r.m.s).
The AD chip adopts AD9680-1000, the maximum resolution of the chip is 14 bits, the highest sampling rate is 1GSPS, the spurious-free dynamic range is 80dBc (fIN=1 GHZ), and the high-speed 2-channel JESD204B serial output is supported. The AD9680-1000 can sample the broadband analog signal up to the second Nyquist zone, and meets the requirement of undistorted sampling of signals in the range of 550 MHz-950 MHz. In order to realize the synchronous requirement of the multi-channel AD chip between the multiple boards, an LMK04828 clock chip is adopted, the chip has lower root mean square jitter, supports the JEDEDECJESD 204B protocol which is popular at present, can reach up to 14 pairs of differential devices (including 7 pairs of SYSREFClocks), and can meet the requirement of realizing the synchronous acquisition of the multi-channel power frequency withstand voltage current and voltage between the multiple boards. The synchronous realization principle of the multi-plate multi-channel AD chip is shown in figure 1.
Fig. 1 realizes synchronous data acquisition of 2 4-channel AD boards to power frequency withstand voltage test current and voltage. One AD board card is used as a main board to send a control signal and a clock reference signal to the other AD board card which is used as a slave board, so that multichannel synchronous acquisition among multiple board cards is realized.
For the motherboard, the on-board acquisition clock and the processing clock are generated by an LMK04828 clock chip on the motherboard, and all the clocks have fixed phase relation. For the slave board, the on-board acquisition clock and the processing clock are generated by the slave board LMK04828 clock chip, all clocks have a fixed phase relation, and meanwhile, the slave board LMK04828 clock chip receives the clock signal and the trigger signal generated by the master board LMK04828 clock chip, and the clocks generated by the slave board LMK04828 clock chip and the master board LMK04828 clock chip also have a fixed phase relation. Finally, all clocks on the two boards have a fixed phase relation, so that multi-board multichannel synchronous acquisition of current and voltage of the power frequency withstand voltage test is realized.
SYSREF signals
The JESD204B technology is adopted to realize delay and synchronous acquisition of the multichannel AD chip, and the SYSREF signal is very important. The generation of the SYSREF signal meets two requirements: with respect to the setup and hold times of the device clock, and needs to run at the proper frequency. Generally, for lower speed ADC chips, the SYSREF signal setup and hold time is easier to meet, and for faster speed ADC chips, the higher device clock rate reduces the SYSREF signal setup and hold time, which may require the necessary dynamic delay adjustment to meet timing requirements under different conditions. The SYSREF may be either a continuous signal or an intermittent signal, the frequency of which must be equal to the local multi-frame clock frequency or an integer division of the local multi-frame clock frequency. The value of SYSREF can be determined by equation (1), where fBITRATE is the bit rate of the serializer/deserializer in JESD204B transmission, K is the number of frames per multiframe, F is the number of 8-bit words per frame, and n is any positive integer.
Synchronous data receiving flow
The working flow of the multi-board multi-channel synchronous acquisition of the current and the voltage of the power frequency withstand voltage test is shown in figure 2. After the equipment is powered on, each chip on the two boards, such as an FPGA chip, an LMK04828 chip, an AD chip and the like, is firstly configured, after the configuration of the two boards is completed, a clock reference signal and a synchronous trigger signal are firstly sent out by the main board, after the synchronous trigger signal and the clock reference signal are received from the boards, the synchronous time sequence among 2 boards is completed, and finally, the multi-channel synchronous acquisition among multiple boards is realized.
The invention and its embodiments have been described without limitation, and the examples shown are only one of the embodiments of the invention, without the actual embodiment being limited thereto. In summary, those skilled in the art, having benefit of this disclosure, will appreciate that many changes can be made without departing from the spirit and scope of the invention as disclosed herein.
Claims (4)
1. A multi-board multi-channel synchronous acquisition technology based on an alternating current power frequency withstand voltage test is characterized by comprising the following steps:
s1, verifying a data synchronous acquisition technology of a multi-board card by adopting 2 4-channel signal acquisition boards, wherein each 4-channel signal acquisition board consists of a high-speed AD chip and a field programmable logic device (FPGA), the AD chip converts an external intermediate frequency signal into a digital signal and then supplies the digital signal into the FPGA for preprocessing, and the FPGA transmits a preprocessing result to a next-stage target unit;
s2, adopting one AD chip as a main board to send a control signal and a clock reference signal to the other AD chip as a slave board;
s3, adopting JESD204B technology to realize delay and synchronous acquisition of the multichannel AD chip, generating SYSREF signal when the AD chip operates, wherein the SYSREF signal can be determined by a formula (1), fBITRATE in the formula (1) is the bit rate of a serializer/deserializer in JESD204B transmission, K is the frame number of each multiframe, F is the 8-bit word number of each frame, n is any positive integer,
s4, for a main board, an on-board acquisition clock and a processing clock are generated by an on-board LMK04828 clock chip, all clocks have a fixed phase relation, for a slave board, the on-board acquisition clock and the processing clock are generated by an on-board LMK04828 clock chip, all clocks have a fixed phase relation, meanwhile, the on-board LMK04828 clock chip receives a clock signal and a trigger signal generated by the on-board LMK04828 clock chip, and further, clocks generated by the on-board LMK04828 clock chip and the on-board LMK04828 clock chip also have a fixed phase relation, and finally, all clocks on two boards have a fixed phase relation, so that multi-board-card multichannel synchronous acquisition of power frequency withstand voltage test current and voltage is realized.
2. The multi-board multi-channel synchronous acquisition technology based on the alternating current power frequency withstand voltage test according to claim 1, which is characterized in that:
the number of the signal acquisition channels in the S1 is 4;
simultaneously monitoring 4 paths of currents and 4 paths of voltages (alternating current 0-250V) respectively: 1 path of test PT secondary coil current, 1 path of tested equipment grounding current, 1 path of alternating current power frequency withstand voltage test boosting operation box current and 1 path of test PT shell grounding current. 1 path of alternating current power frequency withstand voltage test boosting operation box voltage, 1 path of test PT secondary coil voltage and 2 paths of standby voltage;
the signal acquisition bandwidth and the center frequency are 550 MHz-950 MHz and 750MHz respectively;
the effective bit is not less than 9.5bit;
the signal sampling rate is not less than 1000MSPS;
amplitude consistency among channels is not more than 0.5dB (R.M.S);
the phase consistency between the channels is not more than 5 ° (r.m.s).
3. The multi-board multi-channel synchronous acquisition technology based on the alternating current power frequency withstand voltage test according to claim 1, which is characterized in that:
the AD chip adopts AD9680-1000, the maximum resolution of the chip is 14 bits, the highest sampling rate is 1GSPS, the spurious-free dynamic range is 80dBc (fIN=1 GHZ), the serial output of the high-speed 2-channel JESD204B is supported, the AD9680-1000 can sample broadband analog signals up to a second Nyquist zone, and the requirement of undistorted sampling of signals in the range of 550 MHz-950 MHz is met.
4. The multi-board multi-channel synchronous acquisition technology based on the alternating current power frequency withstand voltage test according to claim 1, which is characterized in that:
the generation of the SYSREF signal in S3 needs to meet two requirements, with respect to the setup and hold time of the device clock, and needs to be run at a proper frequency, which is generally easier for a lower speed ADC chip, and a higher device clock rate reduces the setup and hold time of the SYSREF signal for a faster speed ADC chip, where the SYSREF signal may be a continuous signal or an intermittent signal, and the frequency must be equal to the local multi-frame clock frequency or an integer division of the local multi-frame clock frequency.
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| CN118174730A (en) * | 2024-05-15 | 2024-06-11 | 贵州航天电子科技有限公司 | Amplitude-phase compensation method and device for multichannel narrow pulse signals and electronic equipment |
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| CN118174730A (en) * | 2024-05-15 | 2024-06-11 | 贵州航天电子科技有限公司 | Amplitude-phase compensation method and device for multichannel narrow pulse signals and electronic equipment |
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