CN117201387A

CN117201387A - Path selection method, path selection device, electronic equipment and storage medium

Info

Publication number: CN117201387A
Application number: CN202311192152.1A
Authority: CN
Inventors: 丁楠
Original assignee: China Mobile Communications Group Co Ltd; China Mobile Suzhou Software Technology Co Ltd
Current assignee: China Mobile Communications Group Co Ltd; China Mobile Suzhou Software Technology Co Ltd
Priority date: 2023-09-15
Filing date: 2023-09-15
Publication date: 2023-12-08

Abstract

The disclosure provides a path selection method, a path selection device, electronic equipment and a storage medium, wherein the method comprises the following steps: acquiring first network topology information, wherein the first network topology information at least comprises node information in a network and link cost information between adjacent nodes; and sending the first network topology information to a Field Programmable Gate Array (FPGA) so that the FPGA can determine an optimal path based on the first network topology information.

Description

Path selection method, path selection device, electronic equipment and storage medium

Technical Field

The present disclosure relates to the field of routing paths, and in particular, to a path selection method, a device, an electronic apparatus, and a storage medium.

Background

The path selection method refers to a method that a software defined network (Software Defined Network, SDN) controller calculates an optimal path from a start node to a target node by using information of each node in a network topology and link cost information. In the related art, due to the advantages of simple software deployment, strong flexibility and the like, a path selection method is generally realized by using software. However, since the computational power of the SDN controller is limited, a manner of implementing a path selection algorithm by using software will increase the load of the SDN controller, which further causes problems such as routing path selection delay.

Disclosure of Invention

The present disclosure provides a path selection method, apparatus, electronic device, and storage medium to solve the problems in the related art.

An embodiment of a first aspect of the present disclosure provides a path selection method, applied to a host, where the method includes:

acquiring first network topology information, wherein the first network topology information at least comprises node information in a network and link cost information between adjacent nodes;

and sending the first network topology information to a Field Programmable Gate Array (FPGA) so that the FPGA can determine an optimal path based on the first network topology information.

In some embodiments of the disclosure, the acquiring the first network topology information includes:

receiving second network topology information sent by network equipment in the network, wherein the second network topology information at least comprises node information in the network and network indexes between adjacent nodes;

determining link cost information between the adjacent nodes based on network indexes between the adjacent nodes;

and determining the first network topology information based on node information in the network and link cost information between adjacent nodes.

In some embodiments of the present disclosure, the sending the first network topology information to a field programmable gate array FPGA includes:

And sending the first network topology information to the FPGA through an open computing language OpenCL.

An embodiment of a second aspect of the present disclosure provides a path selection method applied to a field programmable gate array FPGA, the method including:

receiving first network topology information sent by a host side;

and determining an optimal path based on the node information in the first network topology information and the link cost information between adjacent nodes.

In some embodiments of the disclosure, the determining the optimal path based on the node information in the first network topology information and the link cost information between the neighboring nodes includes:

determining an optimal path from each node to a target node by using Dijkstra algorithm based on node information in the first network topology information and link cost information between adjacent nodes;

an optimal path from the starting node to the target node is determined based on the optimal path from each node to the target node.

In some embodiments of the present disclosure, the determining the optimal path from the start node to the target node based on the optimal path from each node to the target node includes:

in response to at least one node fault, deleting an optimal path corresponding to the fault node from the optimal paths from each node to the target node, and determining the optimal paths from the rest nodes to the target node; the remaining nodes refer to nodes other than the failed node;

And determining the optimal path from the starting node to the target node based on the optimal paths from the remaining nodes to the target node.

In some embodiments of the present disclosure, the receiving the first network topology information sent by the host includes:

and receiving the first network topology information sent by the host through the open computing language OpenCL.

In some embodiments of the present disclosure, the path selection method further includes:

and storing the first network topology information in an on-chip storage space of the FPGA according to a preset bit width.

In some embodiments of the disclosure, the determining the optimal path from each node to the target node by using Dijkstra algorithm based on the node information in the first network topology information and the link cost information between the neighboring nodes includes:

the Dijkstra algorithm of DijTesla is realized on the FPGA through an advanced comprehensive HLS algorithm;

and determining an optimal path from each node to the target node based on the node information in the first network topology information and the link cost information between the adjacent nodes.

An embodiment of a third aspect of the present disclosure provides a path selection device, applied to a host, where the device includes:

A first obtaining unit, configured to obtain first network topology information, where the first network topology information at least includes node information in a network and link cost information between adjacent nodes;

and the first sending unit is used for sending the first network topology information to a Field Programmable Gate Array (FPGA) so that the FPGA can determine an optimal path based on the first network topology information.

An embodiment of a fourth aspect of the present disclosure proposes a path selection device applied to a field programmable gate array FPGA, the device comprising:

the first receiving unit is used for receiving first network topology information sent by the host side;

and the first determining unit is used for determining an optimal path based on the node information in the first network topology information and the link cost information between the adjacent nodes.

A fifth aspect embodiment of the present disclosure proposes an electronic device including:

at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method described in the first aspect embodiment or the second aspect embodiment of the present disclosure.

A sixth aspect embodiment of the present disclosure proposes a non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method described in the first aspect embodiment or the second aspect embodiment of the present disclosure.

In summary, the present disclosure proposes a path selection method, including: the method comprises the steps that a host side obtains first network topology information, wherein the first network topology information at least comprises node information in a network and link cost information between adjacent nodes; and the host end sends the first network topology information to a Field Programmable Gate Array (FPGA) so that the FPGA can determine an optimal path based on the first network topology information. The FPGA receives first network topology information sent by a host terminal; the FPGA determines an optimal path based on node information in the first network topology information and link cost information between adjacent nodes.

According to the scheme provided by the disclosure, the first network topology information acquired by the host side can be sent to the FPGA, and the optimal path is determined through the FPGA, so that the load of the SDN controller of the host side is reduced, and meanwhile, lower path selection delay is realized. Furthermore, the path selection algorithm adopts an FPGA heterogeneous mode, and can provide stronger flexibility in optimizing and upgrading the algorithm.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure and do not constitute an undue limitation on the disclosure.

Fig. 1 is a flow chart of a first path selection method according to an embodiment of the disclosure;

fig. 2 is a flow chart of a second path selection method according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram of a path selection system provided by an example application of the present disclosure;

FIG. 4 is a schematic diagram of creating a FIFO channel when applying the HLS encapsulation function provided by the example of the present disclosure to data flow;

FIG. 5 is a schematic diagram of an iterative process of the Dijkstra algorithm provided by an application example of the present disclosure, performed in a cyclized form;

FIG. 6 is a schematic diagram of an iterative process of the Dijkstra algorithm provided by an application example of the present disclosure, performed in a non-cyclized form;

fig. 7 is a schematic structural diagram of a first path selecting device according to an embodiment of the disclosure;

fig. 8 is a schematic structural diagram of a second path selecting device according to an embodiment of the disclosure;

Fig. 9 is a schematic diagram of a hardware composition structure of an electronic device according to an embodiment of the disclosure.

Detailed Description

Embodiments of the present disclosure are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and intended for the purpose of explaining the present disclosure and are not to be construed as limiting the present disclosure.

SDN is used as a novel network innovation architecture, and compared with the traditional mode of vertical routing distribution, a novel mode of centralized separation is adopted, namely, a control plane and a data plane are separated, and a centralized SDN controller is adopted to realize the function of an original control plane.

The Link State (LS) selection algorithm is used as a path selection algorithm, and the working process of the Link State (LS) selection algorithm benefits from the information of each network node acquired by the SDN controller, the information of all Link costs of the network and the like. The optimal path from the starting node to the target node is calculated by the LS routing algorithm, which essentially calculates the optimal path by Dijkstra's DijTesla algorithm.

Because of the characteristics of relatively simple software deployment, high flexibility, maintainability and the like, the implementation of the path selection algorithm in the related technology is mainly based on pure software. But in recent years, as network technology is continuously developed, the complexity of the network technology is exponentially increased. Meanwhile, due to the characteristics of the SDN controller, various data information sent by the network equipment is carried, and summarizing, classifying and calculating are needed. In the peak period of message proliferation, the load of the SDN controller is larger, and the response of the SDN interaction machine cannot be responded in time. Meanwhile, the SDN controller needs to calculate an optimal path according to a path selection algorithm through summarized information. Its calculation process generally takes a higher weight in the total delay of the network.

As described in scheme a:

scheme a collects the required node and link cost information from the network. And finally calculating an optimal path by adopting an average global load balancing algorithm and a path selection algorithm according to the network node and the adjacency list. However, since solution a is implemented by software integrated on the SDN controller, more delay is often consumed on a complex network link. Meanwhile, the method is limited by the scheduling and interrupt mechanism of the host operating system, and the delay of the scheme A also fluctuates, so that the stability of the whole network is not facilitated.

In order to solve the defects in the related art, the method and the device realize lower path selection delay while reducing the load of an SDN controller at a host side by sending the first network topology information acquired at the host side to the FPGA and determining an optimal path through the FPGA. Furthermore, the path selection algorithm adopts an FPGA heterogeneous mode, and can provide stronger flexibility in optimizing and upgrading the algorithm.

The present disclosure will be described in further detail with reference to the accompanying drawings and specific embodiments.

Fig. 1 is a schematic flow chart of a first path selection method according to an embodiment of the disclosure. The first path selection method provided by the embodiment of the present disclosure is applied to a host, that is, the execution body is the host.

The first path selection method provided by the embodiment of the disclosure comprises the following steps:

step 101: acquiring first network topology information, wherein the first network topology information at least comprises node information in a network and link cost information between adjacent nodes;

in an embodiment, the host side refers to a host side carrying an SDN controller.

In an embodiment, the first network topology information refers to first network topology information of a network where the host side and the target device are located.

In an embodiment, the host side may acquire the first network topology information by acquiring information of each node in the network.

In an embodiment, the host side may further obtain the first network topology information directly through a node server.

In an embodiment, the information of each node in the network directly acquired by the host side may have some useless redundant information, such as manufacturer information of the node device, model information of the node device, etc., so the host side needs to delete the useless redundant information in order to save traffic, reduce data storage amount.

In an embodiment, the link cost information between adjacent nodes in the first network topology information is embodied by network indexes of links between adjacent nodes. The network indexes comprise an average number-of-modulation index, a bandwidth index, a time delay index, a reliability index, a load index and the like.

Based on this, in an embodiment, the acquiring the first network topology information includes:

Step 102: and sending the first network topology information to a Field Programmable Gate Array (FPGA) so that the FPGA can determine an optimal path based on the first network topology information.

In an embodiment, the communication channel between the host and the FPGA may be directly used to send the first network topology information to the FPGA.

In an embodiment, the first network topology information may also be sent to the FPGA through an open computing language (Open Computing Language, openCL).

Based on this, in an embodiment, the sending the first network topology information to a field programmable gate array FPGA includes:

The OpenCL is mainly responsible for calling and distributing the host side and the FPGA storage memory and interface communication. The host end stores the first network topology information into a memory of the host end, and only leaves the first network topology information which needs to accelerate kernel calculation, such as node information, link cost information between adjacent nodes and the like after useless redundant information is screened out. And carrying the data into a global memory through an OpenCL (open peripheral component interconnect express) (Peripheral Component Interconnect Express, PCIe) standard, and distributing the first network topology information to a processing unit corresponding to the FPGA for processing through memory mapping.

In an embodiment, the OpenCL device may be implemented by using the host side, or the OpenCL device may be implemented by using the FPGA. In an embodiment, when the host side sends the first network topology information to the FPGA through the OpenCL, the OpenCL device may first store the first network topology information on its global/constant storage.

In summary, the present disclosure proposes a path selection method, including: acquiring first network topology information, wherein the first network topology information at least comprises node information in a network and link cost information between adjacent nodes; and sending the first network topology information to a Field Programmable Gate Array (FPGA) so that the FPGA can determine an optimal path based on the first network topology information.

Fig. 2 is a schematic flow chart of a second path selection method according to an embodiment of the disclosure. The second path selection method provided by the embodiment of the disclosure is applied to the FPGA, that is, the execution body is the FPGA.

The second path selection method provided by the embodiment of the disclosure includes the following steps:

step 201, receiving first network topology information sent by a host;

in an embodiment, the FPGA may receive the first network topology information sent by the host through a communication channel with the host.

In an embodiment, the FPGA may further send the first network topology information to the FPGA through the OpenCL.

Step 202, determining an optimal path based on node information in the first network topology information and link cost information between adjacent nodes.

In an embodiment, the FPGA determines an optimal path based on node information in the first network topology information and link cost information between neighboring nodes using Dijkstra's Dijkstra algorithm.

In an embodiment, the Dijkstra algorithm is an LS routing algorithm, and may also determine an optimal path based on node information in the first network topology information and link cost information between adjacent nodes by using a distance vector routing algorithm.

Through the second path selection algorithm provided by the disclosure, an optimal path can be determined by using an FPGA based on the first network topology information sent by the host side. The load of the SDN controller at the host side is reduced, and meanwhile, lower path selection delay is realized. Furthermore, the path selection algorithm adopts an FPGA heterogeneous mode, and can provide stronger flexibility in optimizing and upgrading the algorithm.

In an embodiment, the determining the optimal path based on the node information in the first network topology information and the link cost information between the neighboring nodes includes:

The determining the optimal path from each node to the target node by using Dijkstra algorithm comprises the following steps:

initializing a starting node as an origin S, defining S= (v), wherein the distance of v is 0; defining a set of other nodes except the initial node as U; defining the weight (distance v) of the edge between the node in U and S as the link cost, and if the node in U is not adjacent to S, defining the weight of the edge as ++;

s is added from a first node with the minimum distance v between the first node and the S in the U, and the S and the U are updated;

and updating the weight of the edges between each node in the U and the first node by taking the first node as a new starting node S until no node exists in the updated U.

The Dijkstra algorithm not only can determine the optimal path from the starting node to the target node in the network, but also can ensure the accuracy of the result based on the link cost (the weight of the edge) between the adjacent nodes.

In one embodiment, a node in the network may fail, resulting in a link being unavailable.

Based on this, in an embodiment, the determining the optimal path from the start node to the target node based on the optimal path from each node to the target node includes:

Through the scheme, when a certain node in the network fails, the failed node can be directly deleted, and the updated optimal path can be rapidly determined based on the information of other nodes, so that the method is simple and efficient.

In an embodiment, the FPGA has very limited hardware resources, especially limited hardware memory resources. The first network topology information, i.e. the node information and the link cost information between adjacent nodes, often require a smaller storage space, but when the Dijkstra algorithm is utilized, the weights of the edges between other nodes in the network and the starting node often need to occupy a larger storage space.

Based on the above, in order to optimize the storage space, the bit widths of on-chip storage and off-chip storage of the FPGA can be customized by improving the storage space utilization of the FPGA. The on-chip storage of the FPGA is usually SRAM, and has higher data read-write bandwidth compared with the off-chip storage. Therefore, the first network topology information can be stored in the on-chip storage space, and delay is further reduced by storing a high-bandwidth read-write rate on-chip.

Based on this, in an embodiment, the second path selection method according to the embodiment of the disclosure further includes:

In one embodiment, in order to implement the path selection algorithm in an FPGA, a High-Level Synthesis (HLS) algorithm may be employed. Wherein the HLS algorithm is an algorithm that converts a high-level description algorithm into a hardware implementation. The HLS can convert algorithms written in high-level languages such as C/C++ or SystemC into register transmission level (Register Transfer Level, RTL) implementation and integrate the algorithms onto the FPGA to achieve the hardware acceleration effect of software. The purpose of HLS is to more efficiently build and verify hardware by letting the hardware designer describe the design at a higher level of abstraction.

The implementation process of HLS mainly comprises three steps: synthesis, RTL coding and FPGA synthesis. Synthesis refers to converting an algorithm from a high-level language to an RTL level; the RTL code is to convert the synthesized RTL code into hardware description languages such as VHDL/HDL; finally, the FPGA synthesis synthesizes the RTL code onto the FPGA to realize the hardware acceleration effect.

HLS has the following advantages:

the hardware efficiency is improved: the HLS tool can translate the high-level description of the algorithm into RTL code and automatically optimize the hardware architecture to achieve higher hardware efficiency.

Accelerating hardware development: the HLS tool can reduce the traditional manual hardware design process and improve the development efficiency.

Improving hardware maintainability: the RTL code generated by the HLS tool has a good structure and is convenient to maintain and modify.

Support cross-platform development: the HLS tool can be used on different FPGA platforms, and has strong universality.

Based on this, in an embodiment, the determining the optimal path from each node to the target node by using Dijkstra algorithm based on the node information in the first network topology information and the link cost information between the neighboring nodes includes:

The path selection method provided by the embodiment of the present disclosure is further described below with application examples.

As shown in fig. 3, fig. 3 is a schematic structural diagram of a path selection system provided by an application example of the present disclosure. The path selection system 300 includes: host side 301, openCL device side 302, and FPGA303.

The path selection system 300 adopts a design mode of combining OpenCL with HLS, where OpenCL is mainly responsible for calling, allocating and interface communication of the storage memories of the host side and the FPGA. The host receives the second network topology information sent by the network equipment and stores the second network topology information in the memory, sorts various second network topology information, screens out unnecessary data information, and only leaves the first network topology information which needs to accelerate the kernel calculation, such as node information, link cost information between adjacent nodes and the like. And then the data is carried to the global memory of the OpenCL device side 302 through PCIe, and the data is distributed to the corresponding processing units of the FPGA303 for processing through memory mapping. The processing elements (Processing Element, PE) are used as processing units of the work items and are provided with respective private memories for storing intermediate data to be calculated.

In an application example, the path selection algorithm performed by the FPGA on the node cannot be processed in parallel due to the coupling between the predecessor node and the successor node. Therefore, the application example of the present disclosure adopts the hardware pipeline design concept, and is implemented through HLS optimization instructions. The HLS algorithm gives two optimized instructions of Pipeline and Dataflow of a data flow diagram aiming at the Pipeline design. The Pipeline is mainly applied to an unpacked loop body in the function and under the top-level function, and is usually used in combination with an array segmentation and partition instruction, so that data throughput is improved. Dataflow is mainly applied between functions.

Based on this, in an application example, the implementation of Dijkstra algorithm of Dijkstra on the FPGA by advanced synthesis HLS algorithm includes:

and realizing the Dijkstra algorithm on the FPGA through a data flow instruction in a data flow diagram in the HLS algorithm.

In an application example, the Dijkstra algorithm is divided into three parts of processing of reading, calculating and storing by a Dataflow instruction in the HLS algorithm. The reading means reads the first network topology information, the calculating means calculates an optimal path based on the first network topology information by using Dijkstra algorithm, and the storing means stores the calculated optimal path.

As shown In fig. 4, HLS analyzes the data stream of the packing function, creating channels between them, the channel type is typically First In, first Out (FIFO) for scalar variables. For non-scalar variables, such as a group of variables, a Ping-Pong (PIPO) buffer is used. Each channel contains an information indication to determine whether the status of the FIFO or PIPO buffer is full or empty. The existence of the channel enables the next data reading operation to be started before the storage operation is completed, so that the calculation delay of a network routing algorithm is reduced, and the throughput of the whole data is improved.

In an application example, when the Dijkstra algorithm is implemented on the FPGA through a Dataflow instruction in the HLS algorithm, as shown in fig. 5, an iterative process of the Dijkstra algorithm is generally performed in a form of a cyclized roller loop. In fig. 5, the Read section includes Read1 and Read2 … … ReadN when performing different routing methods, the calculation section includes Calculate1 and Calculate2 … … Calculate en, and the storage section includes Write1 and Write2 … … Write n. Wherein, the reading, calculating and storing respectively need to be completed by corresponding hardware resources. However, as shown in fig. 6, if the iterative process of Dijkstra algorithm is performed in the form of uncycled uncroled loop, the parallelism of FPGA processing can be N times as much as the original. Meanwhile, if the read-write contents come from the same Block Random Access Memory (BRAM), but the BRAM has at most two ports, the partition expansion is required to be performed on the data at the same time of the unreoll expansion, so that the overall processing parallelism is N times of the original processing parallelism, and the time delay consumed by sequential processing is greatly reduced.

Based on this, in one embodiment, the implementation of Dijkstra's algorithm on the FPGA by advanced synthesis HLS algorithm includes:

And realizing the Dijkstra algorithm on the FPGA in a non-cyclized Unlolled loop mode through the HLS algorithm.

In one application example, the conventional integer data type byte length is a prime integer multiple of 8. In the path selection method, the maximum bit width of most link costs may be much smaller than the conventional integer data type word length. In order to avoid the waste of storage space resources possibly caused by the traditional data types, storage optimization can be performed by introducing data types with arbitrary accuracy of HLS, the data types with arbitrary accuracy of HLS have smaller data variables with smaller bit widths than the traditional C language data, and a compiler can run through C language simulation. The smaller bit width can generate smaller and faster hardware operators on the FPGA, so that the layout density of the FPGA logic units is increased, and the program running at a higher clock frequency can be met. Taking the C++ language as an example, the storage data type is set to be an ap_int < N > or an ap_ui < N > type, wherein N represents the bit width size of the custom range 1-1024.

When the data optimization design is carried out on the path selection method based on the historical experience value, the bit width of the data is designed to be 16 bits, and the weight of the link cost is always a positive value, so that the normal path selection calculation can be met, unnecessary resource waste on data storage is avoided, and finally the data calculation performance of the FPGA is improved. Specifically, the utilization rate of the SRAM storage space is improved through the change of the data bit width, and the SRAM storage space is used for storing link cost data of high-frequency access, so that the reading rate of the data is improved, and the delay of overall routing calculation is reduced.

Based on this, the path selection method applied to the FPGA further includes:

and realizing the data storage bit width of 16 bits on the FPGA by using the HLS.

In order to implement the first path selection method applied to the host side provided in the embodiment of the present disclosure, the embodiment of the present disclosure further provides a first path selection device, as shown in fig. 7. Fig. 7 is a schematic structural diagram of a first path selecting device according to an embodiment of the present disclosure, where the path selecting device 700 includes:

a first obtaining unit 701, configured to obtain first network topology information, where the first network topology information at least includes node information in a network and link cost information between adjacent nodes;

and the first sending unit 702 is configured to send the first network topology information to a field programmable gate array FPGA, so that the FPGA determines an optimal path based on the first network topology information.

In an embodiment, the first obtaining unit 701 is specifically configured to:

In an embodiment, the first sending unit 702 is specifically configured to:

In order to implement the second path selection method applied to the FPGA provided by the embodiment of the present disclosure, the embodiment of the present disclosure further provides a second path selection device, as shown in fig. 8. Fig. 8 is a schematic structural diagram of a second path selecting device according to an embodiment of the present disclosure, where the path selecting device 800 includes:

a first receiving unit 801, configured to receive first network topology information sent by a host;

a first determining unit 802, configured to determine an optimal path based on node information in the first network topology information and link cost information between neighboring nodes.

In an embodiment, the first determining unit 802 is specifically configured to:

In an embodiment, the first determining unit 802 is further specifically configured to:

In an embodiment, the first receiving unit 801 is specifically configured to:

In one embodiment, the path selection device 800 further includes a storage unit, where the storage unit is configured to:

It should be noted that: in the path selection device provided in the above embodiment, only the division of each program module is used for illustration, and in practical application, the process allocation may be performed by different program modules according to needs, i.e. the internal structure of the path selection device is divided into different program modules, so as to complete all or part of the processes described above. In addition, the path selection device provided in the above embodiment and the path selection method embodiment provided in the embodiment of the present disclosure belong to the same concept, and detailed implementation processes of the path selection device are shown in the method embodiment, and are not repeated here.

Fig. 9 is a schematic diagram of a hardware composition structure of an electronic device according to an embodiment of the disclosure, as shown in fig. 9, where the electronic device 900 includes at least one processor 902; and a memory 901 communicatively coupled to the at least one processor 902; wherein the memory 901 stores instructions executable by the at least one processor 902 for implementing the steps of the path selection method according to the embodiments of the present disclosure.

Optionally, the electronic device may be specifically a path selection device in the embodiment of the present application, and the electronic device may implement a corresponding flow implemented by the path selection device in each method in the embodiment of the present application, which is not described herein for brevity.

It is understood that the electronic device also includes a communication interface 903. The various components in the electronic device are coupled together by a bus system 904. It is appreciated that the bus system 904 is used to facilitate connected communications between these components. The bus system 904 includes a power bus, a control bus, and a status signal bus in addition to a data bus. But for clarity of illustration, the various buses are labeled as bus system 904 in fig. 9.

It is to be appreciated that memory 901 can be either volatile memory or nonvolatile memory, and can include both volatile and nonvolatile memory. Wherein the non-volatile Memory may be a Read Only Memory (ROM), a programmable Read Only Memory (PROM, programmable Read Only Memory), an erasable programmable Read Only Memory (EPROM, erasable Programmable Read Only Memory), an electrically erasable programmable Read Only Memory (EEPROM, electrically Erasable Programmable Read Only Memory), a magnetic random access Memory (FRAM, ferromagnetic random access Memory), a Flash Memory (Flash Memory), a magnetic surface Memory, an optical disk, or a compact disk Read Only (CD ROM, compact Disc Read Only Memory); the magnetic surface memory may be a disk memory or a tape memory. The volatile memory may be random access memory (RAM, random Access Memory), which acts as external cache memory. By way of example, and not limitation, many forms of RAM are available, such as static random access memory (SRAM, static Random Access Memory), synchronous static random access memory (SSRAM, synchronous Static Random Access Memory), dynamic random access memory (DRAM, dynamic Random Access Memory), synchronous dynamic random access memory (SDRAM, synchronous Dynamic Random Access Memory), double data rate synchronous dynamic random access memory (ddr SDRAM, double Data Rate Synchronous Dynamic Random Access Memory), enhanced synchronous dynamic random access memory (ESDRAM, enhanced Synchronous Dynamic Random Access Memory), synchronous link dynamic random access memory (SLDRAM, syncLink Dynamic Random Access Memory), direct memory bus random access memory (DRRAM, direct Rambus Random Access Memory). The memory 901 described in embodiments of the present invention is intended to comprise, without being limited to, these and any other suitable types of memory.

The methods disclosed in the embodiments of the present disclosure described above may be applied to the processor 902 or implemented by the processor 902. The processor 902 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the methods described above may be performed by integrated logic circuitry in hardware or instructions in software in the processor 902. The processor 902 described above may be a general purpose processor, DSP, or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The processor 902 may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present invention. The general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed in the embodiment of the invention can be directly embodied in the hardware of the decoding processor or can be implemented by combining hardware and software modules in the decoding processor. The software modules may be located in a storage medium in memory 901 and processor 902 reads information in memory 901 to perform the steps of the methods described above in connection with the hardware.

In an exemplary embodiment, the electronic device may be implemented by one or more application specific integrated circuits (ASIC, application Specific Integrated Circuit), DSP, programmable logic device (PLD, programmable Logic Device), complex programmable logic device (CPLD, complex Programmable Logic Device), FPGA, general purpose processor, controller, MCU, microprocessor, or other electronic element for performing the aforementioned methods.

The present public security embodiment also provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute the steps of the path selection method according to the embodiment of the present application.

Optionally, the computer readable storage medium may be applied to the path selecting device in the embodiment of the present application, and the computer instructions cause a computer to execute the corresponding flow implemented by the path selecting device in each method of the embodiment of the present application, which is not described herein for brevity.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or units, whether electrically, mechanically, or otherwise.

The units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated in one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated in one unit; the integrated units may be implemented in hardware or in hardware plus software functional units.

Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the above method embodiments may be implemented by hardware associated with program instructions, where the foregoing program may be stored in a computer readable storage medium, and when executed, the program performs steps including the above method embodiments; and the aforementioned storage medium includes: a removable storage device, ROM, RAM, magnetic or optical disk, or other medium capable of storing program code.

Alternatively, the above-described integrated units of the present invention may be stored in a computer-readable storage medium if implemented in the form of software functional modules and sold or used as separate products. Based on such understanding, the technical solutions of the embodiments of the present invention may be embodied in essence or a part contributing to the prior art in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present invention. And the aforementioned storage medium includes: a removable storage device, ROM, RAM, magnetic or optical disk, or other medium capable of storing program code.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A path selection method applied to a host end, comprising:

2. The method of claim 1, wherein the obtaining the first network topology information comprises:

3. The method of claim 1, wherein the sending the first network topology information to a field programmable gate array FPGA comprises:

4. A path selection method applied to a field programmable gate array FPGA, comprising:

receiving first network topology information sent by a host side;

5. The method of claim 4, wherein determining an optimal path based on node information in the first network topology information and link cost information between neighboring nodes comprises:

6. The method of claim 5, wherein determining the optimal path from the originating node to the destination node based on the optimal path from each node to the destination node comprises:

7. The method of claim 4, wherein the receiving the first network topology information sent by the host includes:

8. The method of claim 4, further comprising:

9. The method of claim 5, wherein determining the optimal path from each node to the target node using Dijkstra's Dijkstra algorithm based on the node information in the first network topology information and the link cost information between neighboring nodes, comprises:

10. A path selection device applied to a host end, comprising:

11. A path selection device for use in a field programmable gate array FPGA, comprising:

12. An electronic device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 3 or 4 to 9.

13. A non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of any one of claims 1 to 3 or 4 to 9.